Lookup table based dc offset correction circuit, zero intermediate frequency receiver and lookup table based dc offset correction method

Abstract

The application provides a direct current offset correction circuit based on a lookup table, a zero intermediate frequency receiver and a direct current offset correction method based on a lookup table. The direct current offset correction circuit based on a lookup table comprises a storage module, an analog coarse correction module and a digital fine correction module. In the receiving channel of the zero intermediate frequency receiver, the analog coarse correction module is used to perform analog coarse correction on the direct current offset in the analog signal, and the digital fine correction module is used to perform digital fine correction on the direct current offset in the digital signal. The analog intermediate frequency correction and the digital baseband correction are considered, and the correction precision of the direct current offset is improved. Meanwhile, the direct current offset correction lookup tables generated by radio frequency and intermediate frequency devices are separately established. During correction, indexing and operation are performed based on the analog coarse correction module and the digital fine correction module. Only a small number of calculation input correction parameters need to be saved, the total capacity of the lookup table is reduced, and the storage load of the storage module is reduced.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and in particular to a lookup table-based DC offset correction circuit, a zero-IF receiver, and a lookup table-based DC offset correction method. Background Technology

[0002] Compared to superheterodyne receivers, zero-IF receivers offer advantages such as simpler circuit structure and higher system integration, leading to their widespread application in wireless receiver systems. However, zero-IF receivers also have inherent problems and limitations. One major issue is DC offset, caused by factors such as local oscillator leakage, RF signal leakage, even-order nonlinearity, flicker noise, and baseband amplifier mismatch. DC offset degrades the system's signal-to-noise ratio and increases the bit error rate. Therefore, DC offset correction is essential to ensure good demodulation performance. Furthermore, signal fading during transmission due to factors like distance and geographical location results in significant variations in the received signal. Since receivers can only process signals within a certain amplitude range, excessively large or small signals can cause abnormal receiver operation. Therefore, an AGC (Automatic Gain Control) circuit is needed to control the gain of the receiver's LNA (Low Noise Amplifier), MIXER (Mixer), Analog LPF (Analog Low Pass Filter), etc., so that the amplitude of the receiver's output signal is kept within a constant range, thereby maintaining the normal operation of the system. However, uncorrected DC offset will also affect the output power of the AGC.

[0003] As a key module of a zero-IF receiver, the DC offset correction circuit plays a crucial role in correcting the receiver's DC offset, reducing the system's bit error rate, ensuring the receiver's normal operation, and improving the communication quality of the wireless communication system. Existing technologies employ digital pre-emptive DC offset correction circuits. These circuits estimate the DC offset using digital signal processing before the receiver operates, and then store the estimated value in a register. During receiver operation, the path signal is subtracted from the register value, thereby eliminating the DC offset.

[0004] However, existing DC offset correction circuits have at least two problems: First, because correction is only performed at the analog intermediate frequency and not at the digital baseband, due to the limitations of the analog range, there will be a certain residual DC error after DC offset correction. If correction is only performed at the digital baseband, the input signal may exceed the range because no correction is performed at the analog end, leading to incorrect calculation of the DC offset estimate. Second, because the DC offset is different for different gains and different radio frequency frequencies, when the AGC circuit is working, in order to enable the receiver to work quickly at multiple pre-stored radio frequency points and multiple gains, the DC offset correction circuit needs to pre-store multiple radio frequency points and multiple gains of DC correction codewords, which will result in an excessively large lookup table capacity.

[0005] Therefore, there is an urgent need for a technical solution that can take into account both analog intermediate frequency correction and digital baseband correction while reducing the capacity of the correction lookup table. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a DC offset correction technology based on a lookup table. This technology uses the AGC gain of the zero-IF receiver as the lookup table index value, employs an analog coarse correction module corresponding to the analog coarse correction lookup table and a digital fine correction module corresponding to the digital fine correction lookup table for joint correction, taking into account both analog IF correction and digital baseband correction, thereby improving the accuracy of DC offset correction. Simultaneously, it establishes separate DC offset correction lookup tables for the DC offsets generated by RF and IF devices, and performs index operations based on the analog coarse correction module and the digital fine correction module during use, thereby reducing the total capacity of the lookup table.

[0007] To achieve the above-mentioned objectives and other related objectives, the technical solution provided by the present invention is as follows.

[0008] A lookup table-based DC offset correction circuit is applied in a zero-IF receiver. The zero-IF receiver includes two receiving channels, each receiving channel comprising at least a mixer, an analog filter, an analog-to-digital converter, and a digital filter connected in series. The lookup table-based DC offset correction circuit includes:

[0009] The storage module contains an analog coarse correction lookup table and a digital fine correction lookup table;

[0010] An analog coarse correction module is disposed between the mixer and the analog filter. The first input terminal is connected to the output terminal of the mixer, the second, third and fourth input terminals are respectively connected to the storage module, and the output terminal is connected to the input terminal of the analog filter. The module performs analog coarse correction on the DC offset in the analog signal based on the correction code in the analog coarse correction lookup table.

[0011] A digital fine correction module is located after the digital filter. Its first input terminal is connected to the output terminal of the digital filter, and its second, third, and fourth input terminals are respectively connected to the storage module. Its output terminal is connected to the subsequent processor. The module performs digital fine correction on the DC offset in the digital signal based on the correction code in the digital fine correction lookup table.

[0012] Optionally, the analog coarse calibration lookup table includes an analog RF coarse calibration lookup table and an analog IF coarse calibration lookup table, and the digital fine calibration lookup table includes a digital RF fine calibration lookup table, a digital IF fine calibration lookup table, and a digital IF gain value lookup table.

[0013] Optionally, the analog RF coarse calibration lookup table stores an analog RF DC calibration code, which is related to the RF gain level and the RF local oscillator frequency; the analog IF coarse calibration lookup table stores an analog IF DC calibration code, the RF gain level, and a DC voltage calibration accuracy control code, which is related to the analog IF gain; the digital RF fine calibration lookup table stores a digital RF DC calibration code, which is related to the RF gain level and the RF local oscillator frequency; the digital IF fine calibration lookup table stores a digital IF DC calibration code, the RF gain level, and the IF gain level, which is related to the analog IF gain; and the digital IF gain value lookup table stores an IF gain value, which is related to the IF gain level.

[0014] Optionally, the analog coarse correction module includes a digital adder, a digital-to-analog converter (DAC), and an analog subtractor. The first input of the analog subtractor is connected to the output of the mixer, the second input of the analog subtractor is connected to the output of the DAC, and the output of the analog subtractor is connected to the input of the analog filter. The first input of the DAC is connected to the output of the digital adder, and the second input of the DAC is connected to the storage module. The storage module outputs to the DAC the correction obtained from the analog intermediate frequency coarse correction lookup table based on the analog total gain index, along with the unit DC voltage correction. The DC voltage correction accuracy control code is related to the value; the first input terminal of the digital adder is connected to the storage module, and the storage module outputs the analog RF DC correction code obtained from the analog RF coarse correction lookup table based on the RF gain level and the RF local oscillator frequency index to the first input terminal of the digital adder; the second input terminal of the digital adder is connected to the storage module, and the storage module outputs the analog intermediate frequency DC correction code related to the intermediate frequency gain level obtained from the analog total gain index in the analog intermediate frequency coarse correction lookup table to the second input terminal of the digital adder.

[0015] Optionally, the digital fine correction module includes a digital multiplier, a digital adder, and a digital subtractor. The first input of the digital subtractor is connected to the output of the digital filter, the second input of the digital subtractor is connected to the output of the digital adder, the output of the digital subtractor is connected to the post-processor, the first input of the digital adder is connected to the output of the digital multiplier, the first input of the digital multiplier is connected to the storage module, and the storage module outputs the intermediate frequency gain value obtained from the digital intermediate frequency gain value lookup table based on the intermediate frequency gain level index to the digital multiplier. The second input of the digital multiplier is connected to the storage module, and the storage module outputs the digital radio frequency DC correction code obtained from the digital radio frequency fine correction lookup table based on the radio frequency gain level and the radio frequency local oscillator frequency index to the digital multiplier. The second input of the digital adder is connected to the storage module, and the storage module outputs the digital intermediate frequency DC correction code related to the intermediate frequency gain level obtained from the digital intermediate frequency fine correction lookup table based on the analog total gain index to the digital adder.

[0016] A zero-IF receiver includes two receiving channels and further includes a lookup table-based DC offset correction circuit as described in any of the preceding claims. The lookup table-based DC offset correction circuit includes one storage module, two analog coarse correction modules, and two digital fine correction modules. Each receiving channel is provided with one analog coarse correction module and one digital fine correction module.

[0017] A lookup table-based DC offset correction method, applied to the aforementioned zero-IF receiver, the method comprising:

[0018] For the receiving channel, the analog coarse correction lookup table in the storage module is indexed to obtain and input the correction code in the analog coarse correction lookup table into the analog coarse correction module, and the analog coarse correction module performs analog coarse correction on the DC offset in the analog signal.

[0019] For the receiving channel, the digital fine correction lookup table in the storage module is indexed to obtain and input the correction code in the digital fine correction lookup table into the digital fine correction module, and the DC offset in the digital signal is digitally fine corrected by the digital fine correction module.

[0020] As described above, the DC offset correction circuit based on lookup table, the zero intermediate frequency receiver, and the DC offset correction method based on lookup table of the present invention have at least the following beneficial effects:

[0021] A lookup table-based DC offset correction circuit is designed by combining a storage module, an analog coarse correction module, and a digital fine correction module. On each receiving channel of the zero-IF receiver, an analog coarse correction module corresponding to the analog coarse correction lookup table is used to perform analog coarse correction on the DC offset in the analog signal, and a digital fine correction module corresponding to the digital fine correction lookup table is used to perform digital fine correction on the DC offset in the digital signal. This takes into account both analog IF correction and digital baseband correction, improving the accuracy of DC offset correction. At the same time, separate DC offset correction lookup tables are established for the analog coarse correction lookup table and the digital fine correction lookup table to separate the DC offset generated by the RF and IF devices. During correction, only indexing and calculation based on the analog coarse correction module and the digital fine correction module are needed to obtain more DC offset correction values. Only a few calculation input correction parameters need to be stored, which can effectively reduce the total capacity of the lookup table and reduce the storage load of the storage module. Attached Figure Description

[0022] Figure 1 The diagram shown is a block diagram of a prior art digital pre-type DC offset correction circuit.

[0023] Figure 2 This diagram shows the DC offset correspondence for each receive channel in a zero-IF receiver.

[0024] Figure 3 The diagram shown is a structural block diagram of the DC offset correction circuit based on a lookup table in this invention.

[0025] Figure 4 This is a hierarchical diagram of the DC correction lookup table in this invention.

[0026] Figure 5 The diagram shown is a structural block diagram of the simulation coarse correction module in an optional embodiment of the present invention.

[0027] Figure 6 The diagram shown is a structural block diagram of the digital fine correction module in an optional embodiment of the present invention.

[0028] Figure 7 The diagram shown is a structural block diagram of a zero-IF receiver in an optional embodiment of the present invention. Detailed Implementation

[0029] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] Please see Figures 1 to 7It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. The structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives of the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0031] As mentioned in the background section, the inventors discovered that the DC offset correction circuit, as a key module of the zero-IF receiver, plays a crucial role in correcting the receiver's DC offset, reducing the system's bit error rate, ensuring the receiver's normal operation, and improving the communication quality of the wireless communication system. Existing DC offset correction technologies employ a digital pre-calculation DC offset correction circuit. Before the receiver operates, digital signal processing is used to estimate the DC offset in advance, and the estimated value is stored in a register. During receiver operation, the path signal is subtracted from the register value to eliminate the DC offset. Its circuit structure is as follows: Figure 1 As shown.

[0032] In detail, such as Figure 1 As shown, a digital pre-emptive DC offset correction circuit is set on each receiving channel of the zero intermediate frequency receiver. The digital pre-emptive DC offset correction circuit includes an analog-to-digital converter (ADC), a memory, a digital-to-analog converter (DAC), and an analog subtractor (or analog adder). The digital pre-emptive DC offset correction circuit is connected to the output and input terminals of the programmable gain amplifier (PGA) in each receiving channel, respectively. The input terminal of the ADC is connected to the output terminal of the PGA. The ADC performs analog-to-digital conversion on the received output signal, then performs digital signal processing to obtain a digital estimate of the DC offset and stores it in the memory. The output terminal of the memory is connected to the input terminal of the DAC. The DAC performs digital-to-analog conversion on the DC offset digital estimate output from the memory to obtain an analog estimate of the DC offset. The analog estimate of the DC offset is input to the second input terminal of the analog subtractor. The first input terminal of the analog subtractor is connected to the input signal. The output terminal of the analog subtractor is connected to the input terminal of the PGA. The analog subtractor performs a subtraction operation on the input signal and the DC offset analog estimate to correct the DC offset of the input signal, thereby eliminating the DC offset in the input signal.

[0033] However, as Figure 1 The DC offset correction circuit shown has at least the following two defects:

[0034] 1) Because the correction is only performed at the analog intermediate frequency (before the analog-to-digital converter in the receiving channel) and not at the digital baseband (after the analog-to-digital converter in the receiving channel), there will be a certain residual DC (direct current) error after the DC offset correction due to the limitation of the analog range. If the correction is only performed at the digital baseband, the input signal may exceed the range because the analog end is not corrected, resulting in an error in the calculation of the DC offset estimate.

[0035] 2) Since the DC offset varies with different gains and different RF frequencies, when the automatic gain control circuit is working, in order for the receiver to work quickly at multiple pre-stored RF frequencies and multiple gains, the DC offset correction circuit needs to pre-store multiple RF frequencies and multiple gains of DC correction codewords. Taking 32 RF frequencies and 80 total gain levels as an example, if a lookup table is established based on the total DC offset, a total of 32*80*2 entries need to be stored for the I and Q channels. The total table requires at least 120Kb of capacity, which will result in an excessively large lookup table capacity.

[0036] Meanwhile, the inventors discovered the following logical relationship while studying the DC offset of a zero-IF receiver:

[0037] Since the DC offsets of the I and Q channels of a zero-IF receiver are independent, the analysis will be conducted using the I channel as an example:

[0038] With a fixed gain in the receiving digital path, let the DC offset generated before the analog intermediate frequency be d. in d in DC offset d generated by radio frequency devices RF DC offset d generated by DAC control code DAC Adding them together, let the DC offset generated by the intermediate frequency device be d. IF The total DC offset is d out The correspondence is as follows: Figure 2 As shown.

[0039] Then the following relationship holds:

[0040] d out =d in ×G IF +d IF =(d RF +d DAC )×G IF +d IF (1)

[0041] Among them, G IF d represents the analog intermediate frequency gain value. RFd represents the DC offset value of the analog radio frequency. IF d represents the DC offset value of the analog intermediate frequency. DAC This represents the sum of the DC offset estimates for analog radio frequency and analog intermediate frequency.

[0042] Therefore, the DC offset generated by RF and IF devices can be separated, and corresponding DC offset correction lookup tables can be established for each device to reduce the memory required for the lookup tables.

[0043] Based on this, the present invention provides a DC offset correction technology solution based on a lookup table: a DC offset correction circuit based on a lookup table is designed by combining a storage module, an analog coarse correction module, and a digital fine correction module. On each receiving channel of the zero intermediate frequency receiver, an analog coarse correction module corresponding to the analog coarse correction lookup table is used to perform analog coarse correction on the DC offset in the analog signal, and a digital fine correction module corresponding to the digital fine correction lookup table is used to perform digital fine correction on the DC offset in the digital signal, taking into account both analog intermediate frequency correction and digital baseband correction, thereby improving the correction accuracy of DC offset. At the same time, for the analog coarse correction lookup table and the digital fine correction lookup table, DC offsets generated by RF and intermediate frequency devices are established separately to create DC offset correction lookup tables. During correction, only indexing and calculation based on the analog coarse correction module and the digital fine correction module are needed to obtain more DC offset correction values, and only a few calculation input correction parameters need to be stored, thereby reducing the total capacity of the lookup table and reducing the storage load of the storage module.

[0044] Specifically, such as Figure 3 As shown, this invention provides a DC offset correction circuit based on a lookup table. Figure 3 (As shown in the dashed box), it is applied in a zero-IF receiver. The zero-IF receiver includes two receiving channels, I and Q. Each receiving channel (I or Q receiving channel) includes at least a mixer, an analog filter, an analog-to-digital converter, and a digital filter connected in series. The DC offset correction circuit based on the lookup table includes:

[0045] The storage module contains an analog coarse correction lookup table and a digital fine correction lookup table;

[0046] The analog coarse correction module is located between the mixer and the analog filter. The first input terminal is connected to the output terminal of the mixer, the second, third and fourth input terminals are connected to the storage module, and the output terminal is connected to the input terminal of the analog filter. It performs analog coarse correction on the DC offset in the analog signal based on the correction code in the analog coarse correction lookup table.

[0047] The digital fine correction module is located after the digital filter. Its first input terminal is connected to the output terminal of the digital filter, and its second, third, and fourth input terminals are connected to the storage module. Its output terminal is connected to the subsequent processor. It performs digital fine correction on the DC offset in the digital signal based on the correction code in the digital fine correction lookup table.

[0048] In detail, such as Figures 3-4 As shown, the analog coarse calibration lookup table includes an analog RF coarse calibration lookup table and an analog IF coarse calibration lookup table, while the digital fine calibration lookup table includes a digital RF fine calibration lookup table, a digital IF fine calibration lookup table, and a digital IF gain value lookup table. The DC offset correction data stored in the RF coarse calibration lookup table, the analog IF coarse calibration lookup table, the digital RF fine calibration lookup table, the digital IF fine calibration lookup table, and the digital IF gain value lookup table are all pre-calibrated and will not be elaborated further here.

[0049] More specifically, the analog RF coarse calibration lookup table stores analog RF DC calibration codes, which are related to the RF gain level and the RF local oscillator frequency.

[0050] In an optional embodiment of the invention, the storage format of the analog RF coarse calibration lookup table is shown in Table 1. The analog RF coarse calibration lookup table stores I-channel analog RF DC calibration codes DCI_RF_CTRL and Q-channel analog RF DC calibration codes DCQ_RF_CTRL, which are respectively related to the RF gain level and the RF local oscillator frequency. The column indices RF_index0 to RF_index7 represent the RF gain levels, a total of 8 levels; the row index represents the number of RF frequency points to be stored, a total of 32, corresponding to different RF local oscillator frequencies; and the 8-bit I-channel analog RF DC calibration code DCI_RF_CTRL or Q-channel analog RF DC calibration code DCQ_RF_CTRL represents levels 0 to 255, respectively.

[0051]

[0052] Table 1. Storage format of analog RF coarse calibration lookup table

[0053] More specifically, the analog intermediate frequency coarse correction lookup table stores the analog intermediate frequency DC correction code, RF gain level, and DC voltage correction accuracy control code. The analog intermediate frequency DC correction code is related to the analog intermediate frequency gain.

[0054] In an optional embodiment of the invention, the storage format of the analog intermediate frequency (IF) coarse correction lookup table is shown in Table 2. The analog IF coarse correction lookup table stores the I-channel analog IF DC correction code DCI_IF_CTRL, the Q-channel analog IF DC correction code DCQ_IF_CTRL, the RF gain level RF_index, and the DC voltage correction precision control code IF_OffsetDAC_BIAS_ct, which are related to the analog IF gain. Among them, the gain index 0 to 79 indicates that the total analog gain is 0 to 79 dB; the 2-bit DC voltage correction precision control code IF_OffsetDAC_BIAS_ct controls the unit DC voltage value corresponding to the unit DC correction code of the digital-to-analog converter DAC1 during analog correction, with precision from high to low as 00, 01, 10, and 11; the 8-bit I-channel analog IF DC correction code DCI_IF_CTRL and the Q-channel analog IF DC correction code DCQ_IF_CTRL represent levels 0 to 255, respectively; RF_index represents the RF gain level, with a total of 8 levels, corresponding to RF_index0 to RF_index7.

[0055]

[0056] Table 2. Storage format of analog intermediate frequency coarse correction lookup table

[0057] More specifically, the digital RF fine calibration lookup table stores digital RF DC calibration codes, which are related to the RF gain level and the RF local oscillator frequency.

[0058] In an optional embodiment of the invention, the storage format of the digital RF fine-calibration lookup table is shown in Table 3. The digital RF fine-calibration lookup table stores I-channel digital RF DC correction codes DCI_RF_digerr and Q-channel digital RF DC correction codes DCQ_RF_digerr, each 16 bits, which are related to the RF gain level and the RF local oscillator frequency, respectively. Among them, the 256 row indices 0 to 255 are 5-bit RF local oscillator frequency indices plus 3-bit RF gain level indices RF_index, corresponding to 32 different RF local oscillator frequencies and 8 RF gain levels RF_index0 to RF_index7.

[0059]

[0060] Table 3. Storage Format of Digital RF Fine Calibration Lookup Table

[0061] More specifically, the digital intermediate frequency fine calibration lookup table stores the digital intermediate frequency DC calibration code, RF gain level, and intermediate frequency gain level. The digital intermediate frequency DC calibration code is related to the analog intermediate frequency gain.

[0062] In an optional embodiment of the invention, the storage format of the digital intermediate frequency (IF) fine-calibration lookup table is shown in Table 4. The digital IF fine-calibration lookup table stores the I-channel digital IF DC correction code DCI_IF_digerr, the Q-channel digital IF DC correction code DCQ_IF_digerr, the RF gain level RF_index, and the IF gain level IF_index related to the analog IF gain. Specifically, gain indices 0-79 represent the total analog gain of 0-79 dB; the I-channel digital IF DC correction code DCI_IF_digerr and the Q-channel digital IF DC correction code DCQ_IF_digerr are each 16 bits; RF_index represents the RF gain level, with 3 bits for a total of 8 levels, corresponding to RF_index0-RF_index7; and IF_index represents the IF gain level, with 5 bits for a total of 32 levels.

[0063]

[0064] Table 4. Storage Format of Digital Intermediate Frequency Fine Calibration Lookup Table

[0065] More specifically, the digital intermediate frequency gain value lookup table stores the intermediate frequency gain value, which is related to the intermediate frequency gain level.

[0066] In an optional embodiment of the invention, the storage format of the digital intermediate frequency (IF) gain value lookup table is shown in Table 5. The digital IF gain value lookup table stores the I-channel IF gain value DCI_IF_GAIN and the Q-channel IF gain value DCQ_IF_GAIN related to the IF gain level. Row indices 0 to 31 represent the IF gain level, which is 32 levels from 0 to 31 dB; the I-channel IF gain value DCI_IF_GAIN and the Q-channel IF gain value DCQ_IF_GAIN are each 12 bits.

[0067]

[0068] Table 5. Digital Intermediate Frequency Gain Value Lookup Table Storage Format

[0069] In detail, in an alternative embodiment of the invention, such as Figure 5As shown, the analog coarse correction module includes a digital-to-analog converter (DAC1), a digital adder (Adder1), and an analog subtractor (subtractor1). The first input of the analog subtractor (subtractor1) is connected to the output of the mixer, the second input is connected to the output of the DAC1, and the output is connected to the input of the analog filter. The first input of the DAC1 is connected to the output of the Adder1, and the second input (bias terminal) of the DAC1 is connected to the storage module. The storage module supplies power to the DAC1. C1 outputs a DC voltage correction accuracy control code related to the unit DC voltage correction value obtained from the analog total gain index in the analog intermediate frequency coarse correction lookup table; the first input terminal of the digital adder Adder1 is connected to the storage module, the second input terminal of the digital adder Adder1 is connected to the storage module, the storage module outputs the analog RF DC correction code obtained from the analog RF gain level and RF local oscillator frequency index in the analog RF coarse correction lookup table to the first input terminal of the digital adder Adder1, and the storage module outputs the analog intermediate frequency DC correction code obtained from the analog total gain index in the analog intermediate frequency coarse correction lookup table to the second input terminal of the digital adder Adder1.

[0070] More specifically, during the simulation coarse correction, such as Figure 5 As shown, firstly, the analog RF DC correction code is obtained from the analog RF coarse correction lookup table index in the storage module, and the analog IF DC correction code and DC voltage correction accuracy control code are obtained from the analog IF coarse correction lookup table index in the storage module. Secondly, the analog RF DC correction code and the analog IF DC correction code are superimposed and summed by the digital adder Adder1 to obtain the analog DC correction code. Thirdly, under the bias control of the DC voltage correction accuracy control code, the analog DC correction code is converted from digital to analog by the digital-to-analog converter DAC1 to obtain the analog DC offset correction value. Finally, the analog subtractor subtracts the output signal of the mixer from the analog DC offset correction value to perform analog coarse correction on the DC offset in the analog signal of the receiving channel. The first correction is performed at the analog IF to roughly eliminate the DC offset in the input signal.

[0071] Due to the limitations of the analog range, some residual DC error will still exist after the coarse correction by the analog coarse correction module. Therefore, a second fine correction is required at the digital baseband level.

[0072] In detail, in an alternative embodiment of the invention, such as Figure 6As shown, the digital fine correction module includes a digital multiplier (Multiplier), a digital adder (Adder2), and a digital subtractor (Subtractor2). The first input of Subtractor2 is connected to the output of the digital filter, and the second input is connected to the output of Adder2. The output of Subtractor2 is connected to a subsequent processor (not shown in the figure). The first input of Adder2 is connected to the output of Multiplier, and the first input of Multiplier is connected to a storage module. The storage module connects to Multiplier... The first input terminal outputs the intermediate frequency (IF) gain value obtained from the IF gain level index in the digital IF gain value lookup table to the digital multiplier. The second input terminal of the digital multiplier is connected to the storage module. The storage module outputs the digital radio frequency (RF) DC correction code obtained from the digital RF fine correction lookup table based on the RF gain level and RF local oscillator frequency index to the digital multiplier through the second input terminal of the digital multiplier. The second input terminal of the digital adder 2 is connected to the storage module. The storage module outputs the digital IF DC correction code related to the IF gain level obtained from the analog total gain index in the digital IF fine correction lookup table to the digital adder 2.

[0073] More specifically, during digital fine-tuning, such as Figure 6 As shown, firstly, the intermediate frequency (IF) gain value is obtained from the lookup table of digital IF gain values ​​in the storage module, and the digital radio frequency (RF) DC correction code is obtained from the lookup table of digital RF fine correction in the storage module. Secondly, the IF gain value and the RF DC correction code are multiplied by a digital multiplier to obtain the RF DC offset correction value. Thirdly, the RF DC offset correction value and the IF DC correction code are summed by a digital adder (Adder2) to obtain the RF DC offset correction value, where the IF DC correction code represents the IF DC offset correction value. Finally, the output signal of the digital filter is subtracted by a digital subtractor (subtracter2) to perform digital fine correction on the residual DC offset in the digital signal of the receiving channel, and a second correction is performed at the digital baseband to further eliminate the DC offset in the input signal.

[0074] Thus, the DC offset correction circuit based on lookup table in this invention takes into account both analog intermediate frequency correction and digital baseband correction. At the analog intermediate frequency, the analog coarse correction module performs analog coarse correction on the DC offset in the analog signal, and at the digital baseband, the digital fine correction module performs digital fine correction on the DC offset in the digital signal. The two corrections improve the accuracy of DC offset correction.

[0075] Meanwhile, for the analog coarse correction lookup table and the digital fine correction lookup table, the DC offset generated by the RF and IF devices are established separately to create DC offset correction lookup tables. During correction, only the index operation based on the analog coarse correction module and the digital fine correction module is needed to obtain more DC offset correction values. Only a few calculation input correction parameters need to be stored, which can effectively reduce the total capacity of the lookup table and reduce the storage load of the storage module.

[0076] In an optional embodiment of the present invention, taking 32 radio frequency points and a total gain of 80 levels as an example, for example... Figure 1 The existing DC offset correction technology shown and such Figure 3 The DC offset correction technique based on lookup tables in this invention is compared experimentally, as shown in the example. Figure 1 The existing technical solution shown requires 120Kb of capacity to create a master table, while the technical solution of creating separate tables in this invention only requires about 18Kb of capacity.

[0077] Based on the above-described lookup table-based DC offset correction circuit, the present invention also provides a zero-IF receiver, such as... Figure 7 As shown, the zero intermediate frequency receiver includes two receiving channels, I and Q. Each receiving channel (I or Q) includes at least a mixer, an analog filter, an analog-to-digital converter, and a digital filter connected in series. The input terminals of both the I and Q receiving channels are connected to devices such as low-noise amplifiers (LNAs), which will not be described in detail here. For more information, please refer to existing technologies.

[0078] In detail, such as Figure 7 As shown, the zero-IF receiver also includes the aforementioned lookup table-based DC offset correction circuit. This lookup table-based DC offset correction circuit includes a storage module, two analog coarse correction modules, and two digital fine correction modules. Each receiving channel is equipped with one analog coarse correction module and one digital fine correction module. The DC offset correction for one receiving channel is performed by combining one analog coarse correction module and one digital fine correction module, and the two receiving channels share a single storage module during DC offset correction. Simultaneously, the outputs of the two receiving channels after correction by their respective digital fine correction modules are input to the subsequent digital processor.

[0079] Furthermore, this invention also provides a DC offset correction method based on a lookup table, applied to the aforementioned zero-IF receiver, the method comprising the following steps:

[0080] S1. For the receiving channel, index the analog coarse correction lookup table in the storage module, obtain and input the correction code in the analog coarse correction lookup table into the analog coarse correction module, and perform analog coarse correction on the DC offset in the analog signal through the analog coarse correction module.

[0081] S2. For the receiving channel, index the digital fine correction lookup table in the storage module, obtain and input the correction code in the digital fine correction lookup table into the digital fine correction module, and perform digital fine correction on the DC offset in the digital signal through the digital fine correction module.

[0082] It should be noted that in steps S1 to S2, both analog coarse correction and digital fine correction can be performed simultaneously on both receiving channels, or only one receiving channel can be subjected to analog coarse correction and digital fine correction. The specific correction process of analog coarse correction and digital fine correction can be referred to the relevant description of the DC offset correction circuit based on the lookup table mentioned above, and will not be repeated here.

[0083] In summary, the DC offset correction circuit, zero-IF receiver, and DC offset correction method based on lookup tables provided by this invention combine a storage module, an analog coarse correction module, and a digital fine correction module to design the DC offset correction circuit based on lookup tables. On each receiving channel of the zero-IF receiver, an analog coarse correction module corresponding to the analog coarse correction lookup table is used to perform analog coarse correction on the DC offset in the analog signal, and a digital fine correction module corresponding to the digital fine correction lookup table is used to perform digital fine correction on the DC offset in the digital signal. This takes into account both analog IF correction and digital baseband correction, improving the correction accuracy of DC offset. At the same time, for the analog coarse correction lookup table and the digital fine correction lookup table, the DC offset generated by the RF and IF devices are established separately to create DC offset correction lookup tables. During correction, only indexing and calculation based on the analog coarse correction module and the digital fine correction module are needed to obtain more DC offset correction values. Only a few calculation input correction parameters need to be stored, effectively reducing the total capacity of the lookup table and reducing the storage load of the storage module.

[0084] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A DC offset correction circuit based on a lookup table, applied in a zero-IF receiver, the zero-IF receiver comprising two receiving channels, each receiving channel comprising at least a mixer, an analog filter, an analog-to-digital converter, and a digital filter connected in series, characterized in that, The lookup table-based DC offset correction circuit includes: The storage module contains an analog coarse correction lookup table and a digital fine correction lookup table; An analog coarse correction module is disposed between the mixer and the analog filter. The first input terminal is connected to the output terminal of the mixer, the second, third and fourth input terminals are respectively connected to the storage module, and the output terminal is connected to the input terminal of the analog filter. The module performs analog coarse correction on the DC offset in the analog signal based on the correction code in the analog coarse correction lookup table. A digital fine correction module is located after the digital filter. Its first input terminal is connected to the output terminal of the digital filter, its second, third and fourth input terminals are respectively connected to the storage module, and its output terminal is connected to the subsequent processor. It performs digital fine correction on the DC offset in the digital signal based on the correction code in the digital fine correction lookup table. The analog coarse calibration lookup table includes an analog radio frequency coarse calibration lookup table and an analog intermediate frequency coarse calibration lookup table, and the digital fine calibration lookup table includes a digital radio frequency fine calibration lookup table, a digital intermediate frequency fine calibration lookup table, and a digital intermediate frequency gain value lookup table. The analog RF coarse calibration lookup table stores analog RF DC calibration codes, which are related to the RF gain level and the RF local oscillator frequency. The analog IF coarse calibration lookup table stores analog IF DC calibration codes, the RF gain level, and DC voltage calibration accuracy control codes, which are related to the analog IF gain. The digital RF fine calibration lookup table stores digital RF DC calibration codes, which are related to the RF gain level and the RF local oscillator frequency. The digital IF fine calibration lookup table stores digital IF DC calibration codes, the RF gain level, and the IF gain level, which are related to the analog IF gain. The digital IF gain value lookup table stores IF gain values, which are related to the IF gain level.

2. The DC offset correction circuit based on a lookup table according to claim 1, characterized in that, The analog coarse correction module includes a digital adder, a digital-to-analog converter (DAC), and an analog subtractor. The first input of the analog subtractor is connected to the output of the mixer, the second input of the analog subtractor is connected to the output of the DAC, and the output of the analog subtractor is connected to the input of the analog filter. The first input of the DAC is connected to the output of the digital adder, and the second input of the DAC is connected to the storage module. The storage module outputs to the DAC the DC voltage correction accuracy control code obtained from the analog intermediate frequency coarse correction lookup table based on the analog total gain index, which is related to the unit DC voltage correction value. The first input terminal of the digital adder is connected to the storage module. The storage module outputs the analog RF DC correction code obtained from the analog RF coarse correction lookup table based on the RF gain level and the RF local oscillator frequency index to the first input terminal of the digital adder. The second input terminal of the digital adder is connected to the storage module. The storage module outputs the analog intermediate frequency DC correction code related to the intermediate frequency gain level obtained from the analog total gain index to the second input terminal of the digital adder.

3. The DC offset correction circuit based on a lookup table according to claim 1, characterized in that, The digital fine-correction module includes a digital multiplier, a digital adder, and a digital subtractor. The first input of the digital subtractor is connected to the output of the digital filter, the second input of the digital subtractor is connected to the output of the digital adder, and the output of the digital subtractor is connected to the post-processor. The first input of the digital adder is connected to the output of the digital multiplier, and the first input of the digital multiplier is connected to the storage module. The storage module outputs the intermediate frequency gain value obtained from the digital intermediate frequency gain value lookup table based on the intermediate frequency gain level index to the digital multiplier. The second input of the digital multiplier is connected to the storage module, and the storage module outputs the digital radio frequency (RF) DC correction code obtained from the digital RF fine-correction lookup table based on the RF gain level and the RF local oscillator frequency index to the digital multiplier. The second input of the digital adder is connected to the storage module, and the storage module outputs the digital RF DC correction code related to the RF gain level obtained from the digital RF fine-correction lookup table based on the analog total gain index to the digital adder.

4. A zero-IF receiver, the zero-IF receiver comprising two receiving channels, characterized in that, The zero-IF receiver further includes a lookup table-based DC offset correction circuit as described in any one of claims 1-3. The lookup table-based DC offset correction circuit includes one of the storage modules, two of the analog coarse correction modules, and two of the digital fine correction modules. Each of the receiving channels is provided with one of the analog coarse correction modules and one of the digital fine correction modules.

5. A DC offset correction method based on a lookup table, applied to the zero-IF receiver as described in claim 4, characterized in that, The method includes: For the receiving channel, the analog coarse correction lookup table in the storage module is indexed to obtain and input the correction code in the analog coarse correction lookup table into the analog coarse correction module, and the analog coarse correction module performs analog coarse correction on the DC offset in the analog signal. For the receiving channel, the digital fine correction lookup table in the storage module is indexed to obtain and input the correction code in the digital fine correction lookup table into the digital fine correction module, and the DC offset in the digital signal is digitally fine corrected by the digital fine correction module.

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