Cryptogram processing method, cryptogram processing device, electronic device, and storage medium

Abstract

The present application provides a ciphertext processing method, comprising: performing redundancy encoding on a first initial plaintext and a second initial plaintext to obtain a first plaintext and a second plaintext, wherein the first plaintext is represented as a difference between a first non-redundant plaintext and a second non-redundant plaintext, and the second plaintext is represented as a difference between a third non-redundant plaintext and a fourth non-redundant plaintext; performing homomorphic encryption on the first non-redundant plaintext, the second non-redundant plaintext, the third non-redundant plaintext and the fourth non-redundant plaintext respectively to obtain a first ciphertext, a second ciphertext, a third ciphertext and a fourth ciphertext; and performing a ciphertext operation on the first ciphertext, the second ciphertext, the third ciphertext and the fourth ciphertext to obtain a ciphertext operation result. In addition, the present application also provides a ciphertext processing device, an electronic device, a readable storage medium and a computer program product.

Description

Technical Field

[0001] This invention relates to the field of computer technology / encryption algorithm technology, and more specifically, to a ciphertext processing method, a ciphertext processing device, an electronic device, a readable storage medium, and a computer program product. Background Technology

[0002] Cryptography is the technical science that studies the creation and decryption of codes. Cryptographic algorithms have wide applications in information security and other scenarios, including but not limited to privacy protection and fraud prevention. Homomorphic encryption is an important research direction in cryptography, allowing users to directly manipulate homomorphically encrypted data without decryption.

[0003] In the process of realizing the concept of this invention, the inventors discovered that in related technologies, directly performing ciphertext operations on homomorphically encrypted data requires a large amount of computing resources, and the efficiency of the operation is low. Summary of the Invention

[0004] In view of the above, the present invention provides a method for ciphertext processing, a device for ciphertext processing, an electronic device, a readable storage medium, and a computer program product.

[0005] One aspect of the present invention provides a ciphertext processing method, comprising: performing redundancy encoding on a first initial plaintext and a second initial plaintext to obtain a first plaintext and a second plaintext, wherein the first plaintext is represented as the difference between a first non-redundant plaintext and a second non-redundant plaintext, and the second plaintext is represented as the difference between a third non-redundant plaintext and a fourth non-redundant plaintext; performing homomorphic encryption on the first non-redundant plaintext, the second non-redundant plaintext, the third non-redundant plaintext, and the fourth non-redundant plaintext respectively to obtain a first ciphertext, a second ciphertext, a third ciphertext, and a fourth ciphertext; and performing ciphertext operations on the first ciphertext, the second ciphertext, the third ciphertext, and the fourth ciphertext to obtain a ciphertext operation result.

[0006] According to an embodiment of the present invention, the above-mentioned ciphertext operation includes ciphertext integer addition; wherein, the above-mentioned ciphertext operation on the first ciphertext, the second ciphertext, the third ciphertext, and the fourth ciphertext to obtain the ciphertext operation result includes: determining a first intermediate carry and a first intermediate sum based on the first ciphertext, the second ciphertext, and the third ciphertext; determining a second intermediate carry and a second intermediate sum based on the first intermediate carry, the first intermediate sum, and the fourth ciphertext; and obtaining the ciphertext operation result based on the second intermediate carry and the second intermediate sum.

[0007] According to an embodiment of the present invention, determining the first intermediate carry and the first intermediate sum based on the first ciphertext, the second ciphertext, and the third ciphertext includes: determining the first intermediate carry and the first intermediate sum using Equation 1:

[0008]

[0009] in, This indicates a homomorphic addition operation, equivalent to the logical "OR" operation in plaintext; This represents the homomorphic multiplication operation, which is equivalent to the logical AND operation in plaintext; This represents the i-th bit of the first intermediate carry-in mentioned above; This represents the i-th bit of the first ciphertext mentioned above; This represents the i-th bit of the aforementioned third ciphertext; This represents the i-th bit of the second ciphertext mentioned above; This indicates the NOT of the i-th bit in the second ciphertext mentioned above; This represents the i-th position of the first intermediate sum mentioned above.

[0010] According to an embodiment of the present invention, determining the second intermediate carry and the second intermediate sum based on the first intermediate carry, the first intermediate sum, and the fourth ciphertext includes: determining the second intermediate carry and the second intermediate sum using Equation 2:

[0011]

[0012] in, This represents the i-th bit of the second intermediate carry mentioned above; This represents the i-th bit of the fourth ciphertext mentioned above; This indicates the NOT of the (i-1)th bit of the first intermediate carry mentioned above; This represents the i-th position of the second intermediate sum mentioned above.

[0013] According to an embodiment of the present invention, the method further includes: performing single instruction multiple data encoding on the first ciphertext, the second ciphertext, the third ciphertext, and the fourth ciphertext respectively to obtain a first encoded ciphertext, a second encoded ciphertext, a third encoded ciphertext, and a fourth encoded ciphertext; and performing ciphertext operation on the first encoded ciphertext, the second encoded ciphertext, the third encoded ciphertext, and the fourth encoded ciphertext to obtain the ciphertext operation result.

[0014] According to an embodiment of the present invention, the above-mentioned ciphertext operation includes ciphertext integer addition; wherein, the above-mentioned ciphertext operation on the first coded ciphertext, the second coded ciphertext, the third coded ciphertext, and the fourth coded ciphertext to obtain the above-mentioned ciphertext operation result includes: determining a third intermediate carry and a third intermediate sum based on the first coded ciphertext, the second coded ciphertext, and the third coded ciphertext; determining a fourth intermediate carry and a fourth intermediate sum based on the third intermediate carry, the third intermediate sum, and the fourth coded ciphertext; and obtaining the above-mentioned ciphertext operation result based on the fourth intermediate carry and the fourth intermediate sum.

[0015] According to an embodiment of the present invention, determining the third intermediate carry and the third intermediate sum based on the first encoded ciphertext, the second encoded ciphertext, and the third encoded ciphertext includes: obtaining the third intermediate carry and the third intermediate sum using Equation 3:

[0016]

[0017] Among them, T i + This represents the i-th bit of the third intermediate carry mentioned above; Y represents the i-th bit of the first encoded ciphertext mentioned above; i + This represents the i-th bit of the third encoded ciphertext mentioned above; This represents the i-th bit of the second encoded ciphertext mentioned above; This represents the NOT of the i-th bit of the second encoded ciphertext mentioned above; This represents the i-th position of the third intermediate sum mentioned above.

[0018] According to an embodiment of the present invention, determining the fourth intermediate carry and the fourth intermediate sum based on the third intermediate carry, the third intermediate sum, and the fourth encoded ciphertext includes: obtaining the fourth intermediate carry and the fourth intermediate sum using Equation 4:

[0019]

[0020] in, Y represents the i-th bit of the fourth intermediate carry mentioned above; i - This represents the i-th bit of the fourth encoded ciphertext mentioned above; (T) i + ) 1 This indicates the i-th bit after shifting the third intermediate carry one bit higher; This represents the i-th position of the fourth intermediate sum mentioned above.

[0021] Another aspect of the present invention provides a ciphertext processing apparatus, comprising a first encoding module, an encryption module, and a first processing module. The first encoding module is used to perform redundant encoding on a first initial plaintext and a second initial plaintext to obtain a first plaintext and a second plaintext, wherein the first plaintext is represented as the difference between a first non-redundant plaintext and a second non-redundant plaintext, and the second plaintext is represented as the difference between a third non-redundant plaintext and a fourth non-redundant plaintext; the encryption module is used to perform homomorphic encryption on the first non-redundant plaintext, the second non-redundant plaintext, the third non-redundant plaintext, and the fourth non-redundant plaintext, respectively, to obtain a first ciphertext, a second ciphertext, a third ciphertext, and a fourth ciphertext; and the first processing module is used to perform ciphertext operations on the first ciphertext, the second ciphertext, the third ciphertext, and the fourth ciphertext to obtain a ciphertext operation result.

[0022] Another aspect of the present invention provides an electronic device, comprising: one or more processors; and a memory for storing one or more instructions, wherein, when the one or more instructions are executed by the one or more processors, the one or more processors cause the one or more processors to perform the method as described above.

[0023] Another aspect of the present invention provides a computer-readable storage medium storing computer-executable instructions, which, when executed, are used to implement the method described above.

[0024] Another aspect of the present invention provides a computer program product comprising computer-executable instructions which, when executed, are used to implement the method described above.

[0025] According to embodiments of the present invention, before performing ciphertext operations, two initial plaintexts can be redundantly encoded. Each redundantly encoded plaintext can be represented as the difference between two non-redundant plaintexts. Then, four non-redundant plaintexts are homomorphically encrypted, and ciphertext operations are performed on the four homomorphically encrypted ciphertexts. Compared to the technical solution of directly homomorphically encrypting the initial plaintexts and then performing ciphertext operations on the homomorphically encrypted ciphertexts, this method at least partially overcomes the technical problems of low efficiency and high computational resource consumption in ciphertext operations, effectively reducing the computational overhead of ciphertext operations and improving the efficiency of the operations. Attached Figure Description

[0026] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0027] Figure 1 A flowchart illustrating a ciphertext processing method according to an embodiment of the present invention is shown schematically.

[0028] Figure 2 The diagram illustrates the algorithm structure of the ciphertext addition operation according to an embodiment of the present invention.

[0029] Figure 3 A flowchart illustrating a ciphertext processing method according to another embodiment of the present invention is shown.

[0030] Figure 4 The diagram illustrates the algorithm structure of a ciphertext addition operation according to another embodiment of the present invention.

[0031] Figure 5 A block diagram of a ciphertext processing apparatus according to an embodiment of the present invention is shown schematically.

[0032] Figure 6 A block diagram of an electronic device suitable for implementing a ciphertext processing method according to an embodiment of the present invention is shown schematically. Detailed Implementation

[0033] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the invention for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0035] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0036] When using expressions such as "at least one of A, B, and C," the expression should generally be interpreted in accordance with the meaning commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.). Similarly, when using expressions such as "at least one of A, B, or C," the expression should generally be interpreted in accordance with the meaning commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, or C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).

[0037] Finite-level fully homomorphic encryption (LFHE) is an important component of the fully homomorphic encryption system and a significant scheme for implementing fully homomorphic encryption. Currently, commonly used finite-level fully homomorphic encryption schemes include BV11, BFV12 (FV12), BGV12, Bra12, and CKKS17.

[0038] For ciphertext generated by homomorphic encryption, the ciphertext algorithm and the plaintext algorithm follow the same logical rules; however, the ciphertext algorithm is more complex in its underlying implementation. The ciphertext algorithm requires a series of complex operations to obtain the same computational result as the plaintext algorithm. Under radix-2 encoding, they follow the same Boolean logic. The logical "OR" operation in the plaintext (represented as "+") is equivalent to the homomorphic addition operation in the ciphertext (represented as...). The logical AND operation in plaintext (represented as "×") is equivalent to the homomorphic multiplication operation in ciphertext (represented as...). ).

[0039] Therefore, in a homomorphic encryption system, the logical rules for implementing the radix-2 ciphertext integer algorithm are consistent with those in the plaintext state, and the radix-2 integer algorithm in the plaintext state can be directly ported to the homomorphic encryption system. In a finite-level fully homomorphic encryption scheme, as long as the circuit depth does not exceed the upper limit L, arbitrary homomorphic addition and homomorphic multiplication operations can be performed on the ciphertext, and there is no limit to the number of operations.

[0040] However, when using bit encoding to construct complex radix-2 arithmetic operations, the presence of lengthy carry chains in addition results in a circuit depth that increases dramatically with the bit width, leading to a sharp increase in computational overhead. Typically, to compute complex radix-2 arithmetic operations, those skilled in the art often increase the upper limit of the circuit depth that the scheme can support, but this also increases various parameters of the scheme, significantly reducing computational efficiency.

[0041] In view of this, embodiments of the present invention provide a method for accelerating finite-level fully homomorphic radix-2 arithmetic operations based on redundant encoding by combining the characteristics of finite-level fully homomorphic encryption and the encoding method of redundant binary number systems. This method implements a redundant carry-free algorithm under a finite-level fully homomorphic encryption scheme, thereby achieving a linear increase in circuit depth and computational overhead with increasing bit width. Compared to algorithms such as CLA in related technologies, the method of the present invention exhibits a slower increase in circuit depth and computational overhead. Furthermore, embodiments of the present invention also combine Single Instruction Multiple Data (SIMD) encoding with the above method, transforming the computational overhead into a constant value, further reducing computational overhead and improving computational efficiency.

[0042] Specifically, embodiments of the present invention provide a ciphertext processing method, a ciphertext processing apparatus, an electronic device, a readable storage medium, and a computer program product. The method includes: performing redundant encoding on a first initial plaintext and a second initial plaintext to obtain a first plaintext and a second plaintext, wherein the first plaintext is represented as the difference between a first non-redundant plaintext and a second non-redundant plaintext, and the second plaintext is represented as the difference between a third non-redundant plaintext and a fourth non-redundant plaintext; performing homomorphic encryption on the first non-redundant plaintext, the second non-redundant plaintext, the third non-redundant plaintext, and the fourth non-redundant plaintext respectively to obtain a first ciphertext, a second ciphertext, a third ciphertext, and a fourth ciphertext; and performing ciphertext operations on the first ciphertext, the second ciphertext, the third ciphertext, and the fourth ciphertext to obtain a ciphertext operation result.

[0043] Figure 1 A flowchart illustrating a ciphertext processing method according to an embodiment of the present invention is shown schematically.

[0044] like Figure 1 As shown, the method includes operations S101 to S103.

[0045] In operation S101, the first initial plaintext and the second initial plaintext are redundantly encoded to obtain the first plaintext and the second plaintext. The first plaintext is represented as the difference between the first non-redundant plaintext and the second non-redundant plaintext, and the second plaintext is represented as the difference between the third non-redundant plaintext and the fourth non-redundant plaintext.

[0046] In operation S102, homomorphic encryption is performed on the first non-redundant plaintext, the second non-redundant plaintext, the third non-redundant plaintext, and the fourth non-redundant plaintext respectively to obtain the first ciphertext, the second ciphertext, the third ciphertext, and the fourth ciphertext.

[0047] In operation S103, ciphertext operations are performed on the first ciphertext, the second ciphertext, the third ciphertext, and the fourth ciphertext to obtain the ciphertext operation results.

[0048] According to an embodiment of the present invention, the first initial plaintext and the second initial plaintext can be binary number sequences, or the first initial plaintext and the second initial plaintext can be converted into binary number sequences by a decoding method.

[0049] According to embodiments of the present invention, the redundancy coding may be, for example, redundant binary coding.

[0050] According to embodiments of the present invention, the first plaintext may correspond to multiple sets of first non-redundant plaintext and second non-redundant plaintext, and the second plaintext may correspond to multiple sets of third non-redundant plaintext and fourth non-redundant plaintext. Taking the first plaintext as an example, assume that the set of redundant encoded numbers used is... Representing "-1"; the first plaintext obtained by encoding can be The corresponding first non-redundant plaintext and second non-redundant plaintext can be 1010 and 0101, or 1100 and 0111, or 10101 and 10000, etc.

[0051] According to embodiments of the present invention, homomorphic encryption can employ any finite-level homomorphic encryption method.

[0052] According to embodiments of the present invention, ciphertext operations include ciphertext addition, ciphertext multiplication, comparison judgment, equality circuits, etc.

[0053] According to embodiments of the present invention, ciphertext operations can correspond to binary number logic operations in plaintext state. For example, ciphertext addition corresponds to binary number addition, ciphertext multiplication corresponds to binary number multiplication, and so on.

[0054] According to embodiments of the present invention, ciphertext operations can be implemented by performing any number of homomorphic addition and homomorphic multiplication operations between ciphertexts.

[0055] According to embodiments of the present invention, before performing ciphertext operations, two initial plaintexts can be redundantly encoded. Each redundantly encoded plaintext can be represented as the difference between two non-redundant plaintexts. Then, four non-redundant plaintexts are homomorphically encrypted, and ciphertext operations are performed on the four homomorphically encrypted ciphertexts. Compared to the technical solution of directly homomorphically encrypting the initial plaintexts and then performing ciphertext operations on the homomorphically encrypted ciphertexts, this method at least partially overcomes the technical problems of low efficiency and high computational resource consumption in ciphertext operations, effectively reducing the computational overhead of ciphertext operations and improving the efficiency of the operations.

[0056] The following is for reference. Figure 2 Taking ciphertext addition as an example in ciphertext arithmetic operations, for... Figure 1 The method shown will be further explained.

[0057] According to an embodiment of the present invention, a digital set is used as The redundancy coding method performs redundancy coding on the first initial plaintext and the second initial plaintext to obtain the first plaintext. Second plaintext As shown in formulas (1) and (2) respectively:

[0058]

[0059]

[0060] in, and The value can be Any one of them, It represents -1.

[0061] According to an embodiment of the present invention, the first plaintext Second plaintext Both can be expressed as the difference between two non-redundant numbers, as shown in formulas (3) and (4):

[0062]

[0063]

[0064] in, This represents the first non-redundant plaintext. This represents the second non-redundant plaintext. This represents the third non-redundant plaintext. This indicates the fourth non-redundant plaintext.

[0065] Homomorphic encryption of the first, second, third, and fourth non-redundant plaintexts respectively yields the first ciphertext x. + Second ciphertext x - Third ciphertext y + and the fourth ciphertext y - .

[0066] In an embodiment of the present invention, the result of redundant addition without carry on the first plaintext and the second plaintext is s. Combining formulas (1) to (4), the result s can be expressed as shown in formula (5):

[0067]

[0068] in, This represents the i-th bit of the first ciphertext. This represents the i-th bit of the second ciphertext. This represents the i-th bit of the third ciphertext. This represents the i-th bit of the fourth ciphertext.

[0069] Figure 2 The diagram illustrates the algorithm structure of the ciphertext addition operation according to an embodiment of the present invention.

[0070] like Figure 2 As shown, in the encrypted addition operation process shown in formula (5) of this embodiment of the invention, It can break down the addition-plus-minus process (Plus-Plus-Minus, PPM) and the subtraction-subtraction-addition process (Minus-Minus-Plus, MMP).

[0071] The addition and subtraction process can be based on the first, second, and third ciphertexts to determine the first intermediate carry and the first intermediate sum. This is equivalent to calculating the first three terms. Its value range is {-1, 0, 1, 2}, which is consistent with the expression The range of values ​​is the same. The addition and subtraction process can be shown in formula (6):

[0072]

[0073] in, This represents the i-th digit of the first carry-over. This indicates the NOT of the i-th bit in the second ciphertext; This represents the i-th position of the first middle element.

[0074] According to an embodiment of the present invention, the "NOT" of the i-th bit of the second ciphertext can be obtained, for example, by... To achieve this, ct1 represents the ciphertext of the binary number "1", and the implementation of the "NOT" of the i-th bit of the second ciphertext is not limited to this.

[0075] The subtraction-addition process can determine the second intermediate carry and the second intermediate sum based on the first intermediate carry, the first intermediate sum, and the fourth ciphertext. This is equivalent to calculating... The expression takes values ​​in the range {-2, -1, 0, 1}, which is consistent with the expression... The range of values ​​is the same. The subtraction and addition process can be shown in formula (7):

[0076]

[0077] in, This represents the i-th digit of the second carry-over. This represents the NOT of the (i-1)th bit in the first carry-in. This represents the i-th position of the second middle sum.

[0078] According to an embodiment of the present invention, the implementation of both the addition-addition process and the subtraction-addition process requires 2 homomorphic multiplication operations and 5 homomorphic addition operations. Therefore, the circuit depth required for ciphertext addition operation is 2n, where n represents the bit width of the operand.

[0079] According to an embodiment of the present invention, after obtaining the second intermediate carry and the second intermediate sum, the calculation result s can be expressed as follows:

[0080] According to embodiments of the present invention, u can be respectively + and t - Decryption is performed to obtain the result of redundant, carry-free addition of the first and second plaintexts.

[0081] According to embodiments of the present invention, by employing redundant coding, the computational overhead of ciphertext addition operations between ciphertexts is reduced to an integer multiple of the bit width, effectively reducing computational overhead and improving computational efficiency. For example, when performing ciphertext addition operations on 512-bit ciphertexts, compared to related technologies that do not use redundant coding (e.g., CLA), the computational speed of the technical solution of the present invention is about 7 times faster, while the memory usage is only about 15% of that of CLA.

[0082] Figure 3 A flowchart illustrating a ciphertext processing method according to another embodiment of the present invention is shown.

[0083] like Figure 3 As shown, the method includes operations S301 to S304.

[0084] In operation S301, the first initial plaintext and the second initial plaintext are redundantly encoded to obtain the first plaintext and the second plaintext. The first plaintext is represented as the difference between the first non-redundant plaintext and the second non-redundant plaintext, and the second plaintext is represented as the difference between the third non-redundant plaintext and the fourth non-redundant plaintext.

[0085] In operation S302, homomorphic encryption is performed on the first non-redundant plaintext, the second non-redundant plaintext, the third non-redundant plaintext, and the fourth non-redundant plaintext respectively to obtain the first ciphertext, the second ciphertext, the third ciphertext, and the fourth ciphertext.

[0086] In operation S303, the first ciphertext, the second ciphertext, the third ciphertext, and the fourth ciphertext are encoded using single instruction multiple data, respectively, to obtain the first encoded ciphertext, the second encoded ciphertext, the third encoded ciphertext, and the fourth encoded ciphertext.

[0087] In operation S304, ciphertext operations are performed on the first ciphertext, the second ciphertext, the third ciphertext, and the fourth ciphertext to obtain the ciphertext operation result.

[0088] According to embodiments of the present invention, Single Instruction Multiple Data (SIMD) encoding can operate on data in multiple SIMD data slots simultaneously to achieve formal parallel computing.

[0089] According to embodiments of the present invention, ciphertext operations performed on the SIMD-encoded ciphertext can be implemented by multiple SIMD operations.

[0090] According to embodiments of the present invention, SIMD operations include SIMD homomorphic addition, SIMD homomorphic multiplication, and SIMD shift operations. The SIMD homomorphic addition and multiplication operations correspond to the homomorphic addition and multiplication operations described above. A SIMD operation is equivalent to performing a homomorphic operation on the data in all SIMD data slots simultaneously. The SIMD shift operation can shift data in the data slots, including but not limited to cyclic shift and ordinary shift operations.

[0091] According to embodiments of the present invention, combining redundancy coding and SIMD coding methods results in a ciphertext processing method that can achieve constant circuit depth and constant computational overhead.

[0092] The following is for reference. Figure 4 Taking ciphertext addition as an example in ciphertext arithmetic operations, for... Figure 3 The method shown will be further explained.

[0093] According to an embodiment of the present invention, operations S301 to S302 can be implemented according to the method of operations S101 to S102 and formulas (1) to (4), which will not be repeated here.

[0094] According to embodiments of the present invention, SIMD encoding can encode multiple bits of ciphertext into a single SIMD data. Taking a ciphertext with a bit width of 4 as an example, the first ciphertext x is encoded into... + Second ciphertext x - Third ciphertext y + and the fourth ciphertext y - Perform single instruction multiple data encoding to obtain the first encoded ciphertext X. + Second coded ciphertext X - Third-level ciphertext Y + and the fourth encoded ciphertext Y - As shown in Table 1.

[0095] Table 1

[0096]

[0097] The result of the redundant carry-free addition operation based on SIMD can be shown in Equation (8):

[0098] Rcfasimd(X+ X - Y + Y - )={S + -S -} (8)

[0099] Figure 4 The diagram illustrates the algorithm structure of a ciphertext addition operation according to another embodiment of the present invention.

[0100] like Figure 4 As shown, similar to the ciphertext addition operation performed on the ciphertext before SIMD encoding, the ciphertext addition operation between ciphertexts after SIMD encoding can also be decomposed into an addition-plus-subtraction process and a subtraction-subtraction-plus process.

[0101] The addition and subtraction process can be based on the first coded ciphertext, the second coded ciphertext, and the third coded ciphertext to determine the third intermediate carry and the third intermediate sum, as shown in formula (9):

[0102]

[0103] Among them, T i + This represents the i-th digit of the third carry-in. Y represents the i-th bit of the first encoded ciphertext; i + This represents the i-th bit of the third encoded ciphertext; This represents the i-th bit of the second encoded ciphertext; This represents the NOT of the i-th bit of the second encoded ciphertext; This represents the i-th position of the third middle element.

[0104] The subtraction and addition process can be based on the above-mentioned third intermediate carry, the above-mentioned third intermediate sum and the above-mentioned fourth encoded ciphertext to determine the fourth intermediate carry and the fourth intermediate sum, as shown in formula (10):

[0105]

[0106] Among them, T i - Y represents the i-th digit of the fourth carry-in; i - This represents the i-th bit of the fourth encoded ciphertext; (T i + ) 1 This indicates the i-th bit after shifting the third carry one bit higher; U i + This represents the i-th element of the fourth middle element.

[0107] According to an embodiment of the present invention, the result of the SIMD-based redundant carry-free addition operation represented by formula (8) can be obtained from formula (11):

[0108]

[0109] Among them, (T) i - ) 1 This indicates the i-th bit after shifting the fourth middle bit one bit higher.

[0110] According to an embodiment of the present invention, after combining SIMD encoding, the calculation of the addition-addition and subtraction processes is equivalent to operating on only one bit. Therefore, the addition-addition and subtraction processes only require two SIMD homomorphic multiplication operations and five SIMD homomorphic addition operations. In addition, the two SIMD homomorphic shift operations introduce an extra 0.5 circuit depth, and the ciphertext addition operation consumes a total of 2.5 circuit depths, which is independent of the bit width of the ciphertext.

[0111] According to embodiments of the present invention, by employing redundancy coding and SIMD coding, the computational overhead of ciphertext addition becomes a constant value, further reducing computational overhead and improving computational efficiency. For example, when performing ciphertext addition on 512-bit wide ciphertext, compared to related technologies that do not use redundancy coding (e.g., CLA), the computation speed of another embodiment of the present invention is nearly 4000 times faster, the content occupancy is only about 1% of that of CLA, and after SIMD coding, the space occupied by the ciphertext is also reduced to about 1 / 3 of the original.

[0112] Figure 5 A block diagram of a ciphertext processing apparatus according to an embodiment of the present invention is shown schematically.

[0113] like Figure 5 As shown, the ciphertext processing device includes a first encoding module 510, an encryption module 520, and a first processing module 530.

[0114] The first encoding module 510 is used to perform redundant encoding on the first initial plaintext and the second initial plaintext to obtain the first plaintext and the second plaintext, wherein the first plaintext is represented as the difference between the first non-redundant plaintext and the second non-redundant plaintext, and the second plaintext is represented as the difference between the third non-redundant plaintext and the fourth non-redundant plaintext.

[0115] The encryption module 520 is used to perform homomorphic encryption on the first non-redundant plaintext, the second non-redundant plaintext, the third non-redundant plaintext, and the fourth non-redundant plaintext respectively to obtain the first ciphertext, the second ciphertext, the third ciphertext, and the fourth ciphertext.

[0116] The first processing module 530 is used to perform ciphertext operations on the first ciphertext, the second ciphertext, the third ciphertext, and the fourth ciphertext to obtain the ciphertext operation results.

[0117] According to an embodiment of the present invention, the ciphertext operation includes ciphertext integer addition. The first processing module 530 includes a first processing unit, a second processing unit, and a third processing unit.

[0118] The first processing unit is used to determine the first intermediate carry and the first intermediate sum based on the first ciphertext, the second ciphertext, and the third ciphertext.

[0119] The second processing unit is used to determine the second intermediate carry and the second intermediate sum based on the first intermediate carry, the first intermediate sum, and the fourth ciphertext.

[0120] The third processing unit is used to obtain the ciphertext operation result based on the second intermediate carry and the second intermediate sum.

[0121] According to an embodiment of the present invention, the device further includes a second encoding module and a second processing module.

[0122] The second encoding module is used to perform single instruction multiple data encoding on the first ciphertext, the second ciphertext, the third ciphertext, and the fourth ciphertext respectively to obtain the first encoded ciphertext, the second encoded ciphertext, the third encoded ciphertext, and the fourth encoded ciphertext.

[0123] The second processing module is used to perform ciphertext operations on the first ciphertext, the second ciphertext, the third ciphertext, and the fourth ciphertext to obtain the ciphertext operation results.

[0124] According to an embodiment of the present invention, the ciphertext operation includes ciphertext integer addition. The second processing module includes a fourth processing unit, a fifth processing unit, and a sixth processing unit.

[0125] The fourth processing unit is used to determine the third intermediate carry and the third intermediate sum based on the first coded ciphertext, the second coded ciphertext, and the third coded ciphertext.

[0126] The fifth processing unit is used to determine the fourth intermediate carry and the fourth intermediate sum based on the third intermediate carry, the third intermediate sum, and the fourth encoded ciphertext.

[0127] The sixth processing unit is used to obtain the ciphertext operation result based on the fourth intermediate carry and the fourth intermediate sum.

[0128] Any one or more of the modules, submodules, units, and subunits according to embodiments of the present invention, or at least part of the functions of any one or more of them, can be implemented in a single module. Any one or more of the modules, submodules, units, and subunits according to embodiments of the present invention can be implemented by being divided into multiple modules. Any one or more of the modules, submodules, units, and subunits according to embodiments of the present invention can be at least partially implemented as hardware circuits, such as field-programmable gate arrays (FPGAs), programmable logic arrays (PLAs), systems-on-a-chip, systems-on-a-substrate, systems-on-package, application-specific integrated circuits (ASICs), or implemented in hardware or firmware by any other reasonable means of integrating or packaging circuits, or implemented in software, hardware, and firmware, or in any suitable combination of any of these three implementation methods. Alternatively, one or more of the modules, submodules, units, and subunits according to embodiments of the present invention can be at least partially implemented as computer program modules, which, when run, can perform corresponding functions.

[0129] For example, any plurality of the first encoding module 510, encryption module 520, and first processing module 530 can be combined into one module / unit / subunit, or any one of these modules / units / subunits can be split into multiple modules / units / subunits. Alternatively, at least part of the functionality of one or more of these modules / units / subunits can be combined with at least part of the functionality of other modules / units / subunits and implemented in one module / unit / subunit. According to embodiments of the present invention, at least one of the first encoding module 510, encryption module 520, and first processing module 530 can be at least partially implemented as hardware circuitry, such as a field-programmable gate array (FPGA), a programmable logic array (PLA), a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit (ASIC), or implemented in hardware or firmware by any other reasonable means of integrating or packaging the circuitry, or implemented in software, hardware, or firmware, or in any suitable combination of any of these three implementation methods. Alternatively, at least one of the first encoding module 510, encryption module 520, and first processing module 530 may be implemented at least partially as a computer program module, which can perform corresponding functions when the computer program module is run.

[0130] It should be noted that the encrypted text processing device part in the embodiments of the present invention corresponds to the encrypted text processing method part in the embodiments of the present invention. The description of the encrypted text processing device part is specifically referred to in the encrypted text processing method part, and will not be repeated here.

[0131] Figure 6A block diagram of an electronic device suitable for implementing a ciphertext processing method according to an embodiment of the present invention is shown schematically. Figure 6 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present invention.

[0132] like Figure 6 As shown, a computer electronic device 600 according to an embodiment of the present invention includes a processor 601, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 602 or a program loaded from a storage portion 608 into a random access memory (RAM) 603. The processor 601 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 601 may also include onboard memory for caching purposes. The processor 601 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present invention.

[0133] RAM 603 stores various programs and data required for the operation of electronic device 600. Processor 601, ROM 602, and RAM 603 are interconnected via bus 604. Processor 601 executes various operations of the method flow according to embodiments of the present invention by executing programs in ROM 602 and / or RAM 603. It should be noted that the programs may also be stored in one or more memories other than ROM 602 and RAM 603. Processor 601 may also execute various operations of the method flow according to embodiments of the present invention by executing programs stored in said one or more memories.

[0134] According to an embodiment of the present invention, the electronic device 600 may further include an input / output (I / O) interface 605, which is also connected to a bus 604. The electronic device 600 may also include one or more of the following components connected to the I / O interface 605: an input section 606 including a keyboard, mouse, etc.; an output section 607 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 608 including a hard disk, etc.; and a communication section 609 including a network interface card such as a LAN card, modem, etc. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to the I / O interface 605 as needed. A removable medium 611, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 610 as needed so that computer programs read from it can be installed into the storage section 608 as needed.

[0135] According to embodiments of the present invention, the method flow according to embodiments of the present invention can be implemented as a computer software program. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a computer-readable storage medium, the computer program containing program code for performing the method shown in the flowchart. In such embodiments, the computer program can be downloaded and installed from a network via communication section 609, and / or installed from removable medium 611. When the computer program is executed by processor 601, it performs the functions defined in the system of the embodiments of the present invention. According to embodiments of the present invention, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0136] The present invention also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of the present invention.

[0137] According to embodiments of the present invention, a computer-readable storage medium may be a non-volatile computer-readable storage medium. Examples include, but are not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this invention, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0138] For example, according to embodiments of the present invention, a computer-readable storage medium may include the ROM 602 and / or RAM 603 described above and / or one or more memories other than ROM 602 and RAM 603.

[0139] Embodiments of the present invention also include a computer program product comprising a computer program containing program code for performing the methods provided in the embodiments of the present invention. When the computer program product is run on an electronic device, the program code is used to enable the electronic device to implement the encrypted processing method provided in the embodiments of the present invention.

[0140] When the computer program is executed by the processor 601, it performs the functions defined in the system / apparatus of this embodiment of the invention. According to embodiments of the invention, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0141] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and downloaded and installed via the communication section 609, and / or installed from the removable medium 611. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0142] According to embodiments of the present invention, program code for executing the computer programs provided in the embodiments of the present invention can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0143] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions. Those skilled in the art will understand that the features recited in the various embodiments and / or claims of the present invention can be combined and / or combined in various ways, even if such combinations or combinations are not expressly stated in the present invention. In particular, the features described in the various embodiments and / or claims of this invention can be combined and / or combined in various ways without departing from the spirit and teachings of this invention. All such combinations and / or combinations fall within the scope of this invention.

[0144] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A method for processing encrypted text, comprising: Redundancy coding is performed on the first initial plaintext and the second initial plaintext to obtain the first plaintext and the second plaintext. The first plaintext is represented as the difference between the first non-redundant plaintext and the second non-redundant plaintext, and the second plaintext is represented as the difference between the third non-redundant plaintext and the fourth non-redundant plaintext. The redundancy coding includes binary coding based on the set of numbers of the redundancy coding. The first non-redundant plaintext, the second non-redundant plaintext, the third non-redundant plaintext, and the fourth non-redundant plaintext are all represented as binary numbers. Homomorphic encryption is performed on the first non-redundant plaintext, the second non-redundant plaintext, the third non-redundant plaintext, and the fourth non-redundant plaintext, respectively, to obtain the first ciphertext, the second ciphertext, the third ciphertext, and the fourth ciphertext; and Ciphertext operations are performed on the first ciphertext, the second ciphertext, the third ciphertext, and the fourth ciphertext to obtain ciphertext operation results. The ciphertext operation includes ciphertext addition, ciphertext multiplication, comparison judgment, and equality circuit. When the ciphertext operation includes the ciphertext addition, the ciphertext operation is performed on the first ciphertext, the second ciphertext, the third ciphertext, and the fourth ciphertext to obtain the ciphertext operation result, including: Based on the first ciphertext, the second ciphertext, and the third ciphertext, determine the first intermediate carry and the first intermediate sum; Based on the first intermediate carry, the first intermediate sum, and the fourth ciphertext, determine the second intermediate carry and the second intermediate sum; and The ciphertext operation result is obtained based on the second intermediate carry and the second intermediate sum.

2. The method according to claim 1, wherein, The step of determining the first intermediate carry and the first intermediate sum based on the first ciphertext, the second ciphertext, and the third ciphertext includes: The first intermediate carry and the first intermediate sum are determined using Equation 1: in, This indicates a homomorphic addition operation, which is equivalent to the logical "OR" operation in plaintext. This represents a homomorphic multiplication operation, which is equivalent to the logical AND operation in plaintext. This represents the i-th bit of the first intermediate carry; This represents the i-th bit of the first ciphertext; This represents the i-th bit of the third ciphertext; This represents the i-th bit of the second ciphertext; This indicates the NOT of the i-th bit of the second ciphertext; This represents the i-th bit of the first intermediate bit.

3. The method according to claim 1, wherein, The step of determining the second intermediate carry and the second intermediate sum based on the first intermediate carry, the first intermediate sum, and the fourth ciphertext includes: The second intermediate carry and the second intermediate sum are determined using Equation 2: in, This represents the i-th bit of the second intermediate carry; This represents the i-th bit of the fourth ciphertext; This indicates the (i-1)th bit of the first intermediate carry as "NOT"; This represents the i-th bit of the second intermediate sum.

4. The method according to claim 1, further comprising: The first ciphertext, the second ciphertext, the third ciphertext, and the fourth ciphertext are respectively encoded using single instruction multiple data to obtain the first encoded ciphertext, the second encoded ciphertext, the third encoded ciphertext, and the fourth encoded ciphertext. as well as Ciphertext operations are performed on the first ciphertext, the second ciphertext, the third ciphertext, and the fourth ciphertext to obtain the ciphertext operation result.

5. The method according to claim 4, wherein, The ciphertext arithmetic operations include ciphertext integer addition; The step of performing ciphertext operations on the first ciphertext, the second ciphertext, the third ciphertext, and the fourth ciphertext to obtain the ciphertext operation result includes: Based on the first coded ciphertext, the second coded ciphertext, and the third coded ciphertext, determine the third intermediate carry and the third intermediate sum; Based on the third intermediate carry, the third intermediate sum, and the fourth encoded ciphertext, determine the fourth intermediate carry and the fourth intermediate sum; and The ciphertext operation result is obtained based on the fourth intermediate carry and the fourth intermediate sum.

6. The method according to claim 5, wherein, The step of determining the third intermediate carry and the third intermediate sum based on the first ciphertext, the second ciphertext, and the third ciphertext includes: The third intermediate carry and the third intermediate sum are obtained using Equation 3: in, This represents the i-th bit of the third intermediate carry; This represents the i-th bit of the first encoded ciphertext; This represents the i-th bit of the third encoded ciphertext; This represents the i-th bit of the second encoded ciphertext; This represents the "NOT" of the i-th bit of the second encoded ciphertext; This represents the i-th bit of the third intermediate.

7. The method according to claim 5, wherein, The step of determining the fourth intermediate carry and the fourth intermediate sum based on the third intermediate carry, the third intermediate sum, and the fourth encoded ciphertext includes: The fourth intermediate carry and the fourth intermediate sum are obtained using Equation 4: in, This represents the i-th bit of the fourth intermediate carry; This represents the i-th bit of the fourth encoded ciphertext; This indicates the i-th bit after shifting the third intermediate carry one bit higher; This represents the i-th bit of the fourth intermediate.

8. A encrypted text processing apparatus, comprising: The first encoding module is used to perform redundancy encoding on the first initial plaintext and the second initial plaintext to obtain the first plaintext and the second plaintext. The first plaintext is represented as the difference between the first non-redundant plaintext and the second non-redundant plaintext, and the second plaintext is represented as the difference between the third non-redundant plaintext and the fourth non-redundant plaintext. The redundancy encoding includes binary encoding based on the set of numbers of the redundancy encoding. The first non-redundant plaintext, the second non-redundant plaintext, the third non-redundant plaintext, and the fourth non-redundant plaintext are all represented as binary numbers. The encryption module is used to perform homomorphic encryption on the first non-redundant plaintext, the second non-redundant plaintext, the third non-redundant plaintext, and the fourth non-redundant plaintext respectively, to obtain the first ciphertext, the second ciphertext, the third ciphertext, and the fourth ciphertext; and The first processing module is used to perform ciphertext operations on the first ciphertext, the second ciphertext, the third ciphertext, and the fourth ciphertext to obtain ciphertext operation results. The ciphertext operation includes ciphertext addition, ciphertext multiplication, comparison judgment, and equality circuit. When the ciphertext operation includes the ciphertext addition, the first processing module is specifically used for: Based on the first ciphertext, the second ciphertext, and the third ciphertext, determine the first intermediate carry and the first intermediate sum; Based on the first intermediate carry, the first intermediate sum, and the fourth ciphertext, determine the second intermediate carry and the second intermediate sum; and The ciphertext operation result is obtained based on the second intermediate carry and the second intermediate sum.

9. An electronic device, comprising: One or more processors; Memory, used to store one or more instructions. When the one or more instructions are executed by the one or more processors, the one or more processors cause the one or more processors to implement the method of any one of claims 1 to 7.

10. A computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, cause the processor to perform the method of any one of claims 1 to 7.

11. A computer program product comprising computer-executable instructions, which, when executed by a processor, are used to implement the method of any one of claims 1 to 7.

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