Image processing circuit, device, method, chip and electronic device

Abstract

The present application provides an image processing circuit, device, method, chip and electronic device, relating to the technical field of data processing. The image processing circuit includes an image signal processing chip, a data caching element and an image enhancement chip. The image signal processing chip is connected to the data caching element, and the data caching element is connected to the image enhancement chip. The image signal processing chip is configured to perform intra-frame block processing on initial image data to obtain at least two data blocks. The data caching element is configured to cache the at least two data blocks processed by the image signal processing chip. The image enhancement chip is configured to perform image processing on the at least two data blocks cached by the data caching element to obtain target image data.

Description

Technical Field

[0001] This application relates to the technical field of data processing, and particularly relates to a processing circuit, device, method, chip and electronic device. Background Art

[0002] With the development of image processing technology, people have higher and higher requirements for the images displayed by electronic devices. To ensure that an electronic device can output high-quality images that meet user needs, various chips for image processing are usually provided in the electronic device in the prior art. However, the existing image processing methods usually take a relatively long time in the process of image processing. Therefore, the existing image processing methods have the problem of relatively long processing time consumption. Summary of the Invention

[0003] This application provides an image processing circuit, device, method, chip and electronic device, which can reduce the delay in the image processing process and, at the same time, reduce the power consumption in the image processing process.

[0004] In a first aspect, an embodiment of this application provides an image processing circuit, including an image signal processing chip, a data caching element and an image enhancement chip. The image signal processing chip is connected to the data caching element, and the data caching element is connected to the image enhancement chip;

[0005] The image signal processing chip is configured to perform intra-frame block processing on initial image data to obtain at least two data blocks;

[0006] The data caching element is configured to cache at least two data blocks processed by the image signal processing chip;

[0007] The image enhancement chip is configured to perform image processing on at least two data blocks cached by the data caching element to obtain target image data.

[0008] In a second aspect, an embodiment of this application provides an image processing device, including the image processing circuit described in the first aspect.

[0009] In a third aspect, an embodiment of this application provides an image processing method, which is applied to the image processing device described in the second aspect. The method includes:

[0010] The image signal processing chip performs intra-frame block processing on initial image data to obtain at least two data blocks;

[0011] The data caching element caches at least two data blocks processed by the image signal processing chip;

[0012] The image enhancement chip performs image processing on at least two data blocks cached by the data caching element to obtain target image data.

[0013] In a fourth aspect, an embodiment of the present application provides an electronic device, including the image processing circuit described in the first aspect, a processor, and a memory. The memory stores a program or instructions that can run on the processor. When the program or instructions are executed by the processor, the steps of the image processing method described in the third aspect are implemented.

[0014] In a fifth aspect, an embodiment of the present application provides an image processing chip. The image processing chip includes a processor and a communication interface. The communication interface is coupled to the processor. The communication interface is used to transmit image data, and the processor is used to run a program or instructions to implement the steps executed by the image enhancement chip in the image processing method described in the third aspect.

[0015] In a sixth aspect, an embodiment of the present application provides a processor chip, characterized in that the processor chip includes a processor and a communication interface. The communication interface is coupled to the processor. The communication interface is used to transmit image data, and the processor is used to run a program or instructions to implement the steps executed by the image signal processing chip in the image processing method described in the third aspect.

[0016] In the embodiments of the present application, by performing intra-frame block processing on the initial image data, at least two data blocks are obtained. In this way, the image signal processing chip can use the data block as the minimum transmission unit to transmit the image data to the data cache element. When the image signal processing chip only completes the transmission of some data blocks of an image frame, the image enhancement chip can obtain the data blocks that have been transmitted from the data cache element and perform image processing on the obtained data blocks. That is, during the transmission of a certain frame of image data to the data cache element, the image enhancement chip can synchronously obtain the data blocks that have been transmitted from the data cache element, which is beneficial to reducing the delay in the image processing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic structural diagram of an image processing circuit provided by some embodiments of the present application;

[0018] Figure 2 is a schematic diagram of performing intra-frame block processing on initial image data in some embodiments of the present application;

[0019] Figure 3 is a schematic flowchart of the image processing circuit processing an image block in some embodiments of the present application;

[0020] Figure 4 is a schematic internal structure diagram of an image enhancement chip in some embodiments of the present application;

[0021] Figure 5It is a schematic internal structure diagram of an image processing unit in some embodiments of the present application;

[0022] Figure 6 It is a schematic flowchart of an image processing method provided in some embodiments of the present application;

[0023] Figure 7 It is a schematic structural diagram of an electronic device provided in some embodiments of the present application;

[0024] Figure 8 It is a schematic hardware structure diagram of an electronic device provided in some embodiments of the present application. Detailed implementation manners

[0025] Next, the technical solutions in the embodiments of the present application will be clearly described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0026] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are usually of the same category, and the number of objects is not limited. For example, the first object can be one or multiple. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally indicates an "or" relationship between the associated objects before and after.

[0027] Please refer to Figure 1 , Figure 1 It is a schematic structural diagram of an image processing circuit provided in an embodiment of the present application. The image processing circuit includes an Image Signal Processing (ISP) module. Among them, the ISP module is an image processing module, a data cache element 200, and an image enhancement chip 300 in an Application Processor (AP) of an electronic device. The image signal processing chip 100 is connected to the data cache element 200, and the data cache element is connected to the image enhancement chip 300. Among them, the data cache element 200 can serve as a high-speed random access memory (Random Access Memory, RAM) of the image enhancement chip 300;

[0028] The image signal processing chip 100 is used to perform intra-frame block processing on the initial image data to obtain at least two data blocks;

[0029] The data caching element 200 is used to cache at least two data blocks processed by the image signal processing chip 100;

[0030] The image enhancement chip 300 is used to perform image processing on at least two data blocks cached by the data caching element 200 to obtain target image data. Among them, the image signal processing chip 100 can be the main control chip in the electronic device, or the image signal processing chip 100 forms the image processing unit 302 in the main control chip of the electronic device. The image enhancement chip 300 can be an external image enhancement chip 300 independent of the main control chip.

[0031] The above initial image data can be a frame of image data, or an image sequence formed by multiple frames of image data. The above intra-frame block processing of the initial image data to obtain at least two data blocks may mean: dividing each frame of the initial image data into at least two data blocks, where specifically, the image frame can be divided into at least two data blocks according to the columns of the image frame, and each data block includes at least one line of image data. For example, please refer to Figure 2 , in an embodiment of the present application, the initial image data 400 includes a first image frame 410, a second image frame 420, and a third image frame 430. After block division, each image frame is divided into 4 data blocks. For example, the first image frame 410 is divided into a first image block 411, a second image block 412, a third image block 413, and a fourth image block 414.

[0032] The above data caching element 200 can be used to cache the data blocks to be processed by the image enhancement chip 300. Among them, the data caching element 200 can adopt various common devices with a caching function in related technologies. For example, it can be a static random access memory (Static Random-Access Memory, SRAM) or a double data rate synchronous dynamic random access memory (Double Data Rate, DDR), etc.

[0033] In the related art, when the image signal processing chip 100 transmits image data to the image enhancement information for processing, it usually uses a frame as the processing unit. In this way, the image enhancement chip 300 needs to wait for the image signal processing chip 100 to transmit a complete frame of image to the data buffer element 200 before it can obtain the frame of image from the data buffer element 200. That is, before the image signal processing chip 100 finishes transmitting a frame of image, the image enhancement chip 300 is in a waiting state. This will cause a problem of relatively large delay in the image processing process.

[0034] Based on this, in the embodiments of the present application, by performing intra-frame block processing on the initial image data, at least two data blocks are obtained. In this way, the image signal processing chip 100 can use the data block as the minimum transmission unit to transmit image data to the data buffer element 200. When the image signal processing chip 100 only finishes transmitting some data blocks of an image frame, the image enhancement chip 300 can obtain the data blocks that have been transmitted from the data buffer element 200 and perform image processing on the obtained data blocks. For example, please refer to Figure 3 , which is a schematic diagram of the transmission of 4 data blocks of an image frame. When the data blocks 1 and 2 of the image frame are transmitted to the data buffer element 200 and the data blocks 3 and 4 of the image frame have not been completely transmitted, the image enhancement chip 300 can obtain the data blocks 1 and 2 from the data buffer element 200 for processing. At the same time, the image signal processing chip 100 can synchronously transmit the data blocks 3 and 4 to the data buffer element 200. That is, during the process of transmitting a frame of image data to the data buffer element 200, the image enhancement chip 300 can synchronously obtain the data blocks that have been transmitted from the data buffer element 200, which is beneficial to reducing the delay in the image processing process.

[0035] In a specific embodiment of the present application, the initial image data may be a face image taken in a relatively dim environment, for example, a face image taken at night. Since the environment is relatively dim, the clarity of the face in the initial image data is not high, and there are many noise points on the face. Based on this, in the embodiment of the present application, in order to improve the quality of the face image taken by the electronic device in a dim environment, after the image sensor collects the initial image data, the initial image data is transmitted to the image signal processing chip 100, and the image signal processing chip 100 performs intra-frame block processing on the initial image data to obtain at least two data blocks. The data blocks are transmitted to the data cache element 200, and the image enhancement chip 300 obtains the data blocks from the data cache element 200, and performs image processing such as brightness enhancement processing, color enhancement processing, contrast enhancement processing, noise reduction processing, wide dynamic processing, etc. on the acquired data blocks to obtain the target image data. In this way, by performing image processing such as brightness enhancement processing, color enhancement processing, contrast enhancement processing, noise reduction processing, wide dynamic processing, etc. on the data block, the clarity of the face in the obtained target image data can be improved. At the same time, the noise in the image can be removed, thereby improving the quality of face images taken by electronic devices in dim environments.

[0036] The image signal processing chip 100 can be connected to the display screen of the electronic device to which it belongs. After the image enhancement chip 300 completes the processing of each data block in the initial image data and obtains the target image data, the image enhancement chip 300 returns the target image data to the image signal processing chip 100, and the image signal processing chip 100 can save the target image data. Alternatively, the image signal processing chip 100 can also transmit the target image data to the display screen for display based on the connection between the image signal processing chip 100 and the display screen.

[0037] In another specific embodiment of the present application, the initial image data may be a video sequence of video data currently played by an electronic device. Among them, the video data may be video data with poor image quality. For example, the clarity of each frame of image in the video data is relatively low. If the initial image data is directly displayed, it will cause a problem of poor user viewing experience. Based on this, in the embodiment of the present application, to improve the quality of the video played by the electronic device, before sending the initial image data for display, the image signal processing chip 100 may perform intra-frame block processing on each frame of image in the initial image data to obtain at least two data blocks corresponding to each frame of image, and respectively transmit the data blocks of each frame to the data cache element 200. The image signal processing chip 100 obtains the data blocks from the data cache element 200, and performs image processing such as clarity processing, noise reduction processing, and sharpening processing on the obtained data blocks to obtain target image data. In this way, by performing image processing such as clarity processing, noise reduction processing, and sharpening processing on the data blocks, the image quality of the obtained target image data can be improved. After the image enhancement chip 300 completes the processing of each data block in the initial image data to obtain the target image data, the image enhancement chip 300 returns the target image data to the image signal processing chip 100, and the image signal processing chip 100 may save the target image data. Alternatively, the image signal processing chip 100 may also transmit the target image data to the display screen for display based on the connection with the display screen.

[0038] In this embodiment, by performing intra-frame block processing on the initial image data to obtain at least two data blocks, in this way, the image signal processing chip 100 can use the data block as the minimum transmission unit to transmit the image data to the data cache element 200. When the image signal processing chip 100 only completes the transmission of some data blocks of an image frame, the image enhancement chip 300 can obtain the data blocks that have been transmitted from the data cache element 200 and perform image processing on the obtained data blocks. That is, during the transmission of a certain frame of image data to the data cache element 200, the image enhancement chip 300 can synchronously obtain the data blocks that have been transmitted from the data cache element 200, which is beneficial to improving the real-time performance of online image processing and reducing the delay of the image processing process.

[0039] Optionally, the image signal processing chip 100 includes a first output interface 101, the data cache element 200 includes a first input interface 201 and a second output interface 202, and the image enhancement chip 300 includes a second input interface 301;

[0040] The first output interface 101 is connected to the first input interface 201, and the second output interface 202 is connected to the second input interface 301;

[0041] The image signal processing chip 100 is further configured to, during the in-frame block processing of the initial image data, transmit each obtained data block to the data cache element 200 through the first output interface 101 every time a data block is processed;

[0042] The data cache element 200 is further configured to receive each data block transmitted by the image signal processing chip 100 through the first input interface 201 and cache each data block;

[0043] The image enhancement chip 300 is further configured to, every time the data cache element 200 caches a data block, obtain each data block from the data cache element 200 through the second input interface 301 and perform image processing on the obtained data block.

[0044] In a specific embodiment of the present application, the initial image data may be a face image taken in a relatively dim environment. For example, it may be a face image taken at night. Due to the relatively dim environment, the clarity of the face in the initial image data is not high and there are many noise points on the face. Based on this, in the embodiment of the present application, to improve the quality of the face image taken by the electronic device in a dim environment, after the image sensor collects the initial image data, the initial image data is transmitted to the image signal processing chip 100, and the image signal processing chip 100 performs in-frame block processing on the initial image data to obtain at least two data blocks. During the in-frame block processing of the initial image data by the image signal processing chip 100, every time a data block is processed, the data block is transmitted to the data cache element 200 through the first output interface 101; every time the data cache element 200 caches a data block, the image enhancement chip 300 obtains each data block from the data cache element 200 through the second input interface 301 and performs image processing such as brightness enhancement processing, color enhancement processing, contrast enhancement processing, noise reduction processing, and wide dynamic range processing on the obtained data block to obtain target image data. In this way, by performing image processing such as brightness enhancement processing, color enhancement processing, contrast enhancement processing, noise reduction processing, and wide dynamic range processing on the data block, the clarity of the face in the obtained target image data can be improved, and at the same time, the noise points in the image can be removed, thereby improving the quality of the face image taken by the electronic device in a dim environment.

[0045] Among them, the image signal processing chip 100 can be connected to the display screen of the electronic device to which it belongs. After the image enhancement chip 300 completes the processing of each data block in the initial image data to obtain the target image data, the image enhancement chip 300 transmits the target image data back to the image signal processing chip 100, and the image signal processing chip 100 can save the target image data. Alternatively, the image signal processing chip 100 can also transmit the target image data to the display screen for display based on the connection with the display screen.

[0046] In another specific embodiment of the present application, the initial image data may be a video sequence of video data currently played by an electronic device. Among them, the video data may be video data with poor image quality. For example, the clarity of each frame of image in the video data is relatively low. If the initial image data is directly displayed, it will cause a problem of poor user viewing experience. Based on this, in the embodiments of the present application, to improve the quality of the video played by the electronic device, before the image signal processing chip 100 sends the initial image data for display, it can perform intra-frame block processing on each frame of image in the initial image data to obtain at least two data blocks corresponding to each frame of image. During the process of the image signal processing chip 100 performing intra-frame block processing on the initial image data, each time a data block is processed, the data block is transmitted to the data buffer element 200 through the first output interface 101; when the data buffer element 200 caches each data block, the image enhancement chip 300 obtains each data block from the data buffer element 200 through the second input interface 301, and performs image processing such as clarity processing, noise reduction processing, and sharpening processing on the obtained data blocks to obtain the target image data. In this way, by performing image processing such as clarity processing, noise reduction processing, and sharpening processing on the data blocks, the image quality of the obtained target image data can be improved. After the image enhancement chip 300 completes the processing of each data block in the initial image data to obtain the target image data, the image enhancement chip 300 transmits the target image data back to the image signal processing chip 100, and the image signal processing chip 100 can save the target image data. Alternatively, the image signal processing chip 100 can also transmit the target image data to the display screen for display based on the connection with the display screen.

[0047] In this embodiment, when the image enhancement chip 300 obtains each data block from the data caching element 200 through the second input interface 301 every time a data block is cached in the data caching element 200, and performs image processing on the obtained data block. In this way, since there is no backlog of data blocks in the data caching element 200, the timeliness of image data processing can be further improved, and thus the delay in the image processing process can be further reduced.

[0048] Optionally, the image enhancement chip 300 includes an image processing unit 302 and at least two data caching units with different data processing performances, and the image processing unit 302 is connected to each data caching unit;

[0049] The image processing unit 302 is configured to perform image processing on at least two data blocks cached in the data caching element 200, and store each processed data block into the data caching unit;

[0050] When a temporary variable is generated during the process of the image processing unit 302 processing the at least two data blocks, the image processing unit 302 is further configured to store the temporary variable in the data caching unit corresponding to the usage frequency of the temporary variable;

[0051] Wherein, the usage frequency of the temporary variable is positively correlated with the data processing performance of the data caching unit.

[0052] The above data processing performance may include performances such as the data caching speed and data caching capacity of the data caching unit. Hereinafter, taking the data processing performance as the data caching speed as an example, the embodiments of the present application will be further explained. When the data processing performance is the data caching speed, the usage frequency of the temporary variable is positively correlated with the data caching speed of the data caching unit, that is, the higher the data caching speed of the data caching unit, the higher the usage frequency.

[0053] Please refer to Figure 4 , in an embodiment of the present application, the image enhancement chip 300 includes an image processing unit 302, a first data caching unit 303, a second data caching unit 304, and a third data caching unit 305. Among them, the first data caching unit 303, the second data caching unit 304, and the third data caching unit 305 are respectively connected to the image processing unit 302. Among them, the data caching speeds of the first data caching unit 303, the second data caching unit 304, and the third data caching unit 305 decrease in sequence, the caching capacity of the first data caching unit 303 is less than 2MB, the caching capacity of the second data caching unit 304 is less than 4MB, and the caching capacity of the third data caching unit 305 is less than 8MB.

[0054] It can be understood that the image processing unit 302 is used to perform image processing on the data blocks obtained by the image enhancement chip 300 from the data cache element 200. Since a large number of temporary variables will be generated during the image processing by the image processing unit 302, and the image enhancement chip 300 needs to cache the temporary variables generated by the image processing unit 302 to facilitate the data processing unit to call the generated temporary variables again.

[0055] Based on this, in the embodiments of the present application, the temporary variables generated by the data processing unit can be divided into three levels according to the call frequency, and the temporary variables with the highest usage frequency are cached through the first data cache unit 303, the temporary variables with the second highest usage frequency are cached through the second data cache unit 304, and the temporary variables with the lowest usage frequency are cached through the third data cache unit 305. It can be understood that since the usage frequency of each temporary variable may change during the data processing by the data processing unit, the cached position can be adjusted according to the change in the usage frequency of the temporary variable.

[0056] In a specific embodiment of the present application, the initial image data may be a face image taken in a relatively dim environment. For example, it may be a face image taken at night. Since the environment is relatively dim, the clarity of the face in the initial image data is not high and there are many noise points on the face. Based on this, in the embodiments of the present application, to improve the quality of the face image taken by the electronic device in a dim environment, after the image sensor collects the initial image data, the initial image data is transmitted to the image signal processing chip 100, and the image signal processing chip 100 performs intra-frame block processing on the initial image data to obtain at least two data blocks. During the intra-frame block processing of the initial image data by the image signal processing chip 100, each time a data block is processed, the data block is transmitted to the data cache element 200 through the first output interface 101; when each data block is cached by the data cache element 200, the image enhancement chip 300 obtains each data block from the data cache element 200 through the second input interface 301, and performs image processing such as brightness enhancement processing, color enhancement processing, contrast enhancement processing, noise reduction processing, and wide dynamic range processing on the obtained data block to obtain target image data. In this way, by performing image processing such as brightness enhancement processing, color enhancement processing, contrast enhancement processing, noise reduction processing, and wide dynamic range processing on the data block, the clarity of the face in the obtained target image data can be improved, and at the same time, the noise points in the image can be removed, thereby improving the quality of the face image taken by the electronic device in a dim environment.

[0057] Among them, when the image enhancement chip 300 generates a temporary variable during the process of processing the data block, the image processing unit 302 stores the temporary variable in the corresponding data cache unit according to the usage frequency of the generated temporary variable, so as to further reduce the latency of the image processing process. After the image enhancement chip 300 completes the processing of each data block in the initial image data and obtains the target image data, the image enhancement chip 300 transmits the target image data back to the image signal processing chip 100, and the image signal processing chip 100 can save the target image data. Alternatively, the image signal processing chip 100 can also transmit the target image data to the display screen for display based on the connection with the display screen.

[0058] In another specific embodiment of the present application, the initial image data may be a video sequence of video data currently played by the electronic device. Among them, the video data may be video data with poor image quality. For example, the clarity of each frame of image in the video data is relatively low. If the initial image data is directly displayed, it will cause a problem of poor user viewing experience. Based on this, in the embodiment of the present application, to improve the quality of the video played by the electronic device, before sending the initial image data for display, the image signal processing chip 100 can perform intra-frame block processing on each frame of image in the initial image data to obtain at least two data blocks corresponding to each frame of image. During the process of the image signal processing chip 100 performing intra-frame block processing on the initial image data, each time a data block is processed, the data block is transmitted to the data cache element 200 through the first output interface 101; when the data cache element 200 caches each data block, the image enhancement chip 300 obtains each data block from the data cache element 200 through the second input interface 301, and performs image processing such as clarity processing, noise reduction processing, and sharpening processing on the obtained data blocks to obtain target image data. The image quality of the obtained target image data can be improved. After the image enhancement chip 300 completes the processing of each data block in the initial image data and obtains the target image data, the image enhancement chip 300 transmits the target image data back to the image signal processing chip 100, and the image signal processing chip 100 can save the target image data. Alternatively, the image signal processing chip 100 can also transmit the target image data to the display screen for display based on the connection with the display screen. Among them, when the image enhancement chip 300 generates a temporary variable during the process of processing the data block, the image processing unit 302 stores the temporary variable in the corresponding data cache unit according to the usage frequency of the generated temporary variable, so as to further reduce the latency of the image processing process.

[0059] In this embodiment, by caching the temporary variables with high usage frequency of the data processing unit in the data cache unit with fast data caching speed, the time required for the data processing unit to call the temporary variables can be reduced, thereby further improving the efficiency of the image enhancement chip 300 in processing image data and facilitating further reduction of the latency in the image processing process.

[0060] Optionally, the data block includes image data of n dimensions, where n is an integer greater than 1; the image enhancement chip 300 includes an image processing unit 302, and the image processing unit 302 includes at least two image processing layers, which are connected in sequence;

[0061] The at least two image processing layers are respectively used to perform different types of image processing on the image processing of the n dimensions;

[0062] Among them, the output of the first image processing layer in any two adjacent image processing layers is the input of the second image processing layer, and when the first image processing layer completes the image processing of one dimension and obtains the intermediate image data of one dimension, the first image processing layer is used to transmit the intermediate image data of the one dimension to the second image processing layer; when the second image processing layer receives each piece of the intermediate data of the one dimension, the second image processing layer is used to perform image processing on the received intermediate image data of the one dimension.

[0063] Among them, since each pixel point in the image includes data of three color channels: red (R), green (G), and blue (B), the data of the R color channel of all pixel points in the data block can be determined as the data of one dimension, the data of the G color channel of all pixel points in the data block can be determined as the data of one dimension, and the data of the B color channel of all pixel points in the data block can be determined as the data of one dimension, so as to obtain image data of three dimensions. At this time, the image data of the n dimensions may refer to the image processing of the R, G, and B three dimensions in the image. In addition, the image data of the n dimensions may also refer to the data of the text dimension and the data of the image dimension in the same data block. Below, taking the image data of the n dimensions including the image processing of the R, G, and B three dimensions as an example, the image processing process of the embodiments of the present application will be further explained.

[0064] In some embodiments of the present application, the initial image data may be a face image taken in a relatively dim environment. For example, it may be a face image taken at night. Due to the relatively dim environment, the clarity of the face in the initial image data is not high and there are many noises on the face. Please refer to Figure 5, the image processing unit 302 includes a first data processing layer 306, a second data processing layer 307, and a third data processing layer 308. Among them, the first data processing layer 306 is used to perform brightness enhancement processing and color enhancement processing on the received image data, the second data processing layer 307 is used to perform contrast enhancement processing on the received image data, and the third data processing layer 308 is used to perform noise reduction processing and wide dynamic range processing on the received image data.

[0065] To improve the quality of face images captured by an electronic device in a dim environment, the specific image processing process in this embodiment includes:

[0066] After the image sensor captures the initial image data, it transmits the initial image data to the image signal processing chip 100. The image signal processing chip 100 performs intra-frame block processing on the initial image data to obtain at least two data blocks. Among them, during the intra-frame block processing of the initial image data by the image signal processing chip 100, each time a data block is processed, it transmits the data block to the data cache element 200 through the first output interface 101; when the data cache element 200 caches each data block, the image enhancement chip 300 obtains each data block from the data cache element 200 through the second input interface 301. Each of the data blocks includes first sub-data, second sub-data, and third sub-data. The first sub-data includes the image data of the R dimension of each pixel point in the data block; the second sub-data includes the image data of the G dimension of each pixel point in the data block; the third sub-data includes the image data of the B dimension of each pixel point in the data block.

[0067] After receiving a data block, the first data processing layer 306 first performs brightness enhancement processing and color enhancement processing on the first sub-data in the data block to obtain first intermediate sub-data; then, the first data processing layer 306 transfers the first intermediate sub-data to the second data processing layer 307. At the same time, the first data processing layer 306 continues to perform brightness enhancement processing and color enhancement processing on the second sub-data in the data block; correspondingly, after the second data processing layer 307 receives the first intermediate sub-data, it performs contrast enhancement processing on the first intermediate sub-data to obtain second intermediate sub-data; then, the second data processing layer 307 transfers the second intermediate sub-data to the third data processing layer 308; when the third data processing layer 308 receives the second intermediate sub-data, it performs noise reduction processing and wide dynamic range processing on the second intermediate sub-data to obtain first target sub-data. It can be understood that every time the first data processing layer 306 finishes processing the sub-data of one dimension, it transfers the processed intermediate data to the next image layer; after the second data processing layer 307 and the third data processing layer 308 receive the intermediate data transferred from the previous layer each time, they process the received intermediate data. In this way, by performing image processing such as brightness enhancement processing, color enhancement processing, contrast enhancement processing, noise reduction processing, and wide dynamic range processing on the data of each dimension in the data block, the clarity of the face in the obtained target image data can be improved. At the same time, the noise in the image can be removed, thereby improving the quality of the face image captured by the electronic device in a dim environment. Among them, when the image enhancement chip 300 generates a temporary variable during the process of processing the data block, the image processing unit 302 stores the temporary variable in the corresponding data cache unit according to the usage frequency of the generated temporary variable, so as to further reduce the delay in the image processing process.

[0068] After the image enhancement chip 300 finishes processing each data block in the initial image data to obtain the target image data, the image enhancement chip 300 transfers the target image data back to the image signal processing chip 100, and the image signal processing chip 100 can save the target image data. Alternatively, the image signal processing chip 100 can also transfer the target image data to the display screen for display based on the connection with the display screen.

[0069] In another embodiment of the present application, the initial image data may be a video sequence of video data currently played by the electronic device. Among them, the video data may be video data with poor image quality. For example, the clarity of each frame image in the video data is relatively low. If the initial image data is directly displayed, it will cause a problem of poor user viewing experience. Please refer to Figure 5, the image processing unit 302 includes a first data processing layer 306, a second data processing layer 307, and a third data processing layer 308. Among them, the first data processing layer 306 is used to perform clarity processing on the received image data, the second data processing layer 307 is used to perform noise reduction processing on the received image data, and the third data processing layer 308 is used to perform sharpening processing on the received image data. Based on this, in the embodiments of the present application, to improve the quality of the video played by the electronic device, the specific processing process of the initial image data includes:

[0070] Before sending the initial image data for display, the image signal processing chip 100 can perform intra-frame block processing on each frame of the initial image data to obtain at least two data blocks corresponding to each frame of the image. During the intra-frame block processing of the initial image data by the image signal processing chip 100, each time a data block is processed, the data block is transmitted to the data cache element 200 through the first output interface 101; when the data cache element 200 caches each data block, the image enhancement chip 300 obtains each data block from the data cache element 200 through the second input interface 301. Each of the data blocks includes first sub-data, second sub-data, and third sub-data. The first sub-data includes the image data of the R dimension of each pixel point in the data block; the second sub-data includes the image data of the G dimension of each pixel point in the data block; the third sub-data includes the image data of the B dimension of each pixel point in the data block.

[0071] After receiving a data block, the first data processing layer 306 first performs clarity processing on the first sub-data in the data block to obtain first intermediate sub-data. Then, the first data processing layer 306 passes the first intermediate sub-data to the second data processing layer 307. At the same time, the first data processing layer 306 continues to perform clarity processing on the second sub-data in the data block. Correspondingly, after receiving the first intermediate sub-data, the second data processing layer 307 performs noise reduction processing on the first intermediate sub-data to obtain second intermediate sub-data. Then, the second data processing layer 307 passes the second intermediate sub-data to the third data processing layer 308. When receiving the second intermediate sub-data, the third data processing layer 308 performs sharpening processing on the second intermediate sub-data to obtain first target sub-data. It can be understood that every time the first data processing layer 306 finishes processing the sub-data of one dimension, it passes the processed intermediate data to the next image layer. After receiving an intermediate data passed from the upper layer each time, the second data processing layer 307 and the third data processing layer 308 perform processing on the received intermediate data. In this way, through image processing such as clarity processing, noise reduction processing, and sharpening processing on the acquired data block, target image data is obtained, which can improve the image quality of the obtained target image data. Among them, when the image enhancement chip 300 generates a temporary variable during the process of processing the data block, the image processing unit 302 stores the temporary variable in the corresponding data cache unit according to the usage frequency of the generated temporary variable, so as to further reduce the latency of the image processing process.

[0072] After the image enhancement chip 300 finishes processing each data block in the initial image data to obtain the target image data, the image enhancement chip 300 returns the target image data to the image signal processing chip 100, and the image signal processing chip 100 can save the target image data. Alternatively, the image signal processing chip 100 can also transmit the target image data to the display screen for display based on the connection with the display screen.

[0073] Specifically, the image enhancement chip 300 may be a neural network processing unit (NPU), because the neural network processor has a large number of operators, such as relu, sigmoid, conv2d, transpose, dense, matmul, tan, pool and other operators. In the process of the neural network processor processing the image, it may be necessary to call various operators to process the image. For operators commonly used in the image processing process, the operators can be hardened through hardware design, and for operators that are not needed in the image processing process, they can be removed from the neural network processor to save the area occupied by the image enhancement chip 300.

[0074] In addition, an image processing model for processing images can be pre-built and trained in the neural network processor, wherein the image processing model can be a model built by a convolutional neural network (CNN). In this way, by using a convolutional neural network to process images, it is helpful to reduce the demand for existing capacity (memory size) and access bandwidth during the image processing process.

[0075] In the related art, when there are multiple image processing layers processing the same data block, the next image processing layer usually needs to wait until the previous image processing layer completes processing of the entire data block before it can receive the processing results of the previous image processing layer, and then further process based on the processing results of the previous image processing layer. Therefore, the waiting time in the image processing process is relatively long, which leads to the problem of large image processing delay.

[0076] In some embodiments of the present application, when different image processing layers process the same data block, after the previous image processing layer completes processing of data of some dimensions in the data block, it can pass the partial results obtained by processing to the next image processing layer for further processing. In this way, the next image processing layer can start processing the received partial results without waiting for the previous image layer to complete the entire data block, which is conducive to reducing the waiting time in the image processing process, and further reducing the delay in the image processing process.

[0077] Optionally, the data cache element 200 includes a static random access memory.

[0078] Specifically, in the related art, a double data rate synchronous dynamic random access memory is usually used as the data cache element 200. However, since the double data rate synchronous dynamic random access memory needs to be dynamically refreshed during operation, the power consumption of the double data rate synchronous dynamic random access memory during operation is relatively high.

[0079] In this embodiment, by using a static random access memory as the data cache element 200, since the static random access memory does not need to be dynamically refreshed during operation, it is beneficial to reduce the power consumption of the electronic device compared with using a double data rate synchronous dynamic random access memory as the data cache element 200.

[0080] An embodiment of the present application further provides an image processing device, and the image processing device includes the image processing circuit described in the above embodiment.

[0081] In this embodiment, since the image processing device includes the image processing circuit described in the above embodiment, the image processing device can implement each process of the image processing circuit in the above embodiment and has the same beneficial effects. To avoid repetition, it will not be described in detail here.

[0082] Please refer to Figure 6 , an embodiment of the present application provides an image processing method, which is applied to the image processing device described in the above embodiment, and the method includes:

[0083] Step 601, the image signal processing chip 100 performs intra-frame block processing on the initial image data to obtain at least two data blocks;

[0084] Step 602, the data cache element 200 caches at least two data blocks processed by the image signal processing chip 100;

[0085] Step 603, the image enhancement chip 300 performs image processing on at least two data blocks cached by the data cache element 200 to obtain target image data.

[0086] Optionally, the image signal processing chip 100 includes a first output interface 101, the data cache element 200 includes a first input interface 201 and a second output interface 202, and the image enhancement chip 300 includes a second input interface 301;

[0087] The first output interface 101 is connected to the first input interface 201, and the second output interface 202 is connected to the second input interface 301;

[0088] The image signal processing chip 100 performs intra-frame block processing on the initial image data to obtain at least two data blocks, including:

[0089] During the process of performing intra-frame block processing on the initial image data, the image signal processing chip 100 transmits each data block obtained through the first output interface 101 to the data cache element 200;

[0090] The data cache element 200 caches at least two data blocks obtained by the image signal processing chip 100, including:

[0091] The data cache element 200 receives each data block transmitted by the image signal processing chip 100 through the first input interface 201 and caches each data block;

[0092] The image enhancement chip 300 performs image processing on at least two data blocks cached by the data cache element 200, including:

[0093] In the case where the data cache element 200 caches each data block, the image enhancement chip 300 obtains each data block from the data cache element 200 through the second input interface 301 and performs image processing on the obtained data block.

[0094] Optionally, the image enhancement chip 300 includes an image processing unit 302 and at least two data cache units with different data processing performances, and the image processing unit 302 is connected to each data cache unit;

[0095] The image enhancement chip 300 performs image processing on at least two data blocks cached by the data cache element 200, including:

[0096] The image processing unit 302 performs image processing on at least two data blocks cached by the data cache element 200 and stores each processed data block in the data cache unit;

[0097] In the case where a temporary variable is generated during the process of the image processing unit 302 processing the at least two data blocks, the image processing unit 302 stores the temporary variable in the data cache unit corresponding to the usage frequency of the temporary variable;

[0098] Wherein, the usage frequency of the temporary variable is positively correlated with the data processing performance of the data cache unit.

[0099] Optionally, the data block includes image processing in n dimensions, where n is an integer greater than 1; the image enhancement chip 300 includes an image processing unit 302, and the image processing unit 302 includes at least two image processing layers, and the at least two image processing layers are connected in sequence;

[0100] The image enhancement chip 300 performs image processing on at least two data blocks cached by the data caching element 200, including:

[0101] The at least two image processing layers perform different types of image processing on the image processing in the n dimensions respectively;

[0102] Among them, the output of the first image processing layer in any two adjacent image processing layers is the input of the second image processing layer, and when the first image processing layer completes image processing for one dimension and obtains intermediate image data for one dimension, the first image processing layer is used to transmit the intermediate image data for one dimension to the second image processing layer; when the second image processing layer receives one piece of the intermediate data for one dimension, the second image processing layer is used to perform image processing on the received intermediate image data for one dimension.

[0103] Optionally, the data caching element includes a static random access memory.

[0104] This embodiment is an image processing method corresponding to the image processing device described in the above embodiment. Its specific implementation process is similar to the working process of the above image processing device. To avoid repetition, it will not be described in detail here.

[0105] As Figure 7 shown, some embodiments of the present application further provide an electronic device 700, including an image processing circuit, a processor 701, and a memory 702. Among them, the image processing circuit is the image processing circuit described in the above embodiment. A program or instruction stored on the memory 702 and executable on the processor 701, when executed by the processor 701, implements each process of the above image processing method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be described in detail here.

[0106] It should be noted that the electronic device in the embodiments of the present application includes the above-mentioned mobile electronic device and non-mobile electronic device.

[0107] Figure 8 It is a schematic diagram of the hardware structure of an electronic device for implementing the embodiments of the present application.

[0108] The electronic device 800 includes but is not limited to: a radio frequency unit 801, a network module 802, an audio output unit 803, an input unit 804, a sensor 805, a display unit 806, a user input unit 807, an interface unit 808, a memory 809, and a processor 810 and other components.

[0109] Among them, the image signal processing chip 100 can be the processor 810, or the image signal processing chip 100 includes the processor 810, that is, the processor 810 is integrated on the image signal processing chip 100. The image processing circuit includes an image signal processing chip 100, a data cache element 200, and an image enhancement chip 300. The image signal processing chip 100 is connected to the data cache element 200, and the data cache element is connected to the image enhancement chip 300. The image signal processing chip 100 is configured to perform intra-frame block processing on the initial image data to obtain at least two data blocks. The data cache element 200 is configured to cache at least two data blocks processed by the image signal processing chip 100. The image enhancement chip 300 is configured to perform image processing on at least two data blocks cached by the data cache element 200 to obtain target image data.

[0110] Optionally, please refer to Figure 1 , the image signal processing chip 100 includes a first output interface 101, the data cache element 200 includes a first input interface 201 and a second output interface 202, and the image enhancement chip 300 includes a second input interface 301;

[0111] The first output interface 101 is connected to the first input interface 201, and the second output interface 202 is connected to the second input interface 301;

[0112] The image signal processing chip 100 is further configured to, during the intra-frame block processing of the initial image data, each time a data block is processed, transmit the data block to the data cache element 200 through the first output interface 101;

[0113] The data cache element 200 is further configured to receive each data block transmitted by the image signal processing chip 100 through the first input interface 201 and cache each data block;

[0114] The image enhancement chip 300 is further configured to, each time the data cache element 200 caches a data block, obtain each data block from the data cache element 200 through the second input interface 301 and perform image processing on the obtained data block.

[0115] Optionally, please refer to Figure 4 , the image enhancement chip 300 includes an image processing unit 302 and at least two data cache units with different data processing capabilities, and the image processing unit 302 is connected to each data cache unit;

[0116] The image processing unit 302 is configured to perform image processing on at least two data blocks cached by the data caching element 200, and store each processed data block into the data caching unit;

[0117] When a temporary variable is generated during the process that the image processing unit 302 processes the at least two data blocks, the image processing unit 302 is further configured to store the temporary variable into the data caching unit corresponding to the usage frequency of the temporary variable;

[0118] Wherein, the usage frequency of the temporary variable is positively correlated with the data processing performance of the data caching unit.

[0119] Optionally, please refer to Figure 5 , the data block includes image data of n dimensions, where n is an integer greater than 1; the image enhancement chip 300 includes an image processing unit 302, and the image processing unit 302 includes at least two image processing layers which are connected in sequence;

[0120] The at least two image processing layers are respectively configured to perform different types of image processing on the image processing of the n dimensions;

[0121] Wherein, the output of the first image processing layer in any adjacent two image processing layers is the input of the second image processing layer, and when the first image processing layer completes the image processing of one dimension and obtains intermediate image data of one dimension, the first image processing layer is configured to transmit the intermediate image data of one dimension to the second image processing layer; when the second image processing layer receives each piece of the intermediate data of one dimension, the second image processing layer is configured to perform image processing on the received intermediate image data of one dimension.

[0122] Optionally, the data caching element 200 includes a static random access memory.

[0123] An embodiment of the present application provides an image processing method based on the electronic device 800, including:

[0124] The image signal processing chip 100 performs intra-frame block processing on the initial image data to obtain at least two data blocks;

[0125] The data caching element 200 caches at least two data blocks processed by the image signal processing chip 100;

[0126] The image enhancement chip 300 performs image processing on at least two data blocks cached by the data caching element 200 to obtain target image data.

[0127] Optionally, please refer toFigure 1 The image signal processing chip 100 includes a first output interface 101, the data caching element 200 includes a first input interface 201 and a second output interface 202, and the image enhancement chip 300 includes a second input interface 301;

[0128] The first output interface 101 is connected to the first input interface 201, and the second output interface 202 is connected to the second input interface 301;

[0129] The image signal processing chip 100 performs intra-frame block processing on the initial image data to obtain at least two data blocks, including:

[0130] During the process of the image signal processing chip 100 performing intra-frame block processing on the initial image data, each time a data block is processed, the data block is transmitted to the data caching element 200 through the first output interface 101;

[0131] The data caching element 200 caches at least two data blocks processed by the image signal processing chip 100, including:

[0132] The data caching element 200 receives each data block transmitted by the image signal processing chip 100 through the first input interface 201 and caches each data block;

[0133] The image enhancement chip 300 performs image processing on at least two data blocks cached by the data caching element 200, including:

[0134] The image enhancement chip 300, in the case where each data block is cached by the data caching element 200, obtains each data block from the data caching element 200 through the second input interface 301 and performs image processing on the obtained data block.

[0135] Optionally, please refer to Figure 4 The image enhancement chip 300 includes an image processing unit 302 and at least two data caching units with different data processing performances, and the image processing unit 302 is connected to each data caching unit;

[0136] The image enhancement chip 300 performs image processing on at least two data blocks cached by the data caching element 200, including:

[0137] The image processing unit 302 performs image processing on at least two data blocks cached by the data caching element 200 and stores each processed data block in the data caching unit;

[0138] In the case where a temporary variable is generated during the process of the image processing unit 302 processing the at least two data blocks, the image processing unit 302 stores the temporary variable in the data cache unit corresponding to the usage frequency of the temporary variable;

[0139] Wherein, the usage frequency of the temporary variable is positively correlated with the data processing performance of the data cache unit.

[0140] Optionally, please refer to Figure 5 , the data block includes image processing in n dimensions, where n is an integer greater than 1; the image enhancement chip 300 includes an image processing unit 302, and the image processing unit 302 includes at least two image processing layers, and the at least two image processing layers are connected in sequence;

[0141] The image enhancement chip 300 performs image processing on at least two data blocks cached by the data cache element 200, including:

[0142] The at least two image processing layers respectively perform different types of image processing on the image processing in n dimensions;

[0143] Wherein, the output of the first image processing layer in any two adjacent image processing layers is the input of the second image processing layer, and when the first image processing layer completes image processing on one dimension and obtains intermediate image data of one dimension, the first image processing layer is used to transmit the intermediate image data of one dimension to the second image processing layer; when the second image processing layer receives each piece of the intermediate data of one dimension, the second image processing layer is used to perform image processing on the received intermediate image data of one dimension.

[0144] Optionally, the data cache includes a static random access memory.

[0145] Those skilled in the art can understand that the electronic device 800 may further include a power supply (such as a battery) for supplying power to each component, and the power supply can be logically connected to the processor 810 through a power management system, so as to implement functions such as management of charging, discharging, and power consumption management through the power management system. Figure 8 The structure of the electronic device shown in does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0146] It should be understood that in the embodiments of the present application, the input unit 804 may include a Graphics Processing Unit (GPU) 8041 and a microphone 8042. The graphics processor 8041 processes the image data of static pictures or videos obtained by an image capture device (such as a camera) in the video capture mode or the image capture mode. The display unit 806 may include a display panel 8061, and the display panel 8061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 807 includes a touch panel 8071 and other input devices 8072. The touch panel 8071 is also called a touch screen. The touch panel 8071 may include two parts: a touch detection device and a touch controller. The other input devices 8072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, power on / off keys, etc.), a trackball, a mouse, and a joystick, which will not be elaborated here. The memory 809 can be used to store software programs and various data, including but not limited to application programs and operating systems. The processor 810 may integrate an application processor and a modem processor. Among them, the application processor mainly processes the operating system, user interface, application programs, etc., and the modem processor mainly processes wireless communication. It can be understood that the above-mentioned modem processor may not be integrated into the processor 810.

[0147] The embodiments of the present application further provide a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, it implements each process of the above-mentioned embodiment of the image processing method and can achieve the same technical effect. To avoid repetition, it will not be elaborated here.

[0148] Among them, the processor is the processor in the electronic device described in the above-mentioned embodiment. The readable storage medium includes a computer-readable storage medium, such as a computer Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disc, etc.

[0149] The embodiments of the present application further provide a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run a program or instruction to implement each process of the above-mentioned embodiment of the image processing method and can achieve the same technical effect. To avoid repetition, it will not be elaborated here.

[0150] It should be understood that the chip mentioned in the embodiments of the present application may also be referred to as a system-on-chip, a system chip, a chip system, or a system-on-chip.

[0151] It should be noted that in this text, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including such element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in a reverse order according to the functions involved. For example, the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, the features described with reference to certain examples may be combined in other examples.

[0152] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-described example methods can be implemented by means of software plus a necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions for causing a terminal (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present application.

[0153] The embodiments of the present application have been described above in conjunction with the accompanying drawings. However, the present application is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Those of ordinary skill in the art, under the inspiration of the present application and without departing from the spirit and scope protected by the claims of the present application, can also make many forms, all of which fall within the protection scope of the present application.

[0154] It should be noted that in this text, the term "including", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including that element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in the reverse order according to the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0155] The embodiments of the present application have been described above in conjunction with the accompanying drawings. However, the present application is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present application, those of ordinary skill in the art can also make many forms without departing from the purpose of the present application and the scope protected by the claims, and all of them fall within the protection scope of the present application.

Claims

1. An image processing circuit, characterized in that, It includes an image signal processing chip, a data cache element, and an image enhancement chip. The image signal processing chip is connected to the data cache element, and the data cache element is connected to the image enhancement chip; The image signal processing chip is used to perform intra-frame block processing on the initial image data to obtain at least two data blocks; The data cache element is used to cache at least two data blocks processed by the image signal processing chip; The image enhancement chip is used to perform image processing on at least two data blocks cached by the data cache element to obtain target image data; The data block includes image data in n dimensions, where n is an integer greater than 1; the image enhancement chip includes an image processing unit, and the image processing unit includes at least two image processing layers, and the at least two image processing layers are connected in sequence; The at least two image processing layers are respectively used to perform different types of image processing on the image processing in the n dimensions; Among them, the output of the first image processing layer in any two adjacent image processing layers is the input of the second image processing layer. And when the first image processing layer completes image processing on one dimension and obtains intermediate image data in one dimension, the first image processing layer is used to transmit the intermediate image data in one dimension to the second image processing layer; when the second image processing layer receives each intermediate data in one dimension, the second image processing layer is used to perform image processing on the received intermediate image data in one dimension.

2. The image processing circuit according to claim 1, wherein The image signal processing chip includes a first output interface, the data cache element includes a first input interface and a second output interface, and the image enhancement chip includes a second input interface; The first output interface is connected to the first input interface, and the second output interface is connected to the second input interface; The image signal processing chip is also used to, during the process of performing intra-frame block processing on the initial image data, each time a data block is processed, transmit the data block to the data cache element through the first output interface; The data cache element is also used to receive each data block transmitted by the image signal processing chip through the first input interface and cache each data block; The image enhancement chip is also used to, each time a data block is cached by the data cache element, obtain each data block from the data cache element through the second input interface and perform image processing on the obtained data block.

3. The image processing circuit according to claim 1, wherein The image enhancement chip includes an image processing unit and at least two data cache units with different data processing performances, and the image processing unit is connected to each data cache unit; The image processing unit is used to perform image processing on at least two data blocks cached by the data cache element and store each processed data block into the data cache unit; When a temporary variable is generated during the process of the image processing unit processing the at least two data blocks, the image processing unit is also used to store the temporary variable in the data cache unit corresponding to the usage frequency of the temporary variable; Among them, the usage frequency of the temporary variable is positively correlated with the data processing performance of the data cache unit.

4. The image processing circuit according to claim 1, characterized in that, The data cache element includes a static random access memory.

5. An image processing apparatus, characterized in that, Comprising the image processing circuit according to any one of claims 1-4.

6. An image processing method, applied to the image processing apparatus according to claim 5, characterized in that, The method includes: The image signal processing chip performs intra-frame block processing on the initial image data to obtain at least two data blocks; The data cache element caches at least two data blocks processed by the image signal processing chip; The image enhancement chip performs image processing on at least two data blocks cached by the data cache element to obtain target image data.

7. The method according to claim 6, characterized in that, The image signal processing chip includes a first output interface, the data cache element includes a first input interface and a second output interface, and the image enhancement chip includes a second input interface; The first output interface is connected to the first input interface, and the second output interface is connected to the second input interface; The image signal processing chip performs intra-frame block processing on the initial image data to obtain at least two data blocks, including: During the process of the image signal processing chip performing intra-frame block processing on the initial image data, each time a data block is processed, the data block is transmitted to the data cache element through the first output interface; The data cache element caches at least two data blocks processed by the image signal processing chip, including: The data cache element receives each data block transmitted by the image signal processing chip through the first input interface and caches each data block; The image enhancement chip performs image processing on at least two data blocks cached by the data cache element, including: In the case where the data cache element caches each data block, the image enhancement chip obtains each data block from the data cache element through the second input interface and performs image processing on the obtained data block.

8. The method according to claim 6, wherein The image enhancement chip includes an image processing unit and at least two data cache units with different data processing performances, and the image processing unit is connected to each data cache unit; The image enhancement chip performs image processing on at least two data blocks cached by the data cache element, including: The image processing unit performs image processing on at least two data blocks cached by the data cache element and stores each processed data block in the data cache unit; When a temporary variable is generated during the process of the image processing unit processing the at least two data blocks, the image processing unit stores the temporary variable in the data cache unit corresponding to the usage frequency of the temporary variable; Among them, the usage frequency of the temporary variable is positively correlated with the data processing performance of the data cache unit.

9. The method according to claim 6, wherein The data block includes image processing in n dimensions, where n is an integer greater than 1; the image enhancement chip includes an image processing unit, and the image processing unit includes at least two image processing layers, and the at least two image processing layers are connected in sequence; The image enhancement chip performs image processing on at least two data blocks cached by the data cache element, including: The at least two image processing layers respectively perform different types of image processing on the image processing in the n dimensions; Wherein, the output of the first image processing layer in any two adjacent image processing layers is the input of the second image processing layer, and when the first image processing layer completes the image processing of one dimension and obtains the intermediate image data of one dimension, the first image processing layer is configured to transmit the intermediate image data of one dimension to the second image processing layer; when the second image processing layer receives each piece of the intermediate data of one dimension, the second image processing layer is configured to perform image processing on the received intermediate image data of one dimension.

10. The method according to any one of claims 6 to 9, characterized in that The data cache includes a static random access memory.

11. An electronic device, characterized in that, Comprising the image processing circuit according to any one of claims 1 to 4, a processor, and a memory, the memory stores a program or instruction that can be run on the processor, and when the program or instruction is executed by the processor, the steps of the image processing method according to any one of claims 6 to 10 are implemented.

12. An image processing chip, characterized in that, The image processing chip includes a processor and a communication interface, the communication interface is coupled to the processor, the communication interface is used to transmit image data, and the processor is used to run a program or instruction to implement the steps performed by the image enhancement chip in the image processing method according to any one of claims 6 to 10.

13. A processor chip, characterized in that, The processor chip includes a processor and a communication interface, the communication interface is coupled to the processor, the communication interface is used to transmit image data, and the processor is used to run a program or instruction to implement the steps performed by the image signal processing chip in the image processing method according to any one of claims 6 to 10.

Images