Display frame rate adjustment method and device, terminal and storage medium

Abstract

Embodiments of the present application provide a display frame rate adjustment method and device, a terminal and a storage medium. The method comprises: receiving a frame rate adjustment instruction, wherein the frame rate adjustment instruction indicates that the display frame rate is adjusted to a second frame rate; receiving an image frame according to a first period length of a vertical synchronization signal VSYNC corresponding to a current first frame rate; performing frame processing on the received image frame to obtain a frame-processed image frame, wherein the frame processing comprises: frame insertion processing or frame extraction processing; when the frame rate of the frame-processed image frame is adjusted to the second frame rate, adjusting the period length of the VSYNC from the first period length to a second period length corresponding to the second frame rate, so as to adjust the display frame rate to the second frame rate, thereby masking the obvious frame drop problem in the period length adjustment process of the VSYNC and reducing the stuttering phenomenon caused by sudden adjustment.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display frame rate adjustment method, apparatus, terminal and storage medium. Background Technology

[0002] Frame rate, also known as refresh rate, indicates how many times the screen image is redrawn per second, or the number of times the screen refreshes per second, measured in Hz (Hertz). A higher refresh rate results in a smoother and more realistic display. However, a high refresh rate significantly increases the image processing speed and workload of the terminal product, placing a great deal of scheduling pressure and load on the terminal during use. It also leads to greater power consumption, greatly shortening the usable time of a single charge.

[0003] Therefore, related products typically employ dynamic refresh rates to save power and reduce terminal load. For example, if a terminal is set to a refresh rate of 120Hz, it will automatically switch to 60Hz when entering a video application. However, dynamic refresh rates require dynamically adjusting the period length of the vertical synchronization signal VSYNC, and the adjustment of the VSYNC period length can easily lead to stuttering due to frame drops. Summary of the Invention

[0004] In view of this, the present disclosure provides a display frame rate adjustment method and apparatus, terminal and storage medium.

[0005] According to a first aspect of the present disclosure, a display frame rate adjustment method is provided, comprising:

[0006] Receive a frame rate adjustment command, wherein the frame rate adjustment command indicates that the display frame rate is adjusted to a second frame rate;

[0007] Image frames are received based on the first cycle length of the vertical synchronization signal VSYNC corresponding to the current first frame rate.

[0008] The received image frames are processed to obtain processed image frames, wherein the frame processing includes: frame interpolation or frame extraction.

[0009] When the frame rate of the image frame after frame processing is adjusted to the second frame rate, the period length of VSYNC is adjusted from the first period length to the second period length corresponding to the second frame rate, so as to adjust the display frame rate to the second frame rate.

[0010] In one embodiment, the step of performing frame processing on the received image frame to obtain a frame-processed image frame includes:

[0011] If the first frame rate is greater than the second frame rate, the received image frame is subjected to frame extraction processing to obtain the processed image frame.

[0012] If the first frame rate is less than the second frame rate, the received image frame is interpolated to obtain the processed image frame.

[0013] In one embodiment, the method further includes:

[0014] Obtain the frame processing period and the target number of frames corresponding to the frame processing period, wherein the target number of frames is different for different frame processing periods;

[0015] The step of performing frame processing on the received image frame to obtain the processed image frame includes:

[0016] The received image frames are subjected to frame extraction or frame interpolation processing according to the target number of frames to obtain the processed image frames.

[0017] In one embodiment, the step of performing frame extraction or frame interpolation on the received image frames according to the target frame number to obtain the processed image frames includes:

[0018] Determine the number of processing frames corresponding to the frame processing period, wherein the number of processing frames increases as the time of the frame processing period increases;

[0019] Based on the number of processing frames, the received image frames are subjected to frame extraction or frame insertion processing according to the target number of frames to obtain the processed image frames.

[0020] In one embodiment, the number of processing frames is determined based on the frame processing coefficient corresponding to the frame processing period and a preset frame processing step size, wherein the frame processing coefficient increases as the time of the frame processing period increases.

[0021] In one embodiment, the frame processing coefficient corresponding to the frame processing cycle is determined by the absolute value of the frame rate difference between the actual frame rate of the previous frame processing cycle and the second frame rate. The smaller the absolute value of the frame rate difference, the larger the frame processing coefficient.

[0022] In one embodiment, the method of performing frame extraction or frame interpolation on received image frames based on the target number of processed frames includes at least one of the following:

[0023] Randomly select or insert several image frames for processing within the frame processing cycle;

[0024] Starting from the first preset position, several image frames are randomly selected or inserted for processing within the frame processing cycle.

[0025] With the second preset position as the termination position, several image frames are randomly selected or inserted for processing within the frame processing cycle.

[0026] Starting from the third preset position, the preset step size is the number of frames between the extracted or inserted image frames, and the number of image frames to be extracted or inserted within the frame processing cycle.

[0027] Starting from the fourth preset position, several image frames are extracted or inserted within the frame processing cycle. The number of frames between two adjacent extractions or insertions increases with time.

[0028] Starting from the fifth preset position, several image frames are extracted or inserted within the frame processing cycle. The number of frames between two adjacent extractions or insertions decreases as time increases.

[0029] According to a second aspect of the present disclosure, a display frame rate adjustment device is provided, comprising:

[0030] The first receiving module is used to receive a frame rate adjustment command, wherein the frame rate adjustment command indicates that the display frame rate is adjusted to a second frame rate;

[0031] The second receiving module is used to receive image frames according to the first cycle length of the vertical synchronization signal VSYNC corresponding to the current first frame rate.

[0032] A frame processing module is used to perform frame processing on the received image frames to obtain processed image frames, wherein the frame processing includes frame insertion processing or frame extraction processing.

[0033] The adjustment module is used to adjust the period length of the VSYNC from the first period length to the second period length corresponding to the second frame rate when the frame rate of the image frame after frame processing is adjusted to the second frame rate, so as to adjust the display frame rate to the second frame rate.

[0034] In one embodiment, the frame processing module is configured to:

[0035] If the first frame rate is greater than the second frame rate, the received image frame is subjected to frame extraction processing to obtain the processed image frame.

[0036] If the first frame rate is less than the second frame rate, the received image frame is interpolated to obtain the processed image frame.

[0037] In one embodiment, the apparatus further includes:

[0038] The acquisition module is used to acquire the frame processing period and the target number of frames corresponding to the frame processing period, wherein the target number of frames corresponding to different frame processing periods is different.

[0039] The frame processing module is used to perform frame extraction or frame insertion processing on the received image frames according to the target number of frames, so as to obtain the processed image frames.

[0040] In one embodiment, the frame processing module includes:

[0041] A determining unit is used to determine the number of processing frames corresponding to the frame processing period, wherein the number of processing frames increases as the time of the frame processing period increases.

[0042] The frame processing unit is used to perform frame extraction or frame insertion processing on the received image frames based on the number of processing frames and the target number of frames, so as to obtain the image frames after frame processing.

[0043] According to a third aspect of the present disclosure, a terminal is provided, the terminal being the apparatus described in the second aspect.

[0044] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided storing executable instructions for implementing the method described in the first aspect when executed by a processor.

[0045] The display frame rate adjustment method, apparatus, terminal, and storage medium provided in this disclosure, after receiving a frame rate adjustment command, continue to receive image frames according to the first cycle length of the vertical synchronization signal VSYNC corresponding to the current first frame rate; and perform frame processing on the received image frames until the frame rate of the processed image frames is adjusted to the target frame rate (second frame rate). Then, the cycle length of VSYNC is adjusted from the first cycle length to the second cycle length corresponding to the target frame rate, thereby adjusting the display frame rate to the second frame rate. In the frame rate adjustment process, this disclosure embodiment performs frame processing on the image frames received based on the current VSYNC cycle length. By gradually adjusting the frame rate of the displayed image frames to the target frame rate before adjusting the VSYNC cycle length, the obvious frame drop problem during the VSYNC cycle length adjustment process is distributed across each frame processing step. This can mask the obvious frame drop problem during the VSYNC cycle length adjustment process and reduce stuttering caused by sudden adjustments.

[0046] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the embodiments of this disclosure. Attached Figure Description

[0047] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of embodiments of this disclosure.

[0048] Figure 1This is a diagram illustrating the stuttering phenomenon that occurs during frame rate adjustment in related technologies;

[0049] Figure 2 This is a flowchart illustrating a first display frame rate adjustment method according to an exemplary embodiment;

[0050] Figure 3 This is a flowchart illustrating a second display frame rate adjustment method according to an exemplary embodiment;

[0051] Figure 4 This is a flowchart illustrating a third display frame rate adjustment method according to an exemplary embodiment;

[0052] Figure 5 This is a flowchart illustrating a fourth display frame rate adjustment method according to an exemplary embodiment;

[0053] Figure 6 This is a flowchart illustrating a fifth display frame rate adjustment method according to an exemplary embodiment;

[0054] Figure 7 This is a schematic diagram illustrating frame processing during display frame rate adjustment according to an exemplary embodiment;

[0055] Figure 8 This is a block diagram illustrating a first display frame rate adjustment device according to an exemplary embodiment;

[0056] Figure 9 This is a block diagram illustrating a second display frame rate adjustment device according to an exemplary embodiment;

[0057] Figure 10 This is a block diagram illustrating a third display frame rate adjustment device according to an exemplary embodiment;

[0058] Figure 11 This is a block diagram illustrating the structural composition of a display frame rate adjustment device according to an exemplary embodiment. Detailed Implementation

[0059] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this disclosure as detailed in the appended claims.

[0060] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. The singular forms “a,” “the,” and “the” as used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0061] It should be understood that although the terms first, second, third, etc., may be used to describe various information in embodiments of this disclosure, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first information may also be referred to as second information without departing from the scope of embodiments of this disclosure, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to a determination."

[0062] The display frame rate adjustment method of this disclosure can be applied to terminals that support video playback or image display, including but not limited to mobile phones, tablets, laptops, handheld computers, personal digital assistants (PDAs), portable media players (PMPs), navigation devices, wearable devices, smart bracelets, handheld game consoles, pedometers, smart home appliances, digital TVs, and desktop computers.

[0063] In related technologies, VSYNC (Vertical Synchronization) can be emitted by the terminal's processing chip or simulated by software. The terminal's application layer synthesizes image frames based on VSYNC, while the terminal's DDIC (Display Driver Integrated Circuit) reads images from the image buffer and refreshes them onto the screen based on VSYNC. Thus, VSYNC ensures that the synthesized image frame rate and the display frame rate remain consistent. The display frame rate, also known as the screen refresh rate, refers to the target number of images read from the image buffer and refreshed onto the screen per second; the synthesized image frame rate refers to the target number of image frames synthesized by the terminal per second.

[0064] Understandably, different display frame rates correspond to different VSYNC cycle lengths. Assuming the display frame rate is FPS and the cycle length is period (in milliseconds), the relationship between the display frame rate and the cycle length can be expressed as: FPS = 1000 / period. Here, the VSYNC cycle length refers to the interval between two adjacent VSYNC calls. For example, when the display frame rate is 60Hz, the corresponding cycle length is approximately 16.666ms; when the display frame rate is 90Hz, the corresponding cycle length is approximately 11.111ms, and so on.

[0065] The screen refresh process involves refreshing each line from left to right (horizontal scanning) and from top to bottom (vertical scanning). After the entire screen refresh is complete, marking the end of one vertical refresh cycle, there is a brief pause during which a VSYNC signal is emitted. VSYNC can be considered the metronome for the terminal's screen refresh. The terminal's screen refresh follows a producer-consumer model: all images are drawn by the application layer, composited under the control of the SurfaceFlinger, and then refreshed to the screen by the display driver chip. The entire process is controlled by VSYNC, and all steps must be completed within one VSYNC cycle.

[0066] However, if the frame rate changes during continuous refresh, the overall screen refresh rhythm changes. For example, if the previous VSYNC cycle is short and the next VSYNC cycle is long, coupled with the buffer in the Android system, it's very easy for the image data that has already been synthesized and placed in the buffer to be replaced by the newly synthesized image data due to the change in the VSYNC cycle, thus causing a stutter, as shown in the example. Figure 1 The JANK shown.

[0067] like Figure 1 As shown, the horizontal axis represents time, the CPU and GPU are the executors of different stages of generating image frames, the rectangles corresponding to the CPU and GPU on the horizontal axis represent image frames at different stages, the numbers inside the rectangles are the sequence numbers of the generated image frames, and the length of the rectangle is the processing time of the image frame at that node; Display corresponds to the terminal screen and is the displayer of the image frames; VSync represents the vertical synchronization signal VSYNC.

[0068] Continue to refer to Figure 1Assuming a VSYNC length (i.e., cycle length) is 8.3ms, which is the duration of one frame at a 120Hz refresh rate (i.e., display frame rate), in the 0th VSYNC phase, image frame m+1 in the buffer is sent to the screen display within the VSYNC0 cycle. However, during the VSYNC1 cycle, the VSYNC cycle length is adjusted to 16.6ms, but then immediately adjusted back to 8.3ms. At this instant, image frame m+2 is only sent to the buffer. Therefore, the screen display continuously shows image frame m+1 for both the VSYNC0 and VSYNC1 cycles (i.e., 2 * 8.3ms), resulting in a noticeable frame skipping. Furthermore, in practical applications, due to the code logic during the synchronization of system hardware and software VSYNC, more than one frame often gets stuck, creating a junk effect during frame adjustment. This junk effect is particularly severe during frame downsizing.

[0069] In this embodiment of the present disclosure, after receiving the frame rate adjustment command, the terminal still synthesizes and reads image frames based on the VSYNC corresponding to the first frame rate before adjustment. At the same time, during this process, the read image frames are further processed by frame interpolation or frame extraction and then refreshed on the screen. When the frame rate of the image frame refreshed on the screen is adjusted to the second frame rate, the period length of VSYNC is adjusted from the first period length to the second period length corresponding to the second frame rate. Correspondingly, the terminal also sends VSYNC based on the second period length, thereby realizing the synthesis and reading of image frames based on the VSYNC corresponding to the second frame rate.

[0070] Specifically, such as Figure 2 As shown, this exemplary embodiment provides a display frame rate adjustment method, including:

[0071] Step S101: Receive a frame rate adjustment command, wherein the frame rate adjustment command indicates that the display frame rate is adjusted to the second frame rate;

[0072] Step S102: Receive image frames according to the first cycle length of the vertical synchronization signal VSYNC corresponding to the current first frame rate;

[0073] Step S104: Perform frame processing on the received image frame to obtain a processed image frame, wherein the frame processing includes: frame insertion processing or frame extraction processing.

[0074] Step S105: When the frame rate of the image frame after frame processing is adjusted to the second frame rate, the period length of VSYNC is adjusted from the first period length to the second period length corresponding to the second frame rate, so as to adjust the display frame rate to the second frame rate.

[0075] In this embodiment, the frame rate adjustment command can be issued based on a frame rate adjustment event or periodically. For example, a frame rate adjustment command can be triggered when the terminal starts or wakes up an application, or when the current application switches to the next application. Alternatively, a trigger period can be set, and the actual display frame rate for each trigger period can be counted. If the display frame rate within the trigger period meets a preset condition (e.g., the actual display frame rate is greater than a preset maximum display frame rate), then a frame rate adjustment command is triggered. Of course, in addition to the triggering methods listed above, other methods can be used to trigger the frame rate adjustment command; this embodiment does not impose any limitations.

[0076] After the terminal's processing chip receives the frame rate adjustment instruction from the upper layer (e.g., the application layer) to adjust the display frame rate to the second frame rate, the processing chip does not directly adjust the period length of the VSYNC signal to adjust the display frame rate to the second frame rate. Instead, it continues to send VSYNC signals at the first period length corresponding to the first frame rate. The display driver chip then continues to receive image frames from the application layer according to the first period length of the VSYNC signal corresponding to the first frame rate, that is, it receives image frames at the first period length frequency.

[0077] Here, during image display, a scanning method is used to display the image data in the display cache line by line. Scanning typically proceeds from left to right, and scanning all lines of the terminal's screen constitutes one image frame. During scanning, after scanning one frame, it needs to return to the first line to begin the next cycle of scanning. There is a time gap during this process; this time gap is the switching point between two image frames. This switching point can be controlled by a generated VSYNC signal. Each time the terminal's display driver chip receives this VSYNC signal, it displays the image data in the display cache on the screen, thereby controlling the display of each image frame.

[0078] Then, the image frames received from the application layer at a frequency of the first cycle length are subjected to frame interpolation or frame extraction to obtain the processed image frames. The processed image frames are the final image frames refreshed on the screen. By interpolating or extracting frames, the actual display frame rate refreshed on the screen is changed.

[0079] Finally, when the actual display frame rate refreshed on the screen is adjusted to the second frame rate, the period length of VSYNC is adjusted from the first period length to the second period length. Accordingly, the processing chip adjusts to send VSYNC with the second period length corresponding to the second frame rate, and the display driver chip receives image frames from the application layer according to the second period length.

[0080] For example, a frame rate adjustment command instructs the display frame rate to be adjusted from a first display frame rate of 120Hz to a second display frame rate of 60Hz. Correspondingly, the first cycle length of VSYNC for the first display frame rate is approximately 8.333ms, and the second cycle length of VSYNC for the second display frame rate is approximately 16.666ms. After receiving this frame rate adjustment command, the processing chip continues to send VSYNC signals with a cycle of 8.333ms. The display driver chip continues to receive image frames from the application layer with a cycle of 8.333ms and performs frame extraction processing on the received image frames. When the cycle length of the extracted image frames is adjusted to the second cycle length of 16.666ms, the cycle length of VSYNC is adjusted from the first cycle length to the second cycle length corresponding to the second frame rate. That is, the processing chip sends VSYNC signals with a cycle of 16.666ms, and the display driver chip receives image frames from the application layer with a corresponding cycle of 16.666ms.

[0081] For example, a frame rate adjustment command instructs the display frame rate to be adjusted from a first display frame rate of 60Hz to a second display frame rate of 120Hz. Correspondingly, the first cycle length of VSYNC for the first display frame rate is approximately 16.666ms, and the second cycle length of VSYNC for the second display frame rate is approximately 8.333ms. After receiving this frame rate adjustment command, the processing chip continues to send VSYNC signals with a cycle of 16.666ms. The display driver chip continues to receive image frames from the application layer with a cycle of 16.666ms and performs frame extraction processing on the received image frames. When the cycle length of the extracted image frames is adjusted to the second cycle length of 8.333ms, the cycle length of VSYNC is adjusted from the first cycle length to the second cycle length corresponding to the second frame rate. That is, the processing chip sends VSYNC signals with a cycle of 8.333ms, and the display driver chip receives image frames from the application layer with a corresponding cycle of 8.333ms.

[0082] The display frame rate adjustment method, apparatus, terminal, and storage medium provided in this disclosure, after receiving a frame rate adjustment command, continue to receive image frames according to the first cycle length of VSYNC corresponding to the current first frame rate; and perform frame processing on the received image frames until the frame rate of the frame-processed image frames is adjusted to the target frame rate (second frame rate). Then, the cycle length of VSYNC is adjusted from the first cycle length to the second cycle length corresponding to the target frame rate, thereby adjusting the display frame rate to the second frame rate. In the frame rate adjustment process, this disclosure embodiment performs frame processing on the image frames received based on the current VSYNC cycle length. By gradually adjusting the frame rate of the displayed image frames to the target frame rate before adjusting the VSYNC cycle length, the obvious frame drop problem during the VSYNC cycle length adjustment process is distributed across each frame processing step. This can mask the obvious frame drop problem during the VSYNC cycle length adjustment process and reduce stuttering caused by sudden adjustments.

[0083] In some possible implementations, in step S104 above, when performing frame processing on the image frames received from the application layer according to the first period length VSYNC, the frame extraction or frame insertion processing on the image frames received from the application layer can be determined according to the relationship between the current first frame rate and the second frame rate.

[0084] Specifically, if the first frame rate is greater than the second frame rate, the received image frame is subjected to frame extraction processing to obtain the image frame after frame processing.

[0085] If the first frame rate is less than the second frame rate, the received image frame is interpolated to obtain the processed image frame.

[0086] For example, if the first frame rate is 120Hz and the second frame rate is 80Hz, then the image frames received from the application layer by VSYNC with a first period length of 8.333ms corresponding to the first frame rate are subjected to frame extraction. By extracting frames, the period length of the actual displayed image frames is increased, so that the period length of the actual displayed image frames is adjusted to 12.5ms corresponding to the second frame rate of 80Hz.

[0087] For example, if the first frame rate is 60Hz and the second frame rate is 80Hz, then the image frames received from the application layer by VSYNC with a first period length of 16.666ms corresponding to the first frame rate are subjected to frame interpolation. By interpolating the frames, the period length of the actual displayed image frames is reduced, so that the period length of the actual displayed image frames is adjusted to 12.5ms corresponding to the second frame rate of 80Hz.

[0088] Furthermore, if the first frame rate is equal to the second frame rate, the received image frames can be processed by frame extraction or frame insertion, or no processing can be performed on the received image frames.

[0089] In some possible implementations, such as Figure 3 As shown, the method further includes:

[0090] Step S103: Obtain the frame processing period and the target number of frames corresponding to the frame processing period, wherein the target number of frames corresponding to different frame processing periods is different.

[0091] Step S104 includes:

[0092] Step S104': Perform frame extraction or frame insertion processing on the received image frames according to the target frame number to obtain the processed image frames.

[0093] In this embodiment, before performing frame processing on the image frames received from the application layer according to the first period length of VSYNC, the frame processing period and the target number of frames corresponding to the frame processing period are also obtained. Based on the frame processing period and the target number of frames corresponding to it, the image frames received from the application layer are processed so that the number of frames of the processed image frames is equal to the target number of frames corresponding to the frame processing period.

[0094] Here, the frame processing period and the target number of frames corresponding to the frame processing period can be parameters pre-stored in the terminal, or the frame processing period can be obtained through external input, and then the target number of frames corresponding to the frame processing period can be further determined based on the frame processing period.

[0095] Understandably, the smaller the frame processing period is set, the faster the frame rate of the processed image frame will be adjusted to the second frame rate. Correspondingly, because the frame insertion or extraction speed is too fast during frame processing, the smoothness of the image presented to the user will also be affected to some extent.

[0096] Since the number of processed image frames obtained within the frame processing cycle after frame processing is the target number of frames, the frame rate after frame processing is adjusted to the second frame rate. Therefore, the target number of frames is determined by the frame processing cycle and the second frame rate, that is, the target number of frames = frame processing cycle / second frame rate.

[0097] For example: if the second frame rate is 60Hz and the frame processing period is 100ms, then the target number of frames is 6;

[0098] For example: if the second frame rate is 60Hz and the frame processing period is 200ms, then the target number of frames is 12.

[0099] For example, if the second frame rate is 120Hz and the frame processing period is 200ms, then the target number of frames is 24.

[0100] In some possible implementations, step S104' can be step S104": based on the image frames received from the application layer according to the first period length of VSYNC, perform frame extraction or frame insertion processing equal to the target frame number within at least one frame processing period to obtain the processed image frames.

[0101] In this embodiment, frame extraction or frame insertion can be performed within at least one consecutive frame processing cycle to gradually approach and eventually equal the target number of processed image frames.

[0102] For example, the first frame rate is 120Hz, the second frame rate is 60Hz, the frame processing period is 200ms, and the target number of frames is 12. Simultaneously, the number of frames corresponding to the first frame rate within one frame processing period is determined to be 24. Therefore, during frame processing, it can be achieved by performing frame extraction within at least one consecutive frame processing period, gradually approaching and eventually equaling the target number of processed image frames within that period:

[0103] The first method: perform frame extraction within one frame processing cycle, extract 12 image frames within that frame processing cycle, and the number of processed image frames is 1.

[0104] The second method involves performing frame extraction within two consecutive frame processing cycles. In the first frame processing cycle, six image frames are extracted, resulting in a total of 18 image frames. In the second frame processing cycle, twelve image frames are extracted, resulting in a total of 12 image frames.

[0105] The third method involves performing frame extraction within three consecutive frame processing cycles. In the first frame processing cycle, four image frames are extracted, resulting in 20 processed image frames. In the second frame processing cycle, eight image frames are extracted, resulting in 16 processed image frames. In the third frame processing cycle, twelve image frames are extracted, resulting in 12 processed image frames.

[0106] The fourth method involves performing frame extraction within four consecutive frame processing cycles. In the first frame processing cycle, four image frames are extracted, resulting in 20 processed image frames. In the second frame processing cycle, eight image frames are extracted, resulting in 16 processed image frames. In the third frame processing cycle, ten image frames are extracted, resulting in 14 processed image frames. In the fourth frame processing cycle, twelve image frames are extracted, resulting in 12 processed image frames.

[0107] ...

[0108] By performing frame extraction or frame insertion within at least one consecutive frame processing cycle, the number of processed image frames obtained within at least one consecutive frame processing cycle gradually approaches and eventually equals the target number of frames.

[0109] In some possible implementations, such as Figure 4 As shown, step S104' includes:

[0110] Step S1041: Determine the number of processing frames corresponding to the frame processing period, wherein the number of processing frames increases as the time of the frame processing period increases;

[0111] Step S1042: Based on the number of processing frames, perform frame extraction or frame insertion processing on the received image frames according to the target number of frames to obtain the processed image frames.

[0112] The following section will explain the distinction between frame extraction and frame interpolation.

[0113] For frame extraction processing, such as Figure 5 As shown, step S104' includes:

[0114] Step S1041': Determine the number of processing frames corresponding to the frame processing period, wherein the number of processing frames increases as the time of the frame processing period increases;

[0115] Step S1042': Based on the number of frames extracted, perform frame extraction or frame interpolation processing on the received image frames according to the target number of frames to obtain the processed image frames.

[0116] Here, one frame extraction cycle is also one frame processing cycle, and the number of frames extracted is the number of frames processed.

[0117] In this embodiment, when performing frame-skipping processing continuously through multiple frame-skipping cycles, it is necessary to determine the number of frames skipped corresponding to each frame-skipping cycle. For example, if the first frame rate is 120Hz, the second frame rate is 60Hz, the frame processing cycle is 200ms, and the target number of frames is 12, and it is also determined that the number of frames corresponding to the first frame rate within one frame processing cycle is 24, then:

[0118] The number of frames extracted in the first frame extraction cycle is 4, and the number of image frames after frame extraction is 20.

[0119] The number of frames extracted in the second frame extraction cycle is 8, and the number of image frames after frame extraction is 16.

[0120] The number of frames extracted in the third frame extraction cycle is 10, and the number of image frames after frame extraction is 14.

[0121] The number of frames extracted in the fourth frame extraction cycle is 12, and the number of image frames after frame extraction is 12. At this point, the number of image frames after frame extraction is equal to the target number of frames, and the frame extraction process ends.

[0122] In this embodiment, by increasing the number of frames drawn in each frame-drawing cycle over time, the number of frames drawn can be gradually increased, and correspondingly, the number of image frames displayed on the screen is gradually reduced, thus ensuring the smoothness of the screen display as much as possible.

[0123] In some possible implementations, the number of frames drawn per frame drawing period increases by an equal amount over time.

[0124] In some possible implementations, the number of frames is determined based on the frame extraction coefficient corresponding to the frame extraction period and a preset frame extraction step size, wherein the frame extraction coefficient increases as the time of the frame extraction period increases.

[0125] For example, N i =k i *L, where N i k is the number of frames drawn in the i-th frame drawing period. i Let k be the frame extraction coefficient corresponding to the i-th frame extraction period, L be the preset frame extraction step size, and k i+1 >k i .

[0126] In some possible implementations, the frame-sampling coefficient corresponding to the frame-sampling period is determined by the absolute value of the frame rate difference between the actual frame rate of the previous frame-sampling period and the second frame rate. The smaller the absolute value of the frame rate difference, the larger the frame-sampling coefficient.

[0127] For example, the frame rate difference is Q. i That is, the absolute value of the difference between the actual frame rate after frame extraction processing in the (i-1)th frame extraction cycle and the second frame rate, where k is the frame extraction coefficient. i =p / Q i p is a constant greater than 0.

[0128] In this embodiment, during the process of extracting frames from the image frames displayed on the screen, the extraction frequency is gradually increased so that the frame rate of the displayed image frames gradually approaches the second frame rate, making the entire extraction process relatively smooth and avoiding sudden changes that could cause noticeable stuttering.

[0129] In some possible implementations, after determining the number of frames to be drawn for each drawing period, the image frame at the corresponding position within the drawing period can be drawn in at least one of the following ways:

[0130] Several image frames are randomly selected within the frame extraction period;

[0131] Starting from the first preset position, several image frames are randomly selected within the frame extraction period. For example, the first preset position is the first 10% of the image frames within the frame extraction period. Assuming there are a total of 20 image frames within the frame extraction period, the first preset position can be the first image frame or the second image frame.

[0132] Using the second preset position as the termination position, several image frames are randomly selected within the frame extraction period. For example, the second preset position is the last 10% of the image frames within the frame extraction period. Assuming there are a total of 20 image frames within the frame extraction period, the second preset position can be the 19th or 20th image frame.

[0133] Starting from the third preset position, the preset step size is the interval number of image frames to be extracted. Within the extraction period, a number of image frames are extracted. For example, if the third preset position is the first 10% of the image frames within the extraction period, the preset step size is determined based on the total number of image frames and the number of extracted frames within the extraction period. Assuming there are a total of 20 image frames within the extraction period and 4 extracted frames, the preset step size is the quotient of the total number of image frames and the number of extracted frames, which is 5. Taking the third preset position as the second image frame as an example, the 2nd, 7th, 12th, and 17th image frames within the extraction period will be extracted sequentially.

[0134] Starting from the fourth preset position, a number of image frames are extracted within the extraction period. The number of frames between two consecutive extractions increases with the extraction time. For example, if the fourth preset position is the first 10% of the image frames in the extraction period, and there are a total of 20 image frames in the extraction period, with 4 frames extracted, the initial frame interval is 2 frames. After that, the frame interval increases by 3 frames for each extraction. Taking the fourth preset position as the second image frame as an example, the 2nd, 4th, 9th, and 17th image frames in the extraction period will be extracted sequentially.

[0135] Starting from the fifth preset position, several image frames are extracted within the extraction period. The interval between two adjacent extractions decreases as the extraction time increases. For example, if the fifth preset position is the first 10% of the image frames in the extraction period, and there are a total of 20 image frames in the extraction period, with 4 frames extracted, and an initial frame interval of 8 frames, then the interval decreases by 2 frames for each subsequent extraction. Taking the fifth preset position as the second image frame as an example, the 2nd, 10th, 16th, and 20th image frames in the extraction period will be extracted sequentially.

[0136] In some possible implementations, the extracted image frames are non-critical frames. If the extracted frame determined by the above method is a critical frame, then the most recent non-critical frame after that frame is extracted instead. Non-critical frames here may include B-frames and / or P-frames within the video. Here, a P-frame refers to an encoded image that compresses the amount of transmitted data by sufficiently reducing the temporal redundancy information of previously encoded frames in the image sequence; it is also called a prediction frame. A B-frame refers to an encoded image that compresses the amount of transmitted data by considering both the temporal redundancy information between it and previously encoded frames in the source image sequence, as well as the temporal redundancy information between it and subsequently encoded frames in the source image sequence; it is also called a bidirectional prediction frame.

[0137] For frame interpolation processing, such as Figure 6 As shown, step S104' includes:

[0138] Step S1041”: Determine the number of interpolated frames corresponding to each interpolation period, wherein the number of interpolated frames increases as the time of the interpolation period increases;

[0139] Step S1042”: Based on the number of interpolated frames, the received image frames are interpolated according to the interpolation period equal to the number of target frames to obtain the processed image frames.

[0140] Here, one frame interpolation period is also one frame processing period, and the number of interpolated frames is the number of frames processed.

[0141] In this embodiment, when performing frame interpolation processing continuously through multiple interpolation cycles, it is necessary to determine the number of interpolated frames corresponding to each interpolation cycle. For example, if the first frame rate is 60Hz, the second frame rate is 120Hz, the frame processing cycle is 200ms, and the target number of frames is 24, and it is also determined that the number of frames corresponding to the first frame rate within one frame processing cycle is 12, then:

[0142] The number of interpolated frames in the first interpolation cycle is 4, and the number of image frames after interpolation is 16.

[0143] The number of interpolated frames in the second interpolation cycle is 8, and the number of image frames after interpolation is 20.

[0144] The number of interpolated frames in the third interpolation cycle is 10, and the number of image frames after interpolation is 22.

[0145] The fourth interpolation cycle has 12 interpolated frames, resulting in 24 image frames after interpolation. At this point, the number of image frames after interpolation equals the target number of frames, and the interpolation process ends.

[0146] In this embodiment, the image frame inserted during frame interpolation can be one or more of the most recent image frames received from the application layer.

[0147] In this embodiment, by increasing the number of interpolated frames corresponding to each interpolation period over time, the number of interpolated frames can be gradually increased, and correspondingly, the number of image frames displayed on the screen gradually increases, thus ensuring the continuity of the screen display as much as possible.

[0148] In some possible implementations, the number of interpolated frames corresponding to each interpolation period increases by an equal amount over time.

[0149] In some possible implementations, the number of interpolated frames is determined based on the interpolation coefficient corresponding to the interpolation period and a preset step size, wherein the interpolation coefficient increases as the time of the interpolation period increases.

[0150] For example, M i =l i *S, where M i Let l be the number of interpolated frames corresponding to the i-th interpolation period. i Let be the interpolation coefficient corresponding to the i-th interpolation period, and S be the preset interpolation step size, and l i+1 >l i .

[0151] In some possible implementations, the interpolation coefficient corresponding to the interpolation period is determined by the absolute value of the frame rate difference between the actual frame rate of the previous interpolation period and the second frame rate. The smaller the absolute value of the frame rate difference, the larger the interpolation coefficient.

[0152] For example, the frame rate difference is 0. i That is, the absolute value of the difference between the actual frame rate after frame interpolation in the (i-1)th interpolation period and the second frame rate, where l is the interpolation coefficient. i =r / O i r is a constant greater than 0.

[0153] In this embodiment, during the frame interpolation process of the image frames sent to the screen, the interpolation frequency is gradually increased so that the frame rate of the sent image frames gradually approaches the second frame rate, making the entire frame interpolation process relatively smooth and avoiding sudden changes that cause obvious stuttering.

[0154] In some possible implementations, after determining the number of interpolation frames corresponding to each interpolation period, image frames at the corresponding positions within the interpolation period can be inserted in at least one of the following ways:

[0155] Several image frames are randomly inserted within the interpolation period;

[0156] Starting from the first preset position, several image frames are randomly inserted within the interpolation period. For example, the first preset position is between the first 20% of the image frames within the interpolation period. Assuming there are a total of 20 image frames within the interpolation period, the first preset position can be between the first image frame and the fourth image frame.

[0157] Using the second preset position as the termination position, several image frames are randomly inserted within the interpolation period. For example, the second preset position is the last 20% of the image frames within the interpolation period. Assuming there are a total of 20 image frames within the interpolation period, the second preset position can be between the 16th and 20th image frames.

[0158] Starting from the third preset position, the preset step size is the number of frames between the inserted image frames. The number of image frames inserted within the interpolation period is a certain number. For example, the third preset position is the first 20% of the image frames within the interpolation period. The preset step size is determined based on the total number of image frames and the number of frames extracted within the interpolation period. Assuming there are a total of 20 image frames within the interpolation period and 4 frames are inserted, the preset step size is the quotient of the total number of image frames and the number of frames inserted, which is 5. Taking the third preset position between the 2nd and 3rd image frames as an example, the insertion will proceed sequentially between the 2nd and 3rd image frames, between the 7th and 8th image frames, between the 12th and 13th image frames, and between the 17th and 18th image frames within the interpolation period.

[0159] Starting from the fourth preset position, several image frames are inserted within the interpolation period. The interval between two adjacent inserted image frames increases with the insertion time. For example, if the fourth preset position is the first 20% of the image frames in the interpolation period, and there are a total of 20 image frames in the interpolation period, with 4 interpolated frames and an initial frame interval of 2 frames, then the frame interval increases by 3 frames for each subsequent insertion. Taking the second and third image frames as an example, image frames will be inserted sequentially between the second and third image frames, between the fourth and fifth image frames, between the ninth and tenth image frames, and between the seventeenth and eighteenth image frames within the interpolation period.

[0160] Starting from the fifth preset position, several image frames are inserted within the interpolation period. The interval between two adjacent inserted image frames decreases as the insertion time increases. For example, the tenth preset position is the first 20% of the image frames in the interpolation period. Assuming there are a total of 20 image frames in the interpolation period, and 4 interpolation frames are inserted, the initial frame interval is 8 frames. After that, the interval decreases by 2 frames for each inserted image frame. Taking the tenth preset position as the interval between the second and third image frames as an example, image frames will be inserted sequentially between the second and third image frames, between the tenth and eleventh image frames, between the sixteenth and seventeenth image frames, and between the twentyth and twenty-first image frames within the interpolation period.

[0161] In some possible implementations, the inserted image frame is a copy of the previous image frame that is closest to the insertion position.

[0162] It should be understood that, in the above embodiments, the execution order of the various steps of the display frame rate adjustment method is not strictly limited, and these steps can be executed in other orders unless explicitly stated herein. Moreover, at least some steps in the above embodiments may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0163] The following provides a specific example in conjunction with any of the above embodiments:

[0164] To address the stuttering issues that occur during frame adjustment and to ensure smoother image display, this exemplary embodiment employs the following display frame rate adjustment method:

[0165] A1: When the screen is refreshing at a stable frame rate, a frame rate adjustment event occurs randomly, requiring the display frame rate to be adjusted. Suppose that the screen is refreshing at a high frame rate (first frame rate) at this time, and the upper layer (e.g., the application layer) requires the screen to refresh at a low frame rate (second frame rate).

[0166] A2: After the real-time operating system (kernel) receives the upper layer's frame rate adjustment request S1 (i.e., frame rate adjustment instruction), it immediately synchronizes the frame rate adjustment request S1 to the display driver chip and enters the delayed frame adjustment mode M1 to wait for the display driver chip's response.

[0167] A3: After receiving the frame rate reduction adjustment request S1, the display driver chip will maintain the current VSYNC cycle. For the short VSYNC cycle (first cycle length) image sent by the application layer, it will gradually extract frames according to the preset step size of the DDIC. There are two attributes that need to be defined for frame extraction: frame extraction step size and frame extraction position.

[0168] A31: Frame skipping step size (i.e., frame skipping number) refers to the step size per second by which the refresh rate decreases from a high refresh rate to a low refresh rate, reducing the target frame rate. This step size is determined by a coefficient, not a constant. Since the first half of the refresh rate reduction is already at a relatively high refresh rate, frame skipping does not significantly affect the persistence of vision. However, as the frame rate decreases, the number of skipped frames should decrease accordingly; otherwise, the persistence of vision will clearly perceive an increase in the inter-frame interval.

[0169] Therefore, let's define the step size coefficient (i.e., the frame skipping coefficient) as α, the difference between the current frame rate and the target frame rate as y, and time as x. Then, the relationship between the difference between the current frame rate and the target frame rate and time is: y = α x +b, where 0 < a < 1. The interval between frames can be determined by the step size.

[0170] A32: Since the image data received by the DDIC terminal is a data stream, it is impossible to identify the specific image information. Therefore, the position of frame extraction can be determined by methods such as scattered extraction or random extraction.

[0171] A4: The DDIC terminal performs frame skipping operation until the actual display refresh rate drops to the target refresh rate (second frame rate). At this time, it sends a frame skipping completion signal S3 to the real-time operating system to indicate that the frame skipping has been completed and proceeds to the next step of adjusting the VSYNC cycle. After receiving the reply S3 from the DDIC terminal, the real-time operating system sends an acknowledgment signal S4 to the DDIC terminal.

[0172] A5: When the DDIC receives the confirmation signal S4 from the real-time operating system, it officially modifies the hardware VSYNC to the VSYNC cycle corresponding to the target refresh rate. The entire screen refresh cycle is officially changed. At the same time, the screen is already running according to the target refresh rate, so the aforementioned JANK phenomenon will absolutely not occur.

[0173] The VSYNC interval is a hardware synchronization signal for screen refresh rate control. In this exemplary embodiment, during frame adjustment, the screen hardware delays the adjustment of the target VSYNC by a set time. When the real-time operating system detects that the VSYNC interval needs to be adjusted from short to long (i.e., when the frame rate decreases), the hardware synchronization signal VSYNC remains unchanged; otherwise, tearing will occur. Simultaneously, the real-time operating system maintains the previous frame rate, while the display driver chip itself, during image refresh, mimics a process similar to backlight dimming, gradually extracting frames from the image sent to the screen by the application layer until the hardware refresh rate actually reaches the target refresh rate. At this point, the screen hardware's VSYNC is changed to the time interval corresponding to the target refresh rate. Since the hardware VSYNC remains unchanged during this process, and only the display driver chip extracts frames from the refreshed content, the frame adjustment process is smooth without noticeable stuttering, ensuring that there is no screen tearing effect.

[0174] like Figure 7As shown, upon receiving a frame rate adjustment command instructing the display frame rate to be adjusted to the second frame rate of 60Hz, while the current first frame rate is 120Hz, based on the display frame rate adjustment method of this application embodiment, the hardware VSYNC maintains its original 8.3ms cycle, and the application layer also continues to synthesize image frames based on the original 8.3ms cycle. However, the image frames sent to the screen display are extracted according to a preset strategy. For example, the image frame m+2 synthesized by the application layer is not sent to the screen display, but instead, image frame m+1 is displayed on the screen display continuously for 2*8.3ms. It can be understood that the impact on screen display caused by frame extraction is more controllable and weaker than the impact caused by directly adjusting the sending cycle of the hardware VSYNC.

[0175] like Figure 8 As shown, this exemplary embodiment also provides a display frame rate adjustment device 10, including:

[0176] The first receiving module 110 is used to receive a frame rate adjustment command, wherein the frame rate adjustment command indicates that the display frame rate is adjusted to a second frame rate;

[0177] The second receiving module 120 is used to receive image frames according to the first cycle length of the vertical synchronization signal VSYNC corresponding to the current first frame rate.

[0178] The frame processing module 140 is used to perform frame processing on the received image frame to obtain a frame-processed image frame, wherein the frame processing includes: frame insertion processing or frame extraction processing.

[0179] The adjustment module 150 is used to adjust the period length of the VSYNC from the first period length to the second period length corresponding to the second frame rate when the frame rate of the image frame after frame processing is adjusted to the second frame rate, so as to adjust the display frame rate to the second frame rate.

[0180] In some possible implementations, the frame processing module 140 is configured to:

[0181] If the first frame rate is greater than the second frame rate, the image frame received from the application layer according to the first period length of VSYNC is subjected to frame extraction processing to obtain the image frame after frame processing.

[0182] If the first frame rate is less than the second frame rate, the image frames received from the application layer according to the first period length of VSYNC are subjected to frame interpolation to obtain the processed image frames.

[0183] In some possible implementations, such as Figure 9 As shown, the device 10 further includes:

[0184] The acquisition module 130 is used to acquire the frame processing period and the target number of frames corresponding to the frame processing period, wherein the target number of frames corresponding to different frame processing periods is different.

[0185] The frame processing module 140 is used to perform frame extraction or frame insertion processing on the received image frames according to the target number of frames to obtain the processed image frames.

[0186] In some possible implementations, such as Figure 10 As shown, the frame processing module 140 includes:

[0187] The determining unit 1401 is used to determine the number of processing frames corresponding to the frame processing period, wherein the number of processing frames increases as the time of the frame processing period increases.

[0188] The frame processing unit 1402 is used to perform frame extraction or frame insertion processing on the received image frames based on the number of processing frames and the target number of frames, so as to obtain the image frames after frame processing.

[0189] This exemplary embodiment also provides a terminal, which includes the apparatus described in any of the above embodiments.

[0190] This exemplary embodiment also provides a computer-readable storage medium storing executable instructions for implementing the method described in any of the above embodiments when executed by a processor.

[0191] The computer-readable storage medium may be a mobile storage device, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, or any other medium capable of storing program code, and may be a non-transient storage medium.

[0192] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0193] In an exemplary embodiment, each module / unit in the device may be implemented by one or more central processing units (CPUs), graphics processing units (GPUs), baseband processors (BPs), application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components to perform the aforementioned methods.

[0194] Figure 11 This is a block diagram illustrating a frame rate adjustment device 800 according to an exemplary embodiment. For example, device 800 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0195] Reference Figure 11 The device 800 may include one or more of the following components: a processing component 802, a memory 804, a power supply component 806, a multimedia component 808, an audio component 810, an input / output (I / O) interface 812, a sensor component 814, and a communication component 816.

[0196] Processing component 802 typically controls the overall operation of device 800, such as operations associated with display, telephone calls, data communication, camera operation, and recording. Processing component 802 may include one or more processors 820 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 802 may include one or more modules to facilitate interaction between processing component 802 and other components. For example, processing component 802 may include a multimedia module to facilitate interaction between multimedia component 808 and processing component 802.

[0197] Memory 804 is configured to store various types of data to support the operation of device 800. Examples of such data include instructions for any application or method operating on device 800, contact data, phonebook data, messages, pictures, videos, etc. Memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0198] Power supply component 806 provides power to various components of device 800. Power supply component 806 may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power to device 800.

[0199] Multimedia component 808 includes a screen that provides an output interface between the device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 808 includes a front-facing camera and / or a rear-facing camera. When the device 800 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0200] Audio component 810 is configured to output and / or input audio signals. For example, audio component 810 includes a microphone (MIC) configured to receive external audio signals when device 800 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 804 or transmitted via communication component 816. In some embodiments, audio component 810 also includes a speaker for outputting audio signals.

[0201] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0202] Sensor assembly 814 includes one or more sensors for providing status assessments of various aspects of device 800. For example, sensor assembly 814 may detect the on / off state of device 800, the relative positioning of components such as the display and keypad of device 800, changes in the position of device 800 or a component of device 800, the presence or absence of user contact with device 800, the orientation or acceleration / deceleration of device 800, and temperature changes of device 800. Sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 814 may also include an accelerometer, a gyroscope, a magnetometer, a pressure sensor, or a temperature sensor.

[0203] Communication component 816 is configured to facilitate wired or wireless communication between device 800 and other devices. Device 800 can access wireless networks based on communication standards, such as WiFi, 4G, or 5G, or combinations thereof. In one exemplary embodiment, communication component 816 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 816 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0204] In an exemplary embodiment, the apparatus 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0205] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 804 including instructions, which can be executed by a processor 820 of the device 800 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0206] Other embodiments of the present disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the embodiments of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed in the present disclosure. The specification and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0207] It should be understood that the embodiments disclosed herein are not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from their scope. The scope of the embodiments disclosed herein is limited only by the appended claims.

Claims

1. A method for adjusting display frame rate, characterized in that, include: Receive a frame rate adjustment command, wherein the frame rate adjustment command indicates that the display frame rate is adjusted to a second frame rate; Image frames are received based on the first cycle length of the vertical synchronization signal VSYNC corresponding to the current first frame rate. The received image frames are processed to obtain processed image frames, wherein the frame processing includes: frame interpolation or frame extraction. When the frame rate of the image frame after frame processing is adjusted to the second frame rate, the period length of the VSYNC is adjusted from the first period length to the second period length corresponding to the second frame rate, so as to adjust the display frame rate to the second frame rate. The step of performing frame processing on the received image frame to obtain the processed image frame includes: Frame processing is performed in each of the multiple consecutive frame processing cycles to obtain the processed image frame. The number of image frames before frame processing is the same in different frame processing cycles, but the number of processed frames is different in different frame processing cycles. The number of processed frames is related to the consecutive arrangement order of the frame processing cycles.

2. The display frame rate adjustment method according to claim 1, characterized in that, The step of performing frame processing on the received image frame to obtain the processed image frame includes: If the first frame rate is greater than the second frame rate, the received image frame is subjected to frame extraction processing to obtain the processed image frame. If the first frame rate is less than the second frame rate, the received image frame is interpolated to obtain the processed image frame.

3. The display frame rate adjustment method according to claim 1, characterized in that, The method further includes: Obtain the plurality of frame processing cycles and the target number of the plurality of frame processing cycles, wherein the target number of the frame processing cycles is different for different frame processing cycles; The step of performing frame processing on the received image frame to obtain the processed image frame includes: The received image frames are subjected to frame extraction or frame interpolation processing according to the target number of frames to obtain the processed image frames.

4. The display frame rate adjustment method according to claim 3, characterized in that, The step of performing frame extraction or frame interpolation processing on the received image frames according to the target frame number to obtain the processed image frames includes: Determine the number of processing frames corresponding to the plurality of frame processing cycles, wherein the number of processing frames increases as the time of the frame processing cycle increases; Based on the number of processing frames, the received image frames are subjected to frame extraction or frame insertion processing according to the target number of frames to obtain the processed image frames.

5. The display frame rate adjustment method according to claim 4, characterized in that, The number of frames to be processed is determined based on the frame processing coefficient corresponding to the frame processing period and the preset frame processing step size, wherein the frame processing coefficient increases as the time of the frame processing period increases.

6. The display frame rate adjustment method according to claim 5, characterized in that, The frame processing coefficient corresponding to the frame processing cycle is determined by the absolute value of the difference between the actual frame rate of the previous frame processing cycle and the second frame rate. The smaller the absolute value of the frame rate difference, the larger the frame processing coefficient.

7. The display frame rate adjustment method according to claim 4, characterized in that, The method of performing frame extraction or frame interpolation on the received image frames based on the number of processed frames and according to the target number of frames includes at least one of the following: Randomly select or insert several image frames for processing within the frame processing cycle; Starting from the first preset position, several image frames are randomly selected or inserted for processing within the frame processing cycle. With the second preset position as the termination position, several image frames are randomly selected or inserted for processing within the frame processing cycle. Starting from the third preset position, the preset step size is the number of frames between the extracted or inserted image frames, and the number of image frames to be extracted or inserted within the frame processing cycle. Starting from the fourth preset position, several image frames are extracted or inserted within the frame processing cycle. The number of frames between two adjacent extractions or insertions increases with time. Starting from the fifth preset position, several image frames are extracted or inserted within the frame processing cycle. The number of frames between two adjacent extractions or insertions decreases as time increases.

8. A display frame rate adjustment device, characterized in that, include: The first receiving module is used to receive a frame rate adjustment command, wherein the frame rate adjustment command indicates that the display frame rate is adjusted to a second frame rate; The second receiving module is used to receive image frames according to the first cycle length of the vertical synchronization signal VSYNC corresponding to the current first frame rate. A frame processing module is used to perform frame processing on the received image frames to obtain processed image frames, wherein the frame processing includes frame insertion processing or frame extraction processing. The adjustment module is used to adjust the period length of the VSYNC from the first period length to the second period length corresponding to the second frame rate when the frame rate of the image frame after frame processing is adjusted to the second frame rate, so as to adjust the display frame rate to the second frame rate. The frame processing module is further configured to perform frame processing in each of a series of consecutive frame processing cycles to obtain the processed image frame. The number of image frames before frame processing is the same in different frame processing cycles, the number of processed frames is different in different frame processing cycles, and the number of processed frames is related to the consecutive arrangement order of the frame processing cycles.

9. The display frame rate adjustment device according to claim 8, characterized in that, The frame processing module is used for: If the first frame rate is greater than the second frame rate, the received image frame is subjected to frame extraction processing to obtain the processed image frame. If the first frame rate is less than the second frame rate, the received image frame is interpolated to obtain the processed image frame.

10. The display frame rate adjustment device according to claim 8, characterized in that, The device further includes: The acquisition module is used to acquire the plurality of frame processing cycles and the target number of the plurality of frame processing cycles, wherein the target number of the different frame processing cycles is different. The frame processing module is used to perform frame extraction or frame insertion processing on the received image frames according to the target number of frames, so as to obtain the processed image frames.

11. The display frame rate adjustment device according to claim 10, characterized in that, The frame processing module includes: A determining unit is used to determine the number of processing frames corresponding to the plurality of frame processing cycles, wherein the number of processing frames increases as the time of the frame processing cycle increases. The frame processing unit is used to perform frame extraction or frame insertion processing on the received image frames based on the number of processing frames and the target number of frames, so as to obtain the image frames after frame processing.

12. A terminal, characterized in that, The terminal includes the apparatus according to any one of claims 8 to 11.

13. A computer-readable storage medium, characterized in that, It stores executable instructions for causing a processor to execute, thereby implementing the method of any one of claims 1 to 7.

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