Semiconductor element and method for forming the same

Abstract

A semiconductor device and a method of forming the same, wherein the method includes forming a patterned dielectric layer including a word line intended region and a pickup neck intended region, the word line intended region and the pickup neck intended region having a first pitch, and the patterned dielectric layer within the pickup neck intended region having a second pitch, wherein the first pitch is less than or equal to the second pitch; forming spacers on sidewalls of the patterned dielectric layer; truncating the spacers of a connection portion of the word line intended region and the spacers of a remaining portion of the word line intended region; forming a mask pattern including a first portion spanning the connection portion and the pickup neck intended region, wherein the spacers of the remaining portion of the word line intended region and the first portion of the mask pattern have a spacing; and forming a dummy structure, a word line, and a pickup neck, wherein the dummy structure is located between the word line and the pickup neck, and a goal of improving process latitude and reducing manufacturing cost is achieved.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device and a method of forming the same, and more particularly to a flash memory. BACKGROUND

[0002] In semiconductor manufacturing, various components are patterned by photolithography and etching processes. As device size continues to shrink, there are still many problems in the manufacturing process of flash memory that need to be improved. Therefore, improving process tolerance and reducing manufacturing cost are the goals that the industry strives to achieve. SUMMARY

[0003] A method of forming a semiconductor device includes providing a substrate having a conductive layer formed thereon; forming a patterned dielectric layer on the conductive layer, the patterned dielectric layer including a word line intended region, a pair of select gate intended regions, wherein the word line intended region is disposed between the select gate intended regions, and a pickup neck intended region surrounding the select gate intended regions, wherein the word line intended region and the pickup neck intended region have a first lateral spacing, and the patterned dielectric layer in the pickup neck intended region has a second lateral spacing, wherein the first lateral spacing is less than or equal to the second lateral spacing; forming spacers on sidewalls of the patterned dielectric layer, wherein after forming the spacers, the patterned dielectric layer is removed; truncating the spacers of a connection portion of the word line intended region and the spacers of a remaining portion of the word line intended region; forming a mask pattern on the spacers, the mask pattern including a first portion laterally spanning the spacers of the connection portion and the spacers of a portion of the pickup neck intended region, wherein the spacers of the remaining portion of the word line intended region and the first portion of the mask pattern have a lateral spacing; and using the mask pattern and the spacers as an etching mask, performing an etching process on the conductive layer to form a dummy structure, a plurality of word lines, a pair of select gates, and a plurality of pickup necks, wherein the dummy structure is laterally positioned between the word lines and the pickup necks.

[0004] A semiconductor device includes a plurality of word lines, a pair of select gates, wherein the word lines are positioned between the select gates, a plurality of pickup necks surrounding the select gates, and a dummy structure laterally positioned between the word lines and the pickup necks, wherein the dummy structure has a lateral spacing from the word lines.

[0005] Due to the gate isolation cut in the previous process, the plurality of word lines and the plurality of pickup necks become a plurality of independent and normally functioning structures, avoiding short circuit caused by conduction. The dummy structure greatly reduces the space of the isolation circuit, reduces the etching load effect of the etching process on the linear structure of the tail end of the plurality of word lines and the pickup necks at the turning point, and also reduces the bowlization or breakage of the linear structure at the turning point. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1A 、 Figure 2A 、 Figure 3A ,Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 7A 、 Figure 8A 、 Figure 9A and Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 are cross-sectional schematic views illustrating intermediate stages of forming a flash memory according to some embodiments of the present application.

[0007] Figure 1B 、 Figure 2B 、 Figure 3B 、 Figure 4B 、 Figure 5B 、 Figure 6B 、 Figure 7B 、 Figure 8B 、 Figure 9B and Figure 6C 、 Figure 7C 、 Figure 8C 、 Figure 9C are cross-sectional schematic views illustrating intermediate stages of forming a flash memory according to some embodiments of the present application.

[0008] REFERENCE NUMERALS

[0009] 10: flash memory

[0010] 10P: pick-up neck predetermined area

[0011] 10S: select gate predetermined area

[0012] 10W: word line predetermined area

[0013] 10W-C: connecting portion

[0014] 20: flash memory

[0015] 20P: pick-up neck predetermined area

[0016] 20S: select gate predetermined area

[0017] 20W: word line predetermined area

[0018] 20W-C: connecting portion

[0019] 100: substrate

[0020] 104: first polymer layer

[0021] 106: patterned first polymer layer

[0022] 108: conductive layer

[0023] 110: patterned conductive layer

[0024] 112: first dielectric layer

[0025] 114: patterned first dielectric layer

[0026] 116: second dielectric layer

[0027] 118: patterned second dielectric layer

[0028] 120: second polymer layer

[0029] 122: patterned second polymer layer

[0030] 124: third dielectric layer

[0031] 126: patterned third dielectric layer

[0032] 128: first antireflective coating

[0033] 130: patterned first antireflective coating

[0034] 134: first mask pattern

[0035] 140: spacer material layer

[0036] 142: spacer

[0037] 150: first photoresist layer

[0038] 154: second antireflective coating

[0039] 160: second mask pattern

[0040] 170: second photoresist layer

[0041] 174: third antireflective coating

[0042] 180: third mask pattern

[0043] 180A: first portion

[0044] 180B: second portion

[0045] 180C: third portion

[0046] 200: dummy structure

[0047] 210: word line

[0048] 220: select gate

[0049] 230: pickup neck

[0050] B-B’: line segment

[0051] C-C’: line segment

[0052] D1: first spacing

[0053] D2: second spacing

[0054] S: spacing DETAILED DESCRIPTION

[0055] Figures 1A-9A 、 Figure 9B and Figure 9C Figures 1A-1C illustrate top views and corresponding cross-sectional views of intermediate stages of forming a flash memory 10 according to some embodiments of the present application. In the present embodiments, the flash memory 10 is a negative-and (“not and”, NAND) flash memory. As shown in Figure 1A, the flash memory 10 includes a plurality of word lines 210, a pair of select gates 220 positioned longitudinally, e.g., in the Y direction, on both sides of and sandwiching the plurality of word lines 210, a plurality of pairs of pick-up necks 230 surrounding the select gates 220, and a dummy structure 200 positioned laterally between the plurality of word lines 210 and the plurality of pairs of pick-up necks 230. Figure 9A

[0056] The dummy structure 200 effectively reduces the etch loading effect at the tail ends of the plurality of word lines 210, avoiding the occurrence of bowing or even breaking. The dummy structure 200 has a lateral spacing S from the plurality of word lines 210, where the spacing S is, for example, between 10 nm and 150 nm. If the spacing S is greater than 150 nm, the isolation of the circuit space can still cause the etch loading effect at the tail ends of the plurality of word lines 210, leading to the occurrence of bowing or even breaking. On the other hand, if the spacing S is less than 10 nm, the process margin is not easy to control, which can cause the dummy structure 200 to physically contact the plurality of word lines 210 and thus to be conductive, resulting in a short circuit. The dummy structure 200 is a non-continuous structure and can be designed in various shapes. In a specific embodiment, the dummy structure 200 can include a plurality of bullet-shaped structures, as shown in Figure 1B. Figure 9A

[0057] Referring to Figure 1C, the plurality of word lines 210, the pair of select gates 220, the plurality of pairs of pick-up necks 230, and the dummy structure 200 can be formed on the substrate 100 in sequence, for example, by a deposition process, such as a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or a chemical vapor deposition (CVD) process. Figure 1A Figure 1A ​​​Only the third dielectric layer 124 is shown in the diagram. A first mask pattern 134, including a word line pre-defined region 10W, a pair of select gate pre-defined regions 10S, and a pickup neck pre-defined region 10P, can then be formed on the third dielectric layer 124. In subsequent processes, multiple word lines 210, a pair of select gates 220, and multiple pairs of pickup necks 230 can be formed in the word line pre-defined region 10W, the select gate pre-defined region 10S, and the pickup neck pre-defined region 10P, respectively. Figure 9A The virtual structure 200 in the middle will be by Figure 1A The pattern defined by the connecting portion 10W-C of the word line pre-defined area 10W and a portion of the select gate pre-defined area 10S is formed. The connecting portion 10W-C includes multiple U-shaped structures that connect every two adjacent strip structures in the word line pre-defined area 10W.

[0058] Continue to refer to Figure 1A The word line pre-defined region 10W is vertically positioned, for example, in the Y direction, between the select gate pre-defined regions 10S. Both the word line pre-defined region 10W and the select gate pre-defined region 10S are laterally positioned, for example, in the X direction, extending towards the pickup neck pre-defined region 10P, such that the word line pre-defined region 10W and the pickup neck pre-defined region 10P have a first spacing D1 in the X direction. Furthermore, the first mask pattern 134 within the pickup neck pre-defined region 10P has a second spacing D2 in the X direction. The first spacing D1 is less than or equal to the second spacing D2. The first spacing D1 may be between 20nm and 300nm, for example, between 100nm and 200nm, while the second spacing D2 may be between 100nm and 300nm, for example, between 140nm and 200nm. A photoresist layer is formed on the third dielectric layer 124 by a photolithography process, followed by an exposure process and a development process on the photoresist layer to complete the first mask pattern 134.

[0059] Figure 1B yes Figure 1A The schematic cross-sectional view of the flash memory 10 shown herein, wherein it comprises... Figure 1A The plane perpendicular to line segment B-B' is used in the diagram. Subsequent cross-sectional views, whose figures are numbered with the letter "B", are obtained from the same plane as the perpendicular plane containing line segment B-B' in the corresponding top view. Please refer to... Figure 1B In addition to the previously mentioned film layers, the flash memory 10 further includes a substrate 100, a first polymer layer 104 between the substrate 100 and the conductive layer 108, a second polymer layer 120 between the second dielectric layer 116 and the third dielectric layer 124, a first anti-reflective coating 128 above the third dielectric layer 124, and a first mask pattern 134. In a self-aligned dual patterning process, the second polymer layer 120 can serve as an intermediate layer for the hard mask, while the second dielectric layer 116 can protect the underlying film layers from the effects of intermediate etching processes.

[0060] Continue to refer to Figure 1B A first polymer layer 104 may be formed on the substrate 100. The material of the first polymer layer 104 may include polyimide (PI), benzocyclobutene (BCB), or polybenzo[…]. Polybenzoxazole (PBO), other similar materials, or combinations thereof. The thickness of the first polymer layer 104 may be between 40 nm and 120 nm, for example, between 60 nm and 100 nm. The first polymer layer 104 protects the substrate 100 from subsequent processes and can serve as a dielectric layer for other components.

[0061] Please refer to Figure 1B A conductive layer 108 may be formed on the first polymer layer 104. The material of the conductive layer 108 may include amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. Metals may include cobalt, ruthenium, aluminum, tungsten, copper, silver, gold, nickel, other similar materials, combinations thereof, or multiple layers thereof. The conductive layer 108 may be tungsten. The thickness of the conductive layer 108 may be between 30 nm and 80 nm, for example, between 40 nm and 70 nm.

[0062] Continue to refer to Figure 1B A first dielectric layer 112 may be formed on the conductive layer 108. In some embodiments, the material of the first dielectric layer 112 may include silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), or silicon oxycarbonitride (e.g., SiO). x N y C 1-x-y The dielectric layer 112 can be silicon nitride. The dielectric layer 112 can be between 30 nm and 70 nm, for example, between 40 nm and 60 nm. The dielectric layer 112 can be either tetraethylorthosilicate (TEOS), undoped silica glass, or doped silicon oxide (such as boron-doped phospho-silicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), or boron-doped silicon glass (BSG)), a low dielectric constant dielectric material, or other suitable dielectric material.

[0063] Please refer to Figure 1BA second dielectric layer 116 can be formed over the first dielectric layer 112. In some embodiments, the second dielectric layer 116 can include a similar material as the first dielectric layer 112. The second dielectric layer 116 can have a thickness between 130 nm and 220 nm, such as between 140 nm and 200 nm. In addition to providing protection and insulation to underlying film layers, the second dielectric layer 116 can also reduce stress caused by direct contact between film layers above and below.

[0064] With continued reference to Figure 1B A second polymer layer 120 can be formed over the second dielectric layer 116. The second polymer layer 120 can include a similar material as the first polymer layer 104. The second polymer layer 120 can have a thickness between 30 nm and 130 nm, such as between 60 nm and 100 nm. As previously described, the second polymer layer 120 can act as an intermediate layer for the hard mask. In other words, the final structure of the flash memory 10 will include all film layers below the second polymer layer 120.

[0065] With reference to Figure 2A A third dielectric layer 124 can be formed over the second polymer layer 120. The third dielectric layer 124 can include a similar material as the first dielectric layer 112 or the second dielectric layer 116. The third dielectric layer 124 can be any suitable carbide material. The third dielectric layer 124 can have a thickness between 80 nm and 170 nm, such as between 100 nm and 150 nm. In some embodiments, the third dielectric layer 124 can act as a template for a subsequently formed spacer 142.

[0066] With continued reference to Figure 2B A photolithography process can be performed to pattern the third dielectric layer 124. A first anti-reflective coating 128 and a photoresist layer can be sequentially deposited over the third dielectric layer 124. The photoresist layer can be patterned using a photomask to form a first mask pattern 134. The first anti-reflective coating 128 can include an oxynitride, such as silicon oxynitride. The first anti-reflective coating 128 can have a thickness between 5 nm and 40 nm, such as between 10 nm and 30 nm. The first mask pattern 134 can have a thickness between 70 nm and 140 nm, such as between 80 nm and 130 nm. The first anti-reflective coating 128 can effectively control the critical dimensions of the patterned third dielectric layer 126 that is subsequently formed.

[0067] With reference to Figure 2A and Figure 2BWith the first mask pattern 134 as an etching mask, the first anti-reflective coating 128 and the third dielectric layer 124 are sequentially etched by an etching process. One or more cycles of the etching process can be performed until the shape of the first mask pattern 134 is completely transferred to the first anti-reflective coating 128 and the third dielectric layer 124. The etching selectivity ratio of the first mask pattern 134 to the first anti-reflective coating 128 and the third dielectric layer 124 can be controlled to be between about 0.2 and 3.0. After the dry etching process, the patterned third dielectric layer 126 and the patterned first anti-reflective coating 130 are formed.

[0068] With reference to both of the foregoing embodiments, and continuing with Figure 3A and Figure 3B According to some embodiments of the present disclosure, the patterned third dielectric layer 126 (and the patterned first anti-reflective coating 130) can correspond to the first mask pattern 134. Thus, the patterned third dielectric layer 126 (and the patterned first anti-reflective coating 130) also includes the word line predetermined region 10W, the pair of select gate predetermined regions 10S, and the pickup neck predetermined region 10P. The word line predetermined region 10W is located longitudinally, e.g., in the Y direction, between the select gate predetermined regions 10S. Both the word line predetermined region 10W and the select gate predetermined regions 10S extend laterally, e.g., in the X direction, toward the pickup neck predetermined region 10P, such that the word line predetermined region 10W and the pickup neck predetermined region 10P have a first pitch D1 in the X direction. In addition, the patterned third dielectric layer 126 (and the patterned first anti-reflective coating 130) within the pickup neck predetermined region 10P has a second pitch D2 in the X direction. The first pitch D1 is less than or equal to the second pitch D2. After the third dielectric layer 124 and the first anti-reflective coating 128 are patterned into the patterned third dielectric layer 126 and the patterned first anti-reflective coating 130, portions of the top surface of the underlying second polymer layer 120 are thus exposed.

[0069] With reference to both of the foregoing embodiments, and continuing with Figure 4A and Figure 4B A spacer material layer 140 is conformally deposited on the top surface and sidewalls of the patterned third dielectric layer 126 and the patterned first anti-reflective coating 130, and on the exposed surface of the second polymer layer 120. The spacer material layer 140 is a continuous structure that covers the entire surface of the flash memory 10. The material of the spacer material layer 140 can include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride (e.g., SiO x N y C 1-x-ywhere x and y are in the range of 0 to 1), other similar materials, or combinations thereof. The spacer material layer 140 can have a thickness between 10 nm and 35 nm, such as between 15 nm and 30 nm. In embodiments where silicon oxycarbonitride is formed as the spacer material layer 140, a layer of silicon oxycarbonitride can be deposited using a dielectric material precursor, which includes a silicon source precursor and a nitrogen source precursor.

[0070] Referring to Figure 5A and Figure 5B , a horizontal portion of the spacer material layer 140 (including portions over the patterned first anti-reflective coating 130 and portions over the exposed surface of the second polymer layer 120) is etched. One or more cycles of etching can be performed until the horizontal portion of the spacer material layer 140, the patterned first anti-reflective coating 130, and the portion of the second polymer layer 120 covered by the spacer material layer 140 are completely removed. After the etching process, portions of the top surface of the patterned third dielectric layer 126 and the second dielectric layer 116 are exposed. The remaining portions of the spacer material layer 140 over the sidewalls of the patterned third dielectric layer 126 become spacers 142. The etching process etches (i.e., indirectly patterns) the second polymer layer 120 using the patterned third dielectric layer 126 and the spacers 142 as a mask to form a patterned second polymer layer 122. The patterned third dielectric layer 126 is flush with the top of the spacers 142. The top of the spacers 142 can be higher or lower than the top surface of the patterned third dielectric layer 126 (not shown).

[0071] Referring to Figure 6A and Figure 6B , a suitable etching process is performed to remove the patterned third dielectric layer 126 between the spacers 142 to expose the patterned second polymer layer 122. After the etching process is complete, the portions of the patterned second polymer layer 122 that were covered by the patterned third dielectric layer 126 are thus exposed, and the remaining portions of the patterned second polymer layer 122 remain covered by the spacers 142.

[0072] Referring to Figure 6C , Figure 6A and Figure 6C , in order for each word line 210 subsequently formed in the word line intended region 10W to be an independent and properly functioning gate structure, the spacers 142 on the connection portion 10W-C of the word line intended region 10W must be cut off from the spacers 142 of the rest of the word line intended region 10W. In addition, in order to avoid shorting caused by the conduction of multiple pairs of pickup necks 230 subsequently formed in the pickup neck intended region 10P, the spacers 142 in a portion of the pickup neck intended region 10P must also be cut off. This step is referred to as a gate insulating cut (GI cut). As Figure 6AAs shown, the spacer 142 can be patterned to form a second mask pattern 160 on the spacer 142.

[0073] Figure 6A yes Figure 7A The schematic cross-sectional view of the flash memory 10 shown herein, wherein it comprises... Figure 7B The second mask pattern 160 is obtained from the vertical plane of the line segment C-C' in the following figures. Subsequent cross-sectional views, whose reference numerals are "C", are obtained from the same plane as the vertical plane containing the line segment C-C' in the corresponding top view. The formation of the second mask pattern 160 includes coating a first photoresist layer 150 onto the surface of the flash memory 10. The first photoresist layer 150 completely covers the second dielectric layer 116, the patterned second polymer layer 122, and the spacers 142, and has a planarized top surface. A second anti-reflective coating 154 may be formed on the first photoresist layer 150. The second mask pattern 160 may be formed on the second anti-reflective coating 154.

[0074] According to some embodiments, the second masking pattern 160 covers the entire surface of the flash memory 10, except for the portion of the spacer 142 that needs to be truncated, which is exposed by development. The exposed portion includes a portion of the word line pre-defined region 10W and the select gate pre-defined region 10S in the Y direction, and a portion of the pickup neck pre-defined region 10P in the X direction. The second masking pattern 160 and the first masking pattern 134 may be made of different types of materials.

[0075] Please refer to Figure 7C , Figure 7C and Figure 6C A suitable etching process is performed on the spacer 142 using the second mask pattern 160 as a mask. The portion of the spacer 142 exposed in the second mask pattern 160 is removed, resulting in a discontinuous structure. Corresponding to the exposed portion of the second mask pattern 160, the area where the spacer 142 is removed includes a portion of the word line predetermined region 10W in the Y direction, extending to a portion of the select gate predetermined region 10S in the Y direction, and a portion of the pickup neck predetermined region 10P in the X direction. In this way, short circuits can be avoided when the multiple word lines 210 and multiple pairs of pickup necks 230 formed subsequently are interconnected during operation. Existing flash memory processes completely remove the connection portion 10W-C of the word line predetermined region 10W, but this embodiment of the invention retains the pattern of the partial connection portion 10W-C as a dummy structure 200, thereby improving the etching load effect. Figure 8A As shown, relative to Figure 8B The spacer 142 is removed from the portion exposed in the second masking pattern 160.

[0076] Please refer to Figure 8C , Figure 8A and Figure 8ATo form the final word line 210, select gate 220, pickup neck 230, and the dummy structure 200 unique to this invention, the flash memory 10 may undergo another patterning process. This step is called partially depleted (PD). Figure 8A As shown, a third mask pattern 180 can be formed on the flash memory 10. The third mask pattern 180 may include a first portion 180A, a second portion 180B, and a third portion 180C. The first portion 180A is laterally, for example in the X direction, and extends from a portion of the word line pre-selection gate pre-selection region 10S in the Y direction to a portion of the pickup neck pre-selection region 10P by the connection portion 10W-C of the word line pre-selection region 10W and the corresponding portion of the connection portion 10W-C in the Y direction, and its portion includes a portion of spacers 142. The first portion 180A of the third mask pattern 180 may be longitudinally, for example in the Y direction, further divided into two ends and a middle portion located between the two ends. The two ends of the first part 180A are connected in the X direction by the word line pre-region 10W-C and the corresponding connection 10W-C in the Y direction by the partial selection gate pre-region 10S to a part of the pickup neck pre-region 10P (including a part of the spacer 142), while the middle part of the first part 180A only covers the connection 10W-C in the X direction.

[0077] like Figure 8B As shown, the special shape of the first portion 180A of the third masking pattern 180 can protect the connection portion 10W-C and the corresponding connection portion 10W-C in the Y direction from being removed in subsequent processes, thus enabling the formation of the dummy structure 200. In the existing flash memory formation method, the first portion 180A of the third masking pattern 180 only has two separate ends, without a middle portion connecting the two, and the two ends only cover a portion of the pickup neck predetermined region 10P, without crossing to the word line predetermined region 10W and the selected gate predetermined region 10S in the X direction, similar to the third portion 180C of the third masking pattern 180 (described in detail below). If the middle portion of the first part 180A, together with the two ends, extends from the word line pre-defined region 10W and the select gate pre-defined region 10S to the pickup neck pre-defined region 10P, the subsequent etching process cannot cut off the conductive layer 108 below the spacer 142 in the pickup neck pre-defined region 10P, causing the pair of pickup necks 230 closest to the word line 210 to conduct to each other, resulting in a short circuit. Therefore, the middle portion is recessed in the negative X direction compared to the two ends.

[0078] The dummy structure 200 can be formed by extending the word line reservation region 10W and the select gate reservation region 10S in the X direction toward the pick neck reservation region 10P, and extending the first portion 180A of the third mask pattern 180 in the X direction to cover the connection portions 10W-C of the word line reservation region 10W and the corresponding connection portions 10W-C in the Y direction of the select gate reservation region 10S. The dummy structure 200 can occupy the space of the isolation circuit, reduce the etching loading effect on the tail ends of the plurality of word lines 210, and reduce the bowl-shaped or broken tail ends of the word lines 210. The spacers 142 of the remaining portions of the word line reservation region 10W have a spacing S in the X direction from the first portion 180A of the third mask pattern 180. The spacing S can be between 10 nm and 150 nm. The boundary of the spacers 142 of the remaining portions of the word line reservation region 10W in the X direction can be defined by the second mask pattern 160, and the boundary of the first portion 180A of the third mask pattern 180 in the X direction can be defined by the third mask pattern 180. Since the X direction dimension of the spacing S is defined by the second mask pattern 160 and the third mask pattern 180 respectively, the dimension can be smaller than the minimum spacing formed by a single machine of a single patterning process.

[0079] With continued reference to Figure 8C , Figure 9A , and Figure 9B , the second portion 180B and the third portion 180C of the third mask pattern 180 can cover the partial select gate reservation region 10S and the partial pick neck reservation region 10P respectively. The formation of the third mask pattern 180 includes coating the second photoresist layer 170 on the surface of the flash memory 10. The second photoresist layer 170 completely covers the second dielectric layer 116, the patterned second polymer layer 122, and the spacers 142, and has a planarized top surface. A third anti-reflective coating layer 174 can be formed on the second photoresist layer 170, which can have similar materials, formation methods, and purposes as the first anti-reflective coating layer 128 or the second anti-reflective coating layer 154. The third mask pattern 180 can be formed on the third anti-reflective coating layer 174. Both the first mask pattern 134 and the third mask pattern 180 are positive photoresists, while the second mask pattern 160 is a negative photoresist.

[0080] Please refer to Figure 9C , Figure 9A , and Figure 9AAfter the third mask pattern 180 is formed, a suitable etching process is performed. The portions not covered by the third mask pattern 180 can be etched by the spacers 142 as a mask to etch the film layers under the patterned second polymer layer 122 and remove the patterned second polymer layer 122 until the surface of the substrate 100 is exposed. The portions covered by the third mask pattern 180 are protected and only the spacers 142 are removed and the patterned second polymer layer 122 is used as a mask to etch the film layers under it in subsequent processes until the surface of the substrate 100 is exposed. The etching process uses the spacers 142 and the patterned second polymer layer 122 as masks to etch (i.e., indirectly pattern) the second dielectric layer 116 to form the patterned second dielectric layer 118. As shown in Figure 9A the process of the flash memory 10 is completed after the removal of the mask (either the spacers 142 or the patterned second polymer layer 122). The flash memory 10 with the patterned second dielectric layer 118 on top includes a plurality of word lines 210 formed in the word line predetermined area 10W, a pair of select gates 220 formed in the select gate predetermined area 10S, a plurality of pairs of pick-up necks 230 formed in the pick-up neck predetermined area 10P, and dummy structures 200 between the plurality of word lines 210 and the plurality of pairs of pick-up necks 230 in the X direction.

[0081] As shown in Figure 9B the connection portions 10W-C including a plurality of U-shaped structures form a plurality of bullet shapes after the etching process. Since each U-shaped structure of the present embodiment connects two adjacent strip structures in the word line predetermined area 10W and the word line 210 is defined by the sidewalls formed on both sides of each strip structure, each bullet shape formed finally corresponds to four word lines 210 in the X direction, but the present embodiment is not limited thereto. For example, the connection portions 10W-C can connect three adjacent strip structures in the word line predetermined area 10W in a similar M-shaped structure, and each bullet shape formed finally can become wider in the Y direction and correspond to six word lines 210.

[0082] Continuing to refer to Figure 9CThe dummy structure 200 has two ends formed in the select gate predetermined regions 10S on both sides in the Y direction, which are connected to the pair of select gates 220, respectively. The two ends of the dummy structure 200 also occupy the isolation circuit space, so that the linear structure of the pair of pickup necks 230 closest to the original isolation circuit space at the turning point is also protected, reducing the etching load effect, reducing the bowl type or breakage. The plurality of word lines 210 and the dummy structure 200 have a spacing S in the X direction, which can be between 10 nm and 150 nm. Because of the gate insulation cutting in the previous process, the plurality of word lines 210 and the plurality of pairs of pickup necks 230 become a plurality of independent and normally operating structures, avoiding short circuit caused by conduction. The arrangement of the dummy structure 200 greatly reduces the isolation circuit space, reduces the etching load effect of the etching process on the tail end of the plurality of word lines 210 and the linear structure of the pickup neck 230 at the turning point, and also reduces the bowl type or breakage of the linear structure at the turning point.

[0083] As shown in Figure 9B and Figure 9C , the etching process not only etches the second dielectric layer 116 to form the patterned second dielectric layer 118, but also etches the first dielectric layer 112, the conductive layer 108, and the first polymer layer 104 to form the patterned first dielectric layer 114, the patterned conductive layer 110, and the patterned first polymer layer 106, respectively. Figure 10 includes one of the select gates 220 and a plurality of word lines 210. Figure 2A includes only one of the select gates 220 due to the reduced isolation circuit space.

[0084] Figure 2A corresponding to Figure 2A , the step of forming the patterned third dielectric layer 126 on the second polymer layer 120 includes the word line predetermined region 20W, the pair of select gate predetermined regions 20S, and the pickup neck predetermined region 20P (corresponding to the word line predetermined region 10W, the pair of select gate predetermined regions 10S, and the pickup neck predetermined region 10P of Figures 11-16 , respectively). Compared with Figures 3A-8A , the difference between the flash memory 10 and the flash memory 20 is that the connecting part 20W-C of the word line predetermined region 20W includes a single rectangular structure, which connects all the strip structures in the word line predetermined region 20W. Figure 17 The steps of Figure 9A may correspond to

[0085] Please refer to ​ , the dummy structure 200 of the flash memory 20 includes a single comb shape. Compared with ​ , the flash memory 10 and the flash memory 20 have different designs of the connecting part 10W-C and the connecting part 20W-C, resulting in different shapes of the final dummy structure 200.

[0086] Having thus described several aspects of several embodiments of the application, it is to be appreciated various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be within the scope of the application. Accordingly, the foregoing description is by way of example only and is not intended to be limiting.

Claims

1. A method for forming a semiconductor element, characterized by, Comprising: providing a substrate having a conductive layer formed thereon; forming a patterned dielectric layer on the conductive layer, the patterned dielectric layer comprising: a word line predetermined area; a pair of select gate predetermined areas, wherein the word line predetermined area is disposed between the pair of select gate predetermined areas; a pickup neck predetermined area surrounding the pair of select gate predetermined areas, wherein the word line predetermined area and the pickup neck predetermined area have a first pitch in an X direction, and the patterned dielectric layer within the pickup neck predetermined area has a second pitch in the X direction, wherein the first pitch is less than or equal to the second pitch; forming a spacer on sidewalls of the patterned dielectric layer, after forming the spacer, removing the patterned dielectric layer; truncating the spacer of a connection portion of the word line predetermined area from the spacer of a remaining portion of the word line predetermined area; forming a mask pattern on the spacer, the mask pattern comprising a first portion spanning the spacer of the connection portion and the spacer of a portion of the pickup neck predetermined area in the X direction, wherein the spacer of the remaining portion of the word line predetermined area and the first portion of the mask pattern have a separation in the X direction; and performing an etching process on the conductive layer with the mask pattern and the spacer as etching masks to form a dummy structure, a plurality of word lines, a pair of select gates, and a plurality of pairs of pickup necks, wherein the dummy structure is located between the plurality of word lines and the plurality of pairs of pickup necks in the X direction.

2. The method for forming a semiconductor element according to claim 1, wherein Before forming the patterned dielectric layer on the conductive layer, further comprising forming a polymer layer on the conductive layer, wherein forming the spacer comprises conformally depositing a spacer material layer and etching back the spacer material layer, and etching back the spacer material layer further comprises etching the polymer layer to form a patterned polymer layer.

3. The method for forming a semiconductor element according to claim 1, wherein The step of truncating the spacer further comprises truncating a portion of the spacer of the pickup neck predetermined area.

4. The method for forming a semiconductor element according to claim 1, wherein The connection portion is a plurality of U-shaped structures or a single rectangular structure.

5. The method for forming a semiconductor element according to claim 1, wherein A middle portion of the first portion of the mask pattern only covers the connection portion but does not cover the pickup neck predetermined area.

6. The method for forming a semiconductor element according to claim 1, wherein The dummy structure is formed from the conductive layer under the first portion of the mask pattern.

7. The method for forming a semiconductor element according to Claim 1, wherein The separation is between 10 nm and 150 nm.

8. A semiconductor element characterized by comprising: Comprising: a plurality of word lines; a pair of select gates, wherein the plurality of word lines is located between the pair of select gates; a plurality of pairs of pickup necks surrounding the pair of select gates; and a dummy structure located between the plurality of word lines and the plurality of pairs of pickup necks in an X direction, wherein the dummy structure has a separation from the plurality of word lines in the X direction, wherein the dummy structure extends beyond the plurality of word lines in a direction perpendicular to an extension direction of the plurality of word lines. The dummy structure is a non-continuous structure, wherein the non-continuous structure comprises a plurality of bullet shapes or a comb shape, the dummy structure having an end portion connected to the pair of select gates.

9. The semiconductor device according to claim 8, wherein The separation is between 10 nm and 150 nm.

10. The semiconductor device according to claim 8, wherein ​

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