Bumpless superconducting device
The bumpless superconducting device technology, which forms superconducting contacts between substrates, solves the problem of bump bonding in high-density three-dimensional chip integration, achieving high-yield and low-cost connections, and is suitable for chip integration in the high-end market.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MICROSOFT TECHNOLOGY LICENSING LLC
- Filing Date
- 2021-03-25
- Publication Date
- 2026-07-14
AI Technical Summary
In high-density 3D chip integration, existing technologies, such as bump bonding, struggle to achieve high yield and low cost connections. Furthermore, the complex underfill materials and distribution processes make it difficult to meet the demands for low power consumption and high interconnect density.
Using bumpless superconducting device technology, two substrates are connected by a dielectric material to form a superconducting contact between the substrates. The superconducting contact is formed by plasma etching and filling the vias with superconducting material.
It reduces the requirements for precise flatness control, reduces the complexity of underfill material and distribution processes, and improves the reliability and interconnect density of inter-chip connections, making it suitable for high-end markets such as GPUs, NPUs, and CPUs.
Smart Images
Figure CN115700068B_ABST
Abstract
Description
[0001] This application claims priority to U.S. Patent Application No. 16 / 858812, filed April 27, 2020, the entire contents of which are incorporated herein by reference. Technical Field
[0002] This disclosure relates generally to integrated circuits, and more specifically to a bumpless superconducting device. Background Technology
[0003] High-density three-dimensional (3D) chip integration technology typically involves using variations of bump bonding to bond two separate substrates / chips. Bumps are raised metal pillars / spheres, approximately 25-200 micrometers in diameter and 10-200 micrometers in height, formed on the surface of the chip / substrate. Bump bonding requires the substrates to be bonded to be "bumped out" with a suitable bonding metal (SnPb, SnAg, SnCu, In, etc.). Substrate bumping involves the patterning and deposition of a lower bump metallization layer (e.g., Ti, TiW, Cr, Pd, Ni, etc.), which acts as an adhesion promoter and / or diffusion barrier layer, followed by electroplating of the aforementioned bonding metal. Once "bumped out," the substrates or chips are joined by precisely aligning the bumps and applying force, temperature, ultrasonic power, or a combination thereof to form a conductive metal junction between the two chips. Following this joining process, standard practice is to distribute a thermosetting polymer material (typically epoxy) called an underfill between the two bonding layers as a stress-reducing layer and to isolate the bumps from their surroundings.
[0004] The demands for low power consumption, low latency, and higher interconnect density require smaller chip-to-chip connection diameters and tighter spacing. Currently, mass-production chip bumps for HBM (High Bandwidth Memory) use copper pillar microbumps with a diameter of 25 micrometers and a spacing of 55 micrometers. Furthermore, even at this stage, the cost of this package integration is pushing this technology towards high-end markets such as GPUs, NPUs, and CPUs. Maintaining bump and bonding yields at these spacings and diameters is challenging because precise control of alignment and flatness in the bonding process is required to ensure all bumps are bonded. Typically, this flip-chip bonding is non-reworkable. Additionally, reducing the bump diameter results in a reduced bump height, thus limiting the chip-to-chip spacing due to the limited aspect ratio of the plating pillars. This increases stress on the bumps, a function of pillar height. It also imposes additional constraints on underfill materials and underfill distribution processes, requiring the development of highly engineered low-viscosity materials to fill these tight gaps and very precise liquid distribution tools to ensure consistent underfill distribution. Summary of the Invention
[0005] In one example, an integrated circuit is provided, comprising: a first substrate having a plurality of conductive contact pads spaced apart from each other on its surface; a dielectric layer covering the first substrate and the plurality of conductive contact pads; and a second substrate covering the dielectric layer. A plurality of superconducting contacts extend through the second substrate and the dielectric layer to the first substrate, wherein each of the plurality of superconducting contacts is aligned with and in contact with a corresponding conductive contact pad among the plurality of conductive contact pads.
[0006] In another example, a method for forming a superconducting device is disclosed. The method includes: providing a first substrate having a plurality of conductive contact pads spaced apart from each other on its surface; disposing a dielectric layer over the first substrate and the plurality of conductive contact pads; and disposing a second substrate over the dielectric layer. A plurality of vias are formed, extending from the top surface of the second substrate through the second substrate and the dielectric layer to the first substrate, wherein each via extends to and is aligned with a corresponding conductive contact pad among the plurality of conductive contact pads. The method further includes: performing contact material filling to fill the plurality of vias with a superconducting material; and forming a plurality of superconducting contacts extending through the second substrate and the dielectric layer to the first substrate, wherein each of the plurality of superconducting contacts is aligned with and in contact with a corresponding conductive contact pad among the plurality of conductive contact pads.
[0007] In another example, a method for forming an integrated circuit is disclosed. The method includes: providing a first substrate having a plurality of conductive contact pads spaced apart from each other on a surface of the first substrate; disposing a dielectric layer over the first substrate and the plurality of conductive contact pads; and performing a first etching on the first dielectric layer to provide an extended via opening through the dielectric layer to the first substrate, wherein each extended via opening is aligned with a corresponding conductive contact pad among the plurality of conductive contact pads. The method further includes: performing a second etching on a second substrate to form a plurality of through-substrate via (TSV) openings in the second substrate; and disposing the second substrate over the dielectric layer, wherein the plurality of TSV openings are aligned to form a plurality of vias extending from a top surface of the second substrate through the second substrate and the dielectric layer to the first substrate, wherein each via extends to and is aligned with a corresponding conductive contact pad among the plurality of conductive contact pads. The method also includes performing contact material filling to fill a plurality of vias with superconducting material and forming a plurality of superconducting contacts extending through a second substrate and a dielectric layer to a first substrate, wherein each of the plurality of superconducting contacts is aligned with and in contact with a corresponding conductive contact pad in a plurality of conductive contact pads. Attached Figure Description
[0008] Figure 1 A cross-sectional view of a portion of an example integrated circuit is shown.
[0009] Figure 2 A cross-sectional view of a portion of another example integrated circuit is shown.
[0010] Figure 3 A cross-sectional view of the first portion of a bumpless superconducting device in its early stages of fabrication according to the first method is shown.
[0011] Figure 3 A cross-sectional view of the first portion of a bumpless superconducting device in its early stages of fabrication according to the first method is shown.
[0012] Figure 4 This shows the process after depositing the dielectric layer. Figure 3 A cross-sectional view of the structure.
[0013] Figure 5 This illustrates the process after depositing a second substrate on top of the dielectric layer. Figure 4 A cross-sectional view of the structure.
[0014] Figure 6 This illustrates the process following the deposition and patterning of the photoresist material layer, and simultaneously with the first etching process. Figure 5 A cross-sectional view of the structure.
[0015] Figure 7 This shows the process during the second etching process. Figure 6 A cross-sectional view of the structure.
[0016] Figure 8 This shows the result after the second etching process. Figure 7 A cross-sectional view of the structure.
[0017] Figure 9 This shows the process after the superconducting material filling process. Figure 8 A cross-sectional view of the structure.
[0018] Figure 10 A cross-sectional view of the first portion of a bumpless superconductor device is shown in the early stages of its fabrication according to the second method, while it is undergoing the first etching process.
[0019] Figure 11 This shows the result after the first etching process. Figure 10 A cross-sectional view of the structure.
[0020] Figure 12 A cross-sectional view of the second substrate after the second etching process is shown.
[0021] Figure 13 The second substrate after the second etching process is shown. Figure 12 A cross-sectional view of the structure.
[0022] Figure 14 It shows in Figure 11 above the structure Figure 13 After the deposition of the second substrate Figure 11 A cross-sectional view of the structure.
[0023] Figure 15 This shows the process after the superconducting material filling process. Figure 14 A cross-sectional view of the structure. Detailed Implementation
[0024] This disclosure describes a bumpless superconducting device and a method for fabricating a bumpless superconducting device. In one example, two substrates are bonded together by a dielectric material. As an example, a spin-coated thermosetting polymer dielectric can be deposited on a first substrate (e.g., formed of silicon, glass, compound semiconductor, or various other semiconductor materials). A second substrate (e.g., formed of silicon, glass, compound semiconductor, or various other semiconductor materials) can then be aligned and bonded to the first substrate, face up or face down. Applying heat during the bonding process causes the polymer to solidify, thereby bonding the substrates. The substrates can be in chip or wafer form. Subsequently, high aspect ratio vias (e.g., through-substrate vias (TSVs)) are etched through the top substrate using, for example, masked plasma etching (e.g., via a Bosch process). Once the vias reach the dielectric layer between the two substrates, this polymer or other dielectric (using the TSV as an etching mask) can be etched down onto corresponding metal pads on the bottom substrate using different plasma gas mixtures. In this way, very dense vias with very small diameters can be formed. Dielectric pads can be deposited via PECVD or ALD, followed by sputtering of conductive material to line or fill the vias. A variant of this process features vias pre-etched in a second substrate and dielectric layer and aligned to provide dielectric-matched vias before or after the bonding process.
[0025] This disclosure provides an alternative to bump bonding technology for high-density chip integration and also reduces the burden of precise flatness control during substrate bonding processes. The technology also allows for inter-chip metallization using materials other than cryogenically molten metals / alloys to include any sputterable material (e.g., high-temperature superconducting metals). Furthermore, it reduces the complexity of underfill formulations and dispensing processes and engineering design.
[0026] Figure 1A schematic cross-sectional view of a portion of an exemplary bumpless superconducting device 10 is shown. A first substrate 12 includes a plurality of conductive contact pads 20 spaced apart from each other across the top surface of the first substrate 12. The plurality of conductive contact pads 20 can be coupled to an underlying device in the first substrate 12 via conductive contacts (not shown) and / or wires (not shown) within the first substrate 12. A second substrate 16 is aligned and bonded to the first substrate 12 via a dielectric layer 14. A plurality of superconducting contacts 18 extend from the top surface of the second substrate 16 through the second substrate 16 and the dielectric layer 14, and further extend to corresponding contact pads in the plurality of contact pads 20 disposed on the top surface of the first substrate 12. Dielectric pads may be deposited to line or fill vias before forming the plurality of superconducting contacts 18.
[0027] The first substrate 12 and the second substrate 16 may be formed of silicon, glass, compound semiconductor, or some other substrate material. The plurality of superconducting contacts 18 may be formed of a superconducting material, such as aluminum, niobium, niobium titanium nitride, niobium nitride, or some other superconducting material, compound, or alloy. The dielectric layer 14 may be a spin-coated thermosetting polymer dielectric or other dielectric material, which can provide bonding between the first substrate 12 and the second substrate 16 and electrical isolation between the plurality of superconducting contacts 18. Alternatively, a bonding agent may be used to bond the first substrate 12 and the second substrate 16 to the dielectric layer 14.
[0028] Figure 2 The illustration shows a schematic cross-sectional view of a portion of an exemplary bumpless superconducting device 50 with superconducting elements. A first substrate 52 includes a plurality of conductive contact pads 60 spaced apart from each other across the top surface of the first substrate 52. Each of the plurality of conductive contact pads 60 is coupled to a corresponding qubit device 62 disposed within the first substrate 52. Although illustrated as a direct coupling between the qubit device 62 and the conductive contact pads 60, coupling may occur via conductive contacts and / or conductive lines within the first substrate 52. A second substrate 56 is aligned and bonded to the first substrate 52 via a dielectric layer 54. A plurality of superconducting contacts 58 extend from the top surface of the second substrate 56 through the second substrate 56 and the dielectric layer 54 to corresponding conductive contact pads among the plurality of conductive contacts 60 disposed on the top surface of the first substrate 52.
[0029] The first end of each corresponding superconducting contact 58 is coupled to a corresponding resonator 64 on the top surface of the second substrate 56, and the second end of each corresponding superconducting contact 58 is coupled to a corresponding conductive contact pad 60, and thus to a corresponding quantum bit device 62. The resonator 64 can be printed or etched into the top surface of the second substrate 56. Figure 1Similarly, the first substrate 52 and the second substrate 56 may be formed of silicon or other structural materials, the multiple superconducting contacts 58 may be formed of superconducting materials, and the dielectric layer 54 may be a spin-coated thermosetting polymer dielectric or other dielectric materials.
[0030] Turn now Figures 3 to 15 , combined Figure 1 The fabrication of bumpless superconducting devices will be discussed in the context of their formation. The first method... Figures 3 to 9 The text describes a method where, after bonding two substrates together via a dielectric layer, a via is formed through the top substrate and through the dielectric layer. A second method... Figures 10 to 15 The description states that vias are formed through the top substrate and the dielectric layer respectively, and the top substrate is disposed above the dielectric layer so that the vias of the top substrate are aligned with the corresponding vias of the dielectric layer. Then, the top substrate and the bottom substrate are bonded together through the dielectric layer.
[0031] Figure 3 A cross-sectional view of a first portion of a bumpless superconducting device fabricated according to a first method in an early stage of its fabrication is shown. A first substrate 100 is provided, comprising a plurality of conductive contact pads 102 spaced apart from each other across the top surface of the first substrate 100. The first substrate may be formed of silicon or other structural materials. The plurality of conductive contact pads 102 may be coupled to underlying devices in the first substrate 100 via conductive contacts (not shown) and / or wires (not shown) within the first substrate 100. The plurality of conductive contact pads 102 may be formed by photoresist patterning and contact material filling deposition processes. The photoresist may be removed or stripped to form the plurality of conductive contact pads 102.
[0032] like Figure 4 As shown, a dielectric layer 104 is formed on the first substrate 100. Any suitable technique can be used to form the dielectric layer 104, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDPCVD), sputtering, or spin coating, to achieve a thickness suitable for providing the interconnect layer. The dielectric layer 104 can be a spin-coated thermosetting polymer dielectric or other dielectric materials that provide bonding performance and electrical isolation performance. Next, as... Figure 5 As shown, the second substrate 106 is disposed on the dielectric layer 104 and aligned with the first substrate 100. Figure 5 The structure is cured by oven baking or other thermal processes to solidify the dielectric material layer 104 and bond the second substrate 106 to the first substrate 100.
[0033] like Figure 6 As shown, the photoresist material layer 107 has been applied to cover... Figure 5The photoresist material layer 107 has been patterned and developed to expose via openings 108 in the photoresist material layer 107 according to the via pattern. The photoresist material layer 107 may have a thickness that varies according to the radiation wavelength used to pattern the photoresist material layer 107. The photoresist material layer 107 may be formed on the second substrate 106 by spin coating or spin deposition techniques, selectively irradiated (e.g., via deep ultraviolet (DUV) irradiation) and developed to form the via openings 108.
[0034] Figure 6 Etching 200 (e.g., anisotropic reactive ion etching (RIE)) is also shown performing on the second substrate 106 to form a through-substrate via (TSV) opening 110 in the second substrate 106 based on the via pattern shown in the figure. Figure 7 Etching step 200 can be dry etching and employs an etchant that selectively etches the lower second substrate 106 at a faster rate than the upper photoresist material layer 107 and the lower dielectric layer 104. For example, the second substrate 106 can be anisotropically etched in a commercial etcher such as a parallel-plate RIE device or alternatively an electron cyclotron resonance (ECR) plasma reactor using a plasma gas, hereinstantly carbon tetrafluoride (CF4) containing fluorine ions, to replicate the patterned mask pattern of the photoresist material layer 107, thereby creating TSV openings 110. The photoresist material layer 107 is then removed using oxygen-based plasma and wet-cleaned to remove organic residues. As a result, the TSV openings 110 extend to the surface of the dielectric layer 104.
[0035] Figure 7 It is also shown that a second etching 210 is performed to form a via opening 112 extending through the dielectric layer 104 to the first substrate 100 based on the TSV pattern in the second substrate 106. Figure 8 Etching step 210 can be dry etching and employs an etchant that selectively etches the lower dielectric layer 104 at a faster rate than the upper second substrate 106 and the lower first substrate 100. For example, as Figure 8 As shown, the second etching 210 may be an oxygen plasma etching to form an extended via opening 112, each of which is aligned with a corresponding conductive contact pad in a plurality of conductive contact pads 102.
[0036] Next, the structure is then filled with a contact material to deposit a superconducting material, such as aluminum, into the extended via opening 112 to form a plurality of superconducting contacts 114 extending from the top surface of the second substrate 106. Figure 9Multiple superconducting contacts 114 extend from the top surface of the second substrate 106 to corresponding contact pads in multiple contact pads 102. Before forming the multiple superconducting contacts 114, dielectric pads can be deposited to line or fill the extended via openings 112. Contact material filling can be deposited using standard contact material deposition. After the contact material filling deposition, the contact material can be polished down to the surface level of the second substrate 106 by chemical mechanical polishing (CMP). The final structure is... Figure 9 As shown in the image.
[0037] Figure 10 A cross-sectional view of a first portion of a bumpless superconducting device in an early stage of its fabrication according to the second method is shown. A first substrate 130 is provided, comprising a plurality of conductive contact pads 132 spaced apart from each other across the top surface of the first substrate 130. The first substrate 130 may be formed of silicon or other structural materials. The plurality of conductive contact pads 132 may be coupled to underlying devices in the first substrate 130 via conductive contacts (not shown) and / or wires (not shown) within the first substrate 130. The plurality of conductive contact pads 132 may be formed by photoresist patterning and contact material filling deposition processes. The photoresist may be removed or stripped to form the plurality of conductive contact pads 132.
[0038] A dielectric layer 134 is formed on the first substrate 130. Any suitable technique for forming the dielectric layer 134 can be used, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDPCVD), sputtering, or spin coating, to achieve a thickness suitable for providing the interconnect layer. The dielectric layer 134 can be a spin-coated thermosetting polymer dielectric or other dielectric materials that can provide bonding and electrical isolation properties. This polymer can also be photoimageable, meaning that a separate photoresist patterning step is not required. Materials like SU-8 or certain polyimides can be used as both structural dielectrics and photoimageable materials.
[0039] A patterned photoresist material layer 136 has been applied to cover Figure 10 The photoresist material layer 136 is structured and patterned according to the via pattern, and developed to expose the via openings 138 in the photoresist material layer 136. The photoresist material layer 136 may have a thickness that varies according to the radiation wavelength used to pattern the photoresist material layer 136. The photoresist material layer 36 may be formed on the dielectric layer via spin coating or spin deposition techniques, selectively irradiated (e.g., via deep ultraviolet (DUV) irradiation) and developed to form the via openings 138.
[0040] Figure 10It is also shown that etching 220 (e.g., anisotropic reactive ion etching (RIE)) is performed on dielectric layer 134 to form extended via openings 140 to the first substrate 130 based on via patterns in photoresist material layer 136. Figure 11 Etching step 220 can be dry etching, employing an etchant that selectively etches the underlying dielectric layer 134 at a faster rate than the upper photoresist layer 136. For example, as... Figure 11 As shown, etching 220 may be oxygen plasma etching to form extended via openings 140, each of which is aligned with a corresponding conductive contact pad in a plurality of conductive contact pads 132.
[0041] Next, as Figure 12 As shown, a second substrate 150 is provided. Figure 12 As shown, a photoresist material layer 151 has been applied to cover... Figure 12 The photoresist material layer 151 is structured and patterned and developed to expose openings 152 in the photoresist material layer 151 according to the via pattern. The thickness of the photoresist material layer 151 can vary depending on the radiation wavelength used to pattern the photoresist material layer 151. The photoresist material layer 151 can be formed on the second substrate 150 via spin coating or spin deposition techniques, selectively irradiated (e.g., by deep ultraviolet (DUV) irradiation) and developed to form the via openings 152.
[0042] Figure 12 It is also shown that etching 230 (e.g., anisotropic reactive ion etching (RIE)) is performed on the second substrate 150 to form a through-substrate via (TSV) opening 154 in the second substrate 150 based on the via pattern in the photoresist material layer 151. Figure 13 Etching step 230 can be dry etching and employ an etchant that selectively etches the second substrate 150. For example, in a commercially available etcher (e.g., a parallel-plate RIE device, or alternatively an electron cyclotron resonance (ECR) plasma reactor), the second substrate 150 can be anisotropically etched with a plasma gas (here, carbon tetrafluoride (CF4) containing fluorine ions) to replicate the patterned mask pattern of the photoresist material layer 151, thereby creating the TSV opening 154. Figure 13 Subsequently, the photoresist material layer 151 is removed using oxygen-based plasma and wet cleaning is performed to remove organic residues, thereby providing... Figure 13 The resulting structure.
[0043] like Figure 14 As shown, the second substrate 150 is disposed on the dielectric layer 134, and the TSV opening 154 of the second substrate 150 is aligned with the extended via opening 140 of the dielectric layer 134. Figure 14The structure undergoes an oven baking process or other thermal process to cure the dielectric material layer 134 and bond the second substrate 150 to the first substrate 130. Next, the structure is filled with contact material to deposit a superconducting material (e.g., aluminum) into the TSV opening 150 and the extended via opening 140 to form a plurality of superconducting contacts 156. Figure 15 Before forming multiple superconducting contacts 156, dielectric pads can be deposited to line or fill openings 150 and 140. Standard contact material deposition can be used to deposit the contact material filler. After the deposition of the contact material filler, the superconducting material is polished down to the surface level of the second substrate via chemical mechanical polishing (CMP) to provide… Figure 15 The resulting structure.
[0044] The aforementioned process flow, which integrates various types of chips, has many potential variations. For example, in an alternative approach, after the second substrate 150 is bonded to the dielectric layer 134, an etching 230 is performed to form a through-substrate via (TSV) opening 154 in the second substrate 150. The TSV opening 154 is aligned with an extended via opening 140 in the dielectric layer 134. This type of approach allows for the formation of a cavity between the bottom and top substrates, which prevents sensitive structures (e.g., qubits) from being covered by the dielectric in the final stack.
[0045] As another example, imagine bonding two substrates, where only the bottom substrate has been fabricated for the IC. The exposed top substrate does not need to be precisely aligned with the underlying layer during bonding because there are no pads to align with. Once bonded, X-ray or IR imaging can be used to align reference points on the top substrate to precisely align with pads on the bottom substrate. IC fabrication on the top substrate is performed on the bonded substrate pair until the final TSV drilling. This process can also facilitate the formation of hermetic cavities using photo-imageable dielectrics to create openings in the inter-chip dielectric. After bonding, vias can be formed to open these cavities, and then metal sputtering is performed in a vacuum to seal the vias. Furthermore, this example illustrates the bonding of two substrates, but the method can be extended to structures with three or more substrates.
[0046] For the purpose of simplification, the terms “overlay,” “cover,” “overlay,” “bottom layer,” and “lower layer” (and their derivatives) are used throughout this disclosure to indicate the relative positions of two adjacent surfaces in a selected orientation. Furthermore, the terms “top” and “bottom” used throughout this disclosure indicate relative surfaces in a selected orientation. Similarly, the terms “above” and “below” are used for illustrative purposes to indicate relative positions in a selected orientation. In fact, the examples used throughout this disclosure represent a selected orientation. However, in the described examples, the selected orientation is arbitrary, and other orientations are possible within the scope of this disclosure (e.g., inverted, rotated 90 degrees, etc.).
[0047] The above description is an example of the subject matter disclosure. Of course, for the purposes of describing this disclosure, it is impossible to describe every possible combination of components or methods, but those skilled in the art will recognize that many further combinations and permutations of this disclosure are possible. Therefore, this subject matter disclosure is intended to cover all such changes, modifications, and variations that fall within the spirit and scope of the appended claims. Furthermore, where the disclosure or claims recite the elements “a,” “an,” “first,” or “another,” or their equivalents, it should be interpreted as including one or more such elements, neither requiring nor excluding two or more such elements. Additionally, where the term “comprising” is used in the detailed description or claims, the term is intended to be included in a manner similar to the term “comprising,” as “comprising” is interpreted when used as a transitional word in the claims. Finally, the term “based on” is interpreted as meaning at least partially based on.
Claims
1. A method for forming an integrated circuit, the method comprising: A first substrate is provided, having a plurality of conductive contact pads spaced apart from each other on its surface; A dielectric layer is disposed on the first substrate and the plurality of conductive contact pads; A second substrate is disposed on the dielectric layer, wherein the dielectric layer is a thermosetting polymer; A plurality of vias are formed, the plurality of vias extending from the top surface of the second substrate through the second substrate and the dielectric layer to the first substrate, wherein each via extends to and is aligned with a corresponding conductive contact pad in the plurality of conductive contact pads, wherein forming the plurality of vias includes: performing a first etching on the second substrate to form a plurality of through-substrate via (TSV) openings in the second substrate, and performing a second etching on the second substrate and the dielectric layer based on a mask pattern formed by the plurality of TSV openings in the second substrate to provide an extended opening through the dielectric layer to the first substrate; Contact material filling is performed to fill the plurality of vias with superconducting material and to form a plurality of superconducting contacts extending through the second substrate and the dielectric layer to the first substrate, wherein each of the plurality of superconducting contacts is aligned with and in contact with a corresponding conductive contact pad in the plurality of conductive contact pads; Fabricate a plurality of qubits disposed within the first substrate, such that each of the plurality of conductive contact pads is coupled to a corresponding qubit among the plurality of qubits; and A plurality of resonators are fabricated on the second substrate such that each of the plurality of superconducting contacts is coupled to a corresponding resonator among the plurality of resonators, and each of the plurality of resonators is coupled to a corresponding qubit among the plurality of qubits.
2. The method according to claim 1, further comprising: The dielectric layer is heated to bond the second substrate to the first substrate.
3. The method of claim 1, wherein both the first substrate and the second substrate are formed of silicon, glass, or a compound semiconductor.
4. The method of claim 1, wherein the plurality of superconducting contacts are formed of one of aluminum, niobium, niobium titanium nitride, and niobium nitride.
5. The method according to claim 1, further comprising: Multiple qubits are fabricated within the first substrate, such that each of the multiple conductive contact pads is coupled to a corresponding qubit among the multiple qubits.
6. The method of claim 1, wherein forming the plurality of vias comprises: A first etching is performed on the dielectric layer to provide an extended via opening through the dielectric layer to the first substrate; Before placing the second substrate on the dielectric layer, a second etching is performed on the second substrate to form a plurality of through-substrate via (TSV) openings in the second substrate; as well as The provision of the second substrate on the dielectric layer includes: placing the second substrate on the dielectric layer, wherein the plurality of TSV openings are aligned with the plurality of extended via openings to form a plurality of vias, the plurality of vias extending from the top surface of the second substrate through the second substrate and the dielectric layer to the first substrate, wherein each via extends to a corresponding conductive contact pad in the plurality of conductive contact pads and is aligned with a corresponding conductive contact pad in the plurality of conductive contact pads.
7. A method for forming an integrated circuit, the method comprising: A first substrate is provided, having a plurality of conductive contact pads spaced apart from each other on its surface; A dielectric layer is disposed on the first substrate and the plurality of conductive contact pads; A second substrate is disposed on the dielectric layer; A plurality of vias are formed, the plurality of vias extending from the top surface of the second substrate through the second substrate and the dielectric layer to the first substrate, wherein each via extends to and is aligned with a corresponding conductive contact pad in the plurality of conductive contact pads; Contact material filling is performed to fill the plurality of vias with superconducting material and to form a plurality of superconducting contacts extending through the second substrate and the dielectric layer to the first substrate, wherein each of the plurality of superconducting contacts is aligned with and in contact with a corresponding conductive contact pad in the plurality of conductive contact pads; A plurality of qubits are fabricated within the first substrate, such that each of the plurality of conductive contact pads is coupled to a corresponding qubit among the plurality of qubits; as well as A plurality of resonators are fabricated on the second substrate such that each of the plurality of superconducting contacts is coupled to a corresponding resonator among the plurality of resonators, and each of the plurality of resonators is coupled to a corresponding qubit among the plurality of qubits.
8. The method according to claim 7, further comprising: The dielectric layer is heated to bond the second substrate to the first substrate, wherein the dielectric layer is a thermosetting polymer.
9. The method of claim 7, wherein both the first substrate and the second substrate are formed of silicon, glass, or a compound semiconductor.
10. The method of claim 7, wherein the plurality of superconducting contacts are formed of one of aluminum, niobium, titanium niobium nitride, and niobium nitride.
11. The method of claim 7, wherein forming the plurality of vias comprises: A first etching is performed on the dielectric layer to provide an extended via opening through the dielectric layer to the first substrate; Before placing the second substrate on the dielectric layer, a second etching is performed on the second substrate to form a plurality of through-substrate via (TSV) openings in the second substrate; as well as The provision of the second substrate on the dielectric layer includes: placing the second substrate on the dielectric layer, wherein the plurality of TSV openings are aligned with the plurality of extended via openings to form a plurality of vias, the plurality of vias extending from the top surface of the second substrate through the second substrate and the dielectric layer to the first substrate, wherein each via extends to a corresponding conductive contact pad in the plurality of conductive contact pads and is aligned with a corresponding conductive contact pad in the plurality of conductive contact pads.
12. A method for forming an integrated circuit, the method comprising: A first substrate is provided, having a plurality of conductive contact pads spaced apart from each other on its surface; A dielectric layer is disposed on the first substrate and the plurality of conductive contact pads; A first etching is performed on the dielectric layer to provide an extended via opening through the dielectric layer to the first substrate, wherein each extended via opening is aligned with a corresponding conductive contact pad among the plurality of conductive contact pads; A second etching is performed on the second substrate to form a plurality of through-substrate via (TSV) openings in the second substrate; The second substrate is disposed on the dielectric layer, wherein the second substrate is disposed on the dielectric layer before or after the second etching, the plurality of TSV openings are aligned with the plurality of extended via openings to form a plurality of vias, the plurality of vias extending from the top surface of the second substrate through the second substrate and the dielectric layer to the first substrate, wherein each via extends to and is aligned with a corresponding conductive contact pad in the plurality of conductive contact pads; as well as Contact material filling is performed to fill the plurality of vias with superconducting material and to form a plurality of superconducting contacts extending through the second substrate and the dielectric layer to the first substrate, wherein each of the plurality of superconducting contacts is aligned with and in contact with a corresponding conductive contact pad in the plurality of conductive contact pads.
13. The method of claim 12, further comprising: Heating the dielectric layer, The second substrate is bonded to the first substrate, wherein the dielectric layer is a thermosetting polymer.
14. The method of claim 12, wherein both the first substrate and the second substrate are formed of silicon, glass, or a compound semiconductor.
15. The method of claim 12, wherein the plurality of superconducting contacts are formed of one of aluminum, niobium, niobium titanium nitride, and niobium nitride.
16. The method of claim 12, further comprising: Multiple qubits are fabricated within the first substrate, such that each of the multiple conductive contact pads is coupled to a corresponding qubit among the multiple qubits.
17. The method of claim 16, further comprising: A plurality of resonators are fabricated on the second substrate such that each of the plurality of superconducting contacts is coupled to a corresponding resonator among the plurality of resonators, and each of the plurality of resonators is coupled to a corresponding qubit among the plurality of qubits.