A dual-channel speed pulse signal alarm device

Abstract

The present invention relates to a dual-channel speed pulse signal alarm device, comprising: a first pulse acquisition circuit, a second pulse acquisition circuit, a pulse synthesis circuit, a square wave generation circuit, an XOR gate circuit and an alarm drive circuit, the input ends of the first pulse acquisition circuit and the second pulse acquisition circuit are respectively connected to two photoelectric speed sensors, the output ends are respectively connected to two input ends of the pulse synthesis circuit, the output end of the pulse synthesis circuit is connected to one input end of the XOR gate circuit, the square wave generation circuit is connected to the other input end of the XOR gate circuit, the output end of the XOR gate circuit is connected to the alarm drive circuit, and the alarm drive circuit is connected to the alarm. Compared with the prior art, the present invention synthesizes the output waveforms of the two photoelectric speed sensors through the pulse synthesis circuit, when the frequencies are inconsistent, the duty cycle of the synthesized waveform will change over time, and has the advantages of small size, high reliability and strong applicability.

Description

Technical Field

[0001] The invention relates to the field of speed detection of a CBTC vehicle-mounted signal system, and in particular to a dual-channel speed pulse signal alarm device. Background Art

[0002] The subway CBTC onboard signal system needs to obtain pulse signals from the photoelectric speed sensor to calculate the vehicle running speed. The field test requires a device that can detect the consistency of sensor channel signals. The existing method is to use a digital oscilloscope to simultaneously measure the frequency of each channel and compare them to draw conclusions.

[0003] As an auxiliary testing link, large instruments have low utilization rates, require manual intervention, occupy a large space on site, require 220V / 110V power supply, and sometimes cannot meet the needs of on-site working space, and have a narrow scope of application. Summary of the invention

[0004] The purpose of the present invention is to provide a dual-channel speed pulse signal alarm device, which synthesizes two different output waveforms of a photoelectric speed sensor through a pulse synthesis circuit. When the frequencies are inconsistent, the duty cycle of the synthesized waveform will change with time, so that the alarm can be driven by comparing it with the standard waveform through an XOR gate circuit. It has the advantages of small size, high reliability and strong applicability.

[0005] The purpose of the present invention can be achieved by the following technical solutions:

[0006] A dual-channel speed pulse signal alarm device comprises: a first pulse acquisition circuit, a second pulse acquisition circuit, a pulse synthesis circuit, a square wave generation circuit, an XNOR gate circuit and an alarm drive circuit, wherein the input ends of the first pulse acquisition circuit and the second pulse acquisition circuit are respectively connected to two outputs of a photoelectric speed sensor, and the output ends are respectively connected to two input ends of the pulse synthesis circuit, the output end of the pulse synthesis circuit is connected to one input end of the XNOR gate circuit, the square wave generation circuit is connected to the other input end of the XNOR gate circuit, the output end of the XNOR gate circuit is connected to the alarm drive circuit, and the alarm drive circuit is connected to the alarm.

[0007] The pulse synthesis circuit is an AND gate circuit, and the square wave generation circuit generates a square wave with a duty cycle of 25%.

[0008] The pulse synthesis circuit is an OR gate circuit, and the square wave generation circuit generates a square wave with a duty cycle of 75%.

[0009] The two pulse acquisition circuits are the same, and only the first one is analyzed. The pulse acquisition circuit includes a first transistor, a first bias resistor, a second bias resistor, a first current limiting resistor, a second current limiting resistor and a protection module. The base of the first transistor is connected to the positive electrode of the output end of the photoelectric speed sensor through the first bias resistor, the collector is connected to the positive electrode of the first DC power supply, and the emitter is connected to the negative electrode of the output end of the photoelectric speed sensor through the second bias resistor and the protection module in sequence. The first current limiting resistor and the second current limiting resistor are connected in series to form a voltage divider circuit, one end of the voltage divider current is connected to the positive electrode of the first DC power supply, and the other end is connected to the negative electrode of the output end of the photoelectric speed sensor through the protection module, and is connected to the second bias resistor. The voltage divider output end of the voltage divider circuit is connected to the input end of the pulse synthesis circuit.

[0010] The pulse acquisition circuit also includes a voltage regulator tube, which is arranged between the first triode and the second bias resistor.

[0011] The protection module includes an anti-reverse diode and a protection resistor connected in parallel with each other.

[0012] The pulse acquisition circuit also includes a decoupling capacitor, one end of which is connected to the voltage divider output end of the voltage divider circuit, and the other end is connected to the negative electrode of the output end of the photoelectric speed sensor through the protection module and is connected to the second bias resistor.

[0013] The square wave generating circuit includes a time base circuit.

[0014] The alarm driving circuit includes a third bias resistor, a fourth bias resistor, a fifth bias resistor, a second transistor, and a third transistor. One end of the third bias resistor is connected to the output end of the XOR gate circuit, and is connected to one end of the fourth bias resistor and the base of the second transistor. The other end of the fourth bias resistor, one end of the fifth bias resistor and the positive electrode of the input end of the alarm are all connected to the positive electrode of the second DC power supply. The other end of the fifth bias resistor is connected to the collector of the second transistor and the base of the third transistor. The emitter of the second transistor is grounded, and the collector of the third transistor is connected to the negative electrode of the input end of the alarm, and the emitter is grounded.

[0015] The alarm is a buzzer.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] 1) The two different output waveforms of a photoelectric speed sensor are synthesized through a pulse synthesis circuit. When the frequencies are inconsistent, the duty cycle of the synthesized waveform will change over time. Therefore, the alarm can be driven by comparing it with the standard waveform through the XOR gate circuit. It has the advantages of small size, high reliability and strong applicability.

[0018] 2) The pulse acquisition circuit can realize isolated sampling of signals, thereby improving reliability.

[0019] 3) The protection module can prevent the reverse impact voltage from passing through and avoid damaging the sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a structural schematic diagram of the present invention;

[0021] Figure 2 is a circuit diagram of an embodiment of the present invention;

[0022] Among them: 1. first pulse acquisition circuit, 2. pulse synthesis circuit, 3. XNOR gate circuit, 4. square wave generation circuit, 5. alarm drive circuit, 6. second pulse acquisition circuit. DETAILED DESCRIPTION

[0023] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. This embodiment is implemented based on the technical solution of the present invention, and provides a detailed implementation method and specific operation process, but the protection scope of the present invention is not limited to the following embodiments.

[0024] A dual-channel speed pulse signal alarm device, such as Figure 1 As shown, it includes: a first pulse acquisition circuit 1, a second pulse acquisition circuit 6, a pulse synthesis circuit 2, a square wave generation circuit 4, an XNOR gate circuit 3 and an alarm drive circuit 5, the input ends of the first pulse acquisition circuit 1 and the second pulse acquisition circuit 6 are respectively connected to the two outputs of a photoelectric speed sensor, and the output ends are respectively connected to the two input ends of the pulse synthesis circuit 2, the output end of the pulse synthesis circuit 2 is connected to one input end of the XNOR gate circuit 3, the square wave generation circuit 4 is connected to the other input end of the XNOR gate circuit 3, the output end of the XNOR gate circuit 3 is connected to the alarm drive circuit 5, and the alarm drive circuit 5 is connected to the alarm.

[0025] The two different output waveforms of a photoelectric speed sensor are synthesized through the pulse synthesis circuit 2. When the frequencies are inconsistent, the duty cycle of the synthesized waveform will change over time. Therefore, the alarm can be driven by comparing it with the standard waveform through the XOR gate circuit. It has the advantages of small size, high reliability and strong applicability.

[0026] The circuit of the present application is lightweight, avoiding the use of large instruments and meters, and is suitable for assisting on-site testing work. In addition, the circuit uses common components, has low cost, and is easy to apply and promote.

[0027] In some embodiments, the pulse synthesis circuit 2 is an AND gate circuit, and the square wave generation circuit 4 generates a square wave with a duty cycle of 25%. In other embodiments, the pulse synthesis circuit 2 is an OR gate circuit, and the square wave generation circuit 4 generates a square wave with a duty cycle of 75%.

[0028] For the implementation method of the pulse synthesis circuit 2 being an OR gate circuit, the two pulse acquisition circuits are the same, and only the first one is analyzed. Figure 2 As shown, specifically, the pulse acquisition circuit includes a first transistor, a first bias resistor, a second bias resistor, a first current limiting resistor, a second current limiting resistor and a protection module. The base of the first transistor is connected to the positive electrode of the output end of the photoelectric speed sensor through the first bias resistor, the collector is connected to the positive electrode of the first DC power supply, and the emitter is connected to the negative electrode of the output end of the photoelectric speed sensor through the second bias resistor and the protection module in turn. The first current limiting resistor and the second current limiting resistor are connected in series to form a voltage divider circuit, one end of the voltage divider current is connected to the positive electrode of the first DC power supply, and the other end is connected to the negative electrode of the output end of the photoelectric speed sensor through the protection module, and is connected to the second bias resistor. The voltage divider output end of the voltage divider circuit is connected to the input end of the pulse synthesis circuit 2. The pulse acquisition circuit also includes a voltage regulator tube, which is arranged between the first transistor and the second bias resistor. The protection module includes an anti-reverse diode and a protection resistor connected in parallel.

[0029] Figure 2 In the figure, R1 is the first bias resistor in the first pulse acquisition circuit 1, R3 is the second bias resistor in the first pulse acquisition circuit 1, similarly, R6 is the first bias resistor in the second pulse acquisition circuit 6, R8 is the second bias resistor in the second pulse acquisition circuit 6, V1 is the first power supply connected to the first pulse acquisition circuit 1, V2 is the first power supply connected to the second pulse acquisition circuit 6, Q1 is the first transistor in the first pulse acquisition circuit 1, Q2 is the first transistor in the second pulse acquisition circuit 6, and R5 is the first transistor in the first pulse acquisition circuit 1. Current limiting resistor, R4 is the second current limiting resistor in the first pulse acquisition circuit 1, R10 is the first current limiting resistor in the second pulse acquisition circuit 6, R10 is the second current limiting resistor in the second pulse acquisition circuit 6, D1 is the voltage-limiting diode in the first pulse acquisition circuit 1, D3 is the voltage-limiting diode in the second pulse acquisition circuit 6, D2 is the anti-reverse diode in the first pulse acquisition circuit 1, R2 is the protection resistor in the first pulse acquisition circuit 1, similarly, D4 is the anti-reverse diode in the second pulse acquisition circuit 6, and R7 is the protection resistor in the second pulse acquisition circuit 6.

[0030] Taking the first pulse acquisition circuit 1 as an example, IN1+ and IN1- are the first output terminals of the photoelectric speed sensor, that is, as the first pulse: Vpp = 8V ± 1V, f = 10kHz, duty cycle 50%. R1 and R3 make Q1 work in the amplification area and play a switch role to control the subsequent circuit. The voltage regulator D1 keeps the channel at 2V, and R4 and R5 play a current limiting role. D2 and R2 prevent the reverse impact voltage from damaging the sensor through IN1-.

[0031] In some embodiments, the pulse acquisition circuit further includes a decoupling capacitor, one end of the decoupling capacitor is connected to the voltage divider output end of the voltage divider circuit, the other end is connected to the negative electrode of the output end of the photoelectric speed sensor through the protection module, and is connected to the second bias resistor. Figure 2 In FIG. 1 , C1 is a decoupling capacitor in the first pulse acquisition circuit 1, and C2 is a decoupling capacitor in the second pulse acquisition circuit 6. The decoupling capacitor can reduce the overshoot and undershoot of the square wave.

[0032] Figure 2 In the figure, U1A is an OR gate circuit, and the two outputs of the photoelectric speed sensor are pulse square waves with the same frequency, a phase difference of 90 degrees and a duty cycle of 50%. Therefore, after passing through the OR gate circuit, a square wave with a duty cycle of 75% is obtained.

[0033] In this embodiment, the square wave generating circuit 4 includes a time base circuit, and a square wave generator is built using LM555CM. The chip power is divided by V1 through R14 and R15 to obtain 2V. The square wave signal with a duty cycle of 75% is calculated at the out end through the values ​​of R1 and R2 and sent to U3A, where U3A is an XOR gate circuit.

[0034] In this embodiment, the alarm is a buzzer, and the alarm driving circuit 5 includes a third bias resistor R19, a fourth bias resistor R16, a fifth bias resistor R17, a second transistor Q3, and a third transistor Q4. One end of the third bias resistor R19 is connected to the output end of the XOR gate circuit 3, and is connected to one end of the fourth bias resistor R16 and the base of the second transistor Q3. The other end of the fourth bias resistor R16, one end of the fifth bias resistor R17 and the positive electrode of the input end of the alarm LS1 are all connected to the positive electrode of the second DC power supply V3. The other end of the fifth bias resistor R17 is connected to the collector of the second transistor Q3 and the base of the third transistor Q4. The emitter of the second transistor Q3 is grounded, and the collector of the third transistor Q4 is connected to the negative electrode of the input end of the alarm LS1, and the emitter is grounded.

[0035] If the two square wave signals with a duty cycle of 75% are exactly the same, U3A outputs a high level, Q3 turns on, Q4 turns off, LS1 has no current flowing through it, and it does not work. For the buzzer, there is no alarm sound. If the two square wave signals with a duty cycle of 75% are inconsistent and deviate, U3A outputs a low level, Q3 turns off, Q4 turns on, and the buzzer LS1 has current flowing through it, starts working, and sounds an alarm.

Claims

1. A dual-channel speed pulse signal alarm device, characterized in that: include: A first pulse acquisition circuit, a second pulse acquisition circuit, a pulse synthesis circuit, a square wave generation circuit, an XNOR gate circuit and an alarm drive circuit, wherein the input ends of the first pulse acquisition circuit and the second pulse acquisition circuit are respectively connected to two outputs of a photoelectric speed sensor, and the output ends are respectively connected to two input ends of the pulse synthesis circuit, the output end of the pulse synthesis circuit is connected to one input end of the XNOR gate circuit, the square wave generation circuit is connected to the other input end of the XNOR gate circuit, the output end of the XNOR gate circuit is connected to the alarm drive circuit, and the alarm drive circuit is connected to the alarm; The pulse synthesis circuit is an OR gate circuit, and the square wave generation circuit generates a square wave with a duty cycle of 75%; The square wave generating circuit includes a time base circuit.

2. A dual-channel speed pulse signal alarm device according to claim 1, characterized in that: The pulse acquisition circuit includes a first transistor, a first bias resistor, a second bias resistor, a first current limiting resistor, a second current limiting resistor and a protection module. The base of the first transistor is connected to the positive electrode of the output end of the photoelectric speed sensor through the first bias resistor, the collector is connected to the positive electrode of the first DC power supply, and the emitter is connected to the negative electrode of the output end of the photoelectric speed sensor through the second bias resistor and the protection module in sequence. The first current limiting resistor and the second current limiting resistor are connected in series to form a voltage divider circuit. One end of the voltage divider circuit is connected to the positive electrode of the first DC power supply, and the other end is connected to the negative electrode of the output end of the photoelectric speed sensor through the protection module and is connected to the second bias resistor. The voltage divider output end of the voltage divider circuit is connected to the input end of the pulse synthesis circuit.

3. A dual-channel speed pulse signal alarm device according to claim 2, characterized in that: The pulse acquisition circuit also includes a voltage regulator tube, which is arranged between the first triode and the second bias resistor.

4. A dual-channel speed pulse signal alarm device according to claim 2, characterized in that: The protection module includes an anti-reverse diode and a protection resistor connected in parallel with each other.

5. A dual-channel speed pulse signal alarm device according to claim 2, characterized in that: The pulse acquisition circuit also includes a decoupling capacitor, one end of which is connected to the voltage divider output end of the voltage divider circuit, and the other end is connected to the negative electrode of the output end of the photoelectric speed sensor through the protection module and is connected to the second bias resistor.

6. A dual-channel speed pulse signal alarm device according to claim 1, characterized in that: The alarm driving circuit includes a third bias resistor, a fourth bias resistor, a fifth bias resistor, a second transistor, and a third transistor. One end of the third bias resistor is connected to the output end of the XOR gate circuit, and is connected to one end of the fourth bias resistor and the base of the second transistor. The other end of the fourth bias resistor, one end of the fifth bias resistor and the positive electrode of the input end of the alarm are all connected to the positive electrode of the second DC power supply. The other end of the fifth bias resistor is connected to the collector of the second transistor and the base of the third transistor. The emitter of the second transistor is grounded, and the collector of the third transistor is connected to the negative electrode of the input end of the alarm, and the emitter is grounded.

7. A dual-channel speed pulse signal alarm device according to claim 1, characterized in that: The alarm is a buzzer.

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