Memory subsystem data migration

Abstract

A method includes receiving a command to write data to a memory device and writing the data to a first memory level of the memory device. The first memory level of the memory device is a dynamic memory level utilizing a single-level cell (SLC), a multi-level cell (MLC), and a three-level cell (TLC). The method further includes migrating the data from the first memory level of the memory device to a second memory level of the memory device. The second memory level of the memory device is a static memory level utilizing a four-level cell (QLC).

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to memory subsystem data migration. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, this application relates to a method for data migration, the method comprising: receiving a command to write data to a memory device; writing the data to a first memory level of the memory device; wherein the first memory level of the memory device is a dynamic memory level utilizing single-level cell (SLC), multi-level cell (MLC), and three-level cell (TLC); and migrating the data from the first memory level of the memory device to a second memory level of the memory device; wherein the second memory level of the memory device is a static memory level utilizing four-level cell (QLC).

[0004] In another aspect, this application relates to an apparatus for data migration, the apparatus comprising: a memory device; and a data migration component coupled to the memory device and configured to: receive a command to write data to the memory device; write the data to a first memory level of the memory device; wherein the data utilizes a single-level cell (SLC), a multi-level cell (MLC), and a three-level cell (TLC); and migrate the data from the first memory level of the memory device to a second memory level of the memory device; wherein the second memory level of the memory device is a static memory level utilizing a four-level cell (QLC).

[0005] In another aspect, this application relates to a system for data migration, the system comprising: a plurality of memory components arranged to form a stackable cross-grid memory cell array; and a processing means coupled to the plurality of memory components, the processing means performing operations including: receiving a host command to write data to at least one of the plurality of memory components; writing the data to a first memory level of the at least one of the plurality of memory components; wherein the first memory level is a dynamic memory level of the at least one of the plurality of memory components utilizing single-level cell (SLC), multi-level cell (MLC), and three-level cell (TLC); and performing media management operations to relocate the data from the first memory level of the at least one of the plurality of memory components to a second memory level of the at least one of the plurality of memory components; wherein the second memory level is a static memory level of the at least one of the plurality of memory components utilizing four-level cell (QLC). Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This is a block diagram of a portion of a memory subsystem according to some embodiments of the present disclosure.

[0009] Figure 3 This is a block diagram of a portion of a memory subsystem according to some embodiments of the present disclosure.

[0010] Figure 4 This is a flowchart of a method corresponding to data migration according to some embodiments of the present disclosure.

[0011] Figure 5 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0012] This disclosure relates to data migration in a memory subsystem, and more specifically, to a memory subsystem that includes a data migration component. The memory subsystem can be a storage system, a storage device, a memory module, or a combination thereof. An example of a memory subsystem is a storage system such as a solid-state drive (SSD). The following description, in conjunction with… Figure 1Examples of storage devices and memory modules are described elsewhere. Generally, a host system may utilize a memory subsystem containing one or more components, such as memory devices for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0013] The memory device may be a non-volatile memory device. An example of a non-volatile memory device is a three-dimensional cross-point memory device containing a cross-point array of non-volatile memory cells. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device (e.g., a three-dimensional cross-point memory device) may be a package of one or more memory components (e.g., memory dies). Each die may consist of one or more planes. Planes may be divided into logical units. For example, a non-volatile memory device may be assembled from multiple memory dies, each of which may individually form a component of the memory device.

[0014] Memory devices can be non-volatile memory devices. An example of a non-volatile memory device is a NAND flash memory device (also known as flash memory). The following section combines... Figure 1 Other examples of non-volatile memory devices are described below. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. Planes may be grouped into logic units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit for storing information. Hereinafter, a block refers to a cell in a memory device used to store data and may contain groups of memory cells, groups of word lines, word lines, or individual memory cells. For some memory devices, a block (also referred to below as a “memory block”) is the smallest erasable area. Pages cannot be erased individually; only the entire block can be erased.

[0015] Each memory device may contain one or more arrays of memory cells. Depending on the cell type, a cell may store one or more bits of binary information and has various logical states related to the number of bits stored. Logical states may be represented by binary values ​​(e.g., "0" and "1") or combinations of these values. Various types of cells exist, such as single-level cells (SLC), multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC). For example, an SLC may store one bit of information and have two logical states.

[0016] Some NAND memory devices employ a floating gate architecture, where memory access is controlled based on the relative voltage variation between the bit lines and word lines. Other examples of NAND memory devices may employ an alternative gate architecture that may include a word line layout that allows for the trapping of charges corresponding to data values ​​within the memory cell based on the properties of the materials used to construct the word lines.

[0017] Some memory cells (e.g., flash cells) can operate in single-level cell (SLC) mode, multi-level cell (MLC) mode, three-level cell (TLC) mode, and four-level cell (QLC) mode (e.g., 1-bit mode, 2-bit mode, 3-bit mode, and 4-bit mode, respectively) (e.g., programming, reading, erasing, etc.). Such cells can be referred to as "mixed-mode" memory cells. Compared to memory devices utilizing single-level cell (SLC), multi-level cell (MLC), and / or three-level cell (TLC) methods, utilizing four-level cell (QLC) methods for the static storage portion of a memory device can provide higher-density memory without increasing the number of memory cells, because each cell can represent more data.

[0018] Utilizing quad-level cell (QLC) storage provides greater storage density per memory cell (e.g., compared to single-level cell (SLC), multi-level cell (MLC), and triple-level cell (TLC)). This greater storage density can provide lower overall write counts per cell and / or lower cost per cell. While lower overall write counts per cell and / or lower cost per cell can be achieved using QLC, it can also lead to lower write performance, shorter cell lifetime, and / or lower reliability (e.g., compared to SLC, MLC, and TLC).

[0019] The aspects of this disclosure address the above and other shortcomings by writing data to a first memory level of the memory device. In some embodiments, the first memory level of the memory device may be a dynamic memory level utilizing single-level cell (SLC), multi-level cell (MLC), and three-level cell (TLC). Data may be migrated from the first memory level of the memory device to a second memory level of the memory device. As used herein, the term "data migration" and variations thereof generally refer to data movement (e.g., writing) within a memory subsystem. "Data migration" may include writing data from one part of the memory subsystem to another part of the memory subsystem as part of foreground and / or background operations. For example, the term "data migration" may refer to writing data from one part of the memory subsystem to another part of the memory subsystem in response to host and / or user commands, and / or may refer to data movement within a memory subsystem as part of background media management operations such as folding operations, wear leveling operations, and / or garbage collection operations, etc. In some embodiments, the second memory level of the memory device may be a static memory level utilizing four-level cell (QLC). As described in more detail in this article, data migration can help eliminate or mitigate the lower write performance associated with QLC and / or reduce the effects of extreme wear conditions, such as wide cross temperatures, where the charge on one or more memory cells crosses the read or write boundary due to the temperature experienced by the memory cells.

[0020] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0021] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0022] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, server, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked commercial device), or such computing device containing memory and processing devices.

[0023] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without intervening components), whether wired or wireless, including, for example, electrical connections, optical connections, magnetic connections, etc.

[0024] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and to read data from memory subsystem 110.

[0025] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Dual Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Dual Data Rate (DDR), Low Power Dual Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize an NVM Fast (NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1The memory subsystem 110 is illustrated as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0026] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0027] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND type flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0028] Each of the memory devices 130 and 140 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), stores one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0029] While non-volatile memory components, such as three-dimensional cross-point arrays of non-volatile memory cells and NAND flash memory (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0030] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0031] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0032] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0033] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to enable desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses, physical media addresses) associated with memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access memory devices 130 and / or 140, and translate responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0034] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access memory device 130 and / or memory device 140.

[0035] In some embodiments, memory device 130 includes a local media controller 135 that operates together with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0036] Memory subsystem 110 may include data migration component 113. Although, in order not to obscure the figures, Figure 1Not shown, but the data migration component 113 may include various circuitry to facilitate: receiving commands to write data to the memory subsystem and / or components of the memory subsystem; writing data to a first memory level of the memory device; wherein the first memory level of the memory device is a dynamic memory level utilizing single-level cell (SLC), multi-level cell (MLC), and three-level cell (TLC) units of the memory subsystem and / or components of the memory subsystem; and / or migrating said data from the first memory level of the memory device to a second memory level of the memory device; wherein the second memory level of the memory device is a static memory level utilizing four-level cell (QLC) units of the memory subsystem and / or components of the memory subsystem. In some embodiments, the data migration component 113 may include dedicated circuitry in the form of an ASIC, FPGA, state machine, and / or other logic circuitry that allows the data migration component 113 to coordinate and / or perform operations to selectively perform data migration operations on the memory devices 130 and / or 140, wherein data is migrated from a dynamic memory level to a static memory level.

[0037] In some embodiments, the memory subsystem controller 115 includes at least a portion of the data migration component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the data migration component 113 is part of the host system 110, an application, or an operating system.

[0038] In some embodiments, the memory subsystem 110, and therefore the data migration component 113, processor 119, and memory devices 130 / 140, may reside on a mobile computing device such as a smartphone, laptop computer, phablet, IoT device, autonomous vehicle, etc. As used herein, the term "mobile computing device" generally refers to a handheld computing device having a tablet or phablet form factor. Generally, a tablet form factor may include a display screen between approximately 3 inches and 5.2 inches (diagonally measured), while a phablet form factor may include a display screen between approximately 5.2 inches and 7 inches (diagonally measured). However, instances of "mobile computing device" are not limited to these, and in some embodiments, "mobile computing device" may refer to IoT devices, as well as other types of edge computing devices.

[0039] In a non-limiting instance, the device (e.g., computing system 100) may include a memory subsystem data migration component 113, which, for brevity, may be referred to herein as a "data migration component." The memory subsystem data migration component 113 may reside on the memory subsystem 110. As used herein, the term "resides on" means that something is physically located on a particular component. For example, "resides on memory subsystem 110" means that the hardware circuitry including the memory subsystem data migration component 113 is physically located on the memory subsystem 110. The term "resides on" may be used interchangeably herein with other terms such as "deployed on" or "located on."

[0040] The memory subsystem data migration component 113 can be configured to receive commands to write data to memory components of the memory subsystem, write data to dynamic memory hierarchies utilizing single-level cell (SLC), multi-level cell (MLC), and three-level cell (TLC), and migrate data from dynamic memory hierarchies to static memory hierarchies utilizing four-level cell (QLC). As described above, the memory component may be a memory die or memory package forming at least a portion of memory device 130 and / or memory device 140. As used herein, "memory hierarchy" refers to a portion of the memory device.

[0041] The memory subsystem data migration component 113 may be further configured to abort data migration from the dynamic memory layer to the static memory layer when a threshold static memory layer fill level is reached, as further discussed herein. In some embodiments, the memory subsystem data migration component 113 may periodically migrate data from the dynamic memory layer to the static memory layer. As an example, the memory subsystem data migration component 113 may migrate data from the dynamic memory layer to the static memory layer within a specific time frame, as further discussed herein.

[0042] Figure 2 This is a block diagram of a portion of a memory subsystem 250 according to some embodiments of the present disclosure. Figure 2 As shown, the memory subsystem 250 may include a host 251, a dynamic memory hierarchy 252 and a static memory hierarchy 253, and a data migration component 113, which may be similar to... Figure 1 The memory subsystem data migration component 113 described herein.

[0043] Dynamic memory hierarchy 252 contains several “dynamic memory cells” or “dynamic blocks”. As used herein, a “dynamic memory cell” or “dynamic block” typically refers to a memory cell that can be allocated to multiple different sizes and is reassigned to different sizes once allocated. For example, the size of different portions of the memory can dynamically increase and / or decrease as memory conditions and / or demands increase and / or decrease.

[0044] As mentioned, dynamic memory hierarchy 252 utilizes single-level cells (SLC), multi-level cells (MLC), and three-level cells (TLC). Embodiments of this disclosure specify that the utilization of SLC, MLC, and TLC can be allocated to multiple different sizes, and reallocated to different sizes after an initial allocation or after a reallocation. In other words, while dynamic memory hierarchy 252 itself is dynamic, the SLC, MLC, and TLC portions of dynamic memory hierarchy 252 are each correspondingly and independently dynamic.

[0045] Controllers (e.g., data migration component 113 and / or memory subsystem controller 115) can be configured to utilize SLC, MLC, and TLC differently (e.g., when encountering different situations and / or different applications). In SLC mode, SLC is written to dynamic memory hierarchy 252; in MLC mode, MLC is written to dynamic memory hierarchy 252; and in TLC mode, TLC is written to dynamic memory hierarchy 252. Because dynamic memory hierarchy 252 is dynamic, the size of dynamic memory hierarchy 252 (e.g., the number of blocks utilized) and / or the size of the set of memory cells associated with said memory hierarchy (e.g., SLC, MLC, and TLC) can change during operation (e.g., during the runtime of the memory subsystem and / or during the runtime of the operating system executed by host 251, i.e., "in operation") to accommodate different memory demands. One or more embodiments specify that different portions of the memory can be used as dynamic memory hierarchy 252. For example, as the demand for memory increases and / or decreases, different portions of the memory (e.g., Figure 1 The size of the different portions of the memory devices 130 and 140 described herein can be dynamically increased and / or decreased.

[0046] For example, one or more embodiments specify that when relatively maximum write speed, relatively minimum power consumption, and / or relatively maximum cell endurance are required, the utilization of SLC in dynamic memory level 252 can be increased compared to the use of MLC and TLC. For example, one or more embodiments specify that when relatively medium write speed, relatively medium power consumption, and / or relatively medium cell endurance are required, the utilization of MLC in dynamic memory level 252 can be increased compared to the utilization of SLC and TLC. For example, one or more embodiments specify that when relatively medium write speed, relatively medium power consumption, and / or relatively medium cell endurance are required, the utilization of TLC in dynamic memory level 252 can be increased compared to the utilization of SLC and MLC.

[0047] Static memory hierarchy 253 contains several “static memory cells” or “static blocks”. As used herein, a “static memory cell” or “static block” generally refers to a collection or group of memory cells within a block of fixed size after being allocated. For example, the static portion of memory does not increase or decrease in size as memory conditions and / or demands increase and / or decrease.

[0048] As mentioned, static memory hierarchy 253 utilizes a four-level cell (QLC). Because static memory hierarchy 253 is static, it is not resized during operation due to various memory requirements. QLC is written to static memory hierarchy 253 in QLC mode. Utilizing QLC for static memory hierarchy 253 provides relatively higher density compared to memory hierarchy utilizing SLC, MLC, and / or TLC. However, QLC provides lower write performance and / or reduced impact from extreme wear conditions (such as wide crossover temperatures) compared to SLC, MLC, and / or TLC. As mentioned, aspects of this disclosure provide writing data to a first memory hierarchy (e.g., dynamic memory hierarchy 252) and migrating data from the first memory hierarchy to a second memory (e.g., static memory hierarchy 253). One or more embodiments specify that the migration of data from the first memory hierarchy to the second memory can occur independently of any direct host interaction.

[0049] One or more embodiments specify that data can be periodically migrated from dynamic memory level 252 to static memory level 253. As an example, the memory subsystem data migration component 113 can migrate data from the dynamic memory level to the static memory level over time intervals ranging from 3 hours to 48 hours and other times. For example, data can be migrated from dynamic memory level 252 to static memory level 253 after a 3-hour interval (e.g., 3 hours after a previous data migration from dynamic memory level 252 to static memory level 253), after a 4-hour interval, after a 6-hour interval, after an 8-hour interval, after a 12-hour interval, after an 18-hour interval, after a 24-hour interval, after a 36-hour interval, and / or after a 48-hour interval. One or more embodiments specify that the migration of data from the first memory level to the second memory can occur independently of any direct host interaction.

[0050] One or more embodiments specify that data can be migrated from dynamic memory level 252 to static memory level 253 when dynamic memory level 252 reaches a threshold dynamic memory level fill level. The threshold dynamic memory level fill level can have different values ​​for different applications. For example, data can be migrated from dynamic memory level 252 to static memory level 253 when dynamic memory level 252 is fully filled (indicating a 100% threshold dynamic memory level fill level), when dynamic memory level 252 is 99% filled (indicating a 99% threshold dynamic memory level fill level) based on the total memory space of dynamic memory level 252, when dynamic memory level 252 is 97% filled (indicating a 97% threshold dynamic memory level fill level) based on the total memory space of dynamic memory level 252, or when dynamic memory level 252 is 95% filled (indicating a 95% threshold dynamic memory level fill level) based on the total memory space of dynamic memory level 252, and when dynamic memory level 252 is filled with other values.

[0051] One or more embodiments specify that data may be migrated from dynamic memory level 252 to static memory level 253 during idle time (e.g., the idle time of the device). As used herein, "idle time" generally refers to a period during which no host operation is performed relative to the memory device and therefore during which no commands are transmitted or otherwise hindered at the interface coupling the host to the memory subsystem. Given the context, the term "idle time" may be used interchangeably with the terms "background operation" or "in the background" where appropriate. Data may be migrated from dynamic memory level 252 to static memory level 253 as a background media management operation (e.g., when the host is not utilizing the interface associated with the memory subsystem).

[0052] One or more embodiments specify that when the system has been idle for a threshold idle time interval, data can be migrated from dynamic memory level 252 to static memory level 253. The threshold idle time interval can have different values ​​for different applications. As an example, when the system has been idle for a threshold idle time interval of 1 minute, 5 minutes, 10 minutes, 15 minutes, 30 minutes, or 60 minutes or other values, data can be migrated from dynamic memory level 252 to static memory level 253.

[0053] One or more embodiments specify that data written to dynamic memory level 252 in SLC mode is migrated to static memory level 253 before data written to SLC mode or TLC mode is migrated to static memory level 253. One or more embodiments specify that data written to dynamic memory level 252 in SLC mode is migrated to static memory level 253 before data written to SLC mode or TLC mode is migrated to static memory level 253. One or more embodiments specify that data written to dynamic memory level 252 in TLC mode is migrated to static memory level 253 before data written to SLC mode or MLC mode is migrated to static memory level 253.

[0054] One or more embodiments specify that data written to dynamic memory level 252 is migrated to static memory level 253 in the order in which it was written to dynamic memory level 252 (e.g., sequential order). For example, data written to dynamic memory level 252 relatively earlier may be migrated to static memory level 253 before data written to dynamic memory level 252 relatively later. Therefore, the embodiments herein cover the case where data written to dynamic memory level 252 is migrated to static memory level 253 according to a first-in-first-out (FIFO) strategy. However, the embodiments are not limited thereto, and data written to dynamic memory level 252 may be migrated to static memory level 253 according to a last-in-first-out (LIFO) strategy and / or according to a strategy in which specific data is migrated preferentially according to associated characteristics.

[0055] One or more embodiments specify that when static memory level 253 reaches a threshold static memory level fill level, data migration from dynamic memory level 252 to static memory level 253 may be aborted (e.g., stopped). The threshold static memory level fill level may have different values ​​for different applications. For example, data migration from dynamic memory level 252 to static memory level 253 may be aborted when the static memory level has zero available storage space, 1% of the total storage space of the static memory level, 3% of the total storage space of the static memory level, or 5% of the total storage space of the static memory level, or other integer or fractional values ​​of available storage space. One or more embodiments specify that when static memory level 253 no longer reaches the threshold static memory level fill level (e.g., after an erase operation), data migration from dynamic memory level 252 to static memory level 253 may be resumed (e.g., after aborted migration).

[0056] If passed Figure 2 As shown by the arrow, data can be written from host 251 to dynamic memory level 252. Figure 2 This further demonstrates that data can be accessed by host 251 from both dynamic memory level 252 and static memory level 253. For example, after data is migrated from dynamic memory level 252 to static memory level 253, the data can be accessed from static memory level 253. However, data written to dynamic memory level 252 can be accessed from dynamic memory level 252 (e.g., before the data is migrated from dynamic memory level 252 to static memory level 253). One or more embodiments specify that data cannot be written directly from host 251 to static memory level 253.

[0057] For example, one or more embodiments specify that sequential data, such as images, videos, and / or audio, can be written from host 251 to dynamic memory level 252 in SLC mode, while non-sequential data can be written from host 251 to dynamic memory level 252 in MLC or TLC mode. Generally, sequential data is written to sequential memory cells of the memory device (e.g., physically adjacent sectors of the memory level), while non-sequential data is written to memory cells scattered throughout the memory device (e.g., data is written to non-adjacent physical sectors of the memory level). One or more embodiments specify that when dynamic memory level 252 is full, data can be written directly to static memory level 253 (e.g., bypassing dynamic memory level 252).

[0058] One or more embodiments specify that data written to dynamic memory level 252 may be accessed from dynamic memory level 252 after the data has been migrated to static memory level 253 (e.g., before the data is erased from dynamic memory level 252). Accessing data from dynamic memory level 252 after the data has been migrated to static memory level 253 may provide relatively faster access (e.g., compared to accessing data from static memory level 253) and / or may provide a relatively lower probability of error and / or a lower raw bit error rate (e.g., compared to accessing data from static memory level 253).

[0059] Figure 3 This is a block diagram of a portion of a memory subsystem 254 according to some embodiments of the present disclosure. Figure 3 As shown, the memory subsystem 254 may include a host 251, a static memory hierarchy 255 (e.g., a third memory hierarchy), and a dynamic memory hierarchy 252 (e.g., as shown in the diagram). Figure 2 (as discussed) and static memory level 253 (e.g., as discussed) Figure 2 (As discussed).

[0060] One or more embodiments specify that static memory hierarchy 255 utilizes a single-level cell (SLC). Because static memory hierarchy 255 is static, it is not resized during operation to accommodate various memory requirements. Data is written to static memory hierarchy 255 in SLC mode. Static memory hierarchy 255 may have different sizes (e.g., containing different numbers of memory cells) for different applications. One or more embodiments specify that static memory hierarchy 255 utilizes fewer memory cells than dynamic memory hierarchy 252. One or more embodiments specify that static memory hierarchy 255 utilizes more memory cells than dynamic memory hierarchy 252. One or more embodiments specify that the number of memory cells utilized by static memory hierarchy 255 is equal to that of dynamic memory hierarchy 252. Embodiments of this disclosure specify that data can be migrated from static memory hierarchy 255 to static memory hierarchy 253, dynamic memory hierarchy 252, or both.

[0061] One or more embodiments specify that data can be periodically migrated from static memory level 255 to static memory level 253 and / or dynamic memory level 252. As an example, the memory subsystem data migration component 113 can migrate data from static memory level 255 to static memory level 253 and / or dynamic memory level 252 within a time range of 3 hours to 48 hours and other times. For example, data can be migrated from static memory level 255 to static memory level 253 after a 3-hour interval (e.g., 3 hours after a previous data migration from static memory level 255 to static memory level 253 and / or dynamic memory level 252), after a 4-hour interval, after a 6-hour interval, after an 8-hour interval, after a 12-hour interval, after an 18-hour interval, after a 24-hour interval, after a 36-hour interval, and / or after a 48-hour interval and / or other integer or fractional time interval values.

[0062] One or more embodiments specify that when static memory level 255 reaches a threshold static memory level fill level, data can be migrated from static memory level 255 to static memory level 253 and / or dynamic memory level 252. The threshold static memory level fill level may have different values ​​for different applications. For example, when static memory level 255 is fully filled (indicating a 100% threshold static memory level fill level), when static memory level 255 is 99% filled based on the total memory space of static memory level 255 (indicating a 99% threshold static memory level fill level), when static memory level 255 is 97% filled based on the total memory space of static memory level 255 (indicating a 97% threshold static memory level fill level), or when static memory level 255 is 95% filled based on the total memory space of static memory level 255 (indicating a 95% threshold static memory level fill level), and when static memory level 255 is filled with other integer or fractional values, data can be migrated from static memory level 255 to static memory level 253 and / or dynamic memory level 252.

[0063] One or more embodiments specify that data may be migrated from static memory level 255 to static memory level 253 and / or dynamic memory level 252 during idle periods (e.g., when the device, host, memory subsystem, or components thereof are idle). Data may be migrated from static memory level 255 to static memory level 253 and / or dynamic memory level 252 as background media management operations (e.g., when the host is not utilizing the interface associated with the memory subsystem).

[0064] One or more embodiments specify that when the system has been idle for a threshold idle time interval, data may be migrated from static memory level 255 to static memory level 253 and / or dynamic memory level 252. The threshold idle time interval may have different values ​​for different applications. As an example, when the system has been idle for a threshold idle time interval of 1 minute, 5 minutes, 10 minutes, 15 minutes, 30 minutes, or 60 minutes, or other integer or fractional values, data may be migrated from static memory level 255 to static memory level 253 and / or dynamic memory level 252.

[0065] One or more embodiments specify that, before migrating data written to dynamic memory level 252 to static memory level 253, data written to static memory level 255 in SLC mode will be migrated to static memory level 253. One or more embodiments specify that, after migrating data written to dynamic memory level 252 to static memory level 253, data written to static memory level 255 in SLC mode will be migrated to static memory level 253. One or more embodiments specify that, after migrating data written to dynamic memory level 252 in SLC mode to static memory level 253, but before migrating data written to dynamic memory level 252 in MLC mode or TLC mode to static memory level 253, data written to static memory level 255 in SLC mode will be migrated to static memory level 253.

[0066] If passed Figure 3 As shown by the arrows, data can be written from host 251 to dynamic memory level 252 and / or static memory level 255. Figure 3 This further illustrates that data can be accessed by host 251 from each of dynamic memory level 252, static memory level 255, and static memory level 253. For example, after data is migrated from static memory level 255 to static memory level 253, the data can be accessed from static memory level 253. However, data written to static memory level 255 can be accessed from static memory level 255 before the data is migrated from static memory level 255 to static memory level 253. One or more embodiments specify that data cannot be written directly from host 251 to static memory level 253.

[0067] One or more embodiments specify that data written to static memory level 255 may be accessed from static memory level 255 after the data has been migrated to static memory level 253 (e.g., before the data is erased from static memory level 255). Accessing data from static memory level 255 after the data has been migrated to static memory level 253 may provide relatively faster access (e.g., compared to accessing data from static memory level 253) and / or provide a relatively lower probability of error or raw bit error rate (e.g., compared to accessing data from static memory level 253).

[0068] Figure 4 This is a flowchart of a method 470 corresponding to data migration according to some embodiments of the present disclosure. Method 470 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 470 is performed by… Figure 1 The data migration component 113 is executed. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0069] At operation 472, a command to write data to a memory device can be received. In some embodiments, the memory device may be similar to... Figure 1 The memory device 130 described herein. As described above, memory components may be memory dies or memory packages, which are coupled to each other to create a memory cell array, such as a three-dimensional stackable cross-mesh memory cell array used by a memory subsystem to store data.

[0070] At operation 474, data can be written to the first memory level of the memory device. The embodiment specifies that the first memory level of the memory device is a dynamic memory level utilizing single-level cell (SLC), multi-level cell (MLC), and three-level cell (TLC) architectures.

[0071] At operation 476, data can be migrated from the first memory level of the memory device to the second memory level of the memory device. The embodiment specifies that the second memory level of the memory device is a static memory level utilizing a four-level cell (QLC).

[0072] In some embodiments, method 470 may include periodically migrating data from a first memory tier of the memory device to a second memory tier of the memory device. As an example, data may be migrated from the first memory tier of the memory device to the second memory tier of the memory device within a range of 3 hours to 48 hours and other values.

[0073] In some embodiments, method 470 may include migrating data from the first memory level of the memory device to a second memory level of the memory device when the first memory level of the memory device reaches a threshold first memory level fill level.

[0074] In some embodiments, method 470 may include suspending data migration from the first memory level of the memory device to the second memory level of the memory device when the second memory level of the memory device reaches a threshold second memory level fill level.

[0075] In some embodiments, method 470 may include accessing data from the first memory level of the memory device before migrating data from a first memory level of the memory device to a second memory level of the memory device.

[0076] Figure 5 This is a block diagram of an example computer system 500 in which embodiments of this disclosure may operate. For example, Figure 5 This describes an instance machine of computer system 500, within which a set of instructions is executable to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 500 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of data migration component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0077] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, while a single machine is described, the term "machine" should also be considered to include any collection of machines that individually or collectively execute a set (or more) of instructions to perform any one or more of the methods discussed herein.

[0078] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518 that communicates with each other via a bus 530.

[0079] Processing device 502 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 for communication via network 520.

[0080] Data storage system 518 may include machine-readable storage medium 524 (also referred to as computer-readable medium) on which one or more sets of instructions 526 or software embodying any one or more of the methods or functions described herein are stored. Instructions 526 may also reside wholly or at least partially within main memory 504 and / or processing device 502 during execution by computer system 500, which also constitute machine-readable storage medium. Machine-readable storage medium 524, data storage system 518, and / or main memory 504 may correspond to... Figure 1 The memory subsystem 110.

[0081] In one embodiment, instruction 526 includes implementing a data migration component (e.g., Figure 1The data migration component 113) contains functional instructions. Although the machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing the one or more sets of instructions. It should also be considered that the term "machine-readable storage medium" includes any medium capable of storing or encoding a set of instructions that are executable by a machine and cause the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0082] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithms are described and represented as a way for those skilled in the art of data processing to most effectively communicate the essence of their work to others skilled in the art. Algorithms herein are generally considered to be a self-consistent sequence of operations that produce a desired result. These operations are those that require physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0083] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0084] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0085] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods. Structures for these various systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using a variety of programming languages.

[0086] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0087] In the foregoing description, embodiments of this disclosure have been described with reference to specific examples thereof. It will be apparent that various modifications can be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A method for data migration, the method comprising: receiving a command (472) to write data to a memory device (130, 140); writing the data to a first memory tier (252) of the memory device; wherein the first memory tier of the memory device is a dynamic memory tier (474) utilizing single level cell (SLC), multi-level cell (MLC), and triple level cell (TLC), wherein the dynamic memory tier includes a number of memory cells that can be allocated to a plurality of different sizes and once allocated are reallocated to different sizes; and migrating the data from the first memory tier of the memory device to a second memory tier (253) of the memory device; wherein the second memory tier of the memory device is a static memory tier (476) utilizing quad level cell (QLC), wherein the static memory tier includes a number of sets or groups of memory cells within blocks that are fixed in size once allocated to a size.

2. The method of claim 1, wherein migrating the data from the first memory tier of the memory device to the second memory tier of the memory device is performed periodically.

3. The method of claim 1, wherein migrating the data from the first memory tier of the memory device to the second memory tier of the memory device is performed when the first memory tier of the memory device reaches a threshold first memory tier fill level.

4. The method of any one of claims 1-3, further comprising suspending the migration of the data from the first memory tier of the memory device to the second memory tier of the memory device when the second memory tier of the memory device reaches a threshold second memory tier fill level.

5. The method of any one of claims 1-3, further comprising accessing the data from the first memory tier of the memory device prior to migrating the data from the first memory tier of the memory device to the second memory tier of the memory device.

6. An apparatus for data migration, the apparatus comprising: a memory device (130, 140); and a data migration component (113) coupled to the memory device and configured to: receive a command to write data to the memory device; write the data to a first memory tier (252) of the memory device; wherein the first memory tier of the memory device utilizes single level cell (SLC), multi-level cell (MLC), and triple level cell (TLC); and migrate the data from the first memory tier of the memory device to a second memory tier (253) of the memory device; wherein the second memory tier of the memory device is a static memory tier utilizing quad level cell (QLC), wherein the static memory tier includes a number of sets or groups of memory cells within blocks that are fixed in size once allocated to a size.

7. The apparatus of claim 6, wherein the first memory hierarchy of the memory device utilizing single level cell (SLC), multi-level cell (MLC), and triple level cell (TLC) is a dynamic memory hierarchy, wherein the dynamic memory hierarchy includes a number of memory cells that can be allocated to a plurality of different sizes and once allocated are reallocated to different sizes.

8. The apparatus of claim 7, wherein the data migration component is configured to: write the data to a third memory hierarchy (255) of the memory device; wherein the third memory hierarchy of the memory device is a static memory hierarchy utilizing single level cell (SLC).

9. The apparatus of claim 8, wherein the second memory hierarchy of the memory device includes a greater number of memory cells than the third memory hierarchy of the memory device.

10. The apparatus of claim 8, wherein the data migration component is configured to migrate the data written to the third memory hierarchy of the memory device to the second memory hierarchy of the memory device or the first memory hierarchy of the memory device or both.

11. The apparatus of any one of claims 6-7, wherein the data migration component is configured to migrate the data from the first memory hierarchy of the memory device to the second memory hierarchy of the memory device during an idle time of the apparatus.

12. A system (100, 500) for data migration, the system comprising: a plurality of memory components arranged to form a stackable cross-grided array of memory cells; and a processing device (502) coupled to the plurality of memory components, the processing device performing operations comprising: receiving a host command to write data to at least one of the plurality of memory components; writing the data to a first memory hierarchy (252) of the at least one of the plurality of memory components; wherein the first memory hierarchy is a dynamic memory hierarchy of the at least one of the plurality of memory components utilizing single level cell (SLC), multi-level cell (MLC), and triple level cell (TLC), wherein the dynamic memory hierarchy includes a number of memory cells that can be allocated to a plurality of different sizes and once allocated are reallocated to different sizes; and performing a media management operation to relocate the data from the first memory hierarchy of the at least one of the plurality of memory components to a second memory hierarchy (253) of the at least one of the plurality of memory components; wherein the second memory hierarchy is a static memory hierarchy of the at least one of the plurality of memory components utilizing quad level cell (QLC), wherein the static memory hierarchy includes a number of sets or groups of memory cells within blocks that are fixed in size once allocated to a size.

13. The system of claim 12, wherein the processing device is to perform operations comprising accessing the data from the first memory level of the at least one of the plurality of memory components prior to performing the media management operation to relocate the data from the first memory level of the at least one of the plurality of memory components to the second memory level of the at least one of the plurality of memory components.

14. The system of claim 13, wherein the processing device is to perform operations comprising accessing the data from the second memory level of the at least one of the plurality of memory components after performing the media management operation to relocate the data from the first memory level of the at least one of the plurality of memory components to the second memory level of the at least one of the plurality of memory components.

15. The system of claim 12, wherein the host command to write data comprises sequential data to single level cell (SLC) of the first memory level.

16. The system of claim 15, wherein the media management operation is performed when the first memory level of the at least one of the plurality of memory components reaches a threshold first memory level fill level.

17. The system of claim 12, wherein the media management operation is performed when the system has been idle for a threshold idle time interval.

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