Layout method and computer system

Abstract

The present invention provides a layout method and a computer system for integrated circuit design. Each wire is treated as a movable soft module, and the wire receives more penalty when it covers more congested area. Therefore, it is easier to move the wire away from the congested area. In addition, to solve local congestion, the present invention provides a new expansion method, which increases the area of a group according to the wire strength of the group and the congestion level of the area occupied by the group. Therefore, better routability and wire length can be achieved.

Description

Technical Field

[0001] This disclosure relates to a layout method for integrated circuit design that can solve both global and local wiring congestion. Background Technology

[0002] In modern very-large-scale integration (VLSI) design, cell placement remains the most critical stage in physical design. The placement result directly affects chip trace length, routability, and timing. Despite the development of numerous algorithms over the past few decades, placement remains one of the most challenging problems, with significant room for improvement.

[0003] To reduce design complexity, many studies divide placement into three stages: global placement (GP), legalization (LG), and detailed placement (DP). The goal of global placement is to place standard cells on the placement area while optimizing specific issues such as trace length and routerizability; the results have a critical impact on the remaining stages. Routing congestion is a major consideration in contemporary global placement algorithms because placement quality directly affects routerizability during routing. However, considering routerizability in placement is quite complex because routing congestion can originate from different sources, termed global routing congestion and local routing congestion. Figure 1 An example is illustrated to show routing congestion caused by different reasons. Each scenario (110, 120, 130) shows 25 g-cells in a region, each of which may experience routing congestion, and a congested region may contain one or more congested g-cells. Specifically, scenario 110 contains four g-cells causing routing congestion (represented by dotted backgrounds), scenario 120 contains three, and scenario 130 contains two. We consider scenarios 110 and 120 as local routing congestion because they can be resolved by moving cells away from the congested region. However, the congestion in scenario 130 cannot be eliminated by moving cells; this is considered global routing congestion. To resolve routing congestion during placement, we must address both global and local routing congestion separately. Summary of the Invention

[0004] This disclosure presents a layout method for integrated circuit design in a computer system. The layout region is divided into multiple grids, with multiple cells forming multiple connections, each connection connecting at least two cells. This layout method includes: treating cells as multiple groups and merging groups at each level from bottom to top; performing initial layout; and ungrouping at each level from top to bottom and executing a first layout procedure. The first layout procedure includes: establishing a bounding box for each connection, the bounding box covering a first grid; for each connection, calculating a congestion penalty based on the overlap area between the bounding box and the first grid and the overflow value of the first grid; and establishing a first objective function based on the congestion penalty of the connection and determining the position of the group such that the first objective function has an extremum.

[0005] In some embodiments, the step of merging groups includes: generating a new group that includes the first group and the second group; and adding at least the internal connection strength of the first group, the internal connection strength of the second group, and a fraction between the first group and the second group to obtain the internal connection strength of the new group, wherein the fraction is negatively correlated with the number of branches of the connection between the first group and the second group.

[0006] In some embodiments, when the first group or the second group belongs to the lowest level in the hierarchy, the corresponding internal connection strength is 0. The aforementioned score is also negatively correlated with the area of ​​the first group and the area of ​​the second group.

[0007] In some embodiments, the first layout procedure further includes: updating the overflow value of each grid; and for each group, obtaining the second grid in the grid that has the largest overlap with the group, calculating the expansion ratio based on the overflow value of the second grid and the internal connection strength of the group, and adjusting the size of the group according to the expansion ratio.

[0008] In some embodiments, the first layout procedure further includes: when calculating the expansion ratio, multiplying the internal connection strength of the corresponding group by a weight that is positively correlated with the current level.

[0009] In some embodiments, the expansion ratio is calculated according to the following mathematical formula.

[0010]

[0011]

[0012]

[0013] Where 'l' represents the current level. This indicates the i-th group at the current level. Represents the i-th group The expansion ratio, N L Indicates the number of levels. γ minγ max o T and η T It is a pre-defined real number. Represents the i-th group The overflow value of the corresponding second grid, Represents the i-th group Internal wiring strength, o max η is the maximum overflow value in the grid. max This represents the maximum internal connectivity strength of the group.

[0014] In some embodiments, the layout method further includes: executing a second layout procedure before the first layout procedure. The second layout procedure includes: for each group, calculating the group expansion ratio and adjusting the group size according to the expansion ratio; and establishing a second objective function and determining the position of the group such that the second objective function has an extremum, wherein the second objective function does not include a winding congestion penalty.

[0015] In some embodiments, the winding congestion penalty for each connection is calculated according to the following mathematical formula.

[0016]

[0017] Where C i B represents the congestion penalty for the i-th connection in the network. i Let g represent the bounding box corresponding to the i-th connection, and let G represent the set formed by the mesh. k Represents the bounding box B in the grid. i The covered grid. ρ k Represents the grid g k With enclosure box B i The overlapping area between them and the bounding box B i The ratio between the areas, π k Represents the grid g k Overflow value.

[0018] From another perspective, the embodiments disclosed herein propose a computer system comprising: a program module for treating units as multiple groups and merging these groups at each of multiple levels from bottom to top; a program module for performing an initial layout; and a program module for unpacking the groups at each level from top to bottom and executing a first layout procedure. Attached Figure Description

[0019] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation.

[0020] Figure 1 An example is illustrated to show the different causes of wiring congestion;

[0021] Figure 2 This is a schematic diagram illustrating the unit and its connections according to an embodiment;

[0022] Figure 3 This is a flowchart illustrating a layout method according to one embodiment;

[0023] Figure 4 A detailed flowchart of step 301 is shown;

[0024] Figure 5 This is a diagram illustrating the layout results of high-level and low-level layers, along with the corresponding congestion diagram, based on an embodiment.

[0025] Figure 6 A detailed flowchart of step 303 is illustrated according to one embodiment;

[0026] Figure 7 This is a schematic diagram illustrating the connecting lines and the bounding box according to one embodiment;

[0027] Figure 8 This is a schematic diagram illustrating the connecting lines and the congestion area according to one embodiment;

[0028] Figure 9 This is a schematic diagram illustrating the overlap of the bounding box and the grid according to one embodiment.

[0029] [Symbol Explanation]

[0030] 110, 120, 130: Context

[0031] Units 201-204

[0032] 211~214: Connect the dots

[0033] 301~303, 401~409, 601~610: Steps

[0034] 501, 530: Layout area

[0035] 520,540: Congestion Diagram

[0036] 710: Connection

[0037] 721~724: Foot joint

[0038] 730: Enclosure Box

[0039] 810, 820: Context

[0040] 821~823: Congested Areas

[0041] 831~833: Connecting lines

[0042] 901~904: Grid

[0043] 910: Enclosure Detailed Implementation

[0044] The terms "first," "second," etc., used in this article do not specifically refer to order or sequence; they are merely used to distinguish elements or operations described using the same technical terms.

[0045] Figure 2 This is a schematic diagram illustrating the unit and its connections according to an embodiment. Figure 2 Four units 201-204 are illustrated, which form nets 211-214. Each net connects a pin on unit 201-204, and each net connects at least two units. For example, net 211 connects an input pin of unit 201 to an output pin of unit 202, and so on. Here, the number of branches of a net is defined as the number of pins connected; for example, net 211 has 2 branches, while net 214 has 3 branches. In this embodiment, units 201-204 are logic gates, but in other embodiments they could be flip-flops or other suitable circuits.

[0046] The layout method proposed here is to distribute all the units in a layout area, that is, to determine the position of each unit. Figure 3 This is a flowchart illustrating a layout method according to one embodiment. Please refer to it. Figure 3 The proposed layout method is based on a multi-level framework and includes three steps 301-303. Step 301, also known as coarsening, treats all cells as multiple clusters and merges these clusters at each level from bottom to top. In step 302, an initial layout is performed, which can employ any known method, such as any quadratic placement algorithm. Step 303, also known as uncoarsening or refinement, uncoarses the clusters at each level from top to bottom and determines the position of each cluster. Detailed embodiments are described below.

[0047] Figure 4A detailed flowchart of step 301 is shown. In step 401, the Design Hierarchy Tree (DHT) is built. This step can be referenced in the paper Lin, Jai-Ming, Szu-Ting Li, and Yi-Ting Wang. "Routability-driven Mixed-size Placement Prototyping Approach Considering Design Hierarchy and Indirect Connectivity Between Macros." Proceedings of the 56th Annual Design Automation Conference 2019. Here, 'l' represents the hierarchy, which is initialized to 0. In hierarchy 0, each cell is treated as a group, represented as...

[0048] The two groups to be merged are denoted as follows: as well as The resulting new group is represented as In step 402, a new group is generated. With inclusion group and groups Among them, the group and groups The largest score is between The calculation method is as shown in the following mathematical formula 1.

[0049] [Mathematical Expression 1]

[0050]

[0051] in group area, group The area of ​​A. avg E represents the average area of ​​all groups. μ is a preset (user-defined) real number. j，k Represents a connection group and groups The set formed by connecting lines. m Represents a connection group and groups One of the lines connecting d(e) m ) indicates the connection e m The number of branches. Larger scores. group It has a small area and relatively strong connection strength (the second term in mathematical formula 1). Here, the fraction... with the group The area is negatively correlated. In particular, the fractions... The number of branches d(e) of the connection m There is a negative correlation because if the number of branches in a connection is small, it means that the two groups are connected by fewer lines, and therefore the connection between them is stronger; conversely, if the number of branches in a connection is large, it means that the two groups can be connected by multiple lines, and therefore the connection between them is weaker.

[0052] In step 403, the internal connectivity intensities (ICI) of the new group are calculated as shown in the following mathematical formula 2.

[0053] [Mathematical Expression 2]

[0054]

[0055] in Indicates a new group The internal wiring strength, group The internal wiring strength, group The strength of the internal connections. From another perspective, the group... Internal connection strength, group The internal connection strength and the fraction between the two groups The summation yields the internal connectivity strength of the new group. When the group belongs to the lowest level (l=0), the internal connectivity strength is 0, which means... It is worth noting that larger scores It will produce greater internal wiring strength

[0056] In step 404, it is determined whether to stop merging. In some embodiments, since the number of groups decreases, the decision to continue merging can be based on the number of groups. For example, it can be determined that N... l / N′ l Does α hold true, where N l Let N′ be the initial number of groups at level l. l Let α be the current number of groups, and let α be a real number determined by the user (e.g., 1.7). If the above inequality holds, stop merging (proceed to step 408); otherwise, continue merging (proceed to step 405).

[0057] In step 405, it is determined whether there are suitable groups to merge. Based on the algorithm for designing hierarchical trees, only groups at the same level in the design hierarchical tree are selected. If the result of step 405 is yes, the design hierarchical tree is modified in step 406, and then step 407 is performed to process the new level in the design hierarchical tree. If the result of step 405 is no, the process returns to step 402. For details on steps 405-407, please refer to the paper on designing hierarchical trees; they will not be elaborated upon here.

[0058] In step 408, it is determined whether to stop building new levels. In some embodiments, the decision to stop can also be based on the number of groups, for example, determining N′. l The process checks if β is true, where β is a real number determined by the user; in this embodiment, β = 0.05 × N0. If the result of this inequality is yes, the process ends; otherwise, proceed to step 409 to move to the next level, i.e., l = l + 1.

[0059] In this embodiment, a hierarchical tree is used to merge groups. However, in other embodiments, any algorithm can be used to merge groups, as long as the calculation of the internal connectivity strength of the group at each level conforms to the spirit of this disclosure. In other words, fractions other than those in Equation 1 can be used to calculate the internal connectivity strength when merging groups. Furthermore, the fractions used in merging groups and the fractions used to calculate the internal connectivity strength can be different; as long as the fractions are different when calculating the internal connectivity strength... A positive correlation between the strength of the connection between the two groups aligns with the spirit of this disclosure. Furthermore, in the above embodiments, the connection strength is represented by the number of branches, and the number of branches is negatively correlated with the connection strength. Those skilled in the art will design different fractions based on the above disclosure.

[0060] The next step is to coarsen the mesh. In some known techniques, inflation is used to increase the size of the cells to avoid localized wiring congestion. This can cause the cells to move out of the congested areas. This approach relies on a congestion map, which is determined based on the mesh overflow. However, congestion maps at higher levels are not accurate. Figure 5 This diagram illustrates the layout results of high-level and low-level modules, along with the corresponding congestion diagram, based on an embodiment. Please refer to... Figure 5 Layout region 510 illustrates the layout result at a high level, and congestion diagram 520 is also a result calculated at a high level. Furthermore, layout region 530 shows the layout result at a low level, and congestion diagram 540 is a result calculated at a low level. From... Figure 5It can be seen that there is a significant difference between congestion diagram 520 and congestion diagram 540, because the congestion within the group is unknown. In this embodiment, expansion is performed based on the congestion diagram and the internal interconnection strength of the group, thereby reducing local wiring congestion.

[0061] Figure 6 A detailed flowchart of step 303 is illustrated according to one embodiment. In step 601, the congestion graph is updated. This congestion graph includes the overflow value of each grid. The overflow value is defined as the number of lines required by a grid minus the number of lines that the grid can provide. The larger the overflow value, the more congested the grid is. The overflow value of each grid is updated according to the current layout. Those skilled in the art will understand the congestion graph, and it will not be described in detail here.

[0062] In step 602, the groups in the current level 1 are unpacked. In step 603, the expansion ratio of each group is calculated based on the congestion diagram and the strength of the internal connections. Specifically, the expansion ratio can be calculated according to the following mathematical formulas 3 to 5.

[0063] [Mathematical Expression 3]

[0064]

[0065] [Mathematical Expression 4]

[0066]

[0067] [Mathematical Expression 5]

[0068]

[0069] in group The expansion ratio. Due to the group Multiple grids may overlap; only groups are considered here. The grid with the maximum overlap is denoted by g, and This represents the overflow value of grid g. The overflow value, o, represents the normalized overflow value. max This represents the largest overflow value across all grids. group The internal wiring strength, η represents the strength of the normalized internal connections. max This represents the maximum internal connectivity strength among all groups. Additionally, o T η T γ min γ max N is a preset (user-defined) real number. LThis indicates the total number of levels. In some embodiments, the expansion ratio is limited to between 1 and 2, therefore γ can be set. min =1,γ max =2. In some embodiments, η T It is twice the average strength of the internal connections of all groups in the current level l.

[0070] It is worth noting that l / N in mathematical formula 3 L Let l be a weight, which is positively correlated with the current level l. Since the current level l gradually decreases during the coarsening process, the weight l / N is... L The weights decrease from 1 at the highest level to 0 at the lowest level (because each group contains only one unit at the lowest level). Weight l / N L The reason it's set to decrease is that at higher levels, a group has more internal connectivity, and overflow values ​​are inaccurate. Conversely, at lower levels, a group has less internal connectivity, and overflow values ​​are more accurate. This is used when calculating the inflation ratio. Afterwards, the group can be adjusted according to this expansion ratio. The size (i.e. the area it occupies in the layout area).

[0071] In step 604, a dispersion method driven by the line length is executed. Specifically, an objective function can be established and the position of the group can be determined such that the objective function has an extremum. This objective function can be expressed as the following mathematical formula 6.

[0072] [Mathematical Expression 6]

[0073]

[0074] In this embodiment, the layout area is divided into multiple bins, the size of which can be greater than, equal to, or smaller than the grid size. W(x, y) represents the total length of the lines. U b (x, y) represents the total area of ​​the cells in slot b. M bThis represents the maximum allowed unit area in slot b. λ1 and λ2 are user-defined real numbers. For details of the above mathematical formula 6, please refer to the paper Chen, Tung-Chieh, et al. "NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27.7 (2008): 1228-1240, which will not be elaborated here.

[0075] In step 605, it is determined whether the dispersion is sufficient. If yes, proceed to step 606; otherwise, return to step 604. In some embodiments, the overflow area of ​​each slot can be calculated, defined as the sum of the areas of all units (groups) in the slot minus the area of ​​the slot. A smaller overflow area indicates a lower degree of congestion. Dividing the sum of the overflow areas of all slots by the sum of the areas of all movable modules (groups) yields an area overflow ratio. If this area overflow ratio is less than a preset value (e.g., 0), it is determined that the dispersion is sufficient.

[0076] In step 606, the overflow value of each grid is updated. In step 607, for each group, the expansion ratio is calculated based on the overflow value of the grid and the internal interconnection strength of the group, and the size of the group is adjusted according to this expansion ratio. Step 607 can be referred to step 603, and will not be repeated here.

[0077] In step 608, a layout method driven by routableness is executed. Since global congestion cannot be solved by considering only line length, each connection is treated here as a movable and shape-changeable bounding box. Figure 7 This is a schematic diagram illustrating the wiring and bounding box according to one embodiment. Please refer to... Figure 7 Connector 710 connects pins 721-724, and bounding box 730 is the smallest rectangle capable of encompassing all pins 721-724. In this embodiment, a penalty can be applied based on the area occupied by each connector; the more congested areas the bounding box 730 covers, the more penalties are applied to the corresponding connector. In this way, the position and shape of the bounding box 730 automatically change, moving the connectors to less congested areas. Figure 8 This is a schematic diagram illustrating the connecting lines and congestion area according to one embodiment. Please refer to... Figure 8Scenario 810 illustrates the layout result of a known approach, which includes three congested areas 821-823 and three connecting lines 831-833. Through the method presented in this disclosure, the connecting lines can change shape and position, as shown in Scenario 820, where the shape of connecting lines 831-833 can be changed and they can move to less congested areas.

[0078] Specifically, n is used here. i Let B represent the i-th connection, and B... i Indicates the connection n i The corresponding bounding box. Given the layout position, connect n lines. i The corresponding winding congestion penalty (as a penalty term) is calculated by the following mathematical formula 7.

[0079] [Mathematical Expression 7]

[0080]

[0081] Where C i Indicates the connection n i The winding congestion penalty. G represents the set formed by all meshes. g k Indicates bounding box B i The covered grid, π k Represents the grid g k The overflow value. ρ k Represents the grid g k With enclosure box B i The overlapping area between them and the bounding box B i The ratio between areas. For example, Figure 9 This is a schematic diagram illustrating the overlap of the bounding box and the mesh according to one embodiment. Please refer to... Figure 9 The diagram illustrates four grids, 901 to 904. Grid 901 has an overflow value of 1.41, grid 902 has an overflow value of 1.02, grid 903 has an overflow value of 0.9, and grid 904 has an overflow value of 0.89. Bounding box 910 overlaps with grids 901 to 904, with 15% of its area overlapping with grid 901, 22% with grid 902, 28% with grid 903, and 35% with grid 904. Therefore, the connection n corresponding to bounding box 910... i The winding congestion penalty is 0.15×1.41+0.22×1.02+0.28×0.9+0.35×0.89=0.9994. When connecting line n iCovering more congested areas results in a greater penalty. In other words, in this embodiment, wiring congestion penalty is used to represent wiring feasibility; a larger congestion penalty indicates lower wiring feasibility. To express the above mathematical formula 7 as cell coordinates, mathematical formula 7 can be transformed into the following mathematical formula 8.

[0082] [Mathematical Expression 8]

[0083]

[0084] Where Φ(B) i g k ) represents the grid g k The penalty for the contribution can be calculated using the following mathematical formula 9.

[0085] [Mathematical Expression 9]

[0086]

[0087] Where P x (B i g k ) is bounding box B i With grid g k The width of the overlapping area between them, P y (B i g k ) is bounding box B i With grid g k The height of the overlapping area between them. Due to P x (B i g k ) and P y (B i g k Since they are not differentiable, they can be replaced by bell-shaped potential functions. and As shown in the following mathematical formulas 10 and 11. It can be calculated in a similar way.

[0088] [Mathematical Expression 10]

[0089]

[0090] [Mathematical Expression 11]

[0091]

[0092]

[0093] Where d x Indicates bounding box B iCenter and grid g k The distance between the centers on the X-axis. Indicates bounding box B i The width. Represents the grid g k The width. To calculate the distance d. x We need to obtain bounding box B. i The center coordinates are represented as It is calculated using the following mathematical formula 12. And the width... It is calculated by the following mathematical formula 13.

[0094] [Mathematical Expression 12]

[0095]

[0096] [Mathematical Expression 13]

[0097]

[0098] Where v k Indicates the connection n i One of the units. x k Representation unit v k The X coordinate of the center. Due to the function as well as Since it is not differentiable, it can be calculated using the log-sum-expfunction.

[0099] Based on the above disclosure, the objective function established in step 608 can be expressed as the following mathematical formula 14.

[0100] [Mathematical Expression 14]

[0101]

[0102] The following mathematical expression is 15.

[0103] [Mathematical Expression 15]

[0104]

[0105] Where Ψ represents a list containing all connections. In some embodiments, λ1 and λ2 are set as shown in the following mathematical expressions 16 and 17. λ3 is a preset (user-determined) real number, which may be set to 1 in some embodiments.

[0106] [Mathematical Expression 16]

[0107]

[0108] [Mathematical Expression 17]

[0109]

[0110] In some embodiments, to ensure that the cells are evenly distributed across the layout area, λ1 and λ3 are fixed, while λ2 can be increased (e.g., multiplied by 2) in each iteration. In some embodiments, Equation 14 can be calculated using the conjugate gradient (CG) method to obtain the coordinates x and y of each group, thereby allowing the objective function to have an extremum (the minimum in this example), but this disclosure does not limit the method used to solve Equation 14.

[0111] In step 609, determine whether it is the lowest level. If it is, end the process; otherwise, proceed to step 610 to proceed to a lower level, i.e., l = l-1.

[0112] Steps 603-605 can be collectively referred to as the second layout procedure 620, and steps 606-608 can be collectively referred to as the first layout procedure 630. In this embodiment, the objective function in step 608 includes a winding congestion penalty C(x, y), but the objective function in step 604 does not include a winding congestion penalty. This is because in the initial stage of layout, all groups will be crowded together, and at this time, the winding congestion penalty cannot be considered; the line length must be considered first to disperse these groups. However, this disclosure is not limited to... Figure 6 The flowchart is shown below. In other embodiments, step 604 can use any objective function, or the second layout procedure 620 can be omitted. Furthermore, this disclosure is not limited to the objective function of the above mathematical formula 14; any suitable objective function that includes the winding congestion penalty C(x, y) is in line with the spirit of this disclosure.

[0113] From another perspective, the present invention also proposes a computer system comprising multiple program modules, which can be written in any programming language and / or platform, and which can perform the above-mentioned layout method when executed.

[0114] This disclosure has at least three key features. First, we employ different strategies within a multi-level framework to address both global and local congestion. Second, we propose a model that uses congestion as a connectivity penalty to reduce global congestion. Third, we propose a novel expansion technique that considers both the internal connectivity strength of a group and the congestion value occupied by that group, thereby mitigating local congestion.

[0115] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the appended claims.

Claims

1. A layout method for integrated circuit design, used in a computer system, wherein a layout area is divided into multiple grids, multiple cells form multiple interconnects, and each of the interconnects connects at least two of the cells, characterized in that, This layout method includes: Treat these units as multiple groups, and merge these groups at each level from bottom to top in multiple levels; The initial layout; and From top to bottom, at each of those levels, the groups are unpacked and a first layout procedure is executed, which includes: For each of these connections, a bounding box is created, which covers at least one first grid among the grids; For each of these connections, a routing congestion penalty is calculated based on the overlap area between the bounding box and the at least one first grid and the overflow value of the at least one first grid; and Based on the congestion penalties of these connections, a first objective function is established, and the positions of these groups are determined such that the first objective function has an extremum.

2. The layout method according to claim 1, characterized in that, The steps involved in merging these groups include: A new group is generated to include the first and second groups from these groups; and The internal connection strength of the new group is obtained by adding at least the internal connection strength of the first group, the internal connection strength of the second group, and a fraction between the first group and the second group, wherein the fraction is negatively correlated with the number of branches of the connections between the first group and the second group.

3. The layout method according to claim 2, characterized in that, When the first group or the second group belongs to the lowest level among these levels, the corresponding internal connection strength is 0. The score is also negatively correlated with the area of ​​the first group and the area of ​​the second group.

4. The layout method according to claim 3, characterized in that, The first layout procedure also includes: Update the overflow value of each of these grids; and For each of these groups, a second grid with the greatest overlap with the group is obtained. An expansion ratio is calculated based on the overflow value of the second grid and the internal connectivity strength of the group, and the size of the group is adjusted according to the expansion ratio.

5. The layout method according to claim 4, characterized in that, The first layout procedure also includes: When calculating the expansion ratio, the strength of the internal connectivity of the corresponding group is multiplied by a weight that is positively correlated with a current level among those levels.

6. The layout method according to claim 5, characterized in that, The expansion ratio is calculated based on the following mathematical formula: Where 'l' represents the current level. This indicates the i-th group at the current level. This indicates the i-th group The expansion ratio, N L This indicates the number of those levels. Where γ min γ max o T and η T For a preset real number, in This indicates the i-th group The overflow value corresponding to the second grid. This indicates the i-th group The strength of the internal connection, o max η is the maximum overflow value in these grids. max This indicates the maximum internal connectivity strength of these groups.

7. The layout method according to claim 6, characterized in that, Also includes: A second layout procedure is executed before the first layout procedure, wherein the second layout procedure includes: For each of these groups, calculate the expansion ratio of the group and adjust the size of the group accordingly. as well as Establish a second objective function and determine the positions of these groups such that the second objective function has an extremum, wherein the second objective function does not include these winding congestion penalties.

8. The layout method according to claim 1, characterized in that, The congestion penalty for each of these connections is calculated according to the following mathematical formula: Where C i B represents the congestion penalty of the i-th connection among these connections. i G represents the bounding box corresponding to the i-th connection, and G represents the set formed by these meshes. k This indicates that the grids are bounded by the bounding box B. i The covered grid, Where ρ k This indicates that the grid g k With the enclosure box B i The overlapping area between them and the bounding box B i The ratio between the areas, π k This indicates that the grid g k The overflow value.

9. A computer system wherein a layout area is divided into multiple grids, multiple cells forming multiple connections, each of the connections connecting at least two of the cells, characterized in that, The computer system includes: A program module used to treat these units as multiple groups and merge these groups at each level from bottom to top in multiple levels; The program module used for initialization layout; and A program module for unpacking the groups at each of the levels from top to bottom and performing a first layout procedure, the first layout procedure comprising: For each of these connections, a bounding box is created, which covers at least one first grid among the grids; For each of these connections, a routing congestion penalty is calculated based on the overlap area between the bounding box and the at least one first grid and the overflow value of the at least one first grid; and Based on the congestion penalties of these connections, a first objective function is established, and the positions of these groups are determined such that the first objective function has an extremum.

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