Memory device and operating method thereof

Abstract

The disclosure relates to a memory device and an operating method thereof. The memory device controls an operation based on a measured temperature. The memory device includes a plurality of memory cells, a peripheral circuit configured to perform an operation on the plurality of memory cells, a temperature circuit configured to measure a temperature of the memory device, a monitoring component configured to generate monitoring information based on whether the measured temperature is within a reference range, the monitoring information indicating whether an operation mode is a normal mode to perform the operation or a protection mode to suspend the operation, and an operation controller configured to output a signal for controlling the operation according to the monitoring information. The monitoring component is further configured to store the monitoring information and output the monitoring information to the operation controller in response to receiving the measured temperature from the temperature circuit.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority and benefit to Korean Patent Application No. 10-2021-0103344, filed on August 5, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] The technology and embodiments disclosed in this patent application generally relate to an electronic device, and more particularly, to a memory device and a method of operating the same. Background Technology

[0004] A storage device is an electronic component configured to store data under the control of a host device, such as a computer, smartphone, or tablet. Storage devices include those configured to store data on disks, such as hard disk drives (HDDs), and those configured to store data in semiconductor memory, such as non-volatile memory, such as solid-state drives (SSDs) or memory cards.

[0005] Storage devices may include memory devices configured to store data and memory controllers configured to control the memory devices. Memory devices are classified into volatile memory devices and non-volatile memory devices based on their ability to retain stored data in the absence of power. Non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or ferroelectric RAM (FRAM). Summary of the Invention

[0006] The disclosed embodiments provide a memory device and a method for controlling operation of the memory device based on temperature measurements during and after startup.

[0007] According to one aspect of this disclosure, a memory device is provided, comprising: a plurality of memory cells; peripheral circuitry configured to perform operations on the plurality of memory cells; a temperature circuitry configured to measure the temperature of the memory device; a monitoring component configured to generate monitoring information indicating whether the operating mode is a normal mode for performing operations or a protection mode for suspending operations based on whether the measured temperature is within a reference range; and an operation controller configured to output a signal for controlling operations based on the monitoring information. The monitoring component is further configured to store the monitoring information and output the monitoring information to the operation controller in response to receiving the measured temperature from the temperature circuitry.

[0008] According to another aspect of this disclosure, a method for operating a memory device is provided, the method comprising: initiating a startup operation for starting the memory device; measuring an initial temperature of the memory device during the startup operation; generating monitoring information indicating a startup mode for continuing the startup operation or a protection mode for suspending the startup operation based on whether the initial temperature is within a reference range; and outputting a request to continue or suspend the startup operation based on the monitoring information.

[0009] According to another aspect of this disclosure, a storage device is provided, comprising: a memory device including a plurality of memory cells, each memory cell configured to store data; and a memory controller communicating with the memory device and configured to control the operation of the memory device. The memory device is configured to measure the temperature of the memory device and provide a signal to the memory controller, the signal indicating whether the operating mode of the memory device is a normal mode for performing operations or a protection mode for suspending operations, the signal depending on whether the temperature of the memory device is within a reference range. Attached Figure Description

[0010] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein.

[0011] Figure 1 This is a diagram illustrating a storage device based on some embodiments of the disclosed technology.

[0012] Figure 2 It is shown Figure 1 A diagram showing the structure of the memory device.

[0013] Figure 3 It is shown Figure 2 A diagram illustrating an embodiment of the memory cell array shown.

[0014] Figure 4 This is a diagram illustrating the operation of each component during the startup phase of some implementations based on the disclosed technology.

[0015] Figure 5 This is a diagram showing the monitoring information generated by the monitoring component.

[0016] Figure 6 This is a diagram showing the operation of each component during the startup phase.

[0017] Figure 7 It is shown Figure 1 A diagram showing the pin configuration of the memory device.

[0018] Figure 8This is a diagram illustrating a method of notifying the memory device of its operating mode via a write-prevention signal.

[0019] Figure 9 This is a diagram illustrating a method of notifying the operating mode of a memory device through status information.

[0020] Figure 10 This is a diagram illustrating the operation of each component in the post-startup phase of some implementations based on the disclosed technology.

[0021] Figure 11 This is a diagram illustrating the operation of a memory device based on some embodiments of the disclosed technology.

[0022] Figure 12 This is a diagram illustrating the operation of a memory device based on some embodiments of the disclosed technology.

[0023] Figure 13 It is shown Figure 1 A diagram illustrating another embodiment of the memory controller shown.

[0024] Figure 14 This is a block diagram illustrating a memory card system that applies a storage device according to some embodiments of the disclosed technology.

[0025] Figure 15 This is a block diagram illustrating a solid-state drive (SSD) system that applies some embodiments of a storage device according to the disclosed technology.

[0026] Figure 16 This is a block diagram illustrating a user system that applies a storage device according to some embodiments of the disclosed technology. Detailed Implementation

[0027] The specific structural or functional descriptions disclosed herein are merely illustrative examples of embodiments or implementations of the disclosed technology and should not be construed as limiting the disclosed technology.

[0028] Figure 1 This is a block diagram showing a storage device.

[0029] Reference Figure 1 Storage device 50 is a device for storing data and may include memory device 100 and memory controller 200, which is coupled to control host access and operation of memory device 100.

[0030] Storage device 50 can be a device that stores data based on the control of host 300 such as: mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC or in-vehicle infotainment device.

[0031] Depending on the host interface, which serves as the communication scheme between the host and host 300, the storage device 50 can be manufactured as any of various types of storage devices. For example, the storage device 50 can be implemented using any of the following types of storage devices: solid-state drive (SSD), multimedia card (MMC), embedded MMC (eMMC), size-reduced MMC (RS-MMC), micro MMC (micro-MMC), secure digital card (SD), mini SD card, micro SD card, universal serial bus (USB) storage device, universal flash memory (UFS) device, compact flash memory (CF) card, smart media card (SMC), memory stick, etc.

[0032] The storage device 50 can be manufactured in any of a variety of package types. For example, the storage device 50 can be manufactured in any of the following package types: POP (Package-on-Package), System-in-Package (SIP), System-on-Chip (SOC), Multi-Chip Package (MCP), Chip-on-Board (COB), Wafer-Level Fabrication Package (WFP), and Wafer-Level Stacked Package (WSP).

[0033] Memory device 100 can store data. Memory device 100 operates under the control of memory controller 200. Memory device 100 may include a memory cell array, which includes a plurality of memory cells for storing data. The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells, and the plurality of memory cells may form a plurality of pages. In embodiments, a page may be a unit for storing data in memory device 100 or retrieving data stored in memory device 100. A memory block may be a unit for erasing data.

[0034] In embodiments, the memory device 100 may be a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), a fourth-generation low-power Double Data Rate (LPDDR4) SDRAM, a Graphics Double Data Rate (GDDR) SDRAM, low-power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin-transfer torque random access memory (STT-RAM), etc. In this specification, for ease of description, the case where the memory device 100 is a NAND flash memory is assumed and described.

[0035] In embodiments, the memory device 100 may be implemented as a two-dimensional array structure or a three-dimensional array structure. Although a three-dimensional array structure is described below as an example, this disclosure is not limited to three-dimensional array structures. This disclosure is applicable not only to flash memory devices in which the charge storage layer is configured using floating gates (FGs), but also to charge-fetch flash memory (CTF) in which the charge storage layer is configured using insulating layers.

[0036] In an embodiment, the memory device 100 can be operated using a single-level cell (SLC) method that stores one data bit in a memory cell. Alternatively, the memory device 100 can be operated using a method that stores at least two data bits in a memory cell. For example, the memory device 100 can be operated using a multi-level cell (MLC) method that stores two data bits in a memory cell, a three-level cell (TLC) method that stores three data bits in a memory cell, or a four-level cell (QLC) method that stores four data bits in a memory cell.

[0037] Memory device 100 is configured to receive commands and addresses from memory controller 200 and access address-selected regions in the memory cell array. Therefore, memory device 100 can perform operations corresponding to commands on the address-selected regions. For example, memory device 100 can perform write (programming) operations, read operations, and erase operations based on the received commands. For instance, when a programming command is received, memory device 100 can program data into the address-selected region. When a read command is received, memory device 100 can read data from the address-selected region. When an erase command is received, memory device 100 can erase the data stored in the address-selected region.

[0038] In this embodiment, the storage device 50 may be an automatic storage device 50, which can operate from -40°C to 115°C. The operating temperature range of the automatic storage device 50 may be relatively wider than that of a mobile storage device.

[0039] When the automatic storage device 50 exceeds its normal operating temperature range, the memory device 100 and the memory controller 200 malfunction. Therefore, to prevent malfunctions of the memory device 100 and memory controller 200 due to the temperature of the automatic storage device 50, the firmware of the memory controller 200 can perform operations for temperature control. However, when the size of the code that the firmware can execute is limited, the ability to control temperature using the firmware may also be limited.

[0040] Therefore, some embodiments of the disclosed technology propose a method for measuring temperature by operating the temperature circuit 150 in the memory device 100 during and after startup of the memory device 50. Some embodiments of the disclosed technology further propose autonomously suspending the operation of the memory device 100 based on temperature, and then notifying the memory controller 200 of the suspension when the measured temperature exceeds a predetermined range.

[0041] In an embodiment, the memory device 100 may include a temperature circuit 150. The temperature circuit 150 can measure the temperature of the memory controller 200 and / or the memory device 100. The temperature circuit 150 can measure the temperature when the memory device 50 is started. Based on the temperature measured during the startup of the memory device 50, the temperature circuit 150 can measure the temperature at predetermined time intervals. In some embodiments of the disclosed art, the temperature circuit 150 can measure the temperature at predetermined time intervals after the memory device 50 has started. By measuring the temperature of the memory controller 200 and / or the memory device 100, the temperature circuit 150 provides updated temperature information at predetermined time intervals. The temperature circuit 150 can generate and output temperature information, including information about the measured temperature.

[0042] In an embodiment, the memory device 100 may include a monitoring component 160. The monitoring component 160 may monitor the state of the memory controller 200 and / or the memory device 100 based on temperature information received from the temperature circuit 150. The state of the memory controller 200 and / or the memory device 100 may be a state where it can operate in a startup mode (or normal mode) or a state in a protection mode that is not required for startup mode operation. In the protection mode, operation of the memory controller 200 and / or the memory device 100 is suspended.

[0043] The monitoring component 160 can generate monitoring information based on the results obtained by monitoring the status of the memory controller 200 and / or the memory device 100. The monitoring information can represent the operating mode of the memory controller 200 and / or the memory device 100. The operating mode can be a startup mode (or normal mode) or a protection mode.

[0044] In one embodiment, the memory device 100 may include an operation controller 170. The operation controller 170 may control operation based on monitoring information received from the monitoring component 160.

[0045] The operation controller 170 can operate based on monitoring information received from the monitoring component 160. Monitoring information can be received during and after the startup of the storage device 50. For example, when monitoring information is received from the monitoring component 160 during the startup of the storage device 50 and the monitoring information indicates a startup mode, the operation controller 170 can suspend the startup operation being performed by the storage device 100. When monitoring information is received from the monitoring component 160 during the startup of the storage device 50 and the monitoring information indicates a protection mode, the operation controller 170 can instruct the storage device 100 to continue performing the startup operation. In some other embodiments, when monitoring information is received after the storage device 50 has started, the operation controller 170 can suspend the operation of the storage device 100 or instruct the storage device to resume the suspended operation based on the monitoring information received from the monitoring component 160.

[0046] The memory controller 200 can control all operations of the storage device 50.

[0047] When a power supply voltage is applied to the storage device 50, the memory controller 200 can run firmware (FW). When the storage device 100 is a flash memory device, the memory controller 200 can run FW such as a flash translation layer (FTL) for controlling communication between the host 300 and the storage device 100.

[0048] In this embodiment, the memory controller 200 may include firmware (not shown) that receives data and logical block addresses (LBAs) from the host 300, and converts the logical block addresses (LBAs) into physical block addresses (PBAs) representing the addresses of memory cells containing data to be stored in the memory device 100. Furthermore, the memory controller 200 may store a logical-physical address mapping table in a buffer memory (not shown), which establishes the mapping relationship between logical block addresses (LBAs) and physical block addresses (PBAs).

[0049] The memory controller 200 can control the memory device 100 to perform programming, reading, erasing, and other operations in response to requests from the host 300. For example, when receiving a programming request from the host 300, the memory controller 200 can change the programming request into a programming command and provide the memory device 100 with the programming command, physical block address PBA, and data. When receiving a read request and logical block address LBA from the host 300, the memory controller 200 can change the read request into a read command, select the physical block address PBA corresponding to the logical block address LBA, and then provide the read command and physical block address PBA to the memory device 100. When receiving an erase request and logical block address LBA from the host 300, the memory controller 200 can change the erase request into an erase command, select the physical block address PBA corresponding to the logical block address LBA, and then provide the erase command and physical block address PBA to the memory device 100.

[0050] In one embodiment, the memory controller 200 can control at least two memory devices. The memory controller 200 can control the memory devices according to an interleaving scheme to improve operational performance.

[0051] The host 300 can communicate with the storage device 50 using at least one of the following communication methods: Universal Serial Bus (USB), Serial AT Accessory (SATA), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), FireWire, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM).

[0052] Figure 2 It is shown Figure 1 A diagram showing the structure of the memory device.

[0053] Reference Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0054] Memory cell array 110 includes multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to row decoder 121 via row lines RL. The multiple memory blocks BLK1 to BLKz are connected to page buffer group 123 via bit lines BL1 to BLn. Each of the multiple memory blocks BLK1 to BLKz includes multiple memory cells. In an embodiment, the multiple memory cells may be non-volatile memory cells. Memory cells connected to the same word line can be defined as a page. Therefore, a memory block may include multiple pages.

[0055] A row line RL can include at least one source select line, multiple word lines, and at least one drain select line.

[0056] Each of the memory cells included in the memory cell array 110 can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0057] The peripheral circuit 120 can perform programming, reading, or erasing operations on selected regions of the memory cell array 110 under the control of the control logic 130. The peripheral circuit 120 can drive the memory cell array 110. For example, under the control of the control logic 130, the peripheral circuit 120 can apply various operating voltages to the row lines RL and bit lines BL1 to BLn or discharge the applied voltages.

[0058] The peripheral circuitry 120 may include a row decoder 121, a voltage generator 122, a page buffer group 123, a column decoder 124, an input / output circuit 125, and a sensing circuit 126.

[0059] Row decoder 121 is connected to memory cell array 110 via row line RL. Row line RL may include at least one source select line, multiple word lines, and at least one drain select line. In an embodiment, word lines may include normal word lines and dummy word lines. In an embodiment, row line RL may further include pipe select lines.

[0060] Row decoder 121 decodes the row address RADD received from control logic 130. Row decoder 121 selects at least one memory block from memory blocks BLK1 to BLKz based on the decoded address. Furthermore, row decoder 121 can select at least one word line of the selected memory block to apply the voltage generated by voltage generator 122 to at least one word line WL based on the decoded address.

[0061] For example, in a programming operation, the row decoder 121 can apply a programming voltage to the selected word line and a programming pass voltage with a lower level than the programming voltage to the unselected word line. In a programming verification operation, the row decoder 121 can apply a verification voltage to the selected word line and a verification pass voltage higher than the verification voltage to the unselected word line. In a reading operation, the row decoder 121 can apply a reading voltage to the selected word line and a reading pass voltage higher than the reading voltage to the unselected word line.

[0062] In this embodiment, the erase operation of the memory device 100 is performed on a block-by-block basis. During the erase operation, the row decoder 121 can select a memory block based on the decoded address. During the erase operation, the row decoder 121 can apply a ground voltage to the word line connected to the selected memory block.

[0063] Voltage generator 122 operates under the control of control logic 130. Voltage generator 122 generates multiple voltages using an external power supply voltage supplied to memory device 100. Specifically, voltage generator 122 can generate various operating voltages Vop for programming, reading, and erasing operations in response to the operation signal OPSIG. For example, voltage generator 122 can generate programming voltage, verification voltage, pass voltage, read voltage, erase voltage, etc., under the control of control logic 130.

[0064] In this embodiment, the voltage generator 122 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by the voltage generator 122 is used as the operating voltage of the memory device 100.

[0065] In an embodiment, voltage generator 122 can generate multiple voltages by using an external power supply voltage or an internal power supply voltage.

[0066] For example, voltage generator 122 may include multiple pumping capacitors for receiving internal power supply voltages, and generate multiple voltages by selectively activating the multiple pumping capacitors under the control of control logic 130.

[0067] Multiple generated voltages can be supplied to the memory cell array 110 via the row decoder 121.

[0068] Page buffer group 123 includes first page buffers PB1 to nth page buffers PBn. First page buffers PB1 to nth page buffers PBn are connected to memory cell array 110 via first bit line BL1 to nth bit line BLn, respectively. First bit lines BL1 to nth bit lines BLn operate under the control of control logic 130. Specifically, first bit lines BL1 to nth bit lines BLn can operate in response to page buffer control signal PBSIGNALS. For example, first page buffers PB1 to nth page buffers PBn can temporarily store data received via first bit lines BL1 to nth bit lines BLn, or sense the voltage or current of bit lines BL1 to BLn during read or verification operations.

[0069] Specifically, during programming, when a programming voltage is applied to the selected word line, the first page buffer PB1 to the nth page buffer PBn can transmit the data DATA received through the input / output circuit 125 to the selected memory cell via the first bit line BL1 to the nth bit line BLn. The memory cell of the selected page is programmed based on the transmitted data DATA. During programming verification, the first page buffer PB1 to the nth page buffer PBn can sense the voltage or current received from the selected memory cell via the first bit line BL1 to the nth bit line BLn to read page data.

[0070] During the read operation, the first page buffer PB1 to the nth page buffer PBn read data DATA from the memory cell of the selected page through the first bit line BL1 to the nth bit line BLn, and output the read data DATA to the input / output circuit 125 under the control of the column decoder 124.

[0071] During the erase operation, the first page buffer PB1 to the nth page buffer PBn can either float the first bit line BL1 to the nth bit line BLn or apply an erase voltage.

[0072] Column decoder 124 can communicate data between input / output circuitry 125 and page buffer group 123 in response to column address CADD. For example, column decoder 124 can communicate data with first page buffers PB1 to nth page buffers PBn via data line DL, or with input / output circuitry 125 via column line CL.

[0073] The input / output circuit 125 can transmit data from the memory controller (…). Figure 1 The command CMD and address ADDR received by 200 (as shown) are transmitted to control logic 130, or data DATA are exchanged with column decoder 124.

[0074] In a read or verification operation, the sensing circuit 125 may generate a reference current in response to the enable bit VRYBIT signal and output a pass signal PASS or a failure signal FAIL by comparing the sensed voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current.

[0075] Control logic 130 can respond to commands CMD and address ADDR by controlling peripheral circuitry 120 through outputting operation signals OPSIG, row address RADD, page buffer control signals PBSIGNALS, and enable bit VRYBIT. For example, control logic 130 can control the read operation of a selected memory block in response to a sub-block read command and address. Furthermore, control logic 130 can control the erase operation of selected sub-blocks included in a selected memory block in response to a sub-block erase command and address. Moreover, control logic 130 can determine whether the verification operation passed or failed in response to either the PASS signal or the FAIL signal.

[0076] In one embodiment, control logic 130 may include temperature circuit 150, monitoring component 160, and operation controller 170. In another embodiment, temperature circuit 150, monitoring component 160, and operation controller 170 may be located outside of control logic 130.

[0077] In this embodiment, the temperature circuit 150 can measure the temperature of the memory device 100. For example, the temperature circuit 150 can measure the temperature of the memory device 100 during startup. In some embodiments, the temperature circuit 150 can measure the temperature of the memory device 100 at predetermined time intervals based on the temperature measured during startup operation. In some embodiments, the temperature circuit 150 can measure the temperature of the memory device 100 at predetermined time intervals after startup. By measuring the temperature of the memory device 100, the temperature circuit 150 provides updated temperature information at predetermined time intervals.

[0078] In an embodiment, monitoring component 160 can monitor the state of memory device 100 based on the temperature measured by temperature circuit 150. For example, monitoring component 160 can determine, based on the temperature measured by temperature circuit 150 at startup, whether the memory device 100 is in a state where a startup operation being performed by memory device 100 needs to be suspended or in a state where CAM read operations can be performed on CAM (content addressable memory) blocks included in memory cell array 110.

[0079] Furthermore, the monitoring component 160 can determine, based on the temperature measured by the temperature circuit 150 after startup, whether the memory device 100 is in a state where the operation of the memory device 100 needs to be suspended or a state where the suspended operation can be resumed.

[0080] In an embodiment, the monitoring component 160 may generate monitoring information based on the results obtained by monitoring the state of the memory device 100.

[0081] In an embodiment, the operation controller 170 can control the operations to be performed by the memory device 100 based on monitoring information.

[0082] For example, during startup, the operation controller can, based on monitoring information, instruct the memory device 100 to suspend the startup operation being performed by the memory device 100 or instruct the memory device 100 to perform a CAM read operation on the CAM blocks included in the memory cell array 110. Furthermore, after startup, the operation controller 170 can, based on monitoring information, instruct the memory device to suspend the operation of the memory device 100 or instruct the memory device 100 to resume the suspended operation.

[0083] Figure 3 It is shown Figure 2 A diagram illustrating an embodiment of the memory cell array shown.

[0084] Reference Figure 2 and Figure 3 , Figure 3 It is shown Figure 2 The circuit diagram shows any one of the multiple memory blocks BLK1 to BLKz included in the memory cell array 110 shown.

[0085] In a BLKa memory block, a first select line, a word line, and a second select line arranged in parallel can be connected to each other. For example, a word line can be arranged in parallel between a first select line and a second select line. The first select line can be a source select line (SSL), and the second select line can be a drain select line (DSL).

[0086] More specifically, the storage block BLKa may include multiple strings connected between bit lines BL1 to BLn and source lines SL. Bit lines BL1 to BLn may be connected to strings individually, and source lines SL may be connected to strings collectively. The strings may be configured identically to each other, and therefore, the string ST connected to the first bit line BL1 will be described in detail as an example.

[0087] The string ST may include a source selection transistor SST, a plurality of memory cells F1 to F16, and a drain selection transistor DST connected in series between the source line SL and the first bit line BL1. At least one source selection transistor SST and at least one drain selection transistor DST may be included in a string ST, and the string ST may include more memory cells than the number of memory cells F1 to F16 shown in the figure.

[0088] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells F1 to F16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different strings can be connected to the source select line SSL, and the gates of the drain select transistors DST included in different strings can be connected to the drain select line DSL. The gates of memory cells F1 to F16 can be connected to multiple word lines WL1 to WL16. A group of memory cells in different strings connected to the same word line can be referred to as a physical page PPG. Therefore, the memory block BLKa can include physical pages corresponding to the number of word lines WL1 to WL16.

[0089] A memory cell can store one bit of data. This memory cell is typically referred to as a single-level cell (SLC). A physical page (PPG) can store one logical page (LPG) of data. An LPG of data can include a number of data bits corresponding to the number of cells included in a physical page (PPG). Optionally, a memory cell (MC) can store two or more bits of data. This memory cell is typically referred to as a multi-level cell (MLC). A physical page (PPG) can store two or more LPGs of data.

[0090] Memory cells used to store two or more bits of data are called MLCs. As the number of data bits stored in a single memory cell increases, MLC recently came to refer to memory cells used to store two bits of data. Memory cells used to store three or more bits of data are called three-level cells (TLCs), and memory cells used to store four or more bits of data are called four-level cells (QLCs). Furthermore, memory cells for storing multiple bits of data have been developed, and this can be applied to memory systems storing two or more bits of data.

[0091] In another embodiment, each of the plurality of memory blocks may have a three-dimensional structure. Each memory block may include a plurality of memory cells stacked on a substrate. The plurality of memory cells may be arranged along the +X, +Y, and +Z directions.

[0092] Figure 4 This is a diagram showing the operation of each component during the startup phase.

[0093] Reference Figure 1 and Figure 4 , Figure 4 Show memory device ( Figure 1 The temperature circuit 150, monitoring component 160, and operation controller 170 included in 100 shown are also present. Figure 4The temperature circuit 150, monitoring component 160, and operation controller 170 are shown in the storage device ( Figure 1 The operation during the startup operation shown in 50).

[0094] In an embodiment, when the storage device is started ( Figure 1 When shown as 50), external power POWER can be simultaneously supplied to the memory controller. Figure 1 The 200 shown) and memory device ( Figure 1 (100 as shown).

[0095] In an embodiment, when external power POWER is supplied to the memory device ( Figure 1 When shown as 100), the temperature circuit 150 can measure the temperature of the memory device ( Figure 1 The temperature shown is 100. The measured temperature may be within or outside the predetermined temperature range.

[0096] Temperature circuit 150 measures memory device ( Figure 1 After the temperature (100) shown in the figure is reached, the temperature circuit 150 can provide the monitoring component 160 with temperature information TEM_INF, which includes information about the measured temperature.

[0097] In this embodiment, the monitoring component 160 can monitor the memory device based on the temperature information TEM_INF. Figure 1 The status of the memory device (shown as 100). Monitoring component 160 can generate monitoring information MONITOR_INF based on the monitoring results. Monitoring information MONITOR_INF may include information about whether the memory device is in boot mode or protected mode. Boot mode can be the state of the memory device performing a boot operation, including CAM read operations or other operations. Figure 1 The operating mode shown is 100), and the protection mode can be a memory device that suspends the currently executing boot operation. Figure 1 The 100 shown is the operating mode.

[0098] Monitoring component 160 can store monitoring information MONITOR_INF, enabling the memory device ( Figure 1 The 100 shown operates in startup mode or protection mode, and then provides the monitoring information MONITOR_INF to the operation controller 170.

[0099] For example, when the measured temperature included in the temperature information TEM_INF is within a predetermined temperature range, the monitoring component 160 can store monitoring information MONITOR_INF, which includes information about the startup mode, and then provide the monitoring information MONITOR_INF to the operation controller 170.

[0100] In some other implementations, when the measured temperature included in the temperature information TEM_INF is not within a predetermined temperature range, the monitoring component 160 may store monitoring information MONITOR_INF including information about the protection mode, and then provide the monitoring information MONITOR_INF to the operation controller 170.

[0101] exist Figure 4 In the example, it is assumed that the measured temperature included in the temperature information TEM_INF is within a predetermined temperature range.

[0102] Therefore, the operation controller 170 can output a request for a memory device based on the monitoring information MONITOR_INF received from the monitoring component 160. Figure 1 The 100 shown continues to execute the boot request BT_REQ of the boot operation. When the boot request BT_REQ is output, the memory device ( Figure 1 The 100 shown in the figure can perform actions such as reading the memory cell array ( Figure 2 The CAM read operation is initiated for the data stored in the CAM block (110) shown in the figure.

[0103] Figure 5 This is a diagram showing the monitoring information generated by the monitoring component.

[0104] Reference Figure 4 and Figure 5 , Figure 5 The monitoring component is shown. Figure 4 The monitoring information MONITOR_INF generated in 160 shown in the figure. Figure 5 In this context, we assume that the memory device ( Figure 1 The predetermined temperature range (100) shown is greater than or equal to T1 and less than T2. ​​Therefore, temperatures outside the predetermined temperature range can be less than T1 or greater than or equal to T2.

[0105] In the embodiment, the monitoring component ( Figure 4 As shown in 160, monitoring information MONITOR_INF can be generated based on the temperature information TEM_INF received from the temperature circuit 150. The monitoring information MONITOR_INF may include information about the startup mode (or normal mode) or protection mode.

[0106] In the embodiment, in the storage device ( Figure 1 During the startup phase of 50 shown, the monitoring component ( Figure 4 As shown in Figure 160, monitoring information MONITOR_INF can be generated based on the temperature information TEM_INF received from the temperature circuit 150. The monitoring information MONITOR_INF includes information about the boot mode BT_MODE or the protection mode PT_MODE. The boot mode BT_MODE can be a memory device that performs boot operations such as CAM read operations. Figure 1 The 100 shown is the operating mode, and the protection mode PT_MODE can be a memory device that suspends boot operations ( Figure 1 The 100 shown is the operating mode.

[0107] For example, in storage devices ( Figure 1 During the startup phase of 50 shown in the figure, when the memory device ( Figure 1 When the temperature T_NAND of 100 shown is within the predetermined temperature range, the monitoring component ( Figure 4 As shown in 160), monitoring information MONITOR_INF can be generated, which includes information about the boot mode BT_MODE.

[0108] In some other implementations, in the storage device ( Figure 1 During the startup phase of 50 shown in the figure, when the memory device ( Figure 1 When the temperature T_NAND of 100 shown is outside the predetermined temperature range, the monitoring component ( Figure 4 As shown in 160), monitoring information MONITOR_INF can be generated, which includes information about the protection mode PT_MODE.

[0109] In the embodiment, in the storage device ( Figure 1 The phase following the startup of 50 shown in the figure, the monitoring component ( Figure 4 As shown in Figure 160, monitoring information MONITOR_INF can be generated based on the temperature information TEM_INF received from the temperature circuit 150. The monitoring information MONITOR_INF includes information about the normal mode NM_MODE or the protection mode PT_MODE. The normal mode NM_MODE can be a memory device (…). Figure 1 The 100 shown indicates the mode in which the operation is performed, and the protection mode PT_MODE can be a memory device ( Figure 1 The 100) mode shown is the suspension operation mode.

[0110] For example, in storage devices ( Figure 1In the phase following startup of 50 shown, when the temperature T_NAND of the memory device is within a predetermined temperature range, the monitoring component ( Figure 4 As shown in 160), monitoring information MONITOR_INF can be generated, which includes information about the normal mode NM_MODE.

[0111] In some other implementations, in the storage device ( Figure 1 In the phase following startup (50 shown), when the temperature T_NAND of the memory device is outside the predetermined temperature range, the monitoring component ( Figure 4 As shown in 160), monitoring information MONITOR_INF can be generated, which includes information about the protection mode PT_MODE.

[0112] Figure 6 This is a diagram showing the operation of each component during the startup phase.

[0113] Reference Figure 1 and Figure 6 , Figure 6 The memory device is shown. Figure 1 The temperature circuit 150, monitoring component 160, and operation controller 170 included in 100 shown are also present. Figure 6 The temperature circuit 150, monitoring component 160, and operation controller 170 are shown in the storage device ( Figure 1 The operation during the startup operation shown in 50).

[0114] Unlike Figure 4 In the example, Figure 6 In the example, it is assumed that the measured temperature included in the temperature information TEM_INF is outside the predetermined temperature range.

[0115] Reference Figure 6 The discussion will not be repeated. Figure 4 The operations performed in the example are the same as those in the example, but the main discussion will focus on the operations performed in the example. Figure 4 The operations in the examples are different from the operations in the examples.

[0116] In an embodiment, when external power POWER is supplied to the memory device ( Figure 6 When shown as 100), the temperature circuit 150 can measure the temperature of the memory device ( Figure 6 The temperature shown is 100 (as indicated). In Figure 6 In the example, the measured temperature may be outside the predetermined temperature range.

[0117] Monitoring component 160 can monitor the memory device based on the temperature information TEM_INF received from temperature circuit 150. Figure 1The system monitors the status of device 100 (as shown in the diagram) and, based on the monitoring results, stores monitoring information MONITOR_INF, including information about the protection mode, and then provides the monitoring information MONITOR_INF to the operation controller 170. The protection mode can be a suspended state currently being controlled by the memory device (…). Figure 1 The operation mode of the startup operation performed by 100 shown in the figure.

[0118] In an embodiment, the operation controller 170 may output a request for a memory device based on the monitoring information MONITOR_INF received from the monitoring component 160. Figure 1 The 100 shown indicates a suspend request SUS_REQ for the suspend start operation. When the suspend request SUS_REQ is output, the memory device ( Figure 1 The 100 shown can suspend the startup operation.

[0119] In some implementations, in order to send to the memory controller ( Figure 1 The 200 shown in the figure notifies the memory device ( Figure 1 If the temperature of 100 shown in the figure exceeds the predetermined temperature range, the operation controller 170 can output a write prevention signal WP or a status information STATUS_INF based on the monitoring information MONITOR_INF.

[0120] For example, when the monitoring information MONITOR_INF includes information about the protection mode, the operation controller 170 can output the write-prevention signal WP as a high state or a low state by writing to the write-prevention line WP#, thereby sending a signal to the memory controller. Figure 1 The 200 shown in the figure notifies the memory device ( Figure 1 The 100 shown is operating in protected mode.

[0121] Reference Figure 7 and Figure 8 The write prevention signal WP is described in more detail.

[0122] In some implementations, the operation controller 170 may allow information about the protection mode to be included in the status information STATUS_INF, and then output the status information STATUS_INF to the memory controller. Figure 1 As shown in 200), thereby notifying the memory controller ( Figure 1 200 shown), memory device ( Figure 1 The 100 shown operates in protected mode. When the memory device ( Figure 1 When 100 shown is reset, the operation controller 170 can output the status information STATUS_INF to the memory controller. Figure 1 The 200 shown). When the memory device ( Figure 1 The state of 100 shown changes from sleep state to wake state, and the memory device ( Figure 1 When 100 shown malfunctions in the wake-up state, it can execute the memory device ( Figure 1 The reset of 100 shown in the figure.

[0123] In the embodiments, in the memory device ( Figure 1 After the suspend start-up operation shown in Figure 100, the temperature circuit 150 can measure the temperature of the memory device at predetermined time intervals. Figure 1 The temperature of (100) shown in the figure. Additionally, the monitoring component 160 can receive temperature information TEM_INF from the temperature circuit 150 at predetermined time intervals. Therefore, in the memory device ( Figure 1 After the suspend start operation shown in 100), the temperature circuit 150 provides updated temperature information at predetermined intervals.

[0124] After receiving the updated temperature information, the monitoring component 160 can determine the memory device based on the temperature information TEM_INF received from the temperature circuit 150. Figure 1 Whether the temperature of the memory device (100) shown is within the predetermined temperature range. Figure 1 When the temperature of (100) shown in the figure is within the predetermined temperature range, the monitoring component 160 can generate and store monitoring information MONITOR_INF, which includes information about the startup mode BT_MODE.

[0125] When monitoring component 160 generates and stores monitoring information MONITOR_INF, this MONITOR_INF can be stored in monitoring component 160 to replace previously stored monitoring information MONITOR_INF. When storing monitoring information MONITOR_INF corresponding to updated temperature information, monitoring component 160 can output the newly stored monitoring information MONITOR_INF to operation controller 170. Therefore, whenever the stored monitoring information MONITOR_INF changes, monitoring component 160 can output the changed monitoring information MONITOR_INF to operation controller 170.

[0126] Subsequently, the operation controller 170 can output a request for the memory device based on the monitoring information MONITOR_INF received from the monitoring component 160. Figure 1 The 100 shown indicates that the pending boot request BT_REQ is resumed. When the boot request BT_REQ is output, the memory device ( Figure 1As shown in 100), the startup operation of a CAM read operation, such as reading data stored in a CAM block, can be restored.

[0127] Figure 7 It is shown Figure 1 A diagram showing the pin configuration of the memory device.

[0128] Reference Figure 7 Memory device ( Figure 1 The 100 shown can communicate with an external controller via multiple input / output lines. For example, a memory device ( Figure 1 The 100 shown can communicate with an external controller via control signal lines, which include chip enable line CE#, write enable line WE#, read enable line RE#, address latch enable line ALE, command latch enable line CLE, write prevent line WP#, ready busy line RB, and data input / output line DQ.

[0129] Memory device ( Figure 1 The 100 shown can receive a chip enable signal from an external controller via the chip enable line CE#. Memory device ( Figure 1 The memory device (100) shown can receive a write enable signal from the external controller via the write enable line WE#. The memory device can receive a read enable signal from the external controller via the read enable line RE#. Figure 1 The 100 shown can receive the address latch enable signal from the external controller via the address latch enable line ALE. Memory device ( Figure 1 The 100 shown can receive a command latch enable signal from an external controller via the command latch enable line CLE. Memory device ( Figure 1 As shown in Figure 100, a write-prevention signal can be received from an external controller via the write-prevention line WP#.

[0130] In the embodiment, the memory device ( Figure 1 The 100 shown can send a signal to the memory controller via the ready-to-work line RB. Figure 1 The 200 shown provides a means for outputting a memory device ( Figure 1 The 100 shown indicates whether the device is in a ready or busy state, or a ready-busy signal.

[0131] The chip enable signal can be used to select a memory device ( Figure 1 The control signal of 100 shown. When the chip enable signal is in the "high level" state and the memory device ( Figure 1 The 100 shown corresponds to the "ready" state when the memory device ( Figure 1 The 100 shown can enter a low-power standby state.

[0132] The write enable signal can be used to control the input to the memory device to be stored in the latch. Figure 1 The control signals for commands, addresses, and input data shown in 100).

[0133] The read enable signal can be a control signal used to enable the output of serial data.

[0134] The address latch enable signal is a control signal used by the host to indicate whether the signal input through the input / output line DQ is a command, address, or data signal.

[0135] The command latch enable signal can be a control signal used by the host to indicate whether the signal input through the input / output line DQ is a command, address, or data signal.

[0136] For example, when the command latch enable signal is activated (e.g., logic high), the address latch enable signal is disabled (e.g., logic low), and the write enable signal is activated (e.g., logic low) and then disabled (e.g., logic high), the memory device ( Figure 1 The 100 shown can identify that the signal input through the input / output line DQ is a command.

[0137] For example, when the command latch enable signal is disabled (e.g., logic low), the address latch enable signal is activated (e.g., logic high), and the write enable signal is activated (e.g., logic low) and then disabled (e.g., logic high), the memory device ( Figure 1 The 100 shown can be used to identify that the signal input through the input / output line DQ is an address.

[0138] Write prevention signals can be used to disable write access by memory devices ( Figure 1 The control signals for programming and erasing operations performed by 100 shown in the figure.

[0139] The ready-to-work signal can be used to identify memory devices. Figure 1 The signal indicating the state of the memory device (shown as 100). A low-level ready-to-work signal indicates the state of the memory device ( Figure 1 The 100 shown is performing at least one operation. A high-level ready-to-work signal indicates that the memory device (…) is performing at least one operation. Figure 1 The 100 shown did not perform any operation.

[0140] When memory device ( Figure 1When the 100 shown is performing any of the programming, reading, and erasing operations, the ready-to-work signal can be low. In embodiments of this disclosure, the memory controller ( Figure 1 The 200 shown can determine the end time based on the ready busy signal, which is the time when the programming operation or the erase operation ends.

[0141] In the embodiment, the memory device ( Figure 1 As shown in Figure 100, a write-prevention signal can be output to an external controller via the write-prevention line WP#. Specifically, the memory device ( Figure 1 The 100 shown can output a write-protection signal as a high-level or low-level state, thereby notifying an external controller that the memory device ( Figure 1 The 100 shown operates in startup mode (or normal mode) or protection mode.

[0142] Figure 8 This is a diagram illustrating a method of notifying the memory device of its operating mode via a write-prevention signal.

[0143] Reference Figure 7 and Figure 8 , Figure 8 Showing through Figure 7 The write prevention line WP# shown is output to the memory controller. Figure 1 The write prevention signal WP is shown in Figure 200.

[0144] In this embodiment, the operation controller ( Figure 1 As shown in 170), it can be based on the monitoring component ( Figure 1 The 160 shown receives the monitoring information MONITOR_INF to generate a write prevention signal WP, and outputs the write prevention signal WP to the memory controller. Figure 1 200 shown).

[0145] In some implementations, the monitoring component ( Figure 1 The 160 shown in the figure can be based on the representation of the temperature circuit ( Figure 1 The temperature information TEM_INF, as shown in Figure 150, is used to monitor the memory device (the temperature measured). Figure 1 The status of 100 shown in the diagram. Monitoring component ( Figure 1 The 160 shown can send signals to the operation controller ( Figure 1 As shown in 170), it provides monitoring information MONITOR_INF generated based on monitoring results, and the operation controller ( Figure 1 As shown in 170), a write prevention signal WP can be generated based on the monitoring information MONITOR_INF.

[0146] In this embodiment, when the monitoring information MONITOR_INF includes information about the startup mode BT_MODE or the normal mode NM_MODE, the operation controller ( Figure 1 The 170 shown can generate a high-level write-prevention signal WP and output the write-prevention signal WP to the memory controller. Figure 1 200 as shown). Memory controller ( Figure 1 The 200 shown can check the memory device based on the received write prevention signal WP. Figure 1 Whether 100 shown operates in boot mode BT_MODE or normal mode NM_MODE, and then outputs commands and / or data to the memory device. Figure 1 (100 as shown).

[0147] When the monitoring information MONITOR_INF includes information about the protection mode PT_MODE, the operation controller ( Figure 1 The 170 shown can generate a low-level write-prevention signal and output the write-prevention signal to the memory controller. Figure 1 200 as shown). Memory controller ( Figure 1 The 200 shown can check the memory device based on the received write prevention signal WP. Figure 1 Whether 100 shown is operating in protected mode PT_MODE, and then suspending command and / or data output to the memory device ( Figure 1 As shown in 100). Therefore, when the memory device ( Figure 1 When 100 shown is operating in protected mode PT_MODE, operations such as startup operations or any other operations being performed are suspended, and the memory controller ( Figure 1 The 200 shown can suspend the output of commands and / or data.

[0148] In another embodiment, when the monitoring information MONITOR_INF includes information about the startup mode BT_MODE or the normal mode NM_MODE, the operation controller ( Figure 1 The 170 shown can generate a low-level write-protection signal WP. When the monitoring information MONITOR_INF includes information about the protection mode PT_MODE, the operation controller ( Figure 1 The 170 shown can generate a high-level write prevention signal WP.

[0149] Figure 9 This is a diagram illustrating a method of notifying the operating mode of a memory device through status information.

[0150] Reference Figure 6 and Figure 9 , Figure 9 Showing the operation controller ( Figure 1 The output of 170 shown is sent to the memory controller. Figure 1 The status information STATUS_INF (shown in 200) is shown. Figure 9 The diagram shows that the status information STATUS_INF includes the ready / busy information RB_INF and the monitoring information MONITOR_INF. However, in another embodiment, the status information STATUS_INF may include more information.

[0151] exist Figure 9 In this context, the ready-to-work information RB_INF can represent a memory device ( Figure 1 The state of 100 shown is either ready or busy, and the monitoring information MONITOR_INF can indicate the memory device ( Figure 1 The 100 shown is the operating mode.

[0152] In this embodiment, the operation controller ( Figure 1 As shown in 170), it can be based on the monitoring component ( Figure 1 The monitoring information MONITOR_INF received by (as shown in 160) is used to generate the status information STATUS_INF, and the status information STATUS_INF is output to the memory controller. Figure 1 As shown in 200). The status information STATUS_INF can be stored in the memory device ( Figure 1 The 100 shown is generated during reset and output to the memory controller. Figure 1 As shown in 200). When the memory device ( Figure 1 The state of 100 shown changes from sleep state to wake state, and the memory device ( Figure 1 When 100 shown malfunctions in the wake-up state, it can execute the memory device ( Figure 1 The reset of 100 shown in the figure.

[0153] In the embodiment, the monitoring component ( Figure 1 The 160 shown in the figure can be based on the representation of the temperature circuit ( Figure 1 The temperature information TEM_INF, as shown in Figure 150, is used to monitor the memory device (the temperature measured). Figure 1 The status of 100 shown in the diagram. Monitoring component ( Figure 1 The 160 shown can send signals to the operation controller ( Figure 1 As shown in 170), it provides monitoring information MONITOR_INF generated based on monitoring results, and the operation controller ( Figure 1As shown in 170), status information STATUS_INF can be generated based on monitoring information MONITOR_INF.

[0154] In an embodiment, the memory controller ( Figure 1 The 200 shown can be based on the operation controller ( Figure 1 The status information STATUS_INF received by 170 (shown in the figure) is checked in the memory device ( Figure 1 The operation mode shown is 100), and then subsequent operations are performed.

[0155] For example, when the monitoring information MONITOR_INF included in the status information STATUS_INF includes information about the boot mode BT_MODE or the normal mode NM_MODE, the memory controller ( Figure 1 The 200 shown can check the memory device ( Figure 1 Whether 100 shown operates in boot mode BT_MODE or normal mode NM_MODE, and then outputs commands and / or data to the memory device. Figure 1 (100 as shown).

[0156] When the status information STATUS_INF includes monitoring information MONITOR_INF that includes information about the protection mode PT_MODE, the memory controller ( Figure 1 The 200 shown can check the memory device ( Figure 1 Whether 100 shown is operating in protected mode PT_MODE, and then suspending the connection to the memory device ( Figure 1 The 100 shown outputs commands and / or data. Therefore, when the memory device ( Figure 1 When 100 (as shown) operates in protected mode PT_MODE, the startup operation or the operation being executed is suspended, therefore the memory controller ( Figure 1 The 200 shown can suspend the output of commands and / or data.

[0157] Figure 10 It is a diagram showing the operation of each component in the phase after startup.

[0158] Reference Figures 1 to 10 , Figure 10 Show memory device ( Figure 1 The temperature circuit 150, monitoring component 160, and operation controller 170 included in 100 shown are also present. Figure 10 The temperature circuit 150, monitoring component 160, and operation controller 170 are shown in the storage device ( Figure 1The operations that occur after the startup operation shown in 50), for example, during runtime. In the following description, runtime refers to the period following the startup operation of the storage device.

[0159] In this embodiment, during operation, the temperature circuit 150 can measure the temperature of the memory device at predetermined intervals. Figure 1 The temperature (as shown in Figure 100) is then recorded, and temperature information TEM_INF is provided to monitoring component 160. TEM_INF includes information about the measured temperature. The measured temperature may be within or outside a predetermined temperature range.

[0160] In this embodiment, the monitoring component 160 can monitor the memory device based on the temperature information TEM_INF. Figure 1 The status of 100 shown in the figure. Monitoring component 160 can generate monitoring information MONITOR_INF based on the monitoring results. Monitoring information MONITOR_INF may include information about normal mode or protection mode. Normal mode may be a memory device that continues to perform operations (as shown in the figure). Figure 1 The operating mode shown in Figure 100) is a suspended operation mode of the memory device (and the protection mode can be a suspended operation mode of the memory device). Figure 1 The 100 shown is the operating mode.

[0161] Monitoring component 160 can provide monitoring information MONITOR_INF to operation controller 170, enabling the memory device ( Figure 1 The 100 shown operates in normal mode or protection mode.

[0162] For example, as a result determined based on temperature information TEM_INF, when the measured temperature is within a predetermined temperature range, the monitoring component 160 can provide the operation controller 170 with monitoring information MONITOR_INF, which includes information about the normal mode.

[0163] However, as a result determined based on temperature information TEM_INF, when the measured temperature exceeds the predetermined temperature range, the monitoring component 160 can provide the operation controller 170 with monitoring information MONITOR_INF, which includes information about the protection mode.

[0164] In an embodiment, when the monitoring information MONITOR received from the monitoring component 160 includes information about the memory device ( Figure 1 When the information shown in Figure 100 indicates that the operation is in normal mode, the operation controller 170 may not perform any individual operation.

[0165] However, when the monitoring information MONITOR received from the monitoring component 160 includes information about the memory device ( Figure 1 When the operation controller 170 is in the protected mode state of the operation (shown as 100), it can output a suspend request SUS_REQ. When the suspend request SUS_REQ is output, the memory device ( Figure 1 The 100 shown can complete the currently executing operation and suspend subsequent operations.

[0166] In addition, such as Figure 8 and Figure 9 When the monitoring information MONITOR_INF includes information about the protection mode, the operation controller 170 can output the write prevention signal WP or the status information STATUS_INF to the memory controller. Figure 1 As shown in 200), thus sending to the memory controller ( Figure 1 The 200 shown in the figure notifies the memory device ( Figure 1 The 100 shown is operating in protected mode.

[0167] In the embodiments, in the memory device ( Figure 1 Following the suspension operation shown in Figure 100, the monitoring information MONITOR_INF received from the monitoring component 160 may include information about the normal mode. After the operation controller 170 receives the monitoring information MONITOR_INF including information about the normal mode, the operation controller 170 may output an output for requesting the memory device ( Figure 1 The 100 shown indicates that the suspended operation is resumed via a resume request RES_REQ. When the resume request RES_REQ is output, the memory device ( Figure 1 The suspended operation can be re-executed if it is set to 100 as shown.

[0168] In some implementations, when the monitoring information MONITOR_INF includes information about the normal mode, the operation controller 170 may output the write prevention signal WP or the status information STATUS_INF to the memory controller. Figure 1 As shown in 200), thus sending to the memory controller ( Figure 1 The 200 shown in the figure notifies the memory device ( Figure 1 The 100 shown in the diagram operates in normal mode again.

[0169] As described above, the temperature circuit 150 even when excluding the memory device ( Figure 1 During the runtime period other than the startup period of 100 shown, the memory device ( ) can also be measured at predetermined time intervals. Figure 1The temperature of the memory device (100) shown in the figure is measured, and therefore operations during the runtime can be performed based on the measurement results. Therefore, it is determined whether the temperature measured during the runtime is within a predetermined temperature range. When the temperature measured during runtime is outside the predetermined temperature range, the memory device ( Figure 1 The 100 shown is controlled to operate in protected mode, and a signal is sent to the memory controller ( Figure 1 The 200 shown in the figure notifies the memory device ( Figure 1 The 100 shown operates in protection mode, which can prevent failures.

[0170] Figure 11 This is a diagram illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0171] Reference Figure 11 In step S1101, the memory device can be started. When the memory device is started, external power can be supplied to both the memory controller and the memory device simultaneously.

[0172] In step S1103, the memory device can measure temperature. Specifically, the temperature circuit included in the memory device can measure temperature when the memory device is started.

[0173] In step S1105, the memory device can determine whether the measured temperature is within a reference range. The reference range can be a range within which the memory device is not turned off and can operate normally. As a result of the determination, if the measured temperature is within the reference range (yes), the memory device can proceed to step S1107. As a result of the determination, if the measured temperature is outside the reference range (no), the memory device can proceed to step S1109.

[0174] In step S1107, the memory device can perform a startup operation such as a CAM read operation. That is, when it is determined that the measured temperature is within the range where the memory device is not turned off and can operate normally, the memory device can perform a startup operation.

[0175] In step S1109, the memory device can suspend the startup operation and notify the memory controller that the startup operation has been suspended. That is, when it is determined that the measured temperature is a temperature at which the memory device can be shut down, the memory device can suspend the startup operation. Furthermore, the memory device can notify the memory controller that the startup operation has been suspended by writing prevention signals, status information, etc.

[0176] In an embodiment, when the memory device suspends the startup operation, the memory device can measure the temperature by performing step S1103 again.

[0177] The memory device can measure the temperature at predetermined time intervals. When the measured temperature becomes lower or higher than the reference range, the memory device can restart the startup operation. Furthermore, the memory device can notify the memory controller that the startup operation has resumed by writing prevent signals, status information, etc.

[0178] Figure 12 This is a diagram illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0179] Reference Figure 12 In step S1201, the memory device can measure the temperature at predetermined time intervals during the operating time. Specifically, the temperature circuit included in the memory device can measure the temperature not only during startup but also during the operating time.

[0180] In step S1203, the memory device can determine whether the measured temperature is within a reference range. As during startup, the reference range can be a range within which the memory device is not powered off and can operate normally.

[0181] As a result, if the measured temperature is within the reference range (Yes), the memory device can proceed to step S1201 again. As a result, if the measured temperature is outside the reference range (No), the memory device can proceed to step S1205. That is, if it is determined that the measured temperature is within the reference range, i.e., within the range where the memory device is not turned off and can operate normally, the memory device can continue to perform operations and measure the temperature at predetermined time intervals.

[0182] In step S1205, the memory device can suspend subsequent operations after the currently executing operation has completed. That is, when it is determined that the measured temperature is a temperature at which the memory device can be shut down, the memory device can suspend operations following the currently executing operation. Furthermore, the memory device can notify the memory controller that the operation has been suspended by writing prevention signals, status information, etc.

[0183] In operation S1207, the memory device can measure the temperature at predetermined time intervals. That is, the memory device can suspend operation and then measure the temperature again at predetermined time intervals.

[0184] In step S1209, the memory device can determine whether the measured temperature is within the reference range. That is, after the memory device suspends, the memory device can determine whether the measured temperature has decreased or increased within the reference range.

[0185] When the temperature measured in step S1209 is within the reference range (yes), the memory device can proceed to step S1211. That is, when it is determined that the measured temperature is within the range where the memory device is not turned off and can operate normally, the memory device can resume the suspended operation in step S1211, and then measure the temperature at predetermined time intervals by repeating step S1201. The memory device can notify the memory controller that the suspended operation has been resumed by writing a prevention signal, status information, etc.

[0186] When the temperature measured in step S1209 is not within the reference range (No), that is, when the temperature measured in step S1209 is outside the reference range, the memory device can measure the temperature again at predetermined time intervals by performing step S1207.

[0187] Figure 13 It is shown Figure 1 A diagram illustrating another embodiment of the memory controller shown.

[0188] Reference Figure 13 The memory controller 1000 is connected to the host and the memory device. The memory controller 1000 is configured to access the memory device in response to requests received from the host. For example, the memory controller 1000 is configured to control read operations, programming operations, erase operations, and background operations of the memory device. The memory controller 1000 is configured to provide an interface between the memory device and the host. The memory controller 1000 is configured to drive firmware for controlling the memory device.

[0189] The memory controller 1000 may include a processor 1010, a memory buffer 1020, an error correction code (ECC) circuit 1030, a host interface 1040, a buffer control circuit 1050, a memory interface 1060, and a bus 1070.

[0190] Bus 1070 can be configured to provide a channel between components of memory controller 1000.

[0191] The processor 1010 can control all operations of the memory controller 1000 and perform logical operations. The processor 1010 can communicate with an external host via the host interface 1040 and with the memory device via the memory interface 1060. Furthermore, the processor 1010 can communicate with the memory buffer 1020 via the buffer control circuit 1050. The processor 1010 can use the memory buffer 1020 as working memory, cache memory, or buffer memory to control the operation of the memory device.

[0192] Processor 1010 can perform the functions of Flash Translation Layer (FTL). Processor 1010 can use the FTL to translate logical block addresses (LBAs) provided by the host into physical block addresses (PBAs). The FTL can receive logical block addresses (LPAs) and use a mapping table to translate them into physical block addresses (PBAs). Depending on the mapping unit, there are several address mapping methods in the FTL. Representative address mapping methods include page mapping, block mapping, and hybrid mapping.

[0193] Processor 1010 is configured to randomize data received from the host. For example, processor 1010 may use a randomization seed to randomize data received from the host. The randomized data is then provided as data to be stored to a memory device and programmed into a memory cell array.

[0194] The processor 1010 can perform randomization and derandomization via driver software or firmware.

[0195] The memory buffer 1020 can be used as the working memory, cache memory, or buffer memory of the processor 1010. The memory buffer 1020 can store code and commands executed by the processor 1010. The memory buffer 1020 can store data processed by the processor 1010. The memory buffer 1020 may include static RAM (SRAM) or dynamic RAM (DRAM).

[0196] ECC circuit 1030 can perform ECC operations. ECC circuit 1030 can perform ECC encoding on data to be written to the memory device via memory interface 1060. The ECC-encoded data can be transmitted to the memory device via memory interface 1060. ECC circuit 1030 can perform ECC decoding on data received from the memory device via memory interface 1060. Exemplarily, ECC circuit 1030 can be included as a component of memory interface 1060.

[0197] The host interface 1040 can communicate with an external host under the control of the processor 1010. The host interface 1040 can communicate with the host using at least one of the following communication methods: Universal Serial Bus (USB), Serial AT Accessory (SATA), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), FireWire, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM).

[0198] The buffer control circuit 1050 is configured to control the memory buffer 1020 under the control of the processor 1010.

[0199] The memory interface 1060 is configured to communicate with the memory device under the control of the processor 1010. The memory interface 1060 can communicate commands, addresses, and data with the memory device via channels.

[0200] For example, the memory controller 1000 may not include the memory buffer 1020 and the buffer control circuit 1050.

[0201] For example, processor 1010 can control the operation of memory controller 1000 using code. Processor 1010 can load code from a non-volatile memory device (e.g., read-only memory (ROM)) configured in memory controller 1000. In another example, processor 1010 can load code from a memory device via memory interface 1060.

[0202] For example, the bus 1070 of the memory controller 1000 can be divided into a control bus and a data bus. The data bus can be configured to transmit data within the memory controller 1000, and the control bus can be configured to transmit control information such as commands and addresses within the memory controller 1000. The data bus and the control bus are separate from each other and can operate without interference or influence. The data bus can be connected to the host interface 1040, the buffer control circuit 1050, the ECC circuit 1030, and the memory interface 1060. The control bus can be connected to the host interface 1040, the processor 1010, the buffer control circuit 1050, the memory buffer 1020, and the memory interface 1060.

[0203] Figure 14 This is a block diagram illustrating a memory card system using a storage device according to an embodiment of the present disclosure.

[0204] Reference Figure 14 The memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0205] Memory controller 2100 is connected to memory device 2200. Memory controller 2100 is configured to access memory device 2200. For example, memory controller 2100 is configured to control read operations, write operations, erase operations, and background operations of memory device 2200. Memory controller 2100 is configured to provide an interface between memory device 2200 and a host. Memory controller 2100 is configured to drive firmware for controlling memory device 2200. Memory device 2200 can interact with memory device 100 (… Figure 1 The same applies to 100 shown in the figure.

[0206] For example, the memory controller 2100 may include components such as random access memory (RAM), processing unit, host interface, memory interface, and error corrector.

[0207] The memory controller 2100 can communicate with an external device via connector 2300. The memory controller 2100 can communicate with the external device (e.g., a host) according to a specific communication protocol. Exemplarily, the memory controller 2100 can communicate with the external device via at least one of a variety of communication protocols such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), WiFi, Bluetooth, and NVMe.

[0208] For example, the memory device 2200 may be implemented using various non-volatile memory devices such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM).

[0209] The memory controller 2100 and memory device 2200 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and memory device 2200 can form memory cards such as PC cards (Personal Computer Memory Card International Association (PCMCIA)), compact flash memory (CF) cards, smart media cards (SM and SMC), memory sticks, multimedia cards (MMC, RS-MMC, micro MMC and eMMC), SD cards (SD, mini SD, micro SD and SDHC) and universal flash memory (UFS).

[0210] In an embodiment, the temperature circuit included in the memory device 2200 can measure the temperature during startup or during the running time after startup, and the memory device 2200 can perform operations based on the measured temperature.

[0211] Specifically, the temperature circuit can measure the temperature of the memory device 2200 during startup. When the measured temperature is within a predetermined range, the memory device 2200 can continue to perform the startup operation.

[0212] However, when the measured temperature is outside the predetermined range, the memory device 2200 can suspend the startup operation. When the startup operation is suspended, the memory device 2200 can notify the memory controller 2100 that the startup operation has been suspended by writing a prevention signal or status information.

[0213] After the memory device 2200 suspends the startup operation, the temperature circuit can measure the temperature at predetermined time intervals. When the measured temperature is within a predetermined range, the memory device 2200 can resume the suspended startup operation. The memory device 2200 can notify the memory controller 2100 that the startup operation has been resumed by writing a prevention signal or status information.

[0214] In this embodiment, the temperature circuit can measure the temperature of the memory device 2200 during operation. When the measured temperature is within a predetermined range, the memory device 2200 can continue to perform the operation being executed.

[0215] However, when the measured temperature is outside the predetermined range, the memory device 2200 can complete the operation being performed and then suspend the operation from the next operation onwards. The memory device 2200 can notify the memory controller 2100 that the operation has been suspended by writing a prevention signal or status information.

[0216] After the memory device 2200 suspends an operation, the temperature circuit can measure the temperature at predetermined time intervals. When the measured temperature is within a predetermined range, the memory device 2200 can resume the suspended operation. The memory device 2200 can notify the memory controller 2100 that the operation has been resumed by writing a prevent signal or status information.

[0217] Therefore, by measuring the temperature during startup or during operation time after startup using the temperature circuit in the memory device 2200, and controlling the operation of the memory controller 2100 and the memory device 2200 based on the measured temperature, malfunctions during startup or operation time can be prevented.

[0218] Figure 15This is a block diagram illustrating a solid-state drive (SSD) system using a storage device according to an embodiment of the present disclosure.

[0219] Reference Figure 15 The SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals SIG with the host 3100 through a signal connector 3001 and receives power PWR through a power connector 3002. The SSD 3200 includes an SSD controller 3210, multiple flash memories 3221 to 322n, an auxiliary power supply 3230, and a cache memory 3240.

[0220] In this embodiment, the SSD controller 3210 can be used as a memory controller. Figure 1 (200 as shown).

[0221] SSD controller 3210 can control multiple flash memories 3221 to 322n in response to a signal SIG received from host 3100. Exemplarily, the signal SIG can be a signal based on the interface between host 3100 and SSD 3200. For example, the signal SIG can be a signal defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0222] Auxiliary power supply 3230 is connected to host 3100 via power connector 3002. Auxiliary power supply 3230 can provide power to SSD 3200 when the power supply from host 3100 is unstable. Exemplarily, auxiliary power supply 3230 can be located inside or outside SSD 3200. For example, auxiliary power supply 3230 can be located on the motherboard and provide auxiliary power to SSD 3200.

[0223] Buffer memory 3240 operates as a buffer memory for SSD 3200. Auxiliary power supply 3230 can receive power PWR input from host 3100 and can be charged using power PWR. For example, buffer memory 3240 can temporarily store data received from host 3100 or data received from multiple flash memories 3221 to 322n, or temporarily store metadata (e.g., mapping tables) of flash memories 3221 to 322n. Buffer memory 3240 can include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0224] In an embodiment, the temperature circuit included in each of the plurality of flash memories 3221 to 322n can measure the temperature during startup or during the running time after startup, and each of the plurality of flash memories 3221 to 322n can perform operations based on the measured temperature.

[0225] Specifically, the temperature circuit can measure the temperature of multiple flash memories 3221 to 322n during startup. When the measured temperature is within a predetermined range, the multiple flash memories 3221 to 322n can continue to perform the startup operation.

[0226] However, when the measured temperature is outside the predetermined range, the multiple flash memories 3221 to 322n can suspend the boot operation. When the boot operation is suspended, the multiple flash memories 3221 to 322n can notify the SSD controller 3210 that the boot operation has been suspended by writing a prevent signal or status information.

[0227] After multiple flash memories 3221 to 322n suspend boot operations, the temperature circuit can measure the temperature at predetermined time intervals. When the measured temperature is within a predetermined range, the multiple flash memories 3221 to 322n can resume the suspended boot operation. The multiple flash memories 3221 to 322n can notify the SSD controller 3210 that the boot operation has been resumed by writing a prevent signal or status information.

[0228] In this embodiment, the temperature circuit can measure the temperature of the multiple flash memories 3221 to 322n during operation. When the measured temperature is within a predetermined range, the multiple flash memories 3221 to 322n can continue to perform the operation being executed.

[0229] However, when the measured temperature is outside the predetermined range, the multiple flash memories 3221 to 322n can complete the operation being performed and then suspend the operation from the next operation onwards. The multiple flash memories 3221 to 322n can notify the SSD controller 3210 that the operation has been suspended by writing a prevent signal or status information.

[0230] After multiple flash memories 3221 to 322n suspend operations, the temperature circuit can measure the temperature at predetermined time intervals. When the measured temperature is within a predetermined range, the multiple flash memories 3221 to 322n can resume the suspended operation. The multiple flash memories 3221 to 322n can notify the SSD controller 3210 that the operation has resumed by writing a prevent signal or status information.

[0231] Therefore, by measuring the temperature during startup or during operation time through the temperature circuit in each of the multiple flash memories 3221 to 322n, and controlling the operation of the SSD controller 3210 and the multiple flash memories 3221 to 322n based on the measured temperature, failures during startup or operation time can be prevented.

[0232] Figure 16 This is a block diagram illustrating a user system employing a storage device according to an embodiment of the present disclosure.

[0233] Reference Figure 16 The user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0234] Application processor 4100 can drive components, operating system (OS), user programs, etc., included in user system 4000. For example, application processor 4100 may include controllers, interfaces, graphics engines, etc., for controlling components included in user system 4000. Application processor 4100 may be configured as a system-on-a-chip (SoC).

[0235] Memory module 4200 can operate as main memory, working memory, buffer memory, or cache memory of user system 4000. Memory module 4200 may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. Exemplarily, application processor 4100 and memory module 4200 can be configured as a single semiconductor package by being packaged based on a stacked package (PoP).

[0236] Network module 4300 can communicate with external devices. Exemplarily, network module 4300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. Exemplarily, network module 4300 can be included in application processor 4100.

[0237] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Optionally, storage module 4400 can transfer the data stored therein to application processor 4100. Exemplarily, storage module 4400 can be implemented using non-volatile semiconductor memory devices such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a three-dimensional structure. Exemplarily, storage module 4400 can be configured as a removable drive, such as a memory card of user system 4000 or an external drive.

[0238] For example, the storage module 4400 may include a plurality of non-volatile memory devices, and the plurality of non-volatile memory devices may be connected to a reference. Figure 2 and Figure 3 The memory device described operates in the same manner. The memory module 4400 can be compared with the referenced... Figure 1 The storage device 50 described operates in the same manner.

[0239] User interface 4500 may include interfaces for inputting data or commands to application processor 4100 or outputting data to external devices. Exemplarily, user interface 4500 may include user input interfaces such as: keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric element. User interface 4500 may include user output interfaces such as: liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active-matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0240] In an embodiment, the temperature circuit included in the storage module 4400 can measure the temperature during startup or during the running time after startup, and the storage module 4400 can perform operations based on the measured temperature.

[0241] Specifically, the temperature circuit can measure the temperature of the storage module 4400 during startup. When the measured temperature is within a predetermined range, the storage module 4400 can continue to perform the startup operation.

[0242] However, when the measured temperature is outside the predetermined range, the storage module 4400 can suspend the startup operation. When the startup operation is suspended, the storage module 4400 can notify the application processor 4100 that the startup operation has been suspended by writing a prevention signal or status information.

[0243] After the storage module 4400 suspends the startup operation, the temperature circuit can measure the temperature at predetermined time intervals. When the measured temperature is within a predetermined range, the storage module 4400 can resume the suspended startup operation. The storage module 4400 can notify the application processor 4100 that the startup operation has been resumed by writing a prevent signal or status information.

[0244] In this embodiment, the temperature circuit can measure the temperature of the storage module 4400 during operation. When the measured temperature is within a predetermined range, the storage module 4400 can continue to perform the operation being executed.

[0245] However, when the measured temperature is outside the predetermined range, the storage module 4400 can complete the currently executing operation and then suspend the operation from the next operation onwards. The storage module 4400 can notify the application processor 4100 that the operation has been suspended by writing a prevent signal or status information.

[0246] After the storage module 4400 suspends an operation, the temperature circuit can measure the temperature at predetermined time intervals. When the measured temperature is within a predetermined range, the storage module 4400 can resume the suspended operation. The storage module 4400 can notify the application processor 4100 that the operation has been resumed by writing a prevent signal or status information.

[0247] Therefore, by measuring the temperature during startup or during the running time after startup using the temperature circuit in the storage module 4400, and controlling the operation of the application processor 4100 and the storage module 4400 based on the measured temperature, it is possible to prevent malfunctions during startup or during the running time.

[0248] According to this disclosure, the operation is performed based on the temperature measured at startup and based on the temperature measured after startup, thereby preventing memory device failure and changes in the threshold voltage distribution of memory cells.

Claims

1. A memory device, comprising: Multiple memory units; Peripheral circuitry performs operations on the plurality of memory units; Temperature circuitry for measuring the temperature of the memory device; The monitoring component generates monitoring information based on whether the measured temperature is within the reference range. The monitoring information indicates whether the operating mode is a normal mode for performing the operation or a protection mode for suspending the operation. as well as The operation controller outputs signals to control the operation based on the monitoring information. The monitoring component further responds to receiving the measured temperature from the temperature circuit, stores the monitoring information, and outputs the monitoring information to the operation controller. The operation controller further outputs the status information of the operation mode to an external controller when it detects that a reset operation of the memory device is being performed.

2. The memory device of claim 1, wherein the temperature circuit measures the temperature of the memory device during startup operation.

3. The memory device of claim 1, wherein the monitoring component further generates monitoring information representing the normal mode in response to receiving a measured temperature within the reference range.

4. The memory device of claim 1, wherein the monitoring component further generates monitoring information representing the protection mode in response to receiving a measured temperature outside the reference range.

5. The memory device according to claim 1, wherein the operation controller further outputs the status information or a signal notifying the memory device of the operation mode to the external controller.

6. The memory device of claim 1, wherein the temperature circuit further measures the temperature of the memory device after the startup operation of the memory device.

7. The memory device of claim 1, wherein the monitoring component provides updated monitoring information corresponding to a newly measured temperature received from the temperature circuit.

8. The memory device of claim 1, wherein the operation controller outputs the signal to perform the operation, suspend the operation, or resume the operation.

9. The memory device of claim 1, wherein the temperature circuit, in response to receiving power from an external device, performs a first measurement of the temperature of the memory device.

10. A method of operating a memory device, the method comprising: Initiate the startup operation of the memory device; The initial temperature of the memory device is measured during the startup operation; Monitoring information is generated based on whether the initial temperature is within the reference range. This monitoring information indicates either a startup mode that continues the startup operation or a protection mode that suspends the startup operation. Based on the monitoring information, a request is output to either continue the startup operation or suspend the startup operation. When a reset operation of the memory device is detected, the status information of the operating mode of the memory device is output to an external controller.

11. The method of claim 10, further comprising: The temperature of the memory device is measured repeatedly at predetermined time intervals.

12. The method of claim 10, wherein the repeated temperature measurements occur during the startup operation or during a runtime operation performed after the startup operation.

13. The method of claim 10, further comprising: The system outputs the status information of the operating mode to the external controller or sends a signal to the memory device to indicate the operating mode.

14. The method of claim 11, further comprising: The monitoring information is repeatedly generated based on the newly measured temperature, and updated monitoring information is provided based on the newly measured temperature.

15. The method of claim 14, further comprising: An updated request is output based on the updated monitoring information, and the updated request restores the startup operation or another operation that has been suspended.

16. The method of claim 10, wherein the initial temperature is measured based on power received from an external device.

17. A storage device, comprising: A memory device comprising a plurality of memory cells, each memory cell storing data; as well as A memory controller that communicates with and controls the operation of the memory device. The memory device measures its temperature and provides a signal to the memory controller indicating whether the memory device is operating in a normal mode (performing the operation) or a protective mode (suspending the operation). This signal depends on whether the memory device's temperature is within a reference range. When a reset operation of the memory device is detected, the status information of the operating mode of the memory device is output to the memory controller.

18. The storage device of claim 17, wherein the storage device further measures the temperature of the storage device repeatedly at predetermined time intervals.

19. The storage device of claim 18, wherein the storage device further provides another signal indicating an updated operating mode of the storage device based on whether a newly measured temperature of the storage device is within the reference range.

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