Formation control method for resistive memory cell array

Abstract

A forming control method for a resistive memory cell array is provided. In the forming control method, a verification operation is performed to determine whether the resistive memory cell array has successfully completed a forming operation. In the forming control method, the forming voltage Vform or the pulse width w of the forming pulse is appropriately changed so that all of the resistive memory cells in the resistive memory cell array successfully complete the forming operation.

Description

Technical Field

[0001] This invention relates to a control method for a memory cell array, and more particularly to a method for forming a resistive memory cell array. Background Technology

[0002] Resistive random-access memory (ReRAM) is a type of non-volatile memory consisting of an array of resistive memory cells (ReRAM cells). Because resistive memory requires fewer manufacturing steps and has a faster write speed, it is well-suited to replace embedded flash memory in system-on-a-chip (SoC).

[0003] Generally, resistive memory cells include a resistive element. Adjusting the resistance value of the resistive element controls the storage state of the resistive memory cell. The storage state of a resistive memory cell can be a set state with a low resistance value or a reset state with a high resistance value.

[0004] Please refer to Figure 1 The diagram shown is a schematic of a resistive element. For example... Figure 1 As shown, the resistive element 100 includes a stacked lower electrode 106, an insulating layer 104, and an upper electrode 102. After the resistive element 100 is manufactured, it is in its initial state.

[0005] Before the resistive element 100 can begin to operate, a forming action is required. During the forming action, a forming voltage, such as 2.8V, is provided between the upper electrode 102 and the lower electrode 106. At this time, the oxygen vacancies accumulated in the insulating layer 104 form a conducting filament 108, which connects the upper electrode 102 and the lower electrode 106, thus putting the resistive element 100 into a low-resistance set state.

[0006] After the resistive element 100 has undergone the forming operation, it is further provided with various bias voltages lower than the forming voltage, which allows the resistive element 100 to switch freely between a low resistance value set state and a high resistance value reset state. This is explained below.

[0007] In the low-resistance setting state, a reset action can change the resistive element 100 to a high-resistance reset state. During the reset action, a reset voltage, for example, approximately 1.7V, is provided between the upper electrode 102 and the lower electrode 106. At this time, the conductive wire 108 in the insulating layer 104 undergoes a redox process, causing the conductive wire 108 to be almost disconnected between the upper electrode 102 and the lower electrode 106. That is, after the reset action is completed, the upper electrode 102 and the lower electrode 106 are in a high-resistance reset state.

[0008] In the high-resistance reset state, the resistive element 100 can be changed to a low-resistance setting state via a set action. During the set action, a set voltage, for example, approximately 2.1V, is provided between the upper electrode 102 and the lower electrode 106. At this time, the conductive wire 108 in the insulating layer 104 is fully connected between the upper electrode 102 and the lower electrode 106. That is, after the set action is completed, the upper electrode 102 and the lower electrode 104 are in a low-resistance setting state.

[0009] As explained above, after the resistive element 100 is manufactured, a forming process must be performed first. Only then can the resistive element 100 be reset or set.

[0010] Furthermore, during the read operation, a read voltage, such as approximately 0.3V to 0.8V, is provided between the upper electrode 102 and the lower electrode 106. The storage state of the resistive element 100 is determined based on the read current generated by the resistive element 100. For example, a reference current is provided during the read operation. When the read current is less than the reference current, the resistive element 100 is determined to be in a high-resistance reset state. When the read current is greater than the reference current, the resistive element 100 is determined to be in a low-resistance set state.

[0011] Of course, the reading voltage can also be used for verification. For example, after the forming operation of resistive element 100, in order to further confirm whether the resistive element 100 has successfully formed a conductive wire 108 connected between the upper electrode 102 and the lower electrode 106, a verification operation can be performed on the resistive element 100. That is, when performing the verification operation after the forming operation, a controller (not shown) provides a reading voltage to the resistive element 100 and further determines whether the forming operation is successful based on the reading current generated by the resistive element 100. If the reading current is large, the forming operation of the resistive element 100 is considered successful and the verification operation passes. Conversely, if the reading current is too low, the forming operation of the resistive element 100 is considered a failure and the verification operation fails.

[0012] Similarly, after setting or resetting the resistive element 100, a verification operation can be performed on the resistive element 100, and the verification result can be further confirmed based on the read current generated by the resistive element 100. For example, a verification operation can be performed after a reset operation. If the read current is small and the reset state is determined to be high resistance, the resistive element 100 passes the verification operation, indicating that the reset operation was successful. Conversely, if the read current is too large and the reset state is determined to be low resistance, the resistive element 100 fails the verification operation, indicating that the reset operation failed.

[0013] Please refer to Figure 2 The diagram shown is a schematic of a resistive memory cell array. The resistive memory cell array 200 consists of m×n resistive memory cells c11 to cmn, where m and n are positive integers. Furthermore, the structure of each resistive memory cell c11 to cmn is the same. The following explanation uses resistive memory cell c11 as an example, and the others will not be described in detail.

[0014] The resistive memory cell c11 is a three-terminal device. The resistive memory cell c11 includes a resistive element R. 11 With a selection transistor M 11 Resistive element R 11 The first terminal serves as the first terminal of the resistive storage cell c11, and the resistive element R 11 The second terminal is connected to the selection transistor M 11 The first drain / source terminal is selected by transistor M. 11 The second drain / source terminal serves as the second terminal of the resistive memory cell C11, selecting transistor M. 11 The gate terminal is used as the control terminal of the resistive memory cell C11.

[0015] In the resistive memory cell array 200, the control terminals of the first row of n resistive memory cells c11 to c1n are connected to the word line WL1, the first terminals of the first row of n resistive memory cells c11 to c1n are connected to the corresponding bit lines BL1 to BLn, and the second terminals of the first row of n resistive memory cells c11 to c1n are connected to the corresponding source lines SL1 to SLn. Similarly, the control terminals of the second row of n resistive memory cells c21 to c2n are connected to the word line WL2, the first terminals of the second row of n resistive memory cells c21 to c2n are connected to the corresponding bit lines BL1 to BLn, and the second terminals of the second row of n resistive memory cells c21 to c2n are connected to the corresponding source lines SL1 to SLn, and so on. Similarly, the control terminals of the n resistive memory cells cm1 to cmn in the m-th row are connected to the word line WLm, the first terminals of the n resistive memory cells cm1 to cmn in the m-th row are connected to the corresponding bit lines BL1 to BLn, and the second terminals of the n resistive memory cells cm1 to cmn in the m-th row are connected to the corresponding source lines SL1 to SLn.

[0016] For example, a resistive memory cell array 200 has 1024 word lines, 2048 bit lines, and 2048 source lines. That is, m equals 1024 and n equals 2048.

[0017] Similarly, after the resistive memory cell array 200 is manufactured, each resistive memory cell c11 to cmn needs to be formed first. Only after confirming that the formation of all resistive memory cells c11 to cmn is successful can the resistive memory cells c11 to cmn be reset or set.

[0018] The following uses 1×n and m×1 resistive memory cell arrays as examples to illustrate the formation control method, which can also be applied to m×n resistive memory cell arrays.

[0019] Please refer to Figures 3A to 3C The diagram illustrates a method for controlling the formation of a resistive memory cell array. The resistive memory cell array consists of 1×n resistive memory cells c1 to cn.

[0020] When performing the formation control method, the turn-on voltage V will be... on A word line WL1 provides the ground voltage GND (i.e., 0V) to the source lines SL1-SLn. Then, forming pulses are sequentially provided to the bit lines BL1-BLn. The turn-on voltage V... onThe voltage can be 2.5V, with a pulse width of w and a pulse height of Vform. For example, if the pulse width w is 100ns, the formed voltage Vform... form It is 2.8V.

[0021] First, a forming operation is performed on the resistive memory cell c1. As shown in Figure 3A, a forming pulse is provided to bit line BL1, and the ground voltage GND is provided to the other bit lines BL2 to BLn. In the resistive memory cell c1, since word line WL1 receives the turn-on voltage V... on When transistor M1 is turned on, a voltage V is formed across the two terminals of resistive element R1. form A conductive wire is formed connecting the two terminals of the resistive element R1. Additionally, in the resistive memory cells c2~cn, since the bit lines BL2~BLn receive the ground voltage GND, the resistive elements R2~R... n The two ends do not receive the voltage V formed form However, no conductive wire was formed.

[0022] Next, the resistive memory cell c2 is formed. For example... Figure 3B As shown, a forming pulse is provided to bit line BL2, and the ground voltage GND is provided to other bit lines BL1, BL3~BLn. In the resistive memory cell c2, since word line WL1 receives the turn-on voltage V... on When transistor M2 is turned on, a voltage V is formed across the two ends of resistive element R2. form A conductive wire is formed connecting the two terminals of the resistive element R2. Additionally, the resistive elements R3 to R4 in the resistive memory cells c3 to c1 are... n No conductive filament was formed.

[0023] Similarly, forming pulses are sequentially provided to each individual bit line. Finally, the forming operation is performed on the resistive memory cell cn. Figure 3C As shown, a forming pulse is provided to bit line BLn, and the ground voltage GND is provided to other bit lines. In the resistive memory cell cn, since word line WL1 receives the turn-on voltage V... on Select transistor M n Turn on, resistive element R n The two ends bear the voltage V formed. form And form a conductive wire connected to the resistive element R n Between the two endpoints.

[0024] In other words, by using the above method, after sequentially providing forming pulses to bit lines BL1 to BLn, the forming operation can be performed on the n resistive memory cells of the 1×n resistive memory cell array in sequence.

[0025] Please refer to Figures 4A to 4C The diagram illustrates a method for controlling the formation of a resistive memory cell array. The resistive memory cell array consists of m×1 resistive memory cells c1 to cm.

[0026] During the formation control method, the ground voltage GND (i.e., 0V) is provided to the source line SL1, the forming pulse is provided to the bit line BL1, and the turn-on voltage V is sequentially applied. on Provides word lines WL1 to WLm. The turn-on voltage V... on It can be 2.5V, the pulse width is w, and the pulse height is the forming voltage V. form For example, a pulse width w of 100 ns forms a voltage V. form It is 2.8V.

[0027] First, the resistive memory cell c1 is formed. For example... Figure 4A As shown, the turn-on voltage V will be... on Providing the word line WL1 will turn off the voltage V. off It provides power to other word lines WL2~WLm, provides a forming pulse to bit line BL1, and provides ground voltage GND to source line SL1. For example, the shutdown voltage V off It can operate between -0.3V and -0.1V. In the resistive memory cell C1, since the word line WL1 receives the turn-on voltage V... on When transistor M1 is turned on, a voltage V is formed across the two terminals of resistive element R1. form This forms a conductive wire connected between the two terminals of the resistive element R1. Additionally, in the resistive memory cells c2 to cm, the word lines WL2 to WLm receive the shutdown voltage V. off Resistive elements R2 to R m The two ends do not receive the voltage V formed form However, no conductive wire was formed.

[0028] Next, the resistive memory cell c2 is formed. For example... Figure 4B As shown, the turn-on voltage V will be... on Providing the word line WL2 will turn off the voltage V. offIt provides forming pulses to other word lines WL1, WL3~WLm, and ground voltage GND to source line SL1. Therefore, the resistive element R2 bears the formed voltage V. form Conductive wires are formed between the two terminals of the resistive element R2. However, the resistive elements R3 to Rm in the resistive memory cells c3 to cm do not have conductive wires.

[0029] And so on, providing the turn-on voltage V in sequence. on To a single word line. Finally, the resistive memory cell (cm) is formed. For example... Figure 4C As shown, the turn-on voltage V will be... on Providing the word line WLm will turn off the voltage V. off Providing to other word lines, forming pulses are provided to bit line BL1, and ground voltage GND is provided to source line SL1. Therefore, resistive element R m The two ends bear the voltage V formed. form And form a conductive wire connected to the resistive element R m Between the two endpoints.

[0030] In other words, by using the above method, the turn-on voltage V is provided sequentially. on After reaching word lines WL1 to WLm, the m resistive memory cells of the m×1 resistive memory cell array can be formed sequentially.

[0031] Ideally, in the aforementioned m×1 resistive memory cell array, when the number of word lines is small, such as 20 word lines (m=20), the above method can successfully form the memory cell array. However, when the number of word lines in the resistive memory cell array is large, such as 1024 bit lines (m=1024), considering the load of bit line BL1 and the leakage current of the resistive memory cells, the above-described formation control method will cause the formation operation to fail. This will be explained below.

[0032] Please refer to Figures 5A to 5C The diagram illustrates the actual implementation of a resistive memory cell array formation control method. The resistive memory cell array consists of 1024 × 1 resistive memory cells c1 to c1024. That is, the resistive memory cell array has 1024 bit lines WL1 to WL1024.

[0033] Similarly, during the formation control method, a forming pulse is provided to bit line BL1, and ground voltage GND (i.e., 0V) is provided to source line SL1. Then, the turn-on voltage V is sequentially...on Provided to word lines WL1 to WL1024, while other word lines receive the shutdown voltage V. off That is, the resistive memory cells c1 to c1024 are formed sequentially. The turn-on voltage V... on It can be 2.5V, and the shutdown voltage is V. off Between -0.3V and -0.1V.

[0034] First, the resistive memory cell c1 is formed. For example... Figure 5A As shown, the turn-on voltage V will be... on Providing the word line WL1 will turn off the voltage V. off The forming pulse is provided to the bit line BL1 and the ground voltage GND is provided to the source line SL1, which is supplied to other word lines WL2 to WL1024. In the resistive memory cell c1, since word line WL1 receives the turn-on voltage V... on Select transistor M1 is turned on. At this time, bit line BL1 receives a forming pulse with a pulse height of 2.8V, so the bit line voltage (V) BL1 The voltage is 2.8V. Therefore, the conductive wire is connected between the two terminals of the resistive element R1. That is, the resistive memory cell C1 is successfully formed.

[0035] Next, the resistive memory cell C2 is formed by setting the turn-on voltage V. on Provide to word line WL2 and turn off voltage V off Provided to other word lines WL1, WL3~WL1024. For example... Figure 4B As shown, in the resistive memory cell c1, although the selection transistor M1 receives the turn-off voltage V off However, since the resistive element R1 has been changed to a low resistance setting, transistor M1 will generate a leakage current I. leak1 The current flows from bit line BL1 to source line SL1. In other words, the pulse height decreases due to the leakage current generated by the resistive memory cell c1 and the load on bit line BL1.

[0036] like Figure 5B As shown, when a pulse is generated to bit line BL1, the pulse height of the generated pulse drops to 2.795V, causing the bit line voltage V to decrease. BL1 It is 2.795V. And the bit line voltage V is 2.795V. BL1 The resistive element R2 within the resistive memory cell c2 can still form a conductive wire connecting the two terminals. In other words, the resistive memory cell c2 is successfully formed.

[0037] Similarly, the forming process continues for the resistive memory cell C3. The turn-on voltage V is then... on Provide to word line WL3 and turn off voltage V off When supplied to other word lines, both resistive memory cells C1 and C2 will generate leakage current, causing the bit line voltage V to drop. BL1 It is even lower than 2.795V, but still sufficient for the formation of the resistive memory cell c3 to succeed.

[0038] As the number of resistive memory cells completing the formation process increases, the leakage current on the source line SL1 increases, and the bit line voltage V received by the resistive memory cell also increases. BL1 The lower it will be. For example... Figure 5C As shown, when forming the resistive memory cell c21, the turn-on voltage V is... on Provide to word line WL21 and turn off voltage V off Provided to other word lines. Since the formation of the first twenty resistive memory cells c1 to c20 in the resistive memory cell array was successful, all twenty resistive memory cells c1 to c20 will generate leakage current, and the total leakage current I on the source line SL1... leak Size is At this time, the resistive memory cell C21 can only receive a bit line voltage V of approximately 2.7V. BL1 .

[0039] like Figure 5C As shown, the bit line voltage V is 2.7V. BL1 The voltage is too low to allow the resistive element R inside the resistive memory cell C21 to operate. 21 A conductive wire is formed connecting the two endpoints. That is, the resistive memory cell c21 fails to operate. Similarly, in the resistive memory cell array, the resistive memory cells c22 to c1024 following resistive memory cell c21 will also fail to operate. Summary of the Invention

[0040] This invention relates to a formation control method for a resistive memory cell array, the resistive memory cell array comprising m resistive memory cells, where m is a positive integer. The formation control method includes the following steps: (a) setting i equal to 1; (b) providing an initial formation voltage; (c) generating a formation pulse with the formation voltage and performing a formation operation on the i-th resistive memory cell in the resistive memory cell array; (d) performing a verification operation on the i-th resistive memory cell and determining whether the i-th resistive memory cell passes the verification operation; (e) when the i-th resistive memory cell fails the verification operation... (c) When the verification operation fails and the formation voltage applied to the i-th resistive memory cell has not reached the predetermined number of changes, the formation voltage is increased and step (c) is executed; (f) When the i-th resistive memory cell fails the verification operation and the formation voltage applied to the i-th resistive memory cell reaches the predetermined number of changes, i is incremented by 1 and step (c) is executed; (g) When the i-th resistive memory cell passes the verification operation and i is not equal to m, i is incremented by 1 and step (c) is executed; and (h) When the i-th resistive memory cell passes the verification operation and i is equal to m, the formation control method is completed.

[0041] This invention relates to a formation control method for a resistive memory cell array, the formation control method comprising the following steps: (a) providing an initial formation voltage; (b) providing an initial pulse width; (c) generating a formation pulse based on the formation voltage and the pulse width, and performing a formation operation on a plurality of resistive memory cells in a selected row; (d) determining whether all the resistive memory cells in the selected row have passed the verification operation; (e) when all the resistive memory cells in the selected row have passed the verification operation, determining the next selected row, and executing step (b); (f) when not all the resistive memory cells in the selected row have passed the verification operation... If the verification operation is passed and the pulse width has not reached the first predetermined number of changes, the pulse width is increased and step (c) is executed; (g) if not all resistive memory cells in the selected row pass the verification operation, the pulse width reaches the first predetermined number of changes, and the formation voltage has not reached the second predetermined number of changes, the formation voltage is increased and step (b) is executed; and (h) if not all resistive memory cells in the selected row pass the verification operation, the pulse width reaches the first predetermined number of changes, and the formation voltage reaches the second predetermined number of changes, the next selected row is determined and step (b) is executed.

[0042] To provide a better understanding of the above and other aspects of the present invention, preferred embodiments are described below in detail with reference to the accompanying drawings: Attached Figure Description

[0043] Figure 1 This is a schematic diagram of a resistive element;

[0044] Figure 2 This is a schematic diagram of a resistive memory cell array;

[0045] Figures 3A to 3C This is a schematic diagram of the formation control method for resistive memory cell arrays;

[0046] Figures 4A to 4C This is a schematic diagram of the formation control method for resistive memory cell arrays;

[0047] Figures 5A to 5C The actual situation of forming control methods for resistive memory cell arrays;

[0048] Figure 6A This is a flowchart of the method for forming and controlling a resistive memory cell array according to the first embodiment of the present invention;

[0049] Figure 6B A statistical graph showing the number of forming operations performed on each resistive memory cell in a resistive memory cell array and the corresponding forming voltage;

[0050] Figure 7A This is a flowchart of the method for forming and controlling a resistive memory cell array according to the second embodiment of the present invention;

[0051] Figure 7B A statistical graph showing the number of forming operations performed on each resistive memory cell in a resistive memory cell array and the corresponding forming voltage;

[0052] Figure 8A The present invention relates to a resistive memory; and

[0053] Figure 8B This is a flowchart of the method for forming and controlling a resistive memory cell array according to the third embodiment of the present invention. Detailed Implementation

[0054] In a resistive memory cell array, as the number of resistive memory cells that have successfully formed increases, more leakage current is generated, causing the bit line voltage to drop and affecting subsequent resistive memory cells that have not yet successfully formed.

[0055] Therefore, this invention proposes a method for controlling the formation of resistive memory cell arrays. This invention utilizes a verification process to determine the resistive memory cell and appropriately adjusts the formation voltage V of the formation pulse. form Alternatively, the pulse width w can be adjusted so that all resistive memory cells in the resistive memory cell array can successfully complete the forming process.

[0056] Please refer to Figure 6AThe diagram illustrates a flowchart of the formation control method for a resistive memory cell array according to a first embodiment of the present invention. At the start of the formation control method, i is set to 1 (step S602), and an initial formation voltage V is provided. form (Step S604). Next, to form a voltage V form A forming pulse is generated to sequentially form the resistive memory cells ci to cm (step S606).

[0057] Next, it is determined whether the resistive memory cell ci has passed the verification operation (step S608). If the resistive memory cell ci has passed the verification operation and is not the last resistive memory cell, that is, i equals m is not true (step S610), i is incremented by 1 (step S612) and the process returns to step S608. Alternatively, if the resistive memory cell ci has passed the verification operation and is the last resistive memory cell, that is, i equals m is true (step S610), the formation control method ends.

[0058] Additionally, when the resistive memory cell ci fails the verification process, the generation voltage V is increased. form (Step S614), and return to step S606. For example, to increase the formation voltage V form At that time, the original voltage V can be formed. form Adding an incremental voltage creates a newer forming voltage V. form That is, V form =V form +ΔV.

[0059] For example, the formation control method of the first embodiment of the present invention can be applied to... Figure 5A The resistive memory cell array consists of m×1 resistive memory cells c1 to cm. Here, m is 1024, and the resistive memory cell array has 1024 word lines WL1 to WL1024.

[0060] Please refer to Figure 6B The graph depicts the number of formation operations performed on each resistive memory cell in the resistive memory cell array and the corresponding formation voltage. The initial formation voltage V0 is shown in the graph. form It is 2.8V, forming a voltage V form The incremental voltage ΔV is 0.2V.

[0061] When the formation control method of the first embodiment begins, by Figure 6B The statistical chart shows that i equals 1, and based on the initial formation voltage V of 2.8V... form To generate a forming pulse and to turn on the voltage Von The bits WL1 to WL1024 are sequentially provided, enabling the resistive memory cells c1 to c1024 to perform the first formation operation (1st).

[0062] After the above actions are completed, since i equals 1, resistive memory cell c1 undergoes a verification process. When resistive memory cell c1 passes the verification process, i increases by 1 (i.e., i equals 2), so resistive memory cell c2 undergoes a verification process. This process continues, verifying subsequent resistive memory cells.

[0063] like Figure 6B As shown, when i equals 21, the resistive storage cell c21 fails the verification operation. At this time, a voltage V will be generated. form Increase to 3.0V (2.8V + 0.2V), and based on the formation voltage V of 3.0V. form To generate a pulse and turn on the voltage V on The bits WL21 to WL1024 are sequentially provided, so that the resistive memory cells c21 to c1024 perform a second forming operation (2nd).

[0064] After the above actions are completed, since i equals 21, the verification action starts from the resistive memory cell c21 and is performed on the subsequent resistive memory cells in sequence.

[0065] like Figure 6B As shown, when i equals 150, the resistive storage cell c150 fails the verification operation. At this time, a voltage V will be generated. form Increase to 3.2V (3.0V + 0.2V), and based on the formation voltage V of 3.2V. form To generate a pulse and turn on the voltage V on The bit lines WL150 to WL1024 are sequentially provided, causing the resistive memory cells c150 to c1024 to perform a third forming operation (3rd).

[0066] After the above actions are completed, since i equals 150, the verification action starts from the resistive memory cell c150 and the verification action is performed on the subsequent resistive memory cells in sequence.

[0067] Following the same process, when i equals 510, the resistive memory cell c510 fails the verification operation, thus generating the pulse generation voltage V. form The voltage is increased to 3.4V respectively, and a fourth (4th) formation operation is performed on resistive memory cells c510 to c1024. Additionally, when i equals 775, resistive memory cell c775 fails the verification operation, so the formation voltage V for forming the pulse is... formThe voltage is increased to 3.6V respectively, and the fifth (5th) formation operation is performed on the resistive memory cells c775 to c1024.

[0068] Finally, when the voltage V is formed form When increased to 3.8V, based on the formation voltage V of 3.8V... form The process generates a forming pulse and sequentially performs a sixth forming operation (6th) on resistive memory cells c930 to c1024, after which all resistive memory cells c930 to c1024 pass the verification operation.

[0069] After the above-described formation control method process, it can be confirmed that all resistive memory cells c1 to c1024 have successfully passed the verification operation, thus concluding the formation control method of the present invention.

[0070] In the first embodiment of the present invention, many resistive memory cells undergo multiple formation operations, resulting in a lengthy formation control method. For example, resistive memory cells c930 to c1024 undergo six formation operations. Modifying the formation control method of the first embodiment can solve the above-mentioned problem.

[0071] Please refer to Figure 7A The diagram illustrates a flowchart of the formation control method for a resistive memory cell array according to a second embodiment of the present invention. At the start of the formation control method, i is set to 1 (step S702), and an initial formation voltage V is provided. form (Step S704). Next, to form a voltage V form A forming pulse is generated and a forming operation is performed on the resistive memory cell ci (step S706).

[0072] Next, it is determined whether the resistive memory cell ci has passed the verification action (step S708). If the resistive memory cell ci has passed the verification action and is not the last resistive memory cell, that is, i equals m is not true (step S710), i is incremented by 1 (step S712) and the process returns to step S706. Furthermore, if the resistive memory cell ci has passed the verification action and is the last resistive memory cell, that is, i equals m is true (step S710), the formation control method ends.

[0073] In step 708, if the resistive memory cell ci fails verification, the formation voltage V supplied to the resistive memory cell ci is further determined. form Has the preset number of changes been reached (step S714)? If a voltage V is formed... form If the preset number of changes has not been reached, increase the forming voltage V. form(Step S716), and return to step S706. For example, to increase the formation voltage V form At that time, the original voltage V can be formed. form Adding an incremental voltage ΔV results in a newer forming voltage V. form That is, V form =V form +ΔV. Additionally, if a voltage V is formed... form If the preset number of changes has been reached, the resistive memory cell ci is confirmed as a bad cell, and the process returns to step S712.

[0074] Similarly, the formation control method of the second embodiment of the present invention can be applied to Figure 5A The resistive memory cell array consists of m×1 resistive memory cells c1 to cm. Here, m is 1024, and the resistive memory cell array has 1024 word lines WL1 to WL1024.

[0075] Please refer to Figure 7B The graph depicts the number of formation operations performed on each resistive memory cell in the resistive memory cell array and the corresponding formation voltage. The initial formation voltage V0 is shown in the graph. form It is 2.8V, forming a voltage V form The incremental voltage ΔV is 0.2V, forming voltage V. form The preset number of changes is 1.

[0076] Depend on Figure 7B The statistical chart shows that when the formation control method begins, i equals 1, with an initial formation voltage V of 2.8V. form A forming pulse is generated to perform forming and verification operations on resistive memory cell c1. Furthermore, if resistive memory cell c1 passes the verification operation, i is incremented by 1 (i.e., i equals 2), and forming and verification operations continue on resistive memory cell c2 with a forming pulse of 2.8V pulse height. This process continues in this manner.

[0077] like Figure 7B As shown, when i equals 21, after performing the formation operation using a formation pulse with a pulse height of 2.8V, the resistive memory cell c21 fails the verification operation. This is because the formation voltage V provided for the resistive memory cell c21... form The preset number of changes (1 time) was not reached, therefore a voltage V was generated. formThe voltage is increased to 3.0V (2.8V + 0.2V). Then, a formation pulse with a pulse height of 3.0V is used to perform formation and verification operations on the resistive memory cell c21. Furthermore, after confirming that the resistive memory cell c21 passes the verification operation, i is incremented by 1 (i.e., i equals 22), and the formation and verification operations on the resistive memory cell c22 continue with a formation pulse with a pulse height of 3.0V. This process is repeated.

[0078] like Figure 7B As shown, when i equals 150, after performing the formation operation using a formation pulse with a pulse height of 3.0V, the resistive memory cell c150 fails the verification operation. This is because the formation voltage V provided for the resistive memory cell c150... form The preset number of changes (1 time) was not reached, therefore a voltage V was generated. form The voltage is increased to 3.2V (3.0V + 0.2V). Then, a formation pulse with a pulse height of 3.2V is used to perform formation and verification operations on the resistive memory cell c150. Furthermore, after confirming that the resistive memory cell c150 passes the verification operation, i is incremented by 1 (i.e., i equals 151), and the formation and verification operations on the resistive memory cell c151 continue with a formation pulse with a pulse height of 3.2V. This process is repeated.

[0079] Following the same process, when i equals 510, the resistive memory cell c510 fails the verification operation, thus generating a voltage Vf. orm The voltage is increased to 3.4V respectively. Additionally, when i equals 775, the resistive memory cell c775 fails the verification operation, thus generating voltage V. form They were each increased to 3.6V.

[0080] Finally, when the voltage V is formed form When the voltage is increased to 3.8V, the resistive memory cells c930 to c1024 are formed and verified.

[0081] Once the above process is completed, it can be confirmed that all resistive memory cells c1 to c1024 have successfully passed the verification operation, and the formation control method of the present invention is concluded.

[0082] As can be seen from the above description, the formation control method of the second embodiment can indeed reduce the number of formation operations performed by the resistive memory cell, and significantly reduce the time required for the formation control method. Furthermore, the present invention does not limit the preset number of changes in step S714. For example, the preset number of changes can be set to 2, then each resistive memory cell can perform a maximum of three formation operations.

[0083] Furthermore, the formation control methods of the first and second embodiments are illustrated using an m×1 resistive memory cell array as an example, and the formation operation is performed on a row of resistive memory cells.

[0084] In fact, this invention can also be applied to a 1×n resistive memory cell array. For example, in the second embodiment, the letter "m" in step 710 can be replaced with the letter "n". That is, when applied to a 1×n resistive memory cell array, the turn-on voltage V is received on the bit line WL1. on Then, forming pulses are sequentially provided to bit lines BL1 to BLn to form a row of resistive memory cells.

[0085] Similarly, when applying the first and second embodiments of the present invention to an m×n resistive memory cell array, the formation operation can be performed on m resistive memory cells in one row (column), then the formation operation on m resistive memory cells in the next row can be performed, and so on, until n times, at which point the formation control method for the m×n resistive memory cell array can be completed. Alternatively, the formation operation can be performed on n resistive memory cells in one row, then the formation operation on n resistive memory cells in the next row (row), and so on, until m times, at which point the formation control method for the m×n resistive memory cell array can be completed.

[0086] Both the first and second embodiments of the present invention involve changing the forming voltage V. form The pulse width w remains unchanged, even though the pulse width w can be altered. Of course, this invention can also change the pulse width w or the generated voltage V. form To change the formation of pulses.

[0087] Please refer to Figure 8A The diagram illustrates the resistive memory of this invention. The resistive memory includes a controller 810, a resistive memory cell array, a sense amplifier (SA) 860, a word line selector 820, a bit line selector 830, and a source line selector 840. Essentially, the structure of the m×n resistive memory cell array is the same as... Figure 2 The connection relationship will not be elaborated here. For example, m and n are both positive integers, m equals 1024, and n equals 2048.

[0088] Controller 810 generates word line selection signal WL sel Bit line selection signal BL sel Source line selection signal SL selThis is used to determine the selected memory cell in the resistive memory cell array. Furthermore, the controller 810 can perform formation, setting, resetting, reading, and verification operations on the selected memory cell.

[0089] The controller 810 includes a pulse width control circuit 816 and a voltage generation circuit 814. For example, during the formation of an action, the pulse width control circuit 816 generates a pulse width control signal w. ctrl The operating voltage V generated by the voltage generation circuit 814 OP That is, equal to the voltage V formed. form This causes the selected memory cell to undergo a forming operation. Similarly, during the setting operation, the voltage generation circuit 814 generates an operating voltage V. OP This is equivalent to setting the voltage, causing the selected memory cell to perform a setting action. During the reset action, the operating voltage V generated by the voltage generation circuit 814... OP This is equivalent to a reset voltage, causing the selected memory cell to perform a reset action.

[0090] Additionally, the controller 810 includes a verification control circuit 812. During verification, the verification control circuit 812 receives a storage status signal Ss to determine whether the selected storage cell has passed the verification process. Furthermore, the verification control circuit 812 can control the voltage generation circuit 814 to change the operating voltage V. OP (That is, forming voltage V) form Alternatively, the pulse width control circuit 816 can be used to change the pulse width control signal w. ctrl .

[0091] Word line selector 820 is connected to word lines WL1 to WLm. Word line selector 820 selects word lines according to word line selection signal WL. sel Turn on voltage V on Provided to one of the word lines, while the other word lines provide the shutdown signal V. off For example, the word line selector 820 selects the word line based on the word line selection signal WL. sel Turn on voltage V on The signal V is provided to word line WL1, while the other word lines WL2 to WLm provide the shutdown signal. off At this point, in the resistive memory cell array, word line WL1 is the selected word line, and the first row connected to word line WL1 is the selected row.

[0092] Bit line selector 830 is connected to bit lines BL1 to BLn. Bit line selector 830 selects bit lines according to the bit line selection signal BL1. sel Pulse width control signal (w)ctrl Operating voltage V OP This generates a forming pulse, a setting voltage, or a reset voltage, which is then supplied to the selected bit line. The bit line selector 830 includes a switching circuit 832 and multiple drivers 851-85n. Drivers 851-85n receive the operating voltage V. OP and pulse width control signal w ctrl Furthermore, the switching circuit 832 is connected between the drivers 851-85n and the bit lines BL1-BLn. The switching circuit 832 selects the bit line signal BL1 based on the bit line selection signal BL2. sel The bit line selector 830 determines one of the bit lines BL1 to BLn as the selectable bit line and one of the drivers 851 to 85n as the selected driver, and connects the selected driver to the selectable bit line. During the formation operation, the bit line selector 830 controls the pulse width according to the pulse width control signal w. ctrl With the formation voltage V form This generates a pulse and provides it to the selected positioning line. Similarly, during the setting operation, the bit line selector 830 provides a setting voltage to the selected positioning line. During the reset operation, the bit line selector 830 provides a reset voltage to the selected positioning line.

[0093] Source line selector 840 is connected to source lines SL1 to SLn. Source line selector 840 determines one of the source lines SL1 to SLn as the selected source line based on the source line selection signal SLsel, and connects the selected source line to ground voltage GND (0V) during operation. In other words, the selected memory cell in the resistive memory cell array is determined by the word line selection signal WL. sel Bit line selection signal BL sel Source line selection signal SL sel That's for you to decide.

[0094] Additionally, during read or verification operations, the source line selector 840 can provide a read voltage to the selected source line. Furthermore, the switching circuit 832 in the bit line selector 830 can transfer the current on the selected source line to the sense amplifier 860. The sense amplifier 860 receives the reference current Iref and the current on the selected source line to generate a storage state signal Ss to determine the storage state of the selected memory cell.

[0095] Please refer to Figure 8B The diagram illustrates a flowchart of a resistive memory cell array formation control method according to a third embodiment of the present invention. At the start of the formation control method, an initial formation voltage V is provided. form (Step S802) and the initial pulse width w (Step S804). Next, based on the formed voltage V... formThe pulse width is generated to form a forming pulse, and a forming operation is performed on the resistive memory cells in the selected row (step S806). For example, the forming operation is performed on the resistive memory cells in the selected row that have not yet passed the verification operation.

[0096] Next, it is determined whether all resistive memory cells in the selected row have passed the verification operation (step S808). In this embodiment of the invention, the resistive memory cells in the selected row are first formed. Then, the resistive memory cells that have undergone the forming operation in this selected row continue to undergo the verification operation. That is, the resistive memory cells that underwent the forming operation in step S806 are verified. When all resistive memory cells pass the verification operation, it means that all resistive memory cells in the selected row have completed the forming operation. At this time, the next selected row can be determined (step S814), and the process returns to step S804.

[0097] When it is confirmed that there are still resistive memory cells in the selected row that have not passed the verification process, it means that there are still resistive memory cells in the selected row that have not completed the formation process. At this time, it is determined whether the pulse width w has reached the preset number of changes (step S810). If it is determined that the pulse width w has not reached the preset number of changes, the pulse width w is increased (step S812), and then the process returns to step S806. For example, if the preset number of changes for the pulse width w is two, there will be three pulse widths. For example, the initial pulse width w is 100ns, the pulse width w after the first change is 500ns, and the pulse width w after the second change is 1μs. That is to say, in forming voltage V form If nothing changes, steps S806 to S810 will be performed a maximum of three times.

[0098] Additionally, when the pulse width w has reached the preset number of changes (step S810), it is then determined that a voltage V has been formed. form Has the preset number of changes been reached (step S816)? If a voltage V is formed... form If the preset number of changes (e.g., once) has not been reached, the forming voltage V is increased. form After step S818, proceed to step S804. For example, to increase the formation voltage V form At that time, the original voltage V can be formed. form Adding an incremental voltage creates a newer forming voltage V. form That is, V form =V form +ΔV.

[0099] Furthermore, if a voltage V is formed formWhen the preset number of changes has been reached, although there are still resistive memory cells in the selected row that have failed the verification action, the selected row will no longer undergo any forming action, and the next selected row will be determined (step S814). In the above steps, before determining the next selected row (step S814), it can be further determined whether the number of resistive memory cells in the selected row that have failed the verification action is less than the threshold number. If the number of resistive memory cells that have failed the verification action is less than the threshold number, it means that the forming action of this selected row has been completed. Conversely, if the number of resistive memory cells that have failed the verification action is greater than or equal to the threshold number, it means that this selected row is a failure row.

[0100] For example, a selected row contains 2048 resistive memory cells, and the threshold number is 3. If the number of resistive memory cells in the selected row that failed the verification action is less than 3, then the resistive memory cells in the selected row can be considered to have successfully completed the formation action. If the number of resistive memory cells in the selected row that failed the verification action is 3 or more, then this selected row is considered a failed row and is discarded, and will not be used to store data in the future.

[0101] exist Figure 8B In step S814, the process of selecting the next row continues until the resistive memory cells in the last row of the resistive memory cell array have completed their forming operation. Essentially, in embodiments of the present invention, when there are still resistive memory cells in the selected row that have not passed the verification operation (step S808), after performing step S812 or S818 and returning to step S806, only the resistive memory cells in the selected row that have not yet passed the verification operation are formed. The resistive memory cells that have already passed the verification operation are inhibited from forming; that is, the resistive memory cells that have passed the verification operation will not undergo further forming operation.

[0102] As described above, this invention proposes a method for controlling the formation of resistive memory cell arrays. During the formation process of the resistive memory cell array, a verification process is used to determine the resistive memory cells, and the formation voltage V of the formation pulse is appropriately adjusted. form Alternatively, the pulse width w can be adjusted so that all resistive memory cells in the resistive memory cell array can successfully complete the forming process.

[0103] In summary, although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

[0104] [Symbol Explanation]

[0105] 100: Resistive memory cell

[0106] 102, 106: Electrodes

[0107] 104: Insulation layer

[0108] 108: Conductive wire

[0109] 200: Resistive Memory Cell Array

[0110] 810: Controller

[0111] 812: Verification of control circuit

[0112] 814: Voltage Generation Circuit

[0113] 816: Pulse Width Control Circuit

[0114] 820: Word Line Selector

[0115] 830: Bit Line Selector

[0116] 832: Switching Circuit

[0117] 840: Source Line Selector

[0118] 851~85n: Driver

[0119] 860: Sensing Amplifier

[0120] S602~S614: Procedure Flow

[0121] S702~S716: Procedure Flow

[0122] S802~S818: Procedure Flow

Claims

1. A method for controlling the formation of a resistive memory cell array, wherein the resistive memory cell array comprises m resistive memory cells, and m is a positive integer, the method comprising the following steps: Step (a) Set i to equal 1; Step (b) provides the initial formation voltage; Step (c) Generates a formation pulse with the formation voltage and performs a formation operation on the i-th resistive memory cell in the resistive memory cell array; Step (d) Perform a verification operation on the i-th resistive memory cell and determine whether the i-th resistive memory cell passes the verification operation; Step (e): When the i-th resistive memory cell fails the verification operation and the formation voltage applied to the i-th resistive memory cell has not reached the predetermined number of changes, the formation voltage is increased, and then step (c) is executed. Step (f): When the i-th resistive memory cell fails the verification operation and the formation voltage applied to the i-th resistive memory cell reaches the predetermined number of changes, i is incremented by 1, and then step (c) is executed. Step (g): When the i-th resistive memory cell passes the verification operation and i is not equal to m, increment i by 1 and then execute step (c). as well as Step (h): When the i-th resistive memory cell passes the verification action and i equals m, the formation control method is completed.

2. The formation control method as claimed in claim 1, wherein the formation pulse has a pulse width and a pulse height, and the pulse height is equal to the formation voltage.

3. The formation control method as described in claim 1, wherein the resistive memory cell array is an m×1 resistive memory cell array, and the i-th resistive memory cell comprises: A resistive element, the first end of which is connected to a bit line; as well as The selection transistor has a first drain / source terminal connected to the second terminal of the resistive element, a second drain / source terminal connected to the source line, and a gate terminal connected to the i-th word line.

4. The formation control method as claimed in claim 3, wherein when the formation operation is performed on the i-th resistive memory cell, an enable voltage is provided to the i-th word line, a formation pulse is provided to the bit line, and a ground voltage is provided to the source line.

5. The formation control method as described in claim 4, wherein when performing the verification operation on the i-th resistive memory cell, the turn-on voltage is provided to the i-th word line, the read voltage is provided to the i-th resistive memory cell, and the i-th resistive memory cell is determined to pass the verification operation based on the read current generated by the i-th resistive memory cell.

6. The formation control method as claimed in claim 5, wherein when the read current is greater than a reference current, it is determined that the i-th resistive memory cell has passed the verification operation; and when the read current is less than the reference current, it is determined that the i-th resistive memory cell has failed the verification operation.

7. The formation control method as claimed in claim 1, wherein in step (f), the i-th resistive memory cell is confirmed to be a damaged memory cell.

8. The formation control method as claimed in claim 1, wherein in step (e), when the formation voltage is increased, an incremental voltage is added to the formation voltage to become the updated formation voltage.

9. A method for controlling the formation of a resistive memory cell array, the method comprising the following steps: Step (a) provides the initial formation voltage; Step (b) provides the initial pulse width; Step (c) Generate a formation pulse based on the formation voltage and the pulse width, and perform a formation operation on multiple resistive memory cells in the selected row; Step (d) Determine whether all the resistive memory cells in the selected row have passed the verification action; Step (e) When all the resistive memory cells in the selected row have passed the verification action, determine the next selected row and execute step (b); Step (f): When not all the resistive memory cells in the selected row pass the verification action and the pulse width has not reached the first predetermined number of changes, increase the pulse width and then execute step (c). Step (g): When not all resistive memory cells in the selected row pass the verification operation, the pulse width reaches the first predetermined number of changes, and the formation voltage does not reach the second predetermined number of changes, the formation voltage is increased, and then step (b) is executed; and Step (h): When not all the resistive memory cells in the selected row pass the verification action, the pulse width reaches the first predetermined number of changes, and the formation voltage reaches the second predetermined number of changes, the next selected row is determined, and step (b) is executed.

10. The formation control method of claim 9, wherein step (c) further comprises the following steps: generating the formation pulse according to the formation voltage and the pulse width, performing the formation operation on the resistive memory cells in the selected row, and the resistive memory cells have not yet passed the verification operation.

11. The formation control method of claim 9, wherein the formation pulse has the pulse width and a pulse height, and the pulse height is equal to the formation voltage.

12. The formation control method of claim 9, wherein the resistive memory cell array is an m×n resistive memory cell array, and the selected row includes n resistive memory cells, wherein the first resistive memory cell among the n resistive memory cells includes: A resistive element, the first end of which is connected to the first bit line; as well as The selection transistor has a first drain / source terminal connected to the second terminal of the resistive element, a second drain / source terminal connected to the first source line, and a gate terminal connected to the first word line.

13. The formation control method of claim 12, wherein when the formation operation is performed on the first resistive memory cell, an enable voltage is provided to the first word line, a formation pulse is provided to the first bit line, and a ground voltage is provided to the first source line.

14. The formation control method as claimed in claim 13, wherein when performing the verification operation on the first resistive memory cell, the turn-on voltage is provided to the first word line, the read voltage is provided to the first resistive memory cell, and the first resistive memory cell is determined to pass the verification operation based on the read current generated by the first resistive memory cell.

15. The formation control method of claim 14, wherein when the read current is greater than the reference current, it is determined that the first resistive memory cell has passed the verification operation; and when the read current is less than the reference current, it is determined that the first resistive memory cell has failed the verification operation.

16. The formation control method of claim 12, wherein the step of determining the next selected row continues until the n resistive memory cells in the m-th row of the resistive memory cell array have completed their formation operations, at which point the formation control method ends.

17. The formation control method of claim 12, wherein step (h) further comprises the following steps: Step (h1): When the number of resistive memory cells that failed the verification action in the selected row is less than the threshold number, determine the next selected row and execute step (b); and Step (h2): When the number of resistive memory cells that have failed the verification action in the selected row is greater than or equal to the threshold number, the selected row is a failed row, the next selected row is determined, and step (b) is executed.

18. The formation control method of claim 9, wherein in step (g), when the formation voltage is increased, an incremental voltage is added to the formation voltage to obtain the updated formation voltage.

19. The formation control method of claim 9, wherein when entering step (c) after performing step (f) or step (g), the formation operation is performed on the resistive memory cells in the selected row that have not yet passed the verification operation, and the formation operation is not performed on the resistive memory cells in the selected row that have passed the verification operation.

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