Memory operation completion flag

Abstract

This application relates to a memory operation completion flag. A completion flag of a memory device can indicate whether at least one access operation has completed at the memory device. A controller can poll the completion flag, and if the completion flag indicates that at least one access operation has completed at the memory device, the controller can poll a status register of the memory device to obtain additional information about one or more completed access operations at the memory device.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 400,942, titled “COMPLETION FLAG FOR MEMORY OPERATIONS,” filed August 12, 2021, by Cariello et al., assigned to the assignee hereof and expressly incorporated by reference herein in its entirety. TECHNICAL FIELD

[0003] The following relates generally to one or more systems of memory, and more specifically to completion flags for memory operations. BACKGROUND

[0004] Memory devices are widely used in various electronic devices to store information, such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory devices into various states. For example, binary memory cells can be programmed into one of two supported states, typically corresponding to a logic 1 or logic 0. In some examples, individual memory cells can support more than two possible states, any of which can be stored by the memory cell. To access information stored by a memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to a corresponding state.

[0005] There are a variety of types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3D cross point memory, or NOT-OR (NOR) and NOT-AND (NAND) memory devices, among others. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless they are periodically refreshed by an external power source. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long period of time, even without an external power source. SUMMARY

[0006] A device is described. The device can include a memory die comprising a plurality of planes, a register associated with the memory die and configured to store a plurality of status bits, each status bit corresponding to a respective one of the plurality of planes, and a controller for the memory die, the controller configured to cause the device to set a first status bit of the register corresponding to a first plane of the plurality of planes based at least in part on completion of an access operation at the first plane, set a flag associated with the memory die indicating completion of at least one access operation at the memory die based at least in part on the completion of the access operation at the first plane, receive a command from a second controller to output data associated with the first plane based at least in part on the flag indicating the completion of at least one access operation being set, and output data corresponding to the access operation at the first plane to the second controller based at least in part on the command.

[0007] A device is described. The device can include a controller configured to couple with a memory die of a memory system, wherein the controller is configured to cause the device to identify that a flag associated with the memory die indicates completion of at least one access operation at the memory die, the memory die comprising a plurality of planes, poll a register associated with the memory die and configured to store a plurality of status bits based at least in part on the flag indicating the completion of at least one access operation at the memory die, each status bit corresponding to a respective one of the plurality of planes, identify completion of an access operation at a first plane of the plurality of planes based at least in part on polling the register based at least in part on a first status bit of the register corresponding to the first plane indicating the completion of the access operation at the first plane, transmit a command to the memory die to output data associated with the first plane based at least in part on identifying the completion of the access operation at the first plane, and receive data corresponding to the access operation at the first plane from the memory die based at least in part on the command.

[0008] A non-transitory computer-readable medium storing code is described. The code can include instructions executable by a processor to set a first status bit of a register based at least in part on completion of an access operation at a first plane of a plurality of planes of a memory die, wherein the register is associated with the memory die and is configured to store a plurality of status bits, each status bit corresponding to a respective one of the plurality of planes, and wherein the first status bit corresponds to the first plane, set a flag associated with the memory die indicating completion of at least one access operation at the memory die based at least in part on the completion of the access operation at the first plane, receive a command from a controller to output data associated with the first plane based at least in part on the flag indicating the completion of at least one access operation being set, and output data corresponding to the access operation at the first plane to the controller based at least in part on the command. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 An example of a system to support memory operation completion flags is shown in accordance with examples disclosed herein.

[0010] Figure 2 An example of a timing diagram to support memory operation completion flags is shown in accordance with examples disclosed herein.

[0011] Figure 3 An example of a system to support memory operation completion flags is shown in accordance with examples disclosed herein.

[0012] Figure 4 A block diagram of a memory device to support memory operation completion flags is shown in accordance with examples disclosed herein.

[0013] Figure 5 A block diagram of a memory system controller to support memory operation completion flags is shown in accordance with examples disclosed herein.

[0014] Figure 6 and 7 A flow diagram showing one or more methods to support memory operation completion flags is shown in accordance with examples disclosed herein. DETAILED DESCRIPTION

[0015] A memory system can include a controller and a plurality of memory devices. For example, a memory system can include a plurality of NAND devices, where each NAND device can include a memory die with a set of planes. The memory system can transmit access commands (e.g., read commands, program commands, erase commands) to the memory devices (i.e., one or more of the memory devices can each receive an access command). For example, the memory system can transmit an access command to a memory device (e.g., including a memory die) indicating an access operation to be performed at one plane in the memory device. In some examples, the planes of a memory device can be independent and can perform operations in parallel (e.g., asynchronously).

[0016] In some examples, the controller can perform a round-robin polling of a status register of each active memory device (e.g., each memory device that has received but has not yet acknowledged completion of performing one or more access commands) to determine whether a given memory device has completed an access operation for one or more previous commands. For example, each memory device can include a status register configured to store a number of bits, where each bit is associated with one plane in the memory device and indicates whether an access operation has completed at the associated plane. However, polling the status register can involve excessive signaling overhead (e.g., increased latency and power consumption), for example due to each status register including a number of bits to be transferred in response to each polling request. Moreover, it can not be possible to poll multiple status registers (e.g., of multiple memory dies) simultaneously, for example if the memory dies are all coupled with a host controller via a common bus that can not be wide enough to carry the contents of multiple status registers simultaneously.

[0017] Described herein are systems, techniques, and devices for polling a completion flag associated with a memory device (e.g., a NAND device and associated memory die) and, in some cases, for polling (e.g., simultaneously) multiple completion flags associated with multiple respective memory devices. Such completion flags can reduce signaling overhead and increase possible parallelism of the associated signaling (e.g., if multiple memory devices are coupled with a controller via a common bus), among other benefits to those of ordinary skill in the art. For example, a single completion flag described herein can be a single bit.

[0018] A completion flag of a memory die can indicate whether an access operation at any plane of the corresponding memory die has completed. For example, a memory system can issue an access command corresponding to one or more planes of a memory die. In response to one of the one or more planes of the memory die completing an access operation, the memory device can set a corresponding bit of a status register such that the status register bits can each indicate whether an access operation at the corresponding plane has completed (e.g., whether the corresponding plane is in a ready state). Additionally, the memory device can set a completion flag based on an access operation at any of the one or more planes of the memory die having completed (e.g., based on any of the one or more planes being in a ready state) (e.g., the memory device can set the completion flag to a ‘1’). Thus, the completion flag can indicate whether at least one access operation at the memory die has completed (e.g., whether any bits of a status register of the memory die are set).

[0019] A memory system can poll a completion flag of a memory die (e.g., concurrently with polling a completion flag of one or more other memory dies coupled with a shared bus), and in response to detecting that the completion flag is set (e.g., the completion flag indicates that the associated memory die has completed at least one access operation), the memory system can then read a status register associated with the memory die. In response to the memory system polling the flag, the memory device can reset the flag (e.g., set the completion flag to a ‘0’). Additionally or alternatively, in response to the memory system reading the status register, the memory device can reset the flag and the status register. Setting a flag or bit as used herein can refer to configuring the flag or bit to have a first logical value, and resetting the flag or bit can refer to configuring the flag to have a second logical value different from (e.g., opposite of) the first logical value. For example, setting a flag or bit can have a logical value of ‘1’, while resetting the flag or bit can have a logical value of ‘0’, or setting a flag or bit can have a logical value of ‘0’, while resetting the flag or bit can have a logical value of ‘1’.

[0020] Using the completion flag described herein can reduce signaling overhead (e.g., reduce latency and power consumption) as compared to polling a status register. Additionally, using the completion flag described herein can support an increase in signaling concurrency (e.g., a memory system can concurrently poll or receive completion flags of multiple memory dies even if the multiple dies share a common bus). Although particular examples can be described in the context of a NAND memory device, it should be understood that aspects of the teachings herein can be applied in the context of any memory type.

[0021] Features of the present disclosure are first described in the context of systems, devices, and circuitry that refer to Figure 1 Features of the present disclosure are first described in the context of systems, devices, and circuitry that refer to Figures 2-3timing diagrams and in the context of systems. These and other features of the present disclosure are further described with reference to Figures 4-7 devices and flow diagrams related to memory operation completion markers are illustrated and described in the context of the devices and flow diagrams.

[0022] Figure 1 An example of a system 100 that supports memory operation completion markers is illustrated in accordance with examples disclosed herein. The system 100 includes a host system 105 coupled with a memory system 110.

[0023] The memory system 110 can be or include any device or collection of devices that includes at least one memory array. For example, the memory system 110 can be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-Line Memory Module (DIMM), a Small Outline DIMM (SO-DIMM), or a Non-Volatile DIMM (NVDIMM), among other possibilities.

[0024] The system 100 can be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other conveyance), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes memory and a processing device.

[0025] The system 100 can include a host system 105 that can be coupled with the memory system 110. In some examples, this coupling can include interfacing with a host system controller 106, which can be an example of a controller or control component configured to cause the host system 105 to perform various operations in accordance with examples as described herein. The host system 105 can include one or more devices, and in some cases, can include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 can include an application configured to communicate with the memory system 110 or a device therein. The processor chipset can include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., a NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 can use the memory system 110, for example, to write data to and read data from the memory system 110. Although in some examples the host system 105 can be coupled with the memory system 110 via a bus, in other examples, the host system 105 can be coupled with the memory system 110 via a network, such as a local area network (LAN), a wide area network (WAN), the Internet, or any other network.Figure 1 One memory system 110 is shown in the example of FIG. 1, but the host system 105 can be coupled with any number of memory systems 110.

[0026] The host system 105 can be coupled with the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 can be configured to communicate (e.g., exchange or otherwise transfer control, address, data, and other signals between the memory system 110 and the host system 105) via the physical host interface using an associated protocol. Examples of physical host interfaces can include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DDR- supported DIMM socket interface), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces can be included in or otherwise supported between a host system controller 106 of the host system 105 and a memory system controller 115 of the memory system 110. In some examples, the host system 105 can be coupled with the memory system 110 via a respective physical host interface for each memory device 130 included in the memory system 110 or via a respective physical host interface for each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 can be coupled with the memory system controller 115).

[0027] The memory system 110 can include the memory system controller 115 and one or more memory devices 130. The memory devices 130 can include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 Two memory devices 130-a and 130-b are shown in the example of FIG. 1, but the memory system 110 can include any number of memory devices 130. Moreover, if the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 can include the same or different types of memory cells.

[0028] The memory system controller 115 can be coupled with and in communication with the host system 105 (e.g., via a physical host interface) and can be an example of a controller or control component configured to cause the memory system 110 to perform various operations in accordance with examples as described herein. The memory system controller 115 can also be coupled with and in communication with the memory devices 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory devices 130 - among other such operations - which can be collectively referred to as access operations. In some cases, the memory system controller 115 can be coupled with the memory devices 130 via a bus, and the memory system controller 115 and the memory devices 130 can communicate via the bus using a protocol (e.g., an ONFI protocol). In some cases, the memory system controller 115 can be coupled with multiple memory devices 130 via the same bus, which can be referred to as a shared bus or a common bus.

[0029] In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at memory arrays within the one or more memory devices 130). For example, the memory system controller 115 can receive commands or operations from the host system 105 and can convert the commands or operations into instructions or appropriate commands to effectuate desired accesses of the memory devices 130. In some cases, the memory system controller 115 can exchange data with the host system 105 and the one or more memory devices 130 (e.g., in response to or otherwise associated with commands from the host system 105). For example, the memory system controller 115 can convert responses (e.g., data packets or other signals) associated with the memory devices 130 into corresponding signals for the host system 105.

[0030] The memory system controller 115 can be configured for other operations associated with the memory devices 130. For example, the memory system controller 115 can perform or manage operations such as wear leveling operations, garbage collection operations, error detection operations or error correction operations, among other error control operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translations between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory devices 130.

[0031] The memory system controller 115 can include hardware such as one or more integrated circuits or discrete components, a buffer memory, or a combination thereof. The hardware can include circuitry with specialized (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 can be or include a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0032] The memory system controller 115 can also include a local memory 120. In some cases, the local memory 120 can include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 can additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for internal storage or computation, e.g., in connection with the functions attributed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 can be used as a cache for the memory system controller 115. For example, if data is read from or written to the memory devices 130, the data can be stored in the local memory 120, and the data can be used by the host system 105 (e.g., with reduced latency relative to the memory devices 130) for subsequent retrieval or manipulation (e.g., updating) in accordance with a cache policy, within the local memory 120.

[0033] Although Figure 1 Although the example of the memory system 110 in FIG. 1 has been shown as including the memory system controller 115, in some cases the memory system 110 can not include the memory system controller 115. For example, the memory system 110 can additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135, which can be respectively internal to the memory devices 130, to perform the functions attributed herein to the memory system controller 115. Generally speaking, one or more of the functions attributed herein to the memory system controller 115 can in some cases actually be performed by the host system 105, the local controller 135, or any combination thereof. In some cases, a memory device 130 that is at least partially managed by the memory system controller 115 can be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0034] Memory devices 130 can include one or more arrays of non-volatile memory cells. For example, memory devices 130 can include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), resistive memory, ferroelectric random access memory (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programable ROM (EEPROM), or any combination thereof. Additionally or alternatively, memory devices 130 can include one or more arrays of volatile memory cells. For example, memory devices 130 can include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0035] In some examples, memory devices 130 can include (e.g., on the same die or within the same package) local controllers 135 that can perform operations on one or more memory cells of respective memory devices 130. Local controllers 135 can operate in conjunction with memory system controller 115, or can perform one or more functions attributed herein to memory system controller 115. For example, as shown in FIG. 1, memory device 130-a can include local controller 135-a, and memory device 130-b can include local controller 135-b. Figure 1

[0036] In some cases, memory devices 130 can be or include NAND devices (e.g., NAND flash devices). Memory devices 130 can be or include memory dies 160. For example, in some cases, memory devices 130 can be a package that includes one or more dies 160. In some examples, a die 160 can be a piece of electronic-grade semiconductor (e.g., a silicon die cut from a silicon wafer) that is cut from a wafer. Each die 160 can include one or more planes 165, each plane 165 can include a respective set of blocks 170, where each block 170 can include a respective set of pages 175, each page 175 can include a set of memory cells.

[0037] ​In some cases, the NAND memory devices 130 can include memory cells configured to each store one bit of information, which can be referred to as single-level cells (SLCs). Additionally or alternatively, the NAND memory devices 130 can include memory cells configured to each store multiple bits of information, which can be referred to as multi-level cells (MLCs) if configured to each store two bits of information, triple-level cells (TLCs) if configured to each store three bits of information, quad-level cells (QLCs) if configured to each store four bits of information, or more generally as multi-level memory cells. Multi-level memory cells can provide greater storage density relative to SLC memory cells, but in some cases can involve narrower read or write margins or greater complexity of supporting circuitry.

[0038] In some cases, a plane 165 can refer to a group of blocks 170, and in some cases, simultaneous operations can be performed within different planes 165. For example, simultaneous operations can be performed on memory cells within different blocks 170 so long as the different blocks 170 are in different planes 165. In some cases, individual blocks 170 can be referred to as physical blocks, and a virtual block 180 can refer to a group of blocks 170 within which simultaneous operations can be performed. For example, simultaneous operations can be performed on blocks 170-a, 170-b, 170-c, and 170-d located in planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d can collectively be referred to as a virtual block 180. In some cases, a virtual block can include blocks 170 from different memory devices 130 (e.g., include blocks in one or more planes of memory device 130-a and memory device 130-b). In some cases, blocks 170 within a virtual block can have the same block address within their respective planes 165 (e.g., block 170-a can be “block 0” of plane 165-a, block 170-b can be “block 0” of plane 165-b, and so on). In some cases, performing simultaneous operations in different planes 165 can have one or more restrictions, such as that the simultaneous operations are performed on memory cells within different pages 175 that have the same page address within the respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry being shared across planes 165).

[0039] In some cases, a block 170 can include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 can share a common word line (e.g., be coupled with) and memory cells in the same string can share a common digit line (which can be alternatively referred to as a bit line) (e.g., be coupled with).

[0040] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently programmed or read (e.g., programmed or read simultaneously as part of a single programming or reading operation), and block 170 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently erased (e.g., erased simultaneously as part of a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some cases, used page 175 may not be updated until the entire block 170 containing page 175 is erased.

[0041] In some cases, the memory system controller 115 or the local controller 135 may perform operations on the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, cleanup, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in block 170 to have invalid data in order to erase and reuse block 170, an algorithm called “garbage collection” may be invoked, causing block 170 to be erased and freed up as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting block 170 containing valid and invalid data, selecting pages 175 in the block containing valid data, copying the valid data from the selected pages 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected pages 175 as invalid, and erasing the selected block 170. Therefore, the number of erased blocks 170 can be increased, so that more blocks 170 can be used to store subsequent data (e.g., data subsequently received from the host system 105).

[0042] System 100 can include any number of non-transitory computer-readable media that support the use of memory operation completion tags. For example, host system 105, memory system controller 115, or memory devices 130 can include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) for performing the functions attributed herein to host system 105, memory system controller 115, or memory devices 130. For example, such instructions, if executed by host system 105 (e.g., host system controller 106), memory system controller 115, or memory devices 130 (e.g., local controller 135), can cause host system 105, memory system controller 115, or memory devices 130 to perform one or more of the associated functions described herein.

[0043] In some cases, memory system 110 can provide a managed memory system using memory system controller 115, which can include, for example, one or more memory arrays and associated circuitry in combination with a local (e.g., on-die or in-package) controller (e.g., local controller 135).

[0044] In some examples, memory system controller 115 can perform polling operations on memory devices 130 to determine the status of operations performed by each memory device 130. In some cases, memory system controller 115 can perform polling operations in a round-robin system. For example, memory system controller 115 can first request the status of a first operation being performed at memory device 130-a, then request the status of a second operation being performed at memory device 130-b. In some cases, the second operation can be performed before the first operation. In such examples, memory device 130-b can idly wait for memory system controller 115 to request the status of the second operation. The idle wait time can increase the power consumption and latency of the system.

[0045] As described herein, each of the memory devices 130 can indicate, via a flag (e.g., a completion flag), whether at least one of the planes 165 has completed an access operation. That is, each memory device 130 can indicate to the memory system controller 115 (e.g., using a data line over a data bus that couples the memory device 130 and the memory system controller 115) whether the memory device 130 has completed an access operation for at least one previous command. For example, in response to a plane 165 of a memory device 130 completing an access operation, a local controller 135 associated with the memory device 130 can set a flag associated with the memory device 130 (e.g., can set a bit of a data line associated with the memory device 130 from a busy state to a service ready state). Additionally, the local controller 135 can set a status register 145 at the memory device 130. For example, the status register 145 can include a bit associated with each plane 165 in a die 160. The local controller 135 can set each bit of the status register 145 that corresponds to a plane 165 associated with a completed access operation.

[0046] In some cases, memory system controller 115 can perform a polling operation (e.g., a simultaneous polling operation) on memory devices 130. For example, memory system controller 115 can poll a flag associated with each memory device 130 (e.g., based on a single polling request sent by the memory system controller and received by all memory devices via a shared bus, or via multiple simultaneous polling requests to memory devices 130). In a case where memory system controller 115 determines that a memory device 130 has at least one completed access operation (e.g., based on the flag associated with that memory device 130 being set), memory system controller 115 can read a status register 145 associated with that memory device 130. Using status bits read from status register 145, memory system controller 115 can then identify each of the one or more planes 165 of the memory device 130 associated with the respective completed access operation. In response to identifying the one or more planes 165 of the memory device 130 associated with the completed access operation, memory system controller 115 can service the identified planes 165. In some cases, polling each of memory devices 130 simultaneously by memory system controller 115 can reduce idle time, and reduce latency and power consumption of system 100, as compared to memory system controller 115 polling each of memory devices 130 sequentially. Although particular examples are described herein in the context of memory system controller 115 interacting with memory devices 130 (e.g., to poll completion flags and status registers and receive related information, and to exchange related commands and data), it should be understood that host system controller 106 can alternatively interact with memory devices 130 to implement functionality attributed herein to memory system controller 115 in other examples (e.g., memory system controller 115 can not be present in some examples).

[0047] Figure 2 An example of a timing diagram 200 that supports memory operation completion flags is shown in accordance with examples disclosed herein. Timing diagram 200 can be performed by processing logic, which can include hardware (e.g., processing system, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuitry, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some examples, timing diagram 200 can be performed by a system described with reference to Figure 1 For example, the timing diagram can be performed by memory system controller 215 (e.g., which can be an example of memory system controller 115 or host system controller 106 described with reference to Figure 1 For example, the timing diagram can be performed by memory system controller 215 (e.g., which can be an example of memory system controller 115 or host system controller 106 described with reference to Figure 1The described memory device 130 is an example of execution. In some instances, the memory system controller 215 may execute a set of instructions to control the functional elements of the memory system to perform the functions described below. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Thus, the illustrated examples are used as examples, and the processes shown may be executed in different orders, and some processes may be executed in parallel. Figure 2 It can be shown that system 100 transmits signals and commands between memory system controller 115 and memory device 130 while performing simultaneous polling operations.

[0048] Memory device 230 may include memory die 260 having a set of planes 265, including at least plane 265-a and plane 265-b. Memory device 230 may include register 245 (e.g., a full-plane status register) configured to store a set of status bits, each of which corresponds to one of the planes 265. Register 245 may indicate which plane 265 has completed an access operation and is therefore ready for service (e.g., ready to transmit or receive data associated with the access operation). For example, the status bit of plane 265 (e.g., first plane 265-a) may be set to a first value in response to memory device 230 receiving a command for an access operation at first plane 265-a to indicate that first plane 265-a is busy. After the access operation is completed, the status bit of first plane 265-a may be set (e.g., reset) to a second value indicating that the access operation has been completed and therefore first plane 265-a is ready for another operation. Memory device 230 may additionally include a controller for memory device 230 (e.g., reference 1). Figure 1 The local controller 135 described herein can perform one or more of the operations shown in timing diagram 200 that are performed at memory device 230.

[0049] The memory system controller 215 may be coupled to the memory device 230, and in some cases, may be additionally coupled to one or more other memory devices 230 (e.g., via a shared bus). The memory system controller 215 may transmit and receive communications (e.g., data, commands) to and from the memory device 230, for example, via a bus.

[0050] Memory device 230 can maintain a flag 225 (e.g., a completion flag) (e.g., store and manage its value), where flag 225 can indicate whether any of planes 265 of memory device 230 are associated with a completed access operation. In some cases, flag 225 can include a single bit associated with memory device 230, which can be set to indicate a state of memory device 230. For example, in response to memory device 230 completing an access operation at any of planes 265, memory device 230 can set flag 225 (e.g., to a first value, such as a logic 1, a logic 0, a high active, or a low active) to indicate that at least one plane 265 is associated with a completed access operation. In some cases, flag 225 can already be set (e.g., to the first value) after an access operation at a plane 265 is completed (e.g., based on another plane 265 of memory device 230 being associated with a completed access operation). In these cases, memory device 230 can ensure that flag 225 remains set (e.g., memory device 230 can check whether flag 225 is already set, and if flag 225 is not already set, memory device 230 can set flag 225). In response to memory system controller 215 polling flag 225, memory device 230 can reset flag 225 (e.g., set flag 225 to a second value different from the first value). Additionally, memory device 230 can reset flag 225 in response to memory system controller 215 polling register 245.

[0051] Memory system controller 215 can poll flag 225 (e.g., periodically, opportunistically, or in response to a command) to identify whether the flag indicates completion of at least one access operation at memory device 230. Based on flag 225 indicating that at least one access operation has completed, memory system controller 215 can poll register 245 to identify which plane 265 is associated with the completed access operation. Subsequently, memory system controller 215 can transmit a command to any of planes 265 associated with the completed access operation. In response to receiving the command from memory system controller 215, memory device 230 can transmit data corresponding to the access operation to memory system controller 215 (e.g., via a direct memory access operation). Additionally or alternatively, in some cases, the command transmitted by memory system controller 215 after identifying that a plane 265 has completed an access operation of a previous command can be a write command, as the plane 265 can be ready to execute a write command based on having completed an access operation of a previous command, and in response to receiving the command from memory system controller 215, memory device 230 can write data corresponding to the access operation to the plane 265.

[0052] The timing diagram 200 can illustrate an example of a situation that includes the memory system controller 215 polling the tag 225 associated with the memory device 230 to identify any completed access operations at the memory device 230, which can be used to illustrate various aspects of the teachings herein. For example, at 205, a command to perform an access operation at a first plane 265-a can be received. For example, the memory device 230 can receive a command from the memory system controller 215 to perform an access operation associated with the first plane 265-a. The access operation can be an example of a snapshot read operation.

[0053] At 210, a first status bit of the register 245 corresponding to the first plane 265-a can be set to a first value indicating that the first plane 265-a is busy. For example, the memory device 230 can set the first status bit of the register 245 based on receiving the command associated with the plane 265-a at 205.

[0054] At 220, a command to perform an access operation at a second plane 265-b can be received. For example, the memory device 230 can receive a command from the memory system controller 215 to perform an access operation associated with the first plane 265-a. The access operation can be an example of a snapshot read operation.

[0055] At 235, a second status bit of the register 245 corresponding to the second plane 265-b can be set to the first value indicating that the second plane 265-b is busy. For example, the memory device 230 can set the first status bit based on receiving the command associated with the plane 265-b at 220.

[0056] At 240, the flag 225 can be polled (e.g., based on the memory system controller 215 transmitting the command at 205 and 220). For example, the memory system controller 215 can transmit a poll request (e.g., a read status request) to the memory device 230 for an indication of the flag status (i.e., whether the flag is set to the first value or the second value). Subsequently, based on receiving the poll request from the memory system controller 215, the memory device 230 can output an indication to the memory system controller 215 that the flag 225 is not set (e.g., has been reset). In some cases, the memory system controller 215 can poll more than one memory device 230 in parallel. For example, more than one memory device 230 can be coupled with the same bus, where the bus can thereby couple the memory system controller 215 with each of the memory devices 230. Here, the memory system controller 215 can perform polling of more than one memory device 230 at the same time (e.g., the poll request issued by the memory system controller 215 can be received by multiple memory devices 230 via the common bus). Moreover, different memory devices 230 can output their respective indications of the status of their respective flags 225 at the same time (e.g., each memory device 230 can output the respective flag 225 via one or more respective lines of the bus, e.g., I / O pins or lines, such that different memory devices 230 indicate their respective flags 225 via different lines of the bus during at least partially overlapping time periods).

[0057] At 250, the operation can be performed at the plane 265-a. For example, the memory device 230 can perform the access operation indicated by the command received from the memory system controller 215 at 205.

[0058] At 255, a first status bit of the register 245 (e.g., corresponding to the plane 265-a) can be set by the memory device 230. For example, the memory device 230 can set the first bit to the first value, indicating that the access command at the first plane 265-a has completed.

[0059] At 270, the flag 225 can be set (e.g., to the first value) to indicate that at least one of the planes 265 has completed an access operation. That is, the memory device 230 can set the flag based on the memory device performing the operation at the plane 265-a.

[0060] At 275, the flag 225 can be polled by the memory system controller 215. For example, the memory system controller 215 can transmit a poll request for the flag 225 to the memory device 230. In response, the memory device 230 can output an indication to the memory system controller 215 that the flag 225 is set (e.g., indicating that at least one access operation at the memory device 230 has completed). If the flag 225 has been set to the first value (e.g., at 255), the indication can be output to the memory system controller 215, for example, by the memory device 230, where the indication indicates that the flag 225 has been set to the first value.

[0061] At 280, the flag 225 can be reset to a value indicating that no access operation has completed at the memory device 230 (e.g., in response to the memory system controller 215 polling the flag 225 at 275).

[0062] At 282, an operation can be performed at the plane 265-b. For example, the memory device 230 can perform an access operation indicated by the command received from the memory system controller 215 at 220.

[0063] At 284, a second status bit of the register 245 (e.g., corresponding to the plane 265-b) can be set by the memory device 230. For example, the memory device 230 can set the second bit to a second value indicating that an access command at the second plane 265-b has completed.

[0064] At 286, the flag 225 can be set (e.g., to the first value) indicating that at least one access operation in the plane 265 has completed. That is, the memory device 230 can set the flag based on the memory device performing the operation at the plane 265-b. In the example of the timing diagram 200, the flag 225 can be reset (e.g., based on the reset at 280) prior to setting the flag 225 at 286. In some other cases, the flag 225 can be set prior to 286 (e.g., in the case that the memory system controller 215 polls the flag 225 at 275 after 286). Here, the memory device 230 can ensure that the flag 225 is set at 286 (e.g., rather than resetting the flag 225).

[0065] At 288, the register 245 can be polled by the memory system controller 215. That is, the memory system controller 215 can poll the register 245 in response to determining that the flag 225 has been set at 275. For example, the memory system controller 215 can transmit a poll request to the memory device 230 to determine which plane 265 has completed an access operation. Subsequently, the memory device 230 can output a set of indications (e.g., the status bits of the register 245) to the memory system controller 215 indicating which planes 265 have completed an access operation.

[0066] At 290, the flag 225 can be reset (e.g., set to a second value). For example, the memory device 230 can reset the flag 225 in response to the memory system controller 215 polling the register 245. Additionally, the memory device 230 can optionally reset the register 245 at 290 (e.g., in response to the memory system controller 215 polling the register 245). For example, the memory device 230 can reset the flag 225 in response to having notified the memory system controller 215 that the operation at 282 is complete.

[0067] At 292, a command to output data associated with the first plane 265-a can be transmitted by the memory system controller 215 to the memory device 230. That is, the memory system controller 215 can issue a command to the memory device 230 to output data associated with the first plane 265-a based on the register 245 including a bit indicating that the plane 265-a is associated with a completed access operation. At 294, the data associated with the plane 265-a can be output by the memory device 230 to the memory system controller 215 (e.g., in response to the memory system controller 215 transmitting the command at 292). In some cases, the operations at 292 and 294 can correspond to a direct memory access operation.

[0068] At 296, a command to output data associated with the first plane 265-b can be transmitted by the memory system controller 215 to the memory device 230. That is, the memory system controller 215 can issue a command to the memory device 230 to output data associated with the first plane 265-b based on the register 245 including a bit indicating that the plane 265-b is associated with a completed access operation. At 298, the data associated with the plane 265-b can be output by the memory device 230 to the memory system controller 215 (e.g., in response to the memory system controller 215 transmitting the command at 296). In some cases, the operations at 296 and 298 can correspond to a direct memory access operation.

[0069] Figure 3 An example of a system 300 that supports memory operation completion flags in accordance with examples as disclosed herein is shown. The system 300 can be an example of the memory system 110 described with reference to Figure 1 The system 300 can include a memory system controller 315, which can be an example of the memory system controller 115 or host system controller 106 described with reference to Figure 1 The system 300 can include a memory system controller 315, which can be an example of the memory system controller 115 or host system controller 106 described with reference to Figure 2 The system 300 can include a memory system controller 315, which can be an example of the memory system controller 115 or host system controller 106 described with reference to Figure 1 The system 300 can include a memory system controller 315, which can be an example of the memory system controller 115 or host system controller 106 described with reference toFigure 2 An example of a memory device 230 is described. Each of the memory devices 330 can include a local controller 335 (e.g., which can be an example of a local controller 135 described with reference to Figure 1 An example of a local controller 135), registers 345 (e.g., which can be an example of a register 245 described with reference to Figure 2 An example of a register 245), and a memory die 360 including a set of planes 365 (e.g., which can be an example of a memory die 260, a plane 165, and a plane 265 described with reference to Figure 1 and 2 An example of a memory die 260, a plane 165, and a plane 265).

[0070] The memory system controller 315 can be coupled with the memory devices 330 via a bus 310. The bus 310 can be an example of a shared bus. In some cases, the memory system controller 315 and the memory devices 330 can use an ONFI protocol via the bus 310, and the bus 310 can be referred to as an ONFI bus, although other protocols can be used instead. For example, there can be eight (8) memory devices 330 coupled with the memory system controller 315. In other examples, there can be more or less than eight (8) memory devices 330 coupled with the memory system controller 315. It should be noted that the number of memory devices 330 in the system 300 is not limiting to the claims. The system 300 can support operations according to the timing diagram 200 described with reference to FIG. 2.

[0071] As described with reference to Figure 1 and 2 The memory system controller 315 can be configured to transmit commands 320 (e.g., from a host system) to the memory devices 330. In some examples, the memory system controller 315 can be configured to transmit the commands 320 to the memory devices 330 via the bus 310. The bus 310 can be configured to transmit signals, the commands 320, the data 305, and the tags 325 between the memory system controller 315 and the memory devices 330. In some examples, the bus 310 can be configured to have a number of bits, the number of bits equal to a number of data input / output (DQ) pins of the memory system controller 315. For example, if the memory system controller 315 has eight (8) DQ pins, then the bus 310 can be an eight (8) bit bus 310. In some examples, the bus 310 can also include a number of lines, the number of lines equal to the number of bits (e.g., each line of the bus 310 can be configured to transmit a bit of information). In some examples, the bus 310 can also transmit an indication of the tag 325 of each memory device 330 that is performing an operation concurrently. In some cases, the bus 310 can be an example of an ONFI bus.

[0072] The memory system controller 315 can be configured to transmit commands 320 that initiate access operations at the memory devices 330. In some cases, the memory system controller 315 can transmit commands 320 that initiate simultaneous operations (e.g., operations that can not be initiated at the same time but are performed in parallel at multiple memory devices 330). For example, the memory system controller 315 can transmit a command 320 to the memory device 330-a that initiates a first operation. Additionally, the memory system controller 315 can then transmit a second command 320 to the memory device 330-b that initiates a second operation. In such an example, the first operation and the second operation can be performed by the memory device 330-a and the memory device 330-b simultaneously (e.g., in parallel).

[0073] The memory devices 330 can be configured to indicate, via the flags 325, whether the memory devices 330 have completed any access operations (e.g., performed in response to receiving a command 320 from the memory system controller 315). The flags 325 can be a single bit that indicates whether the associated memory device 330 has serviced a ready (i.e., whether at least one plane 365 of the memory die 360 has completed at least one access operation). In some cases, more than one memory device 330 can indicate a flag associated with the memory device 330 to the memory system controller 315 (e.g., via the bus 310).

[0074] Additionally, each memory device 330 can include a register 345 that has a number of bits (e.g., status bits) that each correspond to one plane 365 in the memory device 330. For example, the memory device 330-a can include a register 345 that includes at least a first bit associated with the plane 365-a and a second bit associated with the plane 365-b. Each bit of the register 345 can indicate whether the corresponding plane 365 has completed an access operation. For example, the first bit of the register 345 can indicate whether the memory device 330-a has completed an access operation at the plane 365-a and the second bit of the register 345 can indicate whether the memory device 330-a has completed an access operation at the plane 365-b.

[0075] The memory system controller 315 can poll the flags 325 associated with each memory device 330. For example, the memory system controller 315 can poll the flags 325 of each memory device 330 associated with a pending access operation. In some examples, the memory system controller 315 can poll the flags 325 associated with more than one memory device 330 simultaneously. For example, in some cases, the memory system controller 315 can transmit a single poll request for the flags 325 via the bus 310, and the poll request can be received by each memory device 330 because the memory devices 330 share the bus 310. In some cases, each memory device 330 can indicate the respective flag 325 using different signal lines (or set of signal lines) of the bus 310, such that the bus 310 carries multiple flags 325 associated with the different memory devices 330 in parallel.

[0076] In some cases, one memory device 330 (or memory die 360) can act as a master memory device 330 (or master memory die 360) for one or more other memory devices 330 (or memory dies 360). For example, in cases where the system 300 includes more memory devices 330 (or memory dies 360) than the number of channels included in the bus 310, the master memory device 330 (or master memory die 360) can track and communicate the completion status of more than one memory device 330 or memory die 360 (e.g., using a pulse position modulation (PPM) signal to build a subnet among the master memory device 330 or die and the one or more other memory devices 330 or memory dies 360 associated with the same completion flag). That is, the master can maintain the flag 325 applied to the one or more memory devices 330 (or memory dies 360) and can track the flag 325 and register 345 of the one or more memory devices 330 (or memory dies 360) and communicate an indication of the status of the associated flag 325, the associated register 345, or both to the memory system controller 315.

[0077] If the memory system controller 315 identifies a flag 325 indicating that the associated memory device 330 has completed at least one access operation, the memory system controller 315 can poll the register 345 associated with the memory device 330. Based on polling the register 345, the memory system controller 315 can identify the one or more planes 365 associated with the completed access operation. In cases where the access operation corresponds to a read command (e.g., a snapshot read command), the memory device 330 can communicate data 305 (e.g., associated with the read command) to the memory system controller 315 via the bus 310 and via a direct memory access operation.

[0078] Figure 4 A block diagram 400 illustrates a memory device 420 supporting a memory operation completion marker according to an example disclosed herein. The memory device 420 may be a reference... Figures 1 to 3 Examples of aspects of the described memory device (e.g., including a memory die). For example, memory device 420 may include references. Figures 1 to 3 The described aspects of the local controller. Memory device 420 or its various components may be instances of various techniques for performing memory operation completion marking as described herein. For example, memory device 420 may include register manager 425, completion mark manager 430, command manager 435, data manager 440, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0079] Register manager 425 may be configured or otherwise support components for setting a first status bit of a register, at least in part, based on the completion of an access operation at a first plane of a plurality of planes of the memory die, wherein the register is associated with the memory die and configured to store a plurality of status bits, each corresponding to a corresponding one of the plurality of planes, and wherein the first status bit corresponds to the first plane. Completion flag manager 430 may be configured or otherwise support components for setting a flag associated with the memory die indicating the completion of at least one access operation at the memory die, at least in part, based on the completion of an access operation at the first plane. Command manager 435 may be configured or otherwise support components for receiving a command from the controller to output data associated with the first plane, at least in part, based on the flag indicating the completion of at least one access operation being set. Data manager 440 may be configured or otherwise support components for outputting data corresponding to an access operation at the first plane to the controller, at least in part, based on a command.

[0080] In some instances, register manager 425 may be configured or otherwise support components for setting a second status bit of a register corresponding to the second plane, at least in part based on the completion of a second access operation at the second plane of the plurality of planes, when a flag associated with the memory die is set. In some instances, command manager 435 may be configured or otherwise support components for receiving a second command from the controller to output data associated with the second plane, at least in part based on a flag indicating the completion of at least one access operation being set. In some instances, data manager 440 may be configured or otherwise support components for outputting data to the controller corresponding to the second access operation at the second plane, at least in part based on the second command.

[0081] In some examples, the completion tag manager 430 can be configured as or otherwise support means for determining whether a tag indicating completion of at least one access operation at the memory die is set based at least in part on completion of the second access operation at the second plane.

[0082] In some examples, the completion tag manager 430 can be configured as or otherwise support means for receiving a poll request for the tag from the controller after setting the tag indicating completion of at least one access operation at the memory die. In some examples, the completion tag manager 430 can be configured as or otherwise support means for outputting an indication to the controller that the tag is set in response to the poll request for the tag. In some examples, the completion tag manager 430 can be configured as or otherwise support means for resetting the tag in response to the poll request for the tag.

[0083] In some examples, the register manager 425 can be configured as or otherwise support means for receiving a poll request for the registers from the controller after setting the tag indicating completion of at least one access operation. In some examples, the register manager 425 can be configured as or otherwise support means for outputting a plurality of indications to the controller in response to the poll request for the registers, each indication indicating a value of a respective status bit of the registers. In some examples, the completion tag manager 430 can be configured as or otherwise support means for resetting the tag in response to the poll request for the registers.

[0084] In some examples, the register manager 425 can be configured as or otherwise support means for receiving a poll request for the registers from the controller after setting the tag indicating completion of at least one access operation. In some examples, the register manager 425 can be configured as or otherwise support means for resetting each of the plurality of status bits in response to the poll request for the registers.

[0085] In some examples, the register manager 425 (e.g., included in the second memory device 420 or, additionally or alternatively, in the second memory die) can be configured or otherwise support means for setting a status bit of a second register corresponding to a plane of the second plurality of planes and indicating completion of an access operation at the plane, where the second register is associated with the second memory die including the second plurality of planes and is configured to store a second plurality of status bits, each status bit corresponding to a respective one of the second plurality of planes. In some examples, the completion flag manager 430 can be configured or otherwise support means for setting a second flag associated with the second memory die indicating completion of at least one access operation at the second memory die based at least in part on completion of the access operation at the plane. In some examples, the command manager 435 can be configured or otherwise support means for receiving a command from the controller to output data associated with the plane based at least in part on the second flag indicating completion of at least one access operation at the second memory die being set. In some examples, the data manager 440 can be configured or otherwise support means for outputting data corresponding to the access operation at the plane to the controller based at least in part on the command to output data associated with the plane.

[0086] In some examples, a bus can couple the memory device 420 and the second memory device 420, and the bus can be configured to simultaneously carry a first poll request for a flag associated with the memory die and a second poll request for a second flag associated with the second memory die.

[0087] In some examples, a bus can couple the memory device 420 and the second memory device 420, and the bus can be configured to simultaneously carry a first indication of a value of a flag associated with the memory die and a second indication of a value of a second flag associated with the second memory die.

[0088] In some examples, to support outputting data corresponding to the access operation at the first plane, the data manager 440 can be configured or otherwise support means for outputting the data to the controller via a direct memory access operation.

[0089] In some examples, the command manager 435 can be configured or otherwise support means for receiving a command from the controller to perform an access operation at the first plane. In some examples, the command manager 435 can be configured or otherwise support means for performing the access operation at the first plane based at least in part on the command to perform the access operation at the first plane.

[0090] In some examples, the access operation at the first plane can be a snapshot read operation at the first plane.

[0091] Figure 5 A block diagram 500 showing a memory system controller 520 that supports memory operation completion markers in accordance with examples as disclosed herein is shown. The memory system controller 520 can be an example of the memory system controller described with reference to Figures 1 to 3 the aspects of the host system controller described. The memory system controller 520, or various components thereof, can be examples of means for performing various techniques related to memory operation completion markers as described herein. For example, the memory system controller 520 can include a completion marker identification manager 525, a register polling manager 530, a command transmission manager 535, a data reception manager 540, or any combination thereof. Each of these components can be in communication, directly or indirectly, with one another (e.g., via one or more buses). Figure 1 The completion marker identification manager 525 can be configured as, or otherwise support, means for identifying that a marker associated with a memory die indicates completion of at least one access operation at the memory die, the memory die including a plurality of planes. The register polling manager 530 can be configured as, or otherwise support, means for polling, based at least in part on the marker indicating completion of the at least one access operation at the memory die, a register associated with the memory die and configured to store a plurality of status bits, each status bit corresponding to a respective one of the plurality of planes. In some examples, the register polling manager 530 can be configured as, or otherwise support, means for identifying completion of an access operation at a first plane of the plurality of planes based at least in part on polling the register, based at least in part on a first status bit of the register corresponding to the first plane indicating completion of the access operation at the first plane. The command transmission manager 535 can be configured as, or otherwise support, means for transmitting, based at least in part on identifying completion of the access operation at the first plane, a command to the memory die to output data associated with the first plane. The data reception manager 540 can be configured as, or otherwise support, means for receiving, based at least in part on the command, data corresponding to the access operation at the first plane from the memory die.

[0092]

[0093] ​In some examples, the completion tag identification manager 525 can be configured as or otherwise support means for polling a plurality of tags including tags associated with memory dies, where each of the plurality of tags is associated with a respective one of a plurality of memory dies included in the memory system. In some examples, the completion tag identification manager 525 can be configured as or otherwise support means for identifying, based at least in part on polling the plurality of tags, that a tag indicates completion of at least one access operation at a memory die.

[0094] In some examples, the completion tag identification manager 525 can be configured as or otherwise support means for identifying, based at least in part on polling the plurality of tags, that a second tag associated with a second memory die included in the memory system indicates that no access operation has completed at the second memory die. In some examples, the register polling manager 530 can be configured as or otherwise support means for refraining from polling a second register associated with the second memory die based at least in part on the second tag associated with the second memory die indicating that no access operation has completed at the second memory die, the second register configured to store a second plurality of status bits, each status bit corresponding to a respective one of a second plurality of planes included in the second memory die.

[0095] In some examples, the completion tag identification manager 525 can be configured as or otherwise support means for identifying that a second access operation at a second memory die is complete based at least in part on polling the plurality of tags, the second memory die associated with a second tag included in the memory system, the second memory die including a second plurality of planes. In some examples, the register polling manager 530 can be configured as or otherwise support means for polling a second register associated with the second memory die and configured to store a second plurality of status bits, each status bit corresponding to a respective one of the second plurality of planes, based at least in part on the second tag indicating that the second access operation at the second memory die is complete. In some examples, the register polling manager 530 can be configured as or otherwise support means for identifying that the second access operation at a second plane of the second plurality of planes is complete based at least in part on polling the second register, the second status bit of the second register corresponding to the second plane indicating that the second access operation at the second plane is complete. In some examples, the command transmission manager 535 can be configured as or otherwise support means for transmitting a second command to the second memory die to output data associated with the second plane based at least in part on identifying that the second access operation at the second plane is complete. In some examples, the data reception manager 540 can be configured as or otherwise support means for receiving data corresponding to the second access operation at the second plane from the second memory die based at least in part on the second command.

[0096] In some examples, to support polling the plurality of tags, the completion tag identification manager 525 can be configured as or otherwise support means for polling each of the plurality of tags simultaneously via a bus coupled with each of the plurality of memory dies.

[0097] In some examples, the completion tag identification manager 525 can be configured as or otherwise support means for receiving a plurality of indications simultaneously via a bus coupled with each of the plurality of memory dies based at least in part on polling the plurality of tags, each of the plurality of indications indicating a value of a respective one of the plurality of tags.

[0098] In some examples, the register polling manager 530 can be configured as or otherwise support means for identifying completion of a second access operation at a second plane of the plurality of planes based at least in part on polling the register based at least in part on a second status bit of the register corresponding to the second plane indicating completion of the second access operation at the second plane. In some examples, the command transmission manager 535 can be configured as or otherwise support means for transmitting, to the memory die, a second command to output data associated with the second plane based at least in part on identifying completion of the second access operation at the second plane. In some examples, the data reception manager 540 can be configured as or otherwise support means for receiving, from the memory die, data corresponding to the second access operation at the second plane based at least in part on the second command.

[0099] In some examples, to support receiving data corresponding to the access operation at the first plane, the data reception manager 540 can be configured as or otherwise support means for receiving the data from the memory die via a direct memory access operation.

[0100] In some examples, the command transmission manager 535 can be configured as or otherwise support means for transmitting, to the memory die, a command to perform an access operation at the first plane, where identifying that the flag associated with the memory die indicates completion of at least one access operation at the memory die includes polling the flag associated with the memory die after transmitting the command to perform the access operation at the first plane.

[0101] In some examples, the access operation at the first plane can be a snapshot read operation at the first plane.

[0102] Figure 6 A flow diagram in accordance with examples as disclosed herein is shown, illustrating a method 600 of supporting a memory operation completion flag. The operations of method 600 can be implemented by a memory device or its components as described herein. For example, the operations of method 600 can be performed by a memory device (e.g., a local controller thereof) as described with reference to FIGS. 1-4. In some examples, a memory device (e.g., a local controller thereof) can execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware. Figures 1 to 4 described. In some examples, a memory device (e.g., a local controller thereof) can execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0103] At 605, the method can include setting a first status bit of a register based at least in part on completion of an access operation at a first plane of a plurality of planes of a memory die, where the register is associated with the memory die and is configured to store a plurality of status bits, each status bit corresponding to a respective one of the plurality of planes, and where the first status bit corresponds to the first plane. Operation 605 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operation 605 can be performed by a register manager 425 as described with reference to Figure 4 The described register manager 425 performs.

[0104] At 610, the method can include setting a flag associated with the memory die indicating completion of at least one access operation at the memory die based at least in part on completion of the access operation at the first plane. Operation 610 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operation 610 can be performed by a completion flag manager 430 as described with reference to Figure 4 The described completion flag manager 430 performs.

[0105] At 615, the method can include receiving a command from the controller to output data associated with the first plane based at least in part on the flag indicating completion of the at least one access operation being set. Operation 615 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operation 615 can be performed by a command manager 435 as described with reference to Figure 4 The described command manager 435 performs.

[0106] At 620, the method can include outputting data corresponding to the access operation at the first plane to the controller based at least in part on the command. Operation 620 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operation 620 can be performed by a data manager 440 as described with reference to Figure 4 The described data manager 440 performs.

[0107] In some examples, the apparatuses described herein can perform one or more methods, such as method 600. The apparatuses can include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for setting, based at least in part on completion of an access operation at a first plane of a plurality of planes, a first status bit of a register corresponding to the first plane, where the register is associated with a memory die that includes the plurality of planes and is configured to store a plurality of status bits, each status bit corresponding to a respective one of the plurality of planes; setting, based at least in part on completion of the access operation at the first plane, a flag associated with the memory die indicating completion of at least one access operation at the memory die; receiving, based at least in part on the flag indicating completion of the at least one access operation being set, a command from a controller to output data associated with the first plane; and outputting, based at least in part on the command, the data corresponding to the access operation at the first plane to the controller.

[0108] Some examples of the method 600 and apparatuses described herein can further include operations, features, circuitry, logic, means, or instructions for setting, based at least in part on completion of a second access operation at a second plane of the plurality of planes, a second status bit of the register corresponding to the second plane while the flag associated with the memory die can be set; receiving, based at least in part on the flag indicating completion of the at least one access operation being set, a second command from the controller to output data associated with the second plane; and outputting, based at least in part on the second command, the data corresponding to the second access operation at the second plane to the controller.

[0109] Some examples of the method 600 and apparatuses described herein can further include operations, features, circuitry, logic, means, or instructions for determining, based at least in part on completion of the second access operation at the second plane, whether the flag indicating completion of the at least one access operation at the memory die is set.

[0110] Some examples of the method 600 and apparatuses described herein can further include operations, features, circuitry, logic, means, or instructions for receiving, from the controller, a polling request for the flag after setting the flag indicating completion of the at least one access operation at the memory die; outputting, in response to the polling request for the flag, an indication to the controller that the flag is set; and resetting, in response to the polling request for the flag, the flag.

[0111] Some examples of the method 600 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for receiving a poll request for the register from the controller after setting the flag indicating completion of the at least one access operation; outputting, to the controller, a plurality of indications in response to the poll request for the register, each indication indicating a value of a respective status bit of the register; and resetting the flag in response to the poll request for the register.

[0112] Some examples of the method 600 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for receiving a poll request for the register from the controller after setting the flag indicating completion of the at least one access operation; and resetting each of the plurality of status bits in response to the poll request for the register.

[0113] Some examples of the method 600 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for setting a status bit of a second register corresponding to a plane of a second plurality of planes and indicating completion of an access operation at the plane, wherein the second register is associated with a second memory die including the second plurality of planes and is configured to store a second plurality of status bits, each status bit corresponding to a respective one of the second plurality of planes; setting a second flag associated with the second memory die indicating completion of at least one access operation at the second memory die based at least in part on completion of the access operation at the plane; receiving a command from the controller to output data associated with the plane based at least in part on the second flag indicating completion of at least one access operation at the second memory die being set; and outputting, to the controller, data corresponding to the access operation at the plane based at least in part on the command to output data associated with the plane.

[0114] In some examples of the method 600 and the apparatus described herein, the bus can couple the controller with the first memory die (e.g., a controller thereof) and the second memory die (e.g., a controller thereof), and the bus can be configured to support simultaneous polling of the flag associated with the memory die and the second flag associated with the second memory die.

[0115] In some examples of the method 600 and the apparatus described herein, the bus can couple the controller with the first memory die (e.g., a controller thereof) and the second memory die (e.g., a controller thereof), and the bus can be configured to simultaneously carry a first indication of a value of the flag associated with the memory die and a second indication of a value of the second flag associated with the second memory die.

[0116] In some examples of the method 600 and apparatus described herein, the operations, features, circuitry, logic, means, or instructions for outputting data corresponding to an access operation at the first plane can include operations, features, circuitry, logic, means, or instructions for outputting the data to the controller via a direct memory access operation.

[0117] Some examples of the method 600 and apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for receiving a command from the controller to perform an access operation at the first plane; and performing the access operation at the first plane based at least in part on the command to perform the access operation at the first plane.

[0118] In some examples of the method 600 and apparatus described herein, the access operation at the first plane includes a snapshot read operation at the first plane.

[0119] Figure 7 A flow diagram in accordance with examples as disclosed herein is shown, illustrating a method 700 of supporting memory operation completion markers. The operations of the method 700 can be implemented by a memory system controller or host system controller as described herein, or a component thereof. For example, the operations of the method 700 can be performed by the memory system controller or host system controller described with reference to any of Figures 1 to 3 and 5. In some examples, a memory system controller can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory system controller or host system controller can perform aspects of the described functions using special-purpose hardware.

[0120] At 705, the method can include identifying that a marker associated with a memory die indicates completion of at least one access operation at the memory die, the memory die including a plurality of planes. Operation 705 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operation 705 can be performed by the completion marker identification manager 525 described with reference to Figure 5

[0121] At 710, the method can include polling a register associated with the memory die and configured to store a plurality of status bits based at least in part on the marker indicating completion of the at least one access operation at the memory die, each status bit corresponding to a respective one of the plurality of planes. Operation 710 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operation 710 can be performed by the register polling manager 530 described with reference to Figure 5

[0122] ​​At 715, the method can include identifying completion of an access operation at a first plane of the plurality of planes based at least in part on polling the register based at least in part on a first status bit of the register corresponding to the first plane of the plurality of planes indicating completion of an access operation at the first plane. Operation 715 can be performed in accordance with examples as disclosed herein. In some examples, aspects of operation 715 can be performed by a register polling manager 530 as described with reference to Figure 5 The register polling manager 530 described performs.

[0123] At 720, the method can include transmitting a command to output data associated with the first plane to the memory die based at least in part on identifying completion of the access operation at the first plane. Operation 720 can be performed in accordance with examples as disclosed herein. In some examples, aspects of operation 720 can be performed by a command transmission manager 535 as described with reference to Figure 5 The command transmission manager 535 described performs.

[0124] At 725, the method can include receiving data corresponding to the access operation at the first plane from the memory die based at least in part on the command. Operation 725 can be performed in accordance with examples as disclosed herein. In some examples, aspects of operation 725 can be performed by a data reception manager 540 as described with reference to Figure 5 The data reception manager 540 described performs.

[0125] In some examples, an apparatus described herein can perform one or more methods, such as method 700. The apparatus can include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for identifying that a flag associated with a memory die indicates completion of at least one access operation at the memory die, the memory die including a plurality of planes; polling a register associated with the memory die and configured to store a plurality of status bits based at least in part on the flag indicating completion of the at least one access operation at the memory die, each status bit corresponding to a respective one of the plurality of planes; identifying completion of an access operation at a first plane of the plurality of planes based at least in part on polling the register based at least in part on a first status bit of the register corresponding to the first plane indicating completion of an access operation at the first plane; transmitting a command to output data associated with the first plane to the memory die based at least in part on identifying completion of the access operation at the first plane; and receiving data corresponding to the access operation at the first plane from the memory die based at least in part on the command.

[0126] Some examples of the method 700 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for polling a plurality of markers including a marker associated with a memory die, where each of the plurality of markers can be associated with a respective one of a plurality of memory dies included in a memory system, and where identifying that the marker indicates completion of at least one access operation at the memory die is based at least in part on polling the plurality of markers.

[0127] Some examples of the method 700 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for identifying, based at least in part on polling the plurality of markers, that a second marker associated with a second memory die included in the memory system indicates that no access operation has completed at the second memory die; and preventing polling of a second register associated with the second memory die based at least in part on the second marker associated with the second memory die indicating that no access operation has completed at the second memory die, the second register configured to store a second plurality of status bits, each status bit corresponding to a respective one of a second plurality of planes included in the second memory die.

[0128] Some examples of the method 700 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for identifying, based at least in part on polling the plurality of markers, that a second marker associated with a second memory die included in the memory system indicates completion of at least one access operation at the second memory die, the second memory die including a second plurality of planes; polling, based at least in part on the second marker indicating completion of at least one access operation at the second memory die, a second register associated with the second memory die and configured to store a second plurality of status bits, each status bit corresponding to a respective one of the second plurality of planes; identifying, based at least in part on polling the second register, completion of a second access operation at a second plane of the second plurality of planes based at least in part on a second status bit of the second register corresponding to the second plane indicating completion of the second access operation at the second plane; transmitting, based at least in part on identifying completion of the second access operation at the second plane, a second command to the second memory die to output data associated with the second plane; and receiving, based at least in part on the second command, data corresponding to the second access operation at the second plane from the second memory die.

[0129] In some examples of the method 700 and the apparatus described herein, the operations, features, circuitry, logic, means, or instructions for polling the plurality of markers can include operations, features, circuitry, logic, means, or instructions for polling each of the plurality of markers simultaneously via a bus coupled with each of the plurality of memory dies.

[0130] Some examples of the method 700 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for receiving, via a bus coupled with each of the plurality of memory dies, a plurality of indications simultaneously based at least in part on polling the plurality of tags, each of the plurality of indications indicating a value of a respective one of the plurality of tags.

[0131] Some examples of the method 700 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for identifying completion of a second access operation at a second plane of the plurality of planes based at least in part on a second status bit of the register corresponding to the second plane indicating completion of the second access operation at the second plane based at least in part on polling the register; transmitting, to the memory die, a second command to output data associated with the second plane based at least in part on identifying completion of the second access operation at the second plane; and receiving, from the memory die, data corresponding to the second access operation at the second plane based at least in part on the second command.

[0132] In some examples of the method 700 and the apparatus described herein, the operations, features, circuitry, logic, means, or instructions for receiving data corresponding to the access operation at the first plane can include operations, features, circuitry, logic, means, or instructions for receiving the data from the memory die via a direct memory access operation.

[0133] Some examples of the method 700 and the apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for transmitting, to the memory die, a command to perform an access operation at the first plane, where the operations, features, circuitry, logic, means, or instructions for identifying that a tag associated with the memory die indicates completion of at least one access operation at the memory die can include operations, features, circuitry, logic, means, or instructions for polling the tag associated with the memory die after transmitting the command to perform the access operation at the first plane.

[0134] In some examples of the method 700 and the apparatus described herein, the access operation at the first plane can be a snapshot read operation at the first plane.

[0135] It should be noted that the method described above describes possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Furthermore, portions from two or more of the methods can be combined.

[0136] An apparatus is described. The apparatus can include a memory die including a plurality of planes, a register associated with the memory die and configured to store a plurality of status bits, each status bit corresponding to a respective one of the plurality of planes, and a controller for the memory die. The controller can be configured to cause the apparatus to set a first status bit of the register corresponding to a first plane of the plurality of planes based at least in part on completion of an access operation at the first plane, set a flag associated with the memory die indicating completion of at least one access operation at the memory die based at least in part on the completion of the access operation at the first plane, receive a command from a second controller to output data associated with the first plane based at least in part on the flag indicating completion of the at least one access operation being set, and output the data corresponding to the access operation at the first plane to the second controller based at least in part on the command.

[0137] In some examples, the controller can be further configured to cause the apparatus to set a second status bit of the register corresponding to a second plane of the plurality of planes based at least in part on completion of a second access operation at the second plane while the flag associated with the memory die is set, receive a second command from the second controller to output data associated with the second plane based at least in part on the flag indicating completion of the at least one access operation being set, and output the data corresponding to the second access operation at the second plane to the second controller based at least in part on the second command.

[0138] In some examples, the controller can be further configured to cause the apparatus to determine whether the flag indicating completion of the at least one access operation at the memory die is set based at least in part on completion of the second access operation at the second plane.

[0139] In some examples, the controller can be further configured to cause the apparatus to receive a poll request for the flag from the second controller after setting the flag indicating completion of the at least one access operation at the memory die, output an indication to the second controller that the flag is set in response to the poll request for the flag, and reset the flag in response to the poll request for the flag.

[0140] In some examples, the controller can be further configured to cause the apparatus to receive a poll request for the register from the second controller after setting the flag indicating completion of the at least one access operation, output a plurality of indications to the second controller, each indication indicating a value of a respective status bit of the register in response to the poll request for the register, and reset the flag in response to the poll request for the register.

[0141] In some examples, the controller can be further configured to cause the device to: receive a poll request for the register from the second controller after setting the flag indicating completion of the at least one access operation; and reset each of the plurality of status bits in response to the poll request for the register.

[0142] In some examples, the device can include: a second memory die including a second plurality of planes; a second register associated with the second memory die and configured to store a second plurality of status bits, each status bit corresponding to a respective one of the second plurality of planes; and a third controller for the second memory die. The third controller can be configured to cause the device to: set a status bit of the second register corresponding to a plane of the second plurality of planes and indicating completion of an access operation at the plane; set a second flag associated with the second memory die indicating completion of at least one access operation at the second memory die based at least in part on completion of the access operation at the plane; receive a command from the second controller to output data associated with the plane based at least in part on the second flag indicating completion of at least one access operation at the second memory die being set; and output data corresponding to the access operation at the plane to the second controller based at least in part on the command to output data associated with the plane.

[0143] In some examples, the device can include a bus coupling the second controller with the controller and the third controller, where the bus can be configured to support simultaneous polling of the flag associated with the memory die and the second flag associated with the second memory die.

[0144] In some examples, the device can include a bus coupling the second controller with the controller and the third controller, where the bus can be configured to simultaneously carry a first indication of a value of the flag associated with the memory die and a second indication of a value of the second flag associated with the second memory die.

[0145] In some examples, to output the data corresponding to the access operation at the first plane, the controller can be configured to cause the device to output the data to the second host controller via a direct memory access operation.

[0146] In some examples, the controller can be further configured to cause the device to: receive a command from the second controller to perform an access operation at the first plane, and perform the access operation at the first plane based at least in part on the command to perform the access operation at the first plane.

[0147] In some examples, the access operation at the first plane can be a snapshot read operation at the first plane.

[0148] Describe an apparatus. The apparatus may include a controller configured to couple to a memory die of a memory system, wherein the controller is configured to cause the apparatus to: identify a marker associated with the memory die indicating the completion of at least one access operation at the memory die, the memory die comprising a plurality of planes; poll a register associated with the memory die and configured to store a plurality of status bits, each status bit corresponding to a corresponding one of the plurality of planes, at least in part based on the marker indicating the completion of the at least one access operation at the memory die; identify the completion of an access operation at a first plane of the plurality of planes, at least in part based on polling the register and at least in part based on a first status bit of the register corresponding to the first plane indicating the completion of the access operation at the first plane; transmit a command to the memory die to output data associated with the first plane, at least in part based on identifying the completion of the access operation at the first plane; and receive data from the memory die corresponding to the access operation at the first plane, at least in part based on the command.

[0149] In some instances, the controller may be further configured to cause the device to poll a plurality of tags containing tags associated with memory dies, each of which may be associated with a corresponding one of a plurality of memory dies contained in the memory system, and wherein the controller may be configured to cause the device to identify tags indicating the completion of at least one access operation at a memory die, at least in part based on polling the plurality of tags.

[0150] In some instances, the controller may be further configured to cause the device to identify, at least in part, a second tag associated with a second memory die contained in the memory system indicating that no access operation has been completed at the second memory die based on polling the plurality of tags, and to prevent polling of a second register associated with the second memory die, the second register being configured to store a second plurality of status bits, each status bit corresponding to a corresponding one in a second plurality of planes contained in the second memory die, based at least in part on the second tag associated with the second memory die indicating that no access operation has been completed at the second memory die.

[0151] In some examples, the controller can be further configured to cause the apparatus to poll the plurality of tags based at least in part on polling the plurality of tags, identify that a second tag associated with a second memory die included in the memory system indicates completion of at least one access operation at the second memory die, the second memory die including a second plurality of planes; poll, based at least in part on the second tag indicating completion of the at least one access operation at the second memory die, a second register associated with the second memory die and configured to store a second plurality of status bits, each status bit corresponding to a respective one of the second plurality of planes; identify, based at least in part on polling the second register, completion of the second access operation at a second plane of the second plurality of planes based at least in part on a second status bit of the second register corresponding to the second plane indicating completion of the second access operation at the second plane; transmit, based at least in part on identifying completion of the second access operation at the second plane, a second command to the second memory die to output data associated with the second plane; and receive, based at least in part on the second command, data corresponding to the second access operation at the second plane from the second memory die.

[0152] In some examples, the controller can be further configured to cause the apparatus to poll each of the plurality of tags simultaneously via a bus coupled with each of the plurality of memory dies.

[0153] In some examples, the controller can be further configured to cause the apparatus to poll each of the plurality of tags based at least in part on polling the plurality of tags, receive a plurality of indications simultaneously via a bus coupled with each of the plurality of memory dies, each of the plurality of indications indicating a value of a respective one of the plurality of tags.

[0154] In some examples, the controller can be further configured to cause the apparatus to identify, based at least in part on polling the register, completion of the second access operation at a second plane of the plurality of planes based at least in part on a second status bit of the register corresponding to the second plane indicating completion of the second access operation at the second plane; transmit, based at least in part on identifying completion of the second access operation at the second plane, a second command to the memory die to output data associated with the second plane; and receive, based at least in part on the second command, data corresponding to the second access operation at the second plane from the memory die.

[0155] In some examples, the controller can be further configured to cause the apparatus to receive the data from the memory die via a direct memory access operation.

[0156] In some examples, the controller can be further configured to cause the apparatus to transmit, to the memory die, a command to perform an access operation at the first plane, wherein to identify the indication of the completion of the at least one access operation at the memory die associated with the memory die, the controller can be further configured to cause the apparatus to poll the flag associated with the memory die after transmitting the command to perform the access operation at the first plane.

[0157] In some examples of the apparatus, the access operation at the first plane can be a snapshot read operation at the first plane.

[0158] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, such signals can represent multiple signals that can be reflected as a single signal over a bus.

[0159] The terms“in electronic communication,”“in conductive contact,”“connected,” and“coupled” can refer to a relationship between components in which signals can flow from one component to another. Components are said to be in electronic communication with one another (or in conductive contact with one another, or connected to one another, or coupled to one another) if there is any conductive path that can support the flow of signals from one component to the other at any time. The conductive path between components that are in electronic communication with one another (or in conductive contact with one another, or connected to one another, or coupled to one another) can be an open circuit or a closed circuit at any given time, based on the operation of the device that includes the connected components. The conductive path between connected components can be a direct conductive path between the components, or the conductive path between connected components can be an indirect conductive path that can include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between connected components can be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0160] The term“coupled” refers to a condition of components that moves from an open circuit relationship between the components, in which signals cannot currently be transmitted between the components through a conductive path, to a closed circuit relationship between the components, in which signals can be transmitted between the components through a conductive path. If a component, such as a controller, couples other components together, the component causes a change that allows signals to flow between the other components through a conductive path that previously did not allow signal flow.

[0161] The term“isolated” refers to a relationship between components where signals cannot currently flow between the components. Components are isolated from each other if there is a break in the circuit between them. For example, components that are separated by a switch positioned between the two components are isolated from each other when the switch is open. If a controller isolates two components, the controller effects a change that prevents signals from flowing between the components using a conductive path through which signals were previously permitted to flow.

[0162] The terms“if’‘when,”“based on,” or“based at least in part on” can be used interchangeably. In some examples, the terms“if’‘when,”“based on,” or“based at least in part on” are used to describe conditional relationships, causative relationships, or correlations in which different steps are linked by causation.

[0163] The term“in response to” can refer to a condition or action occurring at least partially (if not entirely) as a result of a previous condition or action. For example, a first condition or action can be performed, and a second condition or action can occur at least partially as a result of the occurrence of the first condition or action, whether directly or indirectly, and whether mechanically, electronically, digitally, or otherwise.

[0164] Additionally, the term“directly in response to” or“directly responsive to” can refer to a condition or action occurring as a direct result of a previous condition or action. In some examples, a first condition or action can be performed, and a second condition or action can occur directly as a result of the occurrence of the previous condition or action, regardless of whether other conditions or actions occur. In some examples, a first condition or action can be performed, and a second condition or action can occur directly as a result of the occurrence of the previous condition or action, such that no other intervening conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intervening steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed“based on,”“based at least in part on,” or“in response to” some other step, action, event, or condition can additionally or alternatively (e.g., in alternative examples) be performed“directly in response to” or“directly in response to” such other condition or action.

[0165] Devices including memory arrays discussed herein can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as a silicon-on-glass (SOG) or a silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate, or sub-regions of the substrate, can be controlled by doping using various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0166] Switching components or transistors discussed herein can represent field effect transistors (FETs) and include a three-terminal device including a source, a drain, and a gate. The terminals can be connected to other electronic elements by conductive material, such as metal. The source and drain can be conductive and can include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET, respectively, can cause the channel to become conductive. A transistor can be "turned on" or "activated" if a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate. A transistor can be "turned off" or "deactivated" if a voltage less than the threshold voltage of the transistor is applied to the transistor gate.

[0167] The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that can be implemented or that are within the scope of the claims. The term "exemplary" used herein means "serving as an example, instance, or illustration," and not "preferred" over other examples. The detailed description includes specific details for the purpose of providing an understanding of the described techniques. These techniques, however, can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0168] In the appended figures, similar components or features can have similar reference labels. Further, various components of the same type can be distinguished by following the convention of using a first reference number for a first instance of a component and a second reference number for a second instance of the component. If only a single reference is used in the description of a component, it is intended to represent that a plurality of components can be used.

[0169] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transferred over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

[0170] The various illustrative blocks and components described in connection with the disclosure herein can be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein, for example. The general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller or controller, microcontroller, or state machine. The processor can be implemented as a combination of a

[0171] As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of’ or “one or more of’) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” can be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”

[0172] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program elements in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0173] The description herein is presented to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: A memory die, which comprises multiple planes; A register, which is associated with the memory die and configured to store a plurality of status bits, each status bit corresponding to a corresponding one of the plurality of planes; as well as A first controller for the memory die, the first controller being configured to cause the device to: The first status bit of the register corresponding to the first plane is set at least in part based on the completion of an access operation at the first plane of the plurality of planes; At least in part based on the completion of the access operation at the first plane, a flag indicating the completion of at least one access operation at the memory die is set and associated with the memory die; After setting the flag indicating the completion of at least one access operation at the memory die, a polling request for the flag is received from the second controller; In response to the polling request for the flag, an indication that the flag has been set is output to the second controller; In response to the polling request for the flag, the flag is reset; The command to output data associated with the first plane is received from the second controller, based at least in part on the setting of the flag indicating the completion of at least one access operation; as well as At least in part, based on the command, data corresponding to the access operation at the first plane is output to the second controller.

2. The device of claim 1, wherein the first controller is further configured to cause the device to: When the tag associated with the memory die is set, the second status bit of the register corresponding to the second plane is set at least in part based on the completion of the second access operation at the second plane of the plurality of planes; The second command, which receives data associated with the second plane from the second controller, is set at least in part based on the flag indicating the completion of at least one access operation; as well as At least in part, based on the second command, data corresponding to the second access operation at the second plane is output to the second controller.

3. The device of claim 2, wherein the first controller is further configured to cause the device to: Based at least in part on the completion of the second access operation at the second plane, it is determined whether the flag indicating the completion of at least one access operation at the memory die is set.

4. The device according to claim 1, further comprising: A second memory die includes a second plurality of planes; A second register, associated with the second memory die and configured to store a second plurality of status bits, each status bit corresponding to a corresponding one in the second plurality of planes; as well as A third controller for the second memory die, the third controller being configured to cause the device to: Set a status bit in the second register that corresponds to one of the second plurality of planes and indicates the completion of an access operation at said plane; At least in part based on the completion of the access operation at the plane, a second marker associated with the second memory die indicating the completion of at least one access operation at the second memory die is set; A command to output data associated with the plane is received from the second controller, based at least in part on the setting of the second flag indicating the completion of at least one access operation at the second memory die; as well as The second controller outputs data corresponding to the access operation at the plane, based at least in part on the command that outputs data associated with the plane.

5. The device according to claim 4, further comprising: A bus that couples the second controller to the first controller and the third controller, wherein the bus is configured to support simultaneous polling of the tag associated with the memory die and the second tag associated with the second memory die.

6. The device according to claim 4, further comprising: A bus, which couples the second controller to the first controller and the third controller, wherein: The bus is configured to simultaneously carry a first indication of the value of the tag associated with the memory die and a second indication of the value of the second tag associated with the second memory die.

7. The device of claim 1, wherein, in order to output the data corresponding to the access operation at the first plane, the first controller is configured to cause the device to: The data is output to the second controller via a direct memory access operation.

8. The device of claim 1, wherein the first controller is further configured to cause the device to: Receives a command from the second controller to perform the access operation at the first plane; and The access operation is performed at the first plane based at least in part on the command that performs the access operation at the first plane.

9. The device of claim 1, wherein the access operation at the first plane includes a snapshot read operation at the first plane.

10. An apparatus comprising: A memory die, which comprises multiple planes; A register, which is associated with the memory die and configured to store a plurality of status bits, each status bit corresponding to a corresponding one of the plurality of planes; as well as A first controller for the memory die, the first controller being configured to cause the device to: The first status bit of the register corresponding to the first plane is set at least in part based on the completion of an access operation at the first plane of the plurality of planes; At least in part based on the completion of the access operation at the first plane, a flag indicating the completion of at least one access operation at the memory die is set and associated with the memory die; The command to output data associated with the first plane is received from the second controller, based at least in part on the flag indicating the completion of at least one access operation; At least in part, based on the command, data corresponding to the access operation at the first plane is output to the second controller; After setting the flag indicating the completion of at least one access operation, a polling request for the register is received from the second controller; In response to the polling request for the register, a plurality of indications are output to the second controller, each indicating the value of a corresponding status bit of the register; as well as In response to the polling request for the register, the flag is reset.

11. An apparatus comprising: A memory die, which comprises multiple planes; A register, which is associated with the memory die and configured to store a plurality of status bits, each status bit corresponding to a corresponding one of the plurality of planes; as well as A first controller for the memory die, the first controller being configured to cause the device to: The first status bit of the register corresponding to the first plane is set at least in part based on the completion of an access operation at the first plane of the plurality of planes; At least in part based on the completion of the access operation at the first plane, a flag indicating the completion of at least one access operation at the memory die is set and associated with the memory die; The command to output data associated with the first plane is received from the second controller, based at least in part on the flag indicating the completion of at least one access operation; At least in part, based on the command, data corresponding to the access operation at the first plane is output to the second controller; After setting the flag indicating the completion of at least one access operation, a polling request for the register is received from the second controller; as well as In response to the polling request for the register, each of the plurality of status bits is reset.

12. An apparatus comprising: A controller configured to couple to a memory device including a memory die, the controller being external to the memory device, wherein the controller is configured to cause the device to: A polling request for a tag stored in the memory device is transmitted to the memory device, wherein the tag is reset in response to the polling request; At least in part based on transmitting the polling request, receive an indication that the flag has been set; Based at least in part on receiving the instruction, an identification mark stored at the memory device indicates the completion of at least one access operation at the memory die, the memory die comprising a plurality of planes, wherein the mark comprises a single bit; Based at least in part on the completion of at least one access operation at the memory die indicated by the marker, a register contained in the memory device and configured to store a plurality of status bits, each status bit corresponding to a corresponding one of the plurality of planes; The completion of the access operation at the first plane is identified at least in part based on polling the register and at least in part based on a first status bit of the register corresponding to the first plane of the plurality of planes indicating the completion of the access operation at the first plane; At least in part, based on recognizing the completion of the access operation at the first plane, a command is transmitted to the memory die to output data associated with the first plane; as well as Data corresponding to the access operation at the first plane is received from the memory die, at least in part, based on the command.

13. The device of claim 12, wherein the controller is further configured to cause the device to: The polling includes multiple tags associated with the markers on the memory die, wherein: Each of the plurality of tags is associated with a corresponding one in a plurality of memory dies; and The controller is configured to enable the device to identify, at least in part, the completion of at least one access operation at the memory die based on polling the plurality of flags.

14. The device of claim 13, wherein the controller is further configured to cause the device to: Based at least in part on polling the plurality of flags, identifying a second flag associated with the second memory die indicates that no access operation has been completed at the second memory die; and At least in part, based on the second flag associated with the second memory die indicating that no access operation has been completed at the second memory die, polling of the second register associated with the second memory die is prevented. The second register is configured to store a second plurality of status bits, each status bit corresponding to a corresponding one in a second plurality of planes contained in the second memory die.

15. The device of claim 13, wherein the controller is further configured to cause the device to: Based at least in part on polling the plurality of markers, a second marker associated with a second memory die is identified to indicate the completion of at least one access operation at the second memory die, the second memory die comprising a second plurality of planes; Based at least in part on the completion of at least one access operation at the second memory die indicated by the second flag, a second register associated with the second memory die and configured to store a second plurality of status bits, each status bit corresponding to a corresponding one in the second plurality of planes; The completion of the second access operation at the second plane is identified at least in part based on polling the second register and at least in part based on a second status bit of the second register corresponding to the second plane in the second plurality of planes indicating the completion of the second access operation at the second plane; Based at least in part on the recognition of the completion of the second access operation at the second plane, a second command is transmitted to the second memory die to output data associated with the second plane; as well as At least in part, based on the second command, data corresponding to the second access operation at the second plane is received from the second memory die.

16. The device of claim 13, wherein, in order to poll the plurality of tags, the controller is configured to cause the device to: Each of the plurality of tags is simultaneously polled via a bus coupled to each of the plurality of memory dies.

17. The device of claim 13, wherein the controller is configured to cause the device to: At least in part, based on polling the plurality of tags, a plurality of indications are simultaneously received via a bus coupled to each of the plurality of memory dies, each of the plurality of indications indicating the value of the corresponding of the plurality of tags.

18. The device of claim 12, wherein the controller is further configured to cause the device to: The completion of the second access operation at the second plane is identified at least in part based on polling the register and at least in part based on a second status bit of the register corresponding to the second plane in the plurality of planes indicating the completion of the second access operation at the second plane; Based at least in part on the recognition of the completion of the second access operation at the second plane, a second command is transmitted to the memory die to output data associated with the second plane; as well as At least in part, based on the second command, data corresponding to the second access operation at the second plane is received from the memory die.

19. The device of claim 12, wherein, in order to receive the data corresponding to the access operation at the first plane, the controller is further configured to cause the device to: The data is received from the memory die via direct memory access operations.

20. The device of claim 12, wherein the controller is further configured to cause the device to: The controller transmits a command to the memory die to perform the access operation at the first plane, wherein, in order to identify the marker associated with the memory die indicating the completion of at least one access operation at the memory die, the controller is further configured to poll the marker associated with the memory die after transmitting the command to perform the access operation at the first plane.

21. The device of claim 12, wherein the access operation at the first plane includes a snapshot read operation at the first plane.

22. A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to: A first status bit of a register is set based at least in part on the completion of an access operation at a first plane of a plurality of planes of a memory die of a memory device, wherein the register is contained in the memory device and configured to store a plurality of status bits, each status bit corresponding to a corresponding one of the plurality of planes, and wherein the first status bit corresponds to the first plane. Based at least in part on the completion of the access operation at the first plane, a flag indicating the completion of at least one access operation at the memory die is set and stored at the memory device, wherein the flag comprises a single bit; After setting the flag indicating the completion of the at least one access operation, a polling request for the flag is received from a controller outside the memory device; In response to the polling request for the flag, an indication that the flag has been set is output to the controller; In response to the polling request for the flag, the flag is reset; The controller receives a command to output data associated with the first plane, based at least in part on the setting of the flag indicating the completion of at least one access operation; as well as At least in part, based on the command, data corresponding to the access operation at the first plane is output to the controller.

23. The non-transitory computer-readable medium of claim 22, wherein the instructions are further executable by the processor to: When the tag associated with the memory die is set, the second status bit of the register corresponding to the second plane is set at least in part based on the completion of the second access operation at the second plane of the plurality of planes; A second command is received from the controller to output data associated with the second plane, based at least in part on the setting of the flag indicating the completion of at least one access operation; as well as At least in part, based on the second command, data corresponding to the second access operation at the second plane is output to the controller.

24. The non-transitory computer-readable medium of claim 23, wherein the instructions are further executable by the processor to: Based at least in part on the completion of the second access operation at the second plane, it is determined whether the flag indicating the completion of at least one access operation at the memory die is set.

Images