Adjusting read level threshold based on write to write latency

Abstract

The present disclosure relates to adjusting read level thresholds based on writes. A method includes performing a first write operation to write data to a first memory cell of a group of memory cells in a memory device; determining a write-to-write (W2W) delay based on a time difference between the first write operation and a second write operation to a memory cell in the group of memory cells, where the second write operation occurs before the first write operation; identifying a threshold time criterion that is satisfied by the W2W delay; identifying a first read voltage level associated with the threshold time criterion; and associating the first read voltage level with a second memory cell of the group of memory cells. The second memory cell can be associated with a second read voltage level that satisfies a selection criterion based on a comparison of the second read voltage level to the first read voltage level.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to adjusting read level thresholds in memory subsystems based on write-to-write latency. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. These memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, this disclosure relates to a system comprising: a memory device including a group of memory cells; and a processing means operatively coupled to the memory device to perform operations including: performing a first write operation to write data to a first memory cell of the group of memory cells; determining a write-to-write (W2W) latency based on a time difference between the first write operation and a second write operation to a memory cell in the group of memory cells, wherein the second write operation occurs prior to the first write operation; identifying a threshold time criterion satisfied by the W2W latency; identifying a first read voltage level associated with the threshold time criterion; and associating the first read voltage level with a second memory cell of the group of memory cells.

[0004] In another aspect, this disclosure relates to a method comprising: performing a first write operation by a processing means to write data to a first memory cell of a group of memory cells; determining a write-to-write (W2W) time based on the first write operation and a second write operation occurring prior to the first write operation; identifying a threshold time criterion satisfied by the W2W delay in a data structure, wherein the data structure includes an association between the threshold time criterion and a first read voltage level; identifying a second read voltage level associated with a second memory cell of the group of memory cells; and setting the second read voltage level associated with the second memory cell to the value of the first read voltage level in response to determining that the second read voltage level is less than the first read voltage level.

[0005] In another aspect, this disclosure relates to a non-transitory computer-readable medium including instructions that, when executed by a processing device, cause the processing device to perform operations including: performing a first write operation to write data to a first memory cell of a group of memory cells; determining a write-to-write (W2W) time based on the first write operation and a second write operation occurring prior to the first write operation; identifying a threshold time criterion satisfied by the W2W delay in a data structure, wherein the data structure includes an association between the threshold time criterion and a first read voltage level; identifying a second read voltage level associated with a second memory cell of the group of memory cells; and setting the second read voltage level associated with the second memory cell to the value of the first read voltage level in response to determining that the second read voltage level is less than the first read voltage level. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This describes an instance of time-voltage shifting in a memory device according to some embodiments.

[0009] Figure 3 This describes an instance memory cell group and associated metadata containing write timestamps and read level tags, according to some embodiments.

[0010] Figure 4A This is a flowchart of an example method, according to some embodiments, for associating a read voltage level with a memory cell based on a W2W delay.

[0011] Figure 4B This is a flowchart of an example method, according to some embodiments, for associating a read level tag with a memory cell based on W2W delay.

[0012] Figure 4C This is a flowchart of an example method for reading data from a memory cell using a read voltage level associated with the memory cell, according to some embodiments.

[0013] Figure 4D This is a flowchart of an example method for reading data from a memory cell using a read level tag associated with the memory cell, according to some embodiments.

[0014] Figure 5A This describes how, according to some embodiments, threshold time criteria are mapped to a table of read level tags.

[0015] Figure 5B This describes a table that maps read level tags to read voltage levels according to some embodiments.

[0016] Figure 5C This describes how, according to some embodiments, threshold time criteria are mapped to a table of read voltage levels.

[0017] Figure 6 This describes the instance read voltage level generated in response to a write operation according to some embodiments.

[0018] Figure 7 This is a block diagram of an example computer system in which embodiments of this disclosure may operate. Detailed Implementation

[0019] Various aspects of this disclosure relate to read voltage adjustment of memory cells in a memory subsystem based on write-to-write latency. The memory subsystem may be a storage device, a memory module, or a combination of both. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem, which includes one or more components, such as memory devices for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0020] The memory subsystem may include high-density non-volatile memory devices where data needs to be retained when no power is supplied to the memory device. One example of a non-volatile memory device is a three-dimensional cross-point (“3D cross-point”) memory device containing an array of non-volatile memory cells. The 3D cross-point memory device can combine a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Another example is a NAND memory device. The following section will combine... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logical states associated with the number of bits being stored. Logical states may be represented by binary values ​​(e.g., “0” and “1”) or combinations of such values.

[0021] Memory devices can be composed of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are etched onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line can refer to one or more rows of memory cells in a memory device, which are used in conjunction with one or more bit lines to generate the address of each memory cell. The intersection of bit lines and word lines constitutes the address of a memory cell. Hereinafter, a block refers to a cell of a memory device used to store data and can contain groups of memory cells, groups of word lines, word lines, or individual memory cells. One or more blocks can be grouped together to form a plane of a memory device to allow concurrent operation on each plane. A memory device can be referred to as a "drive" and has multiple dies layered in multiple "stacks".

[0022] A read operation can be performed using a signal with a read voltage level (e.g., a word line applied to a memory array). The read threshold voltage level or value (here, "read voltage level") can be a specific voltage applied to a memory cell of the memory device to read data stored at that memory cell. For example, if the threshold voltage of a particular memory cell is identified as being below the read voltage level applied to that memory cell, the data stored at that memory cell can be a specific value (e.g., '1'), and if the threshold voltage of a particular memory cell is identified as being above the read voltage level, the data stored at that memory cell can be another value (e.g., '0'). Therefore, a read voltage level can be applied to a memory cell to determine the value stored at that memory cell.

[0023] In some memory subsystems, when the programmed threshold voltage distribution of a memory cell changes, using the same read voltage level for a read operation may result in read errors, leading to retries and degrading system performance. For example, a memory cell may be programmed to have a threshold voltage lower than the read voltage level. This programmed threshold voltage can change over time and may transition to a level higher than the read voltage level. For instance, the threshold voltage of a memory cell may change from initially being lower than the read voltage level to being higher than it. Therefore, when a read voltage level is applied to the memory cell, the data stored at the memory cell may be misread or misinterpreted as an incorrect value compared to the initially stored value before the threshold voltage transition.

[0024] For certain memory types (i.e., for memory subsystems employing certain types of storage media), the error rate can change over time. Specifically, some non-volatile memories have a threshold voltage programming distribution that shifts or "drifts" higher over time. At a given read voltage level (i.e., the value of the voltage applied to a memory cell as part of a read operation), if the threshold voltage programming distribution shifts, certain reliability statistics may also be affected. One example of a reliability statistic is the bit error rate (BER). BER can be defined as the ratio of the number of erroneous bits to the total number of data bits stored in a cell within a memory subsystem, where a cell can be the entire memory subsystem, the die of a memory device, a collection of codewords, or any other meaningful part of the memory subsystem.

[0025] Some memory subsystems can mitigate the effects of voltage drift by performing read cleanup operations on media cells. Read operations refresh media cells, thereby reducing cell voltage drift. For example, a memory subsystem can perform read operations on each cell of the memory system at periodic intervals (e.g., every 3 hours). Read cleanup operations push down the threshold voltage programming distribution to mitigate voltage drift. Read cleanup operations can be performed as background operations, such as operations with lower priority than normal read and write operations that the memory subsystem can perform when other operations are idle. However, read cleanup can degrade system performance, for example, by reducing quality of service metrics such as read or write latency. Furthermore, read cleanup can introduce read interference, where a read operation performed on a particular cell can cause nearby cells to change over time. Read interference can lead to read errors and data loss. Some memory subsystems can also manage voltage drift by adjusting the read voltage levels of all memory cells in a group based on the amount of time elapsed since the last write to a memory cell in the group. However, such techniques do not account for the different aging processes of different memory cells in the group and generally do not improve performance under heavy workloads or short drift times.

[0026] The present disclosure addresses the above and other drawbacks by using read voltage adjustment techniques, wherein the memory subsystem adjusts the read voltage level based on write-to-write latency. The memory subsystem maintains a read voltage level for each memory cell (e.g., a memory page) in a group of memory cells. The read voltage level may have values ​​such as 0, 1, 2, 3, etc., each of which corresponds to a read voltage level that can be used in a read operation on the memory cell associated with that read voltage level. Therefore, in order to read data from a memory cell, the memory subsystem may access the read voltage level associated with the memory cell, identify the read voltage level associated with that read voltage level, and perform a read operation based on the identified read voltage level.

[0027] Because each read voltage level consumes a relatively small amount of memory (e.g., 1 or 2 bits), and the memory subsystem can efficiently store and update thousands of read voltage levels corresponding to thousands of memory pages. Read voltage level 0 can represent the lowest read voltage and can be the initial read level for a memory cell that has recently been written to or does not contain valid data. Read voltage level 1 can represent a higher read voltage for an older memory cell that was written to in the past for a period of time greater than a threshold (e.g., with a write-to-write latency greater than a threshold). Read voltage level 2 can represent an even higher read voltage for an even older memory cell, and so on. The sequentially numbered read levels can represent sequentially higher read voltages corresponding to progressively older memory cells.

[0028] As time progresses and write operations are performed on individual memory cells, the memory subsystem can update the read voltage level of each memory cell to reflect the amount of time that has elapsed since the write operation was performed on the memory cell. The memory subsystem can update the read voltage level associated with the memory cell according to a threshold aging criterion, such as a threshold time value or range. For example, the memory subsystem can update the read voltage level in response to a write operation. Each read voltage level can be updated by the memory subsystem in response to the threshold aging criterion being met by a write-to-write (W2W) delay of a write operation performed on any memory cell in the group of memory cells. If the threshold aging criterion associated with a higher read voltage level is met, the read voltage level associated with the memory cell can be changed to a higher read voltage level (e.g., corresponding to a higher read voltage value, such as 0.3 volts), or the read voltage level associated with the memory cell can be reset to the lowest read voltage level in response to a write operation performed on the memory cell associated with the read voltage level.

[0029] The advantages of this disclosure include, but are not limited to, improved performance resulting from improved data integrity. Read error rates and read retry rates are reduced by adjusting the read voltage level to compensate for voltage drift. Storing the read voltage level for each memory cell increases performance under heavy workloads and drift time over short to long drift time ranges because the read voltage level for each memory cell can be determined based on the time per memory cell since it was written to a particular memory cell. Because the read voltage level is small (e.g., one or two bits), storing the read level per memory cell is more efficient than alternatives such as storing a timestamp or read voltage level for each memory cell. Furthermore, adjusting the read voltage level reduces or eliminates the need for read refresh operations, thereby reducing read interference effects.

[0030] Figure 1This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0031] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0032] The computing environment 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. The host system 120 uses the memory subsystem 110 to, for example, write data to and read data from the memory subsystem 110. As used herein, “coupled to” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intervening component), whether wired or wireless, and includes connections such as electrical, optical, and magnetic connections.

[0033] Host system 120 may be a computing device, such as a desktop computer, laptop computer, network server, mobile device, vehicle (e.g., airplane, drone, train, car, or other means of transportation), Internet of Things (IoT) device, embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment, or networked business device), or such computing device containing memory and processing power. Host system 120 may be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 may further utilize an NVM Fast (NVMe) interface to access memory components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120.

[0034] The memory device may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. The volatile memory device (e.g., memory device 140) may be, but is not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0035] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory. The crosspoint array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on variations in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them.

[0036] Although non-volatile memory components such as 3D cross-point memory are described, memory device 130 can be based on any other type of non-volatile memory, such as NAND, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0037] One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory component may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. Memory cells of the memory device 130 may be grouped into pages or codewords, which may refer to logical units of the memory device used for storing data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks. Some types of memory (e.g., 3D cross-connects) may group pages across the die and channels to form management units (MUs).

[0038] The memory subsystem controller 115 can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-decoded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0039] The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0040] In some embodiments, local memory 119 may include memory registers that store memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0041] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to enable the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations associated with the memory device 130, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, caching operations, and address translation between logical block addresses and physical block addresses. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0042] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache memory or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0043] In some embodiments, memory device 130 includes a local media controller 135, which operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0044] The memory subsystem 110 includes a read level management component 113, which is used to adjust the read voltage level representing the read voltage level of a memory cell and to read data from the memory cell using the read voltage determined from the read voltage level. The read voltage level identifies the read voltage level to be used when reading cells of an associated memory cell. The read voltage level may have values ​​such as 0, 1, 2, 3, etc., each of which represents a read level and corresponds to a read voltage. As time progresses and write operations are performed on individual memory cells, the memory subsystem updates the read voltage level associated with each memory cell to reflect the amount of time voltage shift, so that read operations use a read level adjusted to compensate for the voltage shift. Further details relating to the operation of the read voltage adjustment component 113 are described below.

[0045] Figure 2 This describes an example of time-shifted voltage in a memory device according to some embodiments. The graph 200 shows a SET voltage distribution 202A corresponding to a programmed value such as 0, and a RESET voltage distribution 204A corresponding to a programmed value such as 1. The horizontal (volt) axis represents the voltage value, increasing to the right. During a certain time period, the initial SET distribution 202A has drifted to the shifted SET distribution 202B. The memory device 130 may be in a power-off state for at least a portion of the time period. The amount of voltage shift between SET distributions 202A and 202B is labeled "power-off SET drift". Similarly, the initial RESET distribution 204A has drifted to the shifted RESET distribution 204B during the same time period. The amount of voltage shift between RESET distributions 204A and 204B is labeled "power-off RESET drift". The threshold read voltage level (not shown) that divides the shifted SET distribution 202B and the shifted RESET distribution 204B has also been shifted. Due to the difference between the applied read voltage and the shift threshold voltage, reading data using a read voltage level that is not adjusted to compensate for the time voltage shift may result in read errors. The initial RESET cell select bias VSEL 206A has also drifted to the shifted RESET cell select bias VSEL 206B, as indicated by the label "RESET cell select bias drift". Because the RESET cell select bias has drifted to the higher voltage VSEL206B, the amount of voltage required to select the RESET cell to write data has also increased.

[0046] Figure 3 This describes instance group 302 of memory cells 304, 314 according to some embodiments and associated metadata 306 including write timestamp 308 and read level tag 320. For example... Figure 3As shown, the memory subsystem 300 includes a memory device 130 and metadata 306. The memory subsystem 300 corresponds to... Figure 1 The memory subsystem 110. Metadata 306 may be stored on the memory device 130 or other storage media (not shown). For example, metadata 306 may be generated and updated by the read level management component 113 of the memory subsystem 300. Although regarding Figure 6 The description of the instance metadata refers to the read level tag stored in the metadata, but the description also applies to storing the read level voltage in the metadata to replace or supplement the read level tag.

[0047] Memory device 130 may include cells arranged in memory cells 304, 314. A memory cell may be a collection of codewords, such as a page, or any other meaningful portion of a memory subsystem. Memory cells 304, 314 may be arranged in group 302. Figure 3 In this example, the first group 302A of memory cells 304 includes memory cells 304A and 304B through 304N. Furthermore, the second group 302B of memory cells 314 includes memory cells 314A and 314B through 314N. Each memory cell group 302 is associated with a write timestamp 308 stored in metadata 306. More specifically, the first group 302A of memory cells is associated with a first write timestamp 308A, and the second group 302B of memory cells is associated with a second write timestamp 308B. Each write timestamp 308 may specify the time when data is written to the memory cell 304 in the associated group 302. A data write operation may, for example, program a memory cell by writing data stored in the memory cell 304 to a different memory cell. Therefore, a data write operation has the effect of resetting the voltage threshold of the memory cell to an initial (e.g., pre-shifted) value. The write timestamp 308 indicates the time when the voltage shift of memory cell 304 in group 302 begins, so the time difference between the current time and the write timestamp represents the amount of time the voltage shift has occurred. Therefore, the time difference is related to the amount of time the threshold voltage (e.g., the read voltage level) has shifted.

[0048] Metadata 306 associates a set of read level tags with each memory cell group 302. Each read level tag 310A, 310B, 310N in the set of read level tags 310 is associated with a corresponding memory cell 304A, 304B, 304N in the first memory cell group 302A. 304. Each read level tag may correspond to a read voltage level. For example, read level tag 310B may have a value "0" to indicate that the read voltage level of the associated memory cell 304A is a specific value, such as 0.1 volts. Read level tag 310B may have a value "1" to indicate that the read voltage level of the associated memory cell 304B is a different specific value, such as 0.2 volts. Read level tags 310 may be reset to an initial value corresponding to an initial (e.g., lowest) read voltage level in response to a write operation performed on the associated memory cell 304. For example, if the read level tag "0" corresponds to the initial read voltage level, the read level management component 113 can set the read level tag 310A associated with the memory cell 304A in response to a write operation performed on the memory cell 304A. Furthermore, the write timestamp 308A associated with the first group 302A can be updated to reflect the time when the write operation on the memory cell 304A was performed.

[0049] The memory device 130 may include a second group 302B of memory cells 314. Group 302B is associated with a second write timestamp 308B, which specifies the time when data is written to the memory cell 314 in the associated group 302. Each read level tag 320A, 320B, 320N in a set of read level tags 320 is associated with a corresponding memory cell 314A, 314B, 314N in the second memory cell group 302B.

[0050] Figure 4A This is a flowchart of an example method 400 for associating a read voltage level with a memory cell based on a W2W delay, according to some embodiments. Method 400 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1 The read level management component 113 performs the operation. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0051] The read level management component 113 maintains a data structure that maps memory cells to corresponding read voltage levels. Each read voltage level can be a value represented using a small number of bits (e.g., 1, 2, or 3 bits). For example, a 1-bit read voltage level can be one of two read voltage levels (level 1 and level 2). A 2-bit read voltage level can be one of four read voltage levels (levels 1, 2, 4, and 4). A read voltage level represented using a small number of bits (e.g., fewer bits than a value such as an integer or floating-point value) may also be referred to herein as a "read level tag". The read voltage level can alternatively be a voltage value used for a read operation, such as 0.2 volts or other values. In some embodiments, a read level tag can be represented using fewer bits than a read voltage level, and the read level tag can be associated with each memory cell. Each read level tag can be mapped to a corresponding read voltage level via a mapping data structure, in which case each read voltage level can be a numerical level identifier (e.g., level 1, level 2, and so on) or a voltage value (e.g., 0.2 volts or other values). Numerical level identifiers can be mapped to voltage values ​​via a mapping table. In other embodiments, the read voltage level, which serves as a numerical level identifier, can be associated with each memory cell, and a mapping table can be used to map the numerical level identifier to a voltage value to perform a read operation.

[0052] The read level management component 113 can initially set the read voltage level of each memory cell to an initial read voltage level for a write operation, for which the write-to-write time is less than a threshold time. For example, the initial read level can be used when reading from the most recently written memory cell. The initial read voltage level can be the base read level of the memory device. "Base read level" will be referred to herein as the initial threshold voltage level exhibited by the memory cell immediately following programming. In some embodiments, the base read level may be stored in the metadata of the memory device 130.

[0053] At operation 402, the processing device performs a write operation to write data to a first memory cell 304A of a group of memory cells. The first memory cell 304A may be in a group of memory cells 302A, which also includes one or more second memory cells 304B. For example, the processing device may receive a request from the host system 120. The request may specify data and a memory location (e.g., address) in memory cell 304A where the write operation will store the specified data. The write operation may store the specified data in one or more memory cells of the first memory cell 304A.

[0054] At operation 404, the processing device determines a write-to-write (W2W) delay based on the time difference between the first write operation and the second write operation to a memory cell in the memory cell group, such that the second write operation occurs before the first write operation. The W2W delay can represent the amount of time that has elapsed since the most recent write to any memory cell in the memory cell group. The W2W delay can be determined as the difference between the time when the write operation was performed (e.g., the current time) and a write timestamp representing the time when the most recent write operation was performed to any memory cell in the memory cell group. The write timestamp can be stored in the metadata of the memory subsystem and associated with the memory cell group. Whenever a write operation is performed on a memory cell in the group, the memory subsystem can update the write timestamp to reflect the time when the write operation was performed (e.g., the current time).

[0055] At operation 406, the processing device identifies a threshold time criterion satisfied by the W2W delay. The processing device may use a data structure to identify reference labels, where each record contains a threshold time criterion. Each threshold time criterion can be a condition that results in a true (if the condition is met) or false (if the condition is not met) outcome when evaluating for a specified W2W delay. The processing device may search the data structure to find records that have a threshold time criterion satisfied by the W2W delay. If the data structure contains a matching record (e.g., a record with a threshold time criterion satisfied by the W2W delay), then the threshold time criterion is or corresponds to the threshold time criterion satisfied by the W2W delay.

[0056] At operation 408, the processing device identifies a first read voltage level associated with a threshold time criterion satisfied by the W2W delay. If the data structure searched at operation 406 contains a matching record (e.g., a record with the threshold criterion satisfied by the W2W delay), the identified first read level is specified by a reference tag contained in the matching record. An instance data structure containing entries mapping the threshold criterion to read voltage levels is... Figure 5C It is displayed in the middle.

[0057] Multiple thresholds can be used, in which case the read voltage level can be selected from more than two read voltage levels. For example, if the write-to-write time is less than a first threshold time, the read voltage level can be set to a first read voltage level; if the write-to-write time is between a first threshold time and a second threshold time, the read voltage level can be set to a second (e.g., higher) read voltage level; and if the write-to-write time is greater than or equal to the second threshold time, the read voltage level can be set to a third (e.g., higher) read voltage level.

[0058] At operation 410, the processing device identifies a second memory cell in the memory cell group, wherein the second memory cell is associated with a second read voltage level that satisfies a selection criterion, and wherein the selection criterion is based on a comparison of the second read voltage level with a first read voltage level. The selection criterion is satisfied if, for example, the second read voltage level label is less than a reference label. Operation 410 can identify each of the second memory cells in the memory group other than the first memory cell (to which a write operation is performed at operation 402). Since the first memory cell is written at operation 402, the read voltage level associated with the first memory cell can be reset to an initial (e.g., base) read voltage level.

[0059] At operation 412, the processing device associates a first read voltage level with a second memory cell. The processing device may, for example, store a record in a data structure that maps a memory cell identifier to a read voltage level. The record may associate a memory cell identifier of the second memory cell with the first read voltage level. The record may replace an existing record that associates a memory cell identifier with a different read voltage level (e.g., a previously associated read voltage level). The associated read voltage level can be used relative to the following context: Figure 4C and 4D In the described read operation.

[0060] Figure 4B This is a flowchart of an example method 420 for associating a read level tag with a memory cell and updating a write timestamp according to some embodiments. Method 420 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 420 is performed by… Figure 1 The read level management component 113 performs the operation. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible. Although the description of method 420 refers to a read level label that can be mapped to a read voltage level, method 420 may alternatively be used to associate a read voltage level with a memory cell. The read voltage level may be a read level identifier (e.g., represented using a small number of bits) or a voltage value (e.g., 0.2 volts).

[0061] At operation 422, the processing device initializes read level tags and write timestamps for the memory cell group. Operation 422 can be performed in response to, for example, a formatting operation or a group-level write operation applied to each memory cell in the group. Each memory cell can be associated with a read level tag, and each read level tag can be set to an initial tag value when the memory cell has been recently written to, resulting in low voltage drift. The initial tag value can be read level tag 0, which may represent the lowest read voltage, for example, the base read level of memory device 130.

[0062] At operation 424, the processing device, in response to a write request, performs a write operation to write specified data to a first memory cell in a group of memory cells, the group of memory cells also including one or more second memory cells. At operation 426, the processing device sets the read level tag associated with the first memory cell to an initial tag value. The initial tag value may correspond to a base read level because the voltage drift of the memory cells in the memory cell is typically reduced by the write operation performed at operation 424.

[0063] At operation 428, the processing device determines the write-to-write (W2W) latency based on the difference between the current time and the write timestamp associated with the memory cell group. The W2W latency can represent the amount of time elapsed between a first write operation performed on a memory cell in the memory cell group and a second write operation performed on any memory cell in the memory cell group that was the most recent write before the first write operation.

[0064] The W2W latency of a memory cell can be determined for a specific write operation based on the difference between the time the write operation was performed and the write timestamp associated with the group of memory cells containing the memory cell. The write timestamp indicates the time when the most recent previous write operation was performed on the group of memory cells. For example, the write timestamp may be stored in metadata. The write timestamp may initially be the time when, for example, a drive format operation or other write operation (e.g., a group-level write operation) affecting all memory cells in the group of memory cells was performed. Whenever a write operation is performed on any memory cell in the group of memory cells, the write timestamp associated with the group can be updated.

[0065] At operation 430, the processing device identifies a reference label corresponding to the W2W delay. The processing device may identify the reference label using a data structure where each record contains a threshold time criterion and a reference label. Each threshold time criterion may be a condition that results in a true (if the condition is met) or false (if the condition is not met) outcome when evaluating for a specified delay time. The condition may contain one or more thresholds. For example, the condition is met if the specified delay time is greater than a threshold. As another example, the condition is met if the specified delay time is between two thresholds. The processing device may search the data structure to find records that have a threshold time criterion satisfied by the W2W delay time determined at operation 428. If the data structure contains a matching record (e.g., a record with a threshold criterion satisfied by the W2W delay), the identified reference label is specified by the reference label contained in the matching record. Instance data structures containing entries mapping threshold criteria to reference labels are described in... Figure 5A and 5C It is displayed in the middle.

[0066] At operation 432, the processing device identifies one of the second memory cells in the memory cell group. Operation 432 can iterate over the memory cells in the memory cell group, for example by selecting a different memory cell each time operation 432 is performed via method 420. Thus, operation 432 causes a subsequent operation (434) to be performed for each memory cell in the memory cell group. For each of the second memory cells in the group, method 420 can set the associated existing read level tag to the reference tag if a reference tag corresponding to a write-to-write (W2W) delay satisfies a threshold criterion. In one instance, if the existing read level tag is less than the reference tag, a selection criterion is satisfied such that existing read level tags greater than or equal to the reference tag are not updated. Therefore, the relatively short W2W delay mapped to the lower value read level tag does not cause the read level management component 113 to change the higher value read level tag (which corresponds to a larger voltage shift) to the lower value read level tag.

[0067] At operation 434, the processing device determines whether the read level tag of the identified memory cell is less than a reference tag. If so, at operation 436, the processing device updates the read level tag associated with the identified memory cell to the reference tag. The processing device may, for example, store a record in a data structure that maps memory cell identifiers to read level tags. The record may associate the memory cell identifier of one of the second memory cells with the reference tag. The record may replace an existing record that associates the memory cell identifier with a different tag (e.g., a selected read level tag). If at operation 422, the processing device determines that the read level tag of the identified memory cell is not less than the reference tag, the processing device continues operation at operation 438.

[0068] At operation 438, the processing device determines whether there is a next unprocessed second memory cell in the group. If so, at operation 440, the processing device identifies the next unprocessed second memory cell and continues operation at operation 434. The next unprocessed second memory cell may be a memory cell in the memory cell group that has not previously been identified by operation 432 or 440. If at operation 438, the processing device determines that there are no other unprocessed second memory cells in the group, the processing device continues operation at operation 442. At operation 442, the processing device updates the write timestamp associated with the memory cell group, for example, based on the current time, to reflect the time when the write operation of operation 424 was performed.

[0069] Figure 4C This is a flowchart of an example method 450 for reading data from a memory cell using a read voltage level associated with the memory cell, according to some embodiments. Method 450 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 450 is performed by… Figure 1 The read level management component 113 performs the operation. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0070] At operation 452, the processing device receives a request to read from a memory cell. At operation 454, the processing device identifies the read voltage level associated with the memory cell in response to the read request. The processing device may use a data structure that maps memory cells to read voltage levels to identify the read voltage level. An example of such a data structure is... Figure 6 The data structure can be shown in the example. Figure 4A Operation 412 or Figure 4B Operation 436 is generated. The processing device may search a data structure to find a record containing a memory cell identifier corresponding to a memory cell from which data will be read. If a matching record containing the memory cell identifier is found, the identified read voltage level is specified by the read voltage level in the matching record. At operation 456, the processing device reads data from the memory cell according to the identified read voltage level.

[0071] Figure 4D This is a flowchart of an example method 460 for reading data from a memory cell using a read level tag, according to some embodiments. Method 460 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 460 is performed by… Figure 1 The read level management component 113 performs the operation. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0072] At operation 462, the processing device receives a request to read from a memory cell. At operation 464, in response to the request to read from the memory cell, the processing device identifies a read level tag associated with the memory cell. The processing device may use a data structure that maps memory cells to read level tags to identify read level tags. Instances of such data structures are shown in... Figure 6 The data structure can be shown in the example. Figure 4A Operation 412 or Figure 4B Operation 436 is generated. The processing device may search the data structure for a record containing a memory cell identifier corresponding to a memory cell from which data will be read. If a matching record containing the memory cell identifier is found, an associated read level tag is assigned by the matching record.

[0073] At operation 466, the processing device identifies the read voltage level corresponding to the read level tag. The processing device can identify the read voltage level using a data structure that maps read level tags to read voltage levels. An example of such a data structure is... Figure 5B As shown in the diagram, the processing device can search a data structure for a record containing a read level tag identified by operation 464. If a matching record containing the read level tag is found, the associated read voltage level is specified by the matching record. At operation 468, the processing device reads data from the memory cell according to the identified read voltage level.

[0074] Figure 5A Table 500 illustrates, according to some embodiments, the mapping of a threshold time criterion 506 to a read level tag 508. Table 500 is available for the read level management component 510 to identify a reference read level tag 508 corresponding to the threshold time criterion 506. Table 500 contains four records 501-504, each of which maps the threshold time criterion 506 to a read level tag 508. For example, the threshold time criterion 506 and the read level tag 508 can be determined using media characterization information.

[0075] The first record 501 contains a threshold time criterion 506 of "W2W >= 0 seconds and < 1 minute" and a read level tag 508 of 0. Therefore, the first record 501 specifies that the W2W delay time between 0 seconds and 1 minute is mapped to a read level tag with a value of 0. The threshold time criterion 506 of the first record 501 thus contains a lower limit delay threshold of 0 seconds and an upper limit delay threshold of 1 minute. For example, if the W2W delay is 20 seconds, the selected reference read level tag has a value of 0 because the 20-second W2W delay satisfies the threshold time criterion "W2W >= 0 seconds and < 1 minute" associated with the read level tag 0 by record 501.

[0076] The second record 502 contains a threshold time criterion 506 of "W2W >= 1 minute and < 60 minutes" and a read level tag 508 of 1. Therefore, the second record 502 specifies that the W2W delay time between 1 minute and 60 minutes is mapped to a read level tag with a value of 1. The threshold time criterion 506 of the second record 502 thus contains a lower limit delay threshold of 1 minute and an upper limit delay threshold of 60 minutes. The third record 503 contains a threshold time criterion 506 of "W2W >= 60 minutes and < 180 minutes" and a read level tag 508 of 2. Therefore, the third record 503 specifies that the W2W delay time between 60 minutes and 180 minutes is mapped to a read level tag with a value of 2. The fourth record 504 contains a threshold time criterion 506 of "W2W >= 180 minutes" and a read level tag 508 of 3. Therefore, the fourth record 504 specifies that a W2W delay time of 180 minutes or more is mapped to a read level tag with a value of 3.

[0077] Figure 5B Table 515 illustrates the mapping of read level tag 508 to read voltage level 510 according to some embodiments. Table 515 is available for the read level management component 113 to identify the read voltage level 510 corresponding to the threshold time criterion 506. Table 515 contains four records 511-514, each of which maps the read level tag 508 to the read voltage level 510. For example, the read level tag 508 and the read voltage level 510 can be determined using media characterization information.

[0078] The first record 511 contains a read level tag 508 (0) and a read voltage level 510 (VDM1). Therefore, the first record 511 specifies that a read level tag with a value of 0 maps to a read voltage boundary level (“VDM”) 1 (e.g., the value 1 or 0.1 volts). The second record 512 specifies that a read level tag with a value of 1 maps to a read voltage level VDM 2 (e.g., the value 2 or 0.15 volts). The third record 513 specifies that a read level tag with a value of 2 maps to a read voltage level VDM3 (e.g., the value 3 or 0.2 volts). The fourth record 514 specifies that a read level tag with a value of 3 maps to a read voltage level VDM 4 (e.g., the value 4 or 0.25 volts).

[0079] Figure 5CTable 520 illustrates the mapping of a threshold time criterion 506 to a read voltage level 510 according to some embodiments. Table 520 may be used by the read level management component 113 as an alternative to or supplement to tables 500 and 515 to identify the read voltage level 510 corresponding to the threshold time criterion 506. Table 520 contains four records 521-524, each of which maps the threshold time criterion 506 to the read voltage level 510. For example, the threshold time criterion 506 and the read voltage level 510 may be determined using media characterization information.

[0080] The first record 521 contains a threshold time criterion 506 (“W2W >= 0 seconds and < 1 minute”) and a read voltage level 510 (1). Therefore, the first record 521 specifies that the W2W delay time between 0 seconds and 1 minute is mapped to a read voltage level of 1. For example, if the W2W delay is 20 seconds, the selected read voltage level is 1 because a 20-second W2W delay satisfies the threshold time criterion “W2W >= 0 seconds and < 1 minute” associated with the read voltage level 1 via record 521.

[0081] The second record 522 contains a threshold time criterion 506 (“W2W >= 1 minute and < 60 minutes”) and a read voltage level 510 (2). Therefore, the second record 522 specifies that the W2W delay time between 1 minute and 60 minutes is mapped to read voltage level 2. The third record 523 contains a threshold time criterion 506 (“W2W >= 60 minutes and < 180 minutes”) and a read voltage level 510 (3). Therefore, the third record 523 specifies that the W2W delay time between 60 minutes and 180 minutes is mapped to read voltage level 3. The fourth record 524 contains a threshold time criterion 506 (“W2W >= 180 minutes”) and a read voltage level 510 (4). Therefore, the fourth record 524 specifies that a W2W delay time of 180 minutes or more is mapped to read voltage level 3. Although in Figures 5A-5C The example demonstrates a specific threshold time criterion, read level label, and read voltage level, but in other examples, different threshold time criterion, read level label, and read voltage level may be used.

[0082] Figure 6 According to example tables 600-610 of some embodiments, each in the tables maps a memory cell identifier to a read voltage level at a corresponding time. Each of tables 600-610 may represent a mapping between memory cells 304 of a memory cell group and a corresponding read voltage level, or alternatively, a mapping with... Figure 3The mapping between the read level labels 310 is shown in Tables 600-610. Each of these tables shows the result of an operation performed by the read level management component 113 in response to a write operation, updating the read voltage level (or, alternatively, the read level label). Each write operation is associated with a time that occurred, as shown above the tables. Although the following text... Figure 6 The description of the example table refers to the reading voltage level, and the description also applies to tables with reading voltage labels to replace or supplement the reading voltage level.

[0083] Table 600 shows the read voltage levels associated with memory cell identifiers at an initial time T=0 minutes (e.g., before any write operation is performed on the memory cell group after the formatting operation). The memory cell group contains memory cells MU0-MU4. Each memory cell is associated with a read voltage level. At the initial time T=0, no write operation has been performed on the memory cell group. As shown in Table 600, each read voltage level has an initial value, such as 0, at time T=0. Furthermore, at time T=0, the write timestamp associated with the memory cell group has a value of 0, and the W2W delay has an initial value of 0.

[0084] Table 602 shows the read voltage level of the memory cell after a write operation is performed on memory cell MU2. The write operation is performed at time T = 2 minutes. At time T = 2 minutes, the write timestamp is 0, and the W2W delay is 2 minutes (calculated as the time of the write operation (2 minutes) minus the write timestamp (0 minutes)). The read level management component 113 can identify: a first memory cell, which is the memory cell that has data written by the write operation that occurs at T = 2 minutes (MU2 in this example); and one or more second memory cells, which are other memory cells in the group that have not had data written by the write operation that occurs at T = 2 minutes (MU0, MU1, MU3, and MU4). Since data is written to MU2, the read level management component 113 sets the read voltage level associated with MU2 to 0. For the other memory cells in the group, the read level management component 113 uses Figure 5A Table 500 (or alternatively, Figure 5C Table 520 indicates the reference read voltage level. Since the W2W delay is 2 minutes, the threshold time criterion of record 502 is met, and according to Table 500, the reference read voltage level is 1.

[0085] The read level management component 113 updates one or more selected read voltage levels that satisfy the selection criteria. In this example, if the selected read voltage level is less than the reference read voltage level, the selection criteria are satisfied, such that a read voltage level greater than or equal to the reference read voltage level is not updated. Therefore, the relatively short W2W delay mapped to the lower read voltage level does not cause the read level management component 113 to change the higher read voltage level corresponding to a larger voltage shift to the lower read voltage level.

[0086] For Table 602, in order to identify the selected read voltage level, the read level management component 113 evaluates the selection criteria based on the value of each of the second read voltage levels. Before the write operation that occurs at T=2 minutes, the value of each of the second read voltage levels is 0 (as shown in the previous table as Table 600). Since each of the selected read voltage levels is 0, which is less than the reference read voltage level 1, each of the second read voltage levels satisfies the selection criteria, and each second read voltage level is selected for updating. The read level management component 113 updates each selected read voltage level by setting each of the selected read voltage levels to the reference read voltage level (1). Therefore, as shown in Table 602, due to the write operation that occurs at T=2 minutes, the read level management component 113 has generated read voltage levels 1, 1, 0, 1, and 1 for MU0, MU1, MU2, MU3, and MU4, respectively.

[0087] Table 604 shows the read voltage level of the memory cell after a write operation is performed on memory cell MU1. The write operation is performed on MU1 at time T = 65 minutes. At time T = 65 minutes, the write timestamp is 2 minutes (the time when the previous write operation occurred), and the W2W delay is 63 minutes (calculated as the write operation time (65 minutes) minus the write timestamp (2 minutes)). The read level management component 113 can identify: a first memory cell (MU1 in this example) that has data written to it through the write operation that occurred at T = 65 minutes; and one or more second memory cells (MU0, MU2, MU3, and MU4) in the group that did not have data written to them through the write operation that occurred at T = 65 minutes. Because data is written to MU1, the read level management component 113 sets the read voltage level associated with MU1 to 0. For the other memory cells in the group, the read level management component 113 uses... Figure 5A Table 500 identifies the reference read voltage level. Since the W2W delay is 63 minutes, the threshold time criterion of record 503 is met, and according to Table 500, the reference read voltage level is 2.

[0088] According to the selection criteria described above, the read level management component 113 updates each selected read voltage level that is less than the reference read voltage level. The values ​​of the read voltage levels prior to the write operation that occurred at time T=65 are shown in the previous table as Table 602. Therefore, the values ​​of the read voltage levels of the second memory cells prior to the write operations that occurred for MU0, MU2, MU3, and MU4 at T=65 are 1, 1, 1, and 1, respectively. Since each of the second read voltage levels is 1, which is less than the reference read voltage level 2, each of the second read voltage levels satisfies the selection criteria. Therefore, each of the second read voltage levels is selected to be updated. The read level management component 113 updates each selected read voltage level by setting each of the selected read voltage levels to the reference read voltage level (2). As shown in Table 604, due to the write operation that occurred at T=65 minutes, the read level management component 113 has generated read voltage levels 2, 0, 2, 2, and 2 for MU0, MU1, MU2, MU3, and MU4, respectively.

[0089] Table 606 shows the read voltage level of the memory cell after a write operation is performed on memory cell MU2. The write operation is performed on MU2 at time T = 68 minutes. At time T = 68 minutes, the write timestamp is 65 minutes (the time when the previous write operation occurred), and the W2W delay is 3 minutes (calculated as the write operation time (68 minutes) minus the write timestamp (65 minutes)). The read level management component 113 can identify: a first memory cell (MU2 in this example) that has data written to it through the write operation that occurred at T = 68 minutes; and one or more second memory cells (MU0, MU1, MU3, and MU4) in the group that did not have data written to them through the write operation that occurred at T = 68 minutes. Because data is written to MU2, the read level management component 113 sets the read voltage level associated with MU2 to 0. For the other memory cells in the group, the read level management component 113 uses... Figure 5A Table 500 identifies the reference read voltage level. Since the W2W delay is 3 minutes, the threshold time criterion of record 502 is met, and according to Table 500, the reference read voltage level is 1.

[0090] According to the selection criteria described above, the read level management component 113 updates each selected read voltage level that is less than the reference read voltage level. The values ​​of the read voltage levels prior to the write operation that occurred at time T=68 are shown in the previous table as Table 604. In this example, the values ​​of the read voltage levels of the second memory cells prior to the write operations that occurred at T=68 for MU0, MU1, MU3, and MU4 are 2, 0, 2, and 2, respectively. The read voltage levels less than the reference read voltage level of 1 satisfy the selection criteria. Only read voltage levels less than 1 are the read voltage levels associated with MU1. The read level management component 113 updates the read voltage level associated with MU1 by setting the read voltage level associated with MU1 to the reference read voltage level (1). Therefore, as shown in Table 606, due to the write operation that occurred at T=68 minutes, the read level management component 113 has generated read voltage levels of 2, 1, 0, 2, and 2 for MU0, MU1, MU2, MU3, and MU4, respectively.

[0091] Table 608 shows the read voltage level of the memory cell after a write operation is performed on memory cell MU3. The write operation is performed on MU3 at time T = 268 minutes. At time T = 268 minutes, the write timestamp is 68 minutes (the time when the previous write operation occurred), and the W2W delay is 200 minutes (calculated as the write operation time (268 minutes) minus the write timestamp (68 minutes)). The read level management component 113 can identify: a first memory cell (MU3 in this example) that has data written to it through the write operation that occurred at T = 268 minutes; and one or more second memory cells (MU0, MU1, MU2, and MU4) in the group that have not had data written to them through the write operation that occurred at T = 268 minutes. Because data is written to MU3, the read level management component 113 sets the read voltage level associated with MU3 to 0. For the other memory cells in the group, the read level management component 113 uses... Figure 5A Table 500 identifies the reference read voltage level. Since the W2W delay is 200 minutes, the threshold time criterion of record 504 is met, and according to Table 500, the reference read voltage level is 3.

[0092] According to the selection criteria described above, the read level management component 113 updates each selected read voltage level that is less than the reference read voltage level. The values ​​of the read voltage levels prior to the write operation that occurred at time T=268 are shown in the previous table as Table 606. Therefore, the values ​​of the read voltage levels of the second memory cells prior to the write operations that occurred for MU0, MU1, MU2, and MU4 at T=268 are 2, 1, 0, and 2, respectively. Since each of the second read voltage levels is less than the reference read voltage level 3, each of the second read voltage levels satisfies the selection criteria. Therefore, each of the second read voltage levels is selected to be updated. The read level management component 113 updates each selected read voltage level by setting each of the selected read voltage levels to the reference read voltage level (3). As shown in Table 608, due to the write operation that occurred at T=268 minutes, the read level management component 113 has set the read voltage levels to 3, 3, 3, 0, and 3 for MU0, MU1, MU2, MU3, and MU4, respectively.

[0093] Table 610 shows the read voltage level of the memory cell after a write operation is performed on memory cell MU4. The write operation is performed on MU4 at time T = 338 minutes. At time T = 338 minutes, the write timestamp is 268 minutes (the time of the previous write operation), and the W2W delay is 70 minutes (calculated as the time of the write operation (338 minutes) minus the write timestamp (268 minutes)). The read level management component 113 can identify: a first memory cell (MU4 in this example) that has data written to it through the write operation that occurred at T = 338 minutes; and one or more second memory cells (MU0, MU1, MU2, and MU3) in the group that have not had data written to them through the write operation that occurred at T = 338 minutes. Because data is written to MU4, the read level management component 113 sets the read voltage level associated with MU4 to 0. For the other memory cells in the group, the read level management component 113 uses... Figure 5A Table 500 identifies the reference read voltage level. Since the W2W delay is 80 minutes, the threshold time criterion of record 503 is met, and according to Table 500, the reference read voltage level is 2.

[0094] According to the selection criteria described above, the read level management component 113 updates each selected read voltage level that is less than the reference read voltage level. The values ​​of the read voltage levels prior to the write operation that occurred at time T=338 are shown in the previous table as Table 608. In this example, the values ​​of the read voltage levels of the second memory cells prior to the write operations that occurred at T=338 for MU0, MU1, MU2, and MU3 are 3, 3, 3, and 0, respectively. The read voltage levels less than the reference read voltage level of 2 satisfy the selection criteria. Only the read voltage levels less than 2 are the read voltage levels associated with MU3 (with read voltage level 0). The read level management component 113 updates the read voltage level associated with MU3 by setting the read voltage level associated with MU3 to the reference read voltage level (2). Therefore, as shown in Table 610, due to the write operation that occurred at T=33 minutes, the read level management component 113 has generated read voltage levels of 3, 3, 3, 2, and 0 for MU0, MU1, MU2, MU3, and MU4, respectively.

[0095] Figure 7 An example machine illustrating computer system 700 is described, within which an instruction set for causing the machine to perform any one or more of the methods discussed herein is executable. In some embodiments, computer system 700 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110, or may be used to perform controller operations (e.g., execute an operating system to perform operations corresponding to...). Figure 1 (Operation of the read level management component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0096] A machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or bridge, a digital or non-digital circuit system, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by that machine. Furthermore, while a single machine is described, the term "machine" should also be understood to include any set of machines that individually or collectively execute a set (or sets of sets) of instructions to perform any one or more of the methods discussed herein.

[0097] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 706 (e.g., flash memory, static random access memory (SRAM)), and a data storage system 718, which communicate with each other via a bus 730.

[0098] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 702 is configured to execute instructions 726 to perform the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 for communication via network 720.

[0099] Data storage system 718 may include machine-readable storage medium 724 (also referred to as computer-readable medium) on which one or more instruction sets 726 or software embodying any one or more of the methods or functions described herein are stored. The instructions 726 may also reside wholly or at least partially within main memory 704 and / or processing device 702 during execution by computer system 700, which also constitute machine-readable storage medium. Machine-readable storage medium 724, data storage system 718, and / or main memory 704 may correspond to... Figure 1 The memory subsystem 110.

[0100] In one embodiment, instruction 726 includes instructions for implementing a component corresponding to the read voltage adjustment (e.g., Figure 1 The read level management component 113) provides functional instructions. Although the machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0101] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithms are described and represented in a way that those skilled in the art of data processing can most effectively communicate the essence of their work to others skilled in the art. Algorithms are, and are generally considered, a self-consistent sequence of operations that produce a desired result. These operations are those that require physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0102] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0103] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0104] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of this disclosure as described herein.

[0105] This disclosure may be provided as a computer program product or software, which may include machine-readable media on which instructions are stored for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any means for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0106] In the foregoing description, embodiments of this disclosure have been described with reference to specific examples thereof. It will be apparent that various modifications can be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be considered illustrative rather than restrictive.

Claims

1. A system comprising: A memory device comprising a group of memory cells; as well as A processing device operatively coupled to the memory device to perform operations including: Perform a first write operation to write data to a first memory cell in the group of memory cells; The write-to-write W2W latency is determined based on the time difference between the first write operation and a second write operation to a memory cell in the memory cell group, wherein the second write operation occurs before the first write operation. Identify the threshold time criterion that the W2W delay satisfies; Identify the first read voltage level associated with the threshold time criterion; and Associating the first read voltage level with a second memory cell in the memory cell group.

2. The system according to claim 1, wherein the operation further comprises: Before associating the first read voltage level with the second memory cell, the second memory cell is identified, wherein the second memory cell is associated with a second read voltage level that satisfies a selection criterion, and wherein the selection criterion is based on a comparison of the second read voltage level with the first read voltage level.

3. The system of claim 2, wherein if the second read voltage level is less than the first read voltage level, then the second read voltage level satisfies the selection criterion.

4. The system according to claim 1, wherein the operation further comprises: In response to performing the write operation, the base read level of the memory device is associated with the first memory cell.

5. The system of claim 1, wherein a data structure comprising a plurality of records is used to identify the threshold time criterion, each record mapping the threshold time criterion to a corresponding read voltage level.

6. The system of claim 5, wherein the threshold time criterion for identifying the W2W delay comprises: The data structure identifies records that include a specific threshold time criterion satisfied by the W2W delay, wherein the identified threshold time criterion is based on the specific threshold time criterion.

7. The system of claim 6, wherein identifying the record in the data structure that includes the specific threshold time criterion satisfied by the W2W delay comprises: The W2W delay is compared with a threshold associated with the specific threshold time criterion.

8. The system of claim 1, wherein the operation further comprises: Receive a request to read from a specified memory location; In response to the request to read from the specified memory cell, the read voltage level associated with the specified memory cell is identified; as well as Data is read from the designated memory cell according to the read voltage level.

9. The system of claim 8, wherein a data structure comprising a plurality of records is used to identify the read voltage level associated with the specified memory cell, each record mapping the memory cell to a corresponding read voltage level.

10. The system of claim 9, wherein identifying the read voltage level associated with the designated memory cell includes: The data structure identifies a record that includes a specific memory cell identifier corresponding to the specified memory cell, wherein the record maps the specific memory cell identifier to a specific read voltage level, and the identified read voltage level is based on the specific read voltage level.

11. The system of claim 1, wherein the W2W latency is determined based on the time difference between the time of performing the first write operation and the time of performing the second write operation on the memory cells of the memory cell group.

12. The system of claim 11, wherein the time of performing the second write operation is specified by a write timestamp associated with the group of memory cells, and wherein the write timestamp is stored in metadata of a memory subsystem comprising the memory device.

13. The system of claim 12, wherein the operation further comprises: In response to performing the write operation, the write timestamp is updated based on the current time.

14. The system of claim 1, wherein associating the first read voltage level with the second memory cell comprises: The record that maps the second memory cell to the first read voltage level is stored in a data structure that includes multiple records, each of which maps a memory cell to a corresponding read voltage level.

15. The system of claim 1, wherein associating the first read voltage level with the second memory cell replaces the existing association between the second memory cell and the second read voltage level.

16. A method comprising: The processing device performs a first write operation to write data to a first memory cell in a group of memory cells; The write-to-write-W2W time is determined based on the first write operation and the second write operation that occurred before the first write operation; The threshold time criterion satisfied by the W2W delay is identified in the data structure, wherein the data structure includes the correlation between the threshold time criterion and the first read voltage level; A second read voltage level that identifies a second memory cell associated with the group of memory cells; Associate the first read voltage level with the second memory cell; as well as In response to determining that the second read voltage level is less than the first read voltage level, the second read voltage level associated with the second memory cell is set to the value of the first read voltage level.

17. The method of claim 16, further comprising: Receive a request to read from a specified memory location; In response to the request to read from the specified memory cell, the read voltage level associated with the specified memory cell is identified; as well as Data is read from the designated memory cell according to the read voltage level.

18. The method of claim 16, further comprising: In response to performing the write operation, the base read level of the memory device including the group of memory cells is associated with the first memory cell.

19. A non-transitory computer-readable medium comprising instructions that, when executed by a processing means, cause the processing means to perform operations including: Perform a first write operation that writes data to a first memory cell in a group of memory cells; The write-to-write-W2W time is determined based on the first write operation and the second write operation that occurred before the first write operation; The threshold time criterion satisfied by the W2W delay is identified in the data structure, wherein the data structure includes the correlation between the threshold time criterion and the first read voltage level; A second read voltage level that identifies a second memory cell associated with the group of memory cells; Associate the first read voltage level with the second memory cell; as well as In response to determining that the second read voltage level is less than the first read voltage level, the second read voltage level associated with the second memory cell is set to the value of the first read voltage level.

20. The non-transitory computer-readable medium of claim 19, wherein the operation further comprises: Receive a request to read from a specified memory location; In response to the request to read from the specified memory cell, the read voltage level associated with the specified memory cell is identified; as well as Data is read from the designated memory cell according to the read voltage level.

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