Performance limitations based on outage times

Abstract

In response to power-on of the memory device, an elapsed power-off time is identified based on the difference between the time of power-on and the time of a previous power-off of the memory device. In response to determining that the elapsed power-off time meets the elapsed time threshold criterion: a request to perform a first write operation on a memory cell of the memory device since power-on is received; a performance parameter associated with the memory cell of the memory device is changed to a first parameter value corresponding to a reduced performance level; and the write operation is performed on the memory cell of the memory device according to the first parameter value corresponding to the reduced performance level. In response to the completion of the write operation, the performance parameter is changed to a value corresponding to a normal performance level.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory subsystems, and more specifically, to performance limitations based on power-down time. Background Technology

[0002] The memory subsystem can be a memory system, a memory module, or a combination of memory devices and memory modules. The memory subsystem may contain one or more memory devices for storing data. Memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention Attached Figure Description

[0003] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0004] Figure 1 An example computing system including a memory subsystem is shown according to some embodiments of the present disclosure.

[0005] Figure 2A Examples of time-voltage shifting in a memory device according to some embodiments are shown.

[0006] Figure 2B Examples of relationships between elapsed power-off time and selective bias power demand that occurs when the memory device is subsequently powered on, according to some embodiments, are shown.

[0007] Figure 3 An example timing diagram is shown, according to some embodiments, regarding the performance limitations of the first write operation after the elapsed power-off time and power-on.

[0008] Figure 4 An example performance limiting component is shown that adjusts performance parameters based on the elapsed power outage time according to some embodiments.

[0009] Figure 5A This is a flowchart of an example method for performance limiting based on elapsed power outage time, according to some embodiments.

[0010] Figure 5B This is a flowchart of an example method 520 for limiting performance using performance parameter values ​​determined based on the elapsed power outage time, according to some embodiments.

[0011] Figure 6 A table showing instance performance levels and corresponding performance parameters according to some embodiments is provided.

[0012] Figure 7 A table showing, according to some embodiments, includes instance performance levels and corresponding elapsed power outage time thresholds and performance parameters.

[0013] Figure 8 This is a block diagram of an example computer system in which embodiments of this disclosure may operate. Detailed Implementation

[0014] This disclosure relates to limiting the performance of operations performed on memory cells in a memory device to increase the available power used for the first write to a memory cell after the memory device is powered on. The memory subsystem may be a memory device, a memory module, or a combination of a memory device and a memory module. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Typically, a host system may use a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0015] The memory subsystem can contain high-density non-volatile memory devices where data retention is required when no power is supplied to the memory device. One example of a non-volatile memory device is a three-dimensional cross-point (“3D cross-point”) memory device containing an array of non-volatile memory cells. A 3D cross-point memory device can combine a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Another example is a NAND memory device. The following section will discuss this further. Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits stored. Logic states may be represented by binary values ​​such as “0” and “1” or combinations of such values.

[0016] Memory devices can consist of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are etched onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line can refer to one or more rows of memory cells in a memory device, which are used in conjunction with one or more bit lines to generate an address for each of the memory cells. The intersection of bit lines and word lines constitutes the address of a memory cell. Hereinafter, a block refers to a cell of a memory device used to store data and can contain groups of memory cells, groups of word lines, word lines, or individual memory cells. One or more blocks can be grouped together to form a plane of a memory device to allow concurrent operation on each plane. A memory device can be referred to as a "drive" having multiple dies layered in multiple "stacks".

[0017] A read operation can be performed using a signal having a read voltage level (e.g., a word line applied to a memory array). The read threshold voltage level or value (referred to herein as "read voltage level") can be a specific voltage applied to a memory cell of the memory device to read data stored at that memory cell. For example, if the threshold voltage of a particular memory cell is identified as being lower than the read voltage level applied to that memory cell, the data stored at that memory cell may be a specific value (e.g., '1'), and if the threshold voltage of a particular memory cell is identified as being higher than the read voltage level, the data stored at that memory cell may be another value (e.g., '0'). Therefore, a read voltage level can be applied to a memory cell to determine the value stored at that memory cell.

[0018] In a conventional memory subsystem, when the threshold voltage programming distribution of a memory cell changes, the applied read voltage level may be inaccurate relative to the changed threshold voltage. For example, a memory cell may be programmed to have a threshold voltage lower than the read voltage level. The programmed threshold voltage can change over time and may transition to a level higher than the read voltage level. For instance, the threshold voltage of a memory cell may change from initially being lower than the read voltage level to being higher than the read voltage level. Therefore, when a read voltage level is applied to the memory cell, the data stored at the memory cell may be misread or misinterpreted as an incorrect value compared to the initially stored value before the threshold voltage transition.

[0019] As another example, for a first write operation on a memory cell that occurs after the memory cell has been powered on following a period of power-off, the voltage shift that occurs when the memory cell is powered off can increase the selection bias (e.g., for selecting the RESET cell). For subsequent write operations after the first write operation, the selection bias returns to normal levels. However, if the memory subsystem performs other operations in parallel with the first write operation, and these other operations (e.g., high-performance operations such as high-speed reads or writes to other memory cells) consume a considerable amount of power, the available power may be insufficient. That is, the amount of available power may not be sufficient to meet the combined power requirements of the higher selection bias of the first write operation and other operations performed in high-speed parallelism. If the available power is insufficient, uncorrectable errors may occur. Existing memory subsystems address this issue by performing an additional write operation when the memory subsystem is powered on. However, this additional write operation, also known as power-on erase, has a performance penalty and is typically disabled by default.

[0020] This disclosure addresses the aforementioned and other drawbacks by using performance limiting techniques that reduce the performance of a memory subsystem for a first write operation after the memory device is powered on. Performance limiting can be performed based on the amount of time the memory device was powered off before power-on. Performance limiting can be performed if the time the memory device was powered off meets a threshold criterion. The amount of performance reduction can be based on the amount of time the memory device was powered off. In one embodiment, in response to power-on of the memory device, the memory subsystem determines the elapsed power-off time based on the difference between the time of power-on and the time of a previous power-off of the memory device. The memory subsystem determines whether the elapsed power-off time meets an elapsed time threshold criterion. In response to determining that the elapsed power-off time meets the elapsed time threshold criterion, the memory subsystem receives a request to perform a first write operation on a memory cell of the memory device, changes the performance parameter associated with the memory cell to a first parameter value corresponding to a reduced performance level, and performs a write operation on the memory cell at the reduced performance level. The first write operation can be a first write operation performed on a memory cell after the memory subsystem is powered on.

[0021] The memory subsystem can also adjust performance parameters based on the amount of power outage time elapsed. For example, when the elapsed power outage time is within a first range, the performance parameters are set to values ​​corresponding to a first reduced performance level; and when the elapsed power outage time is within a second range higher than the first range, the performance parameters are set to values ​​corresponding to a second reduced performance level lower than the first reduced performance level. For example, performance parameters could be the maximum number of memory operations that can be executed in parallel, the memory operation queue depth, or the timing delay between consecutive memory operations. The memory subsystem can reduce performance by changing one or more of these parameters from a second value corresponding to a normal or baseline performance level to a first value corresponding to a reduced performance level. After the write operation is complete, the memory subsystem can restore performance to a normal or baseline level by changing the performance parameters back to the second parameter value. Because the performance parameters are associated with a specific memory cell, a performance reduction during the first write operation will not reduce the performance of other memory cells. The above operations can be performed on each memory cell until all memory cells of the memory device have been written to at least once after power-on.

[0022] Advantages of this disclosure include, but are not limited to, avoiding read errors that may occur when the memory subsystem is powered on. As described above, due to the effects of time voltage shifts, such as cell selection bias drifting to a higher voltage, a first write operation that occurs after a powered-off memory device is powered on can use more power than subsequent write operations. The amount of power used by the first write operation can be proportional to the amount of power-off time elapsed. If the memory subsystem operates in high-performance mode and the memory device is powered off for a sufficient amount of time, there may not be enough power to perform the first write operation and other operations, such as read operations that occur in parallel after power-on. Due to this power deficiency, read errors, including uncorrectable read errors, may occur. Embodiments of this disclosure can avoid power deficiency and associated read errors by limiting the performance of memory operations on the memory cells of the memory device when a first write operation is performed on a memory cell after at least a threshold amount of power-off time has elapsed. If the elapsed power-off time is high enough, for example, at least a threshold amount, the amount of voltage drift and the corresponding amount of power required by the first write operation may be sufficient to cause power deficiency. Since reduced performance reduces power consumption, power deficiency can be avoided by limiting performance during the first write operation.

[0023] Figure 1 An example computing system 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0024] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0025] The computing environment 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is shown. The host system 120 uses the memory subsystem 110, for example, to write data to and read data from the memory subsystem 110. As used herein, “coupled to” generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without an intervening component), whether wired or wireless, and includes connections such as electrical connections, optical connections, magnetic connections, etc.

[0026] Host system 120 may be a computing device, such as a desktop computer, laptop computer, network server, mobile device, vehicle (e.g., aircraft, drone, train, automobile, or other means of transportation), Internet of Things (IoT) device, embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment, or networked commercial device), or such computing device containing memory and processing devices. Host system 120 may be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 may further utilize an NVM High Speed ​​(NVMe) interface to access memory components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120.

[0027] The memory device may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. The volatile memory device (e.g., memory device 140) may be, but is not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0028] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory. The crosspoint array of the non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them.

[0029] Although a non-volatile memory component, such as a 3D cross-point type memory, is described, the memory device 130 may be based on any other type of non-volatile memory, such as NAND, ROM, phase-change memory (PCM), auto-memory, other chalcogenide-based memories, ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0030] One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays. In some embodiments, a particular memory component may include an SLC portion of memory cells as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages or codewords, which may refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks. Some types of memory (e.g., 3D cross-connects) may group pages across the die and channels to form management units (MUs).

[0031] The memory subsystem controller 115 can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include digital circuitry with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0032] The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0033] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0034] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to enable the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical block addresses and physical block addresses associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130 and translate responses associated with the memory device 130 into information for the host system 120.

[0035] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0036] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0037] The memory subsystem 110 includes a performance limiting component 113, which can be used to degrade memory subsystem performance based on the amount of time that the memory subsystem 110 or specific memory devices 130, 140 of the memory subsystem 110 are de-energized before being powered on. The computing environment 100 may include a power circuitry system 160 that provides electrical power to components of the memory subsystem 110. The power circuitry system 160, which provides power to the memory subsystem 110, includes a memory subsystem controller 115, memory devices 130, and memory devices 140. The power circuitry system 160 can provide power in response to a power-on command or signal and can continue to provide power until a power-off signal or command is received.

[0038] In one embodiment, in response to power-on of the memory device 130, the performance limiting component 113 determines the elapsed power-off time based on the difference between the time of power-on and the time of a previous power-off of the memory device 130. The performance limiting component 113 determines whether the elapsed power-off time meets an elapsed time threshold criterion. In response to determining that the elapsed power-off time meets the elapsed time threshold criterion, the performance limiting component 113 receives a request to perform a first write operation on a memory cell of the memory device 130, changes the performance parameter associated with the memory cell to a first parameter value corresponding to a reduced performance level, and performs the write operation on the memory cell at the reduced performance level. The first write operation may be a first write operation performed on the memory cell after power-on of the memory subsystem 110. Alternatively or additionally, a write flag or counter may be associated with each memory cell. When the memory device 130 of the memory cell is powered on, the performance limiting component 113 may set the write flag of each memory cell to false. When a write request is received, the performance limiting component 113 may determine whether the write request is for a first write after power-on by determining whether the write flag is false. If the write flag is false, performance limiting component 113 can perform performance limiting based on the amount of power-off time elapsed, as described above. Then, performance limiting component 113 can set the write flag to true and restore performance to normal levels when the first write operation on the memory cell is complete. For subsequent requests to write to the memory cell, performance limiting component 113 does not perform performance limiting because the write flag is true. If performance limiting component 113 determines that each memory cell has been written to at least once since the memory cell was powered on, it can stop operating.

[0039] In this way, performance limiting component 113 can limit the performance of the operation performed on each memory cell during the first write to the memory cell, and restore the performance of the memory cell to a normal or baseline level after the first write operation.

[0040] The performance limiting component 113 can also adjust the performance parameters based on the elapsed power-off time. For example, when the elapsed power-off time is within a first range, the performance parameters are set to a value corresponding to a first reduced performance level; and when the elapsed power-off time is within a second range higher than the first range, the performance parameters are set to a value corresponding to a second reduced performance level lower than the first reduced performance level. The performance limiting component 113 can perform the above operations before allowing other write operations to be performed, such that the first write operation is the first write operation performed on the memory cell after power-on.

[0041] For example, performance parameters may be the maximum number of memory operations that can be executed in parallel, the memory operation queue depth, or the timing delay between consecutive memory operations. Memory subsystem 110 can degrade performance by changing one or more of these parameters from a second value corresponding to a normal or baseline performance level to a first value corresponding to a reduced performance level. After a write operation is completed, memory subsystem 110 can restore performance to a normal or baseline level by changing the performance parameter back to the second parameter value. Because the performance parameter is associated with a specific memory cell, a performance degradation during the first write operation will not degrade the performance of other memory cells. The above operations can be performed on each memory cell until all memory cells of memory device 130 have been written at least once after power-on. Further details regarding the operation of performance limiting component 113 are described below.

[0042] Figure 2A An example of time-voltage shifting in a memory device 130 according to some embodiments is shown. The graph 200 shows a SET voltage distribution 202A corresponding to a programmed value such as 0, and a RESET voltage distribution 204A corresponding to a programmed value such as 1. The horizontal (volt) axis represents the voltage value, increasing to the right. Over a period of time, the initial SET distribution 202A has drifted to the shifted SET distribution 202B. The memory device 130 may be in a power-off state for at least a portion of the time period. The amount of voltage shift between SET distributions 202A and 202B is labeled "power-off SET drift". Similarly, the initial RESET distribution 204A has drifted to the shifted RESET distribution 204B within the same time period. The amount of voltage shift between RESET distributions 204A and 204B is labeled "power-off RESET drift". The threshold read level voltage (not shown) that divides the shifted SET distribution 202B and the shifted RESET distribution 204B has also been shifted. The initial RESET cell select bias VSEL 206A has also drifted to the shifted RESET cell select bias VSEL 206B, as indicated by the label "RESET cell select bias drift". Since the RESET cell select bias VSEL 206B has drifted to a higher voltage, the power requirement for selecting the RESET cell to write data has also increased.

[0043] Figure 2BExamples of relationships between elapsed power-off time and selection bias power requirements when the memory device 130 is subsequently powered on, according to some embodiments, are illustrated. As shown in graph 210, the power required to generate voltage to select the RESET cell during a write operation increases with the amount of power-off time. Therefore, the power requirement for a first write operation after powering on the memory device 130 containing the RESET cell is relatively low after a relatively short power-off time (e.g., less than a threshold time), but the power requirement for the first write operation after powering on is higher after a longer period of time (e.g., the threshold time). Since the first write operation programs the memory cell containing the cell, the power requirement for subsequent write operations to the memory cell becomes relatively low for a period of time, but increases over time due to the time-voltage shift effect.

[0044] Figure 3 An example timing diagram 300 is shown, illustrating performance limitations of the first write operation after the elapsed power-off time and power-on time according to some embodiments. Timing diagram 300 illustrates example events in the operation of memory device 130. The timing of events is represented by their position on the horizontal (time) axis. A power-off event 302 of the memory device occurs at power-off time 304, and a power-on event 306 of the memory device occurs at power-on time 308. The difference between power-on time 308 and power-off time 304 is the elapsed power-off time 310.

[0045] Power failure event 302 may occur in response to a user cutting off or otherwise disconnecting the power supply to the memory device, an operation to shut down the memory device performed by the memory subsystem 110 or the host system 120, a power failure due to an error or malfunction, or other reasons. For example, power failure event 302 may occur due to a power failure of the memory subsystem 110 or due to a power failure of the memory device 130, while other components of the memory subsystem, such as other memory devices 130, remain powered on. The memory subsystem 110 may be powered off in response to a power failure of the drive containing the memory device. In another example, the memory subsystem 110 (and associated memory devices 130, 140) may be powered off while other components of the drive remain powered on.

[0046] In response to power-on event 306, performance limiting component 113 determines whether the elapsed power-off time 308 meets a threshold criterion, for example, at least a threshold. If not, performance limiting component 113 takes no further action until another power-on event 306 occurs at a subsequent time. If the elapsed power-off time 308 meets the threshold criterion, performance limiting component 113 may wait until a request to perform a first write 318 is received. When the request to perform the first write 318 is received, performance limiting component 113 can identify the memory cell specified by the request to perform the first write 318. Performance limiting component 113 performs performance limiting operation 314 to reduce the performance level of memory subsystem 110 for read and / or write operations performed on the identified memory cell after limiting operation 314.

[0047] Performance limiting component 113 may perform performance limiting operation 314 in response to determining that an elapsed power-off time 310 meets a threshold condition. Alternatively, performance limiting component 113 may perform performance limiting operation 314 in response to a request to perform a first write. Therefore, the performance of the memory subsystem is degraded during the first write 318. When the first write 318 completes, as indicated by the first write completion event 320, performance limiting component 113 performs performance enhancement operation 322 to improve the performance of the memory subsystem. Performance enhancement operation 322 may restore the performance level of the memory subsystem 110 for operations performed on memory cells to a normal performance level (e.g., to a baseline level). After performance enhancement operation 322, memory subsystem 110 may perform one or more reads and / or writes 324 at a normal performance level.

[0048] In one instance, the memory subsystem 110 may perform one or more optional read operations 316 on the memory cell between the power-on time 308 and the first write 312. That is, the optional read operation 316 may be performed before the performance limiting operation 314. As an alternative to waiting for the request to perform the first write 318, for example in response to determining that the elapsed power-off time 308 meets a threshold criterion, the performance limiting component 113 may perform the performance limiting operation 314 earlier.

[0049] Figure 4An example performance limiting component 113 is illustrated, which adjusts performance parameters based on elapsed power outage time according to some embodiments. The performance limiting component 113 includes a power cycle record 402 and one or more sets of performance parameters 410. Each set of performance parameters 410 corresponds to a memory cell 430. Thus, a first memory cell performance parameter 410A is associated with a first memory cell 430, a second memory cell performance parameter 410B is associated with a second memory cell 430B, and an Nth memory cell performance parameter 410N is associated with an Nth memory cell 430C. Since each set of performance parameters 410 is associated with a memory cell 430, changing the value of a particular set of performance parameters will change the performance (e.g., memory operation throughput and / or latency) of memory operations performed on the associated memory cell 430. The performance limiting component 113 can adjust the performance parameter 410 of the first memory cell 430A independently of the performance parameter 410B of the second memory cell 430B.

[0050] Each set of performance parameters includes one or more of the following: host I / O queue depth 412, maximum number of parallel jobs 414, and latency timing parameters 416. The host I / O queue depth 412 specifies the upper limit of how many I / O operations (e.g., reads and writes) can wait in the queue for execution by the memory subsystem 110. The memory subsystem 110 can efficiently identify the next operation to be executed by retrieving the operation at the head of the queue. Reducing the host I / O queue depth 412 can, for example, reduce the performance of the memory subsystem 110 by decreasing the rate at which read and write operations are performed, because it reduces the rate at which read and write requests from the host system 120 can be processed. For example, I / O operations can be read and write operations requested by the host system 120. For example, if the queue depth 412 is 32, a maximum of 32 I / O operations can wait in the operation queue. If the queue depth 412 is reduced to 16, a maximum of 16 I / O operations can wait in the operation queue. Therefore, a queue depth 412 of 16 corresponds to memory subsystem performance below a queue depth of 32.

[0051] The maximum number of concurrent jobs (“maximum jobs”) 414 specifies the upper limit of the number of I / O operations that the memory subsystem 110 can execute in parallel. Reducing the maximum jobs parameter 414 can decrease the performance of the memory subsystem 110. For example, if the maximum jobs 414 is 8, the memory subsystem 110 can execute up to 8 I / O operations in parallel. If the maximum jobs 414 is reduced to 4, the memory subsystem 110 can execute up to 4 I / O operations in parallel. Therefore, a maximum jobs value of 4 corresponds to memory subsystem performance lower than a maximum jobs value of 8.

[0052] The latency timing parameter 416 includes one or more of the following: write-to-read (W2R) latency 418, write-to-write (W2W) latency 420, read-to-read (R2R) latency 422, and read-to-write (R2W) latency 424. Each latency timing parameter 416 specifies the amount of time that the performance-limiting component 113 waits between corresponding operations performed on memory cell 430. For example, the W2R latency 418 specifies the amount of time that the performance-limiting component 113 waits between a write operation to the same memory cell 430 and the next read operation. Therefore, increasing the value of the latency timing parameter 416 can reduce the performance of the memory subsystem 110. For example, a 20-millisecond W2R latency causes the memory subsystem 110 to wait 20 milliseconds between the completion of a write operation to the same memory cell and the initiation of the next read operation. A 30-millisecond W2R latency causes the memory subsystem 110 to wait 30 milliseconds instead of 20 milliseconds, thereby reducing the rate of read operations after a write operation to the same memory cell can be performed.

[0053] Each memory cell 430 may include or be associated with a "power-on write" flag 432. Flag 432 indicates whether the associated memory cell 430 has been written to since the memory cell 430 was powered on. In some embodiments, flag 430 may be used to determine whether the requested write operation is the first write operation since a particular memory cell 430 was powered on. When the memory device containing the memory cell (or memory subsystem 110) is powered on, flag 432 of each memory cell 430 may be set to false. Then, upon completion of the write to the memory cell, each write operation on the memory cell 430 may set flag 432 of the memory cell 430 to true. Performance limiting component 113 may determine whether to degrade the performance of a particular memory cell 430 by checking whether flag 432 of the memory cell 430 is false. If flag 430 of the memory cell 430 specified in the requested write operation is false, performance limiting component 113 may degrade the performance of the requested write operation.

[0054] Figure 5A This is a flowchart of an example method 500 based on the performance of an elapsed power outage time limitation according to some embodiments. Method 500 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figure 1The performance limiting component 113 is executed. Method 500 can be executed for each memory cell before processing the write operation to the memory cell. Although shown in a specific order or sequence, the order of processes can be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0055] In operation 502, in response to the power-on of the memory device, the processing device determines the elapsed power-off time based on the difference between the time when the power-on occurs and the time when the previous power-off of the memory device occurs.

[0056] In operation 504, the processing device determines whether the elapsed power outage time meets an elapsed time threshold criterion. The elapsed time threshold criterion may include a minimum elapsed time value, and the criterion is met when the elapsed power outage time meets or exceeds the minimum time value. For example, the minimum time value may be 24 hours. The threshold criterion may also include a maximum time value, in which case the threshold criterion is met when the elapsed power outage time is between the minimum and maximum time values ​​(e.g., greater than or equal to the minimum time value and less than the maximum time value). The minimum time value may be, for example, 24 hours, and the maximum time value may be, for example, 120 hours. These values ​​are merely examples, and other minimum and maximum time values ​​may be used. If, in operation 504, the processing device determines that the elapsed power outage time does not meet the elapsed time threshold, the processing device may execute operation 514. In operation 514, the processing device enters normal mode and processes write requests without degrading performance parameter values. In normal mode, performance parameters have normal values, such as undegraded values, and the power consumption of the memory subsystem can be at a normal power consumption level. If, in operation 504, the processing device determines that the elapsed power-off time meets an elapsed time threshold criterion, then the processing device may execute operation 506. In operation 506, the processing device receives a request to perform a write operation on a memory cell of the memory device. Since method 506 is executed before processing the write operation, the requested write operation is the first write operation to be performed after the memory device is powered on.

[0057] In operation 508, the processing device changes the performance parameters associated with the memory cells of the memory device to a first parameter value corresponding to a reduced performance level. For example, the processing device may set one or more performance parameters in performance parameter 410 corresponding to memory cell 430 to values ​​corresponding to the reduced performance level, as described above for example regarding... Figure 4 As stated above.

[0058] In operation 510, the processing device performs a write operation on a memory cell of the memory device according to a first parameter value corresponding to a reduced performance level. Since one or more performance parameters in performance parameters 410 corresponding to memory cell 430 have been set to values ​​corresponding to the reduced performance level, performing the write operation in operation 510 causes the write operation to be performed at the reduced performance level.

[0059] In operation 512, in response to the completion of the write operation, the processing device changes the performance parameter of the memory cell to a second parameter value corresponding to the normal performance level. That is, the processing device can restore the performance parameter 410 to its value before the performance adjustment performed in block 508. The prior value can be, for example, a normal value or a baseline value.

[0060] Figure 5B This is a flowchart of an example method 520 for limiting performance using performance parameter values ​​determined based on the elapsed power outage time, according to some embodiments. Method 520 may be performed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 520 is performed by… Figure 1 The performance limiting component 113 is executed. Method 520 can be executed for each memory cell before processing the write operation to that memory cell. Although shown in a specific order or sequence, the order of the processes can be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0061] In operation 522, the processing device receives a request to perform a write operation on a memory cell of the memory device. In operation 524, the processing device determines whether the memory cell has been written to (e.g., programmed) since the memory device has been powered on. If it has been written to, the write operation resets the effects of voltage drift that occurred when the memory device was powered off. Therefore, if in operation 524 the processing device determines that the memory device has been written to since power-on, the processing device can execute operation 536. In operation 536, the processing device enters normal mode and processes the write request without changing performance parameters. Otherwise, the memory cell has been written to since power-on, and the processing device continues to operation 526.

[0062] In operation 526, the processing device determines the elapsed power-off time of the memory device based on the time difference between the power-on of the memory device and the power-off of the memory device prior to power-on. In operation 528, the processing device identifies one or more performance parameter values ​​corresponding to the elapsed power-off time, such as those described herein for example regarding... Figure 7 For example, the processing device identifies which of the performance levels 702 has a lower and upper threshold 716 for power outage time, the lower and upper thresholds specifying a range containing the elapsed power outage time since operation 526. The performance parameter value corresponding to the elapsed power outage time is specified by the identified performance level 702. For example, if the elapsed power outage time is 30 hours, then... Figure 7 Table 700 indicates that the elapsed power outage time is between the upper and lower thresholds 716 associated with the first reduced performance level 706A. The performance parameter 708 specified in Table 700 for the first reduced performance level 706A has the following values: host I / O queue depth 28, maximum parallel jobs 8, and timings (W2R latency, W2W latency, R2R latency, R2W latency) for T7 ms, T8 ms, T9 ms, and T10 ms.

[0063] In operation 530, the processing device sets one or more performance parameters 410 associated with memory cell 430 to corresponding identified performance parameter values. For example, the processing device may set the host I / O queue depth associated with memory cell 430 to 28, the maximum parallel jobs associated with memory cell 430 to 8, and the timing delays associated with memory cell 430 to the timing delays of a first reduced performance level 706A, namely T7 ms, T8 ms, T9 ms, and T10 ms (for W2R delay, W2W delay, R2R delay, and R2W delay, respectively).

[0064] In operation 532, the processing device performs a write operation on the memory cell based on the identified performance parameter values. In operation 534, in response to the completion of the write operation, the processing device sets one or more performance parameters associated with the memory cell to corresponding values ​​corresponding to the normal performance level. For example, Table 700 specifies performance parameter 708 corresponding to normal performance level 704. Based on the normal performance level 704 in Table 700, in operation 534, the processing device may set the host I / O queue depth associated with memory cell 430 to 64, the maximum parallel jobs associated with memory cell 430 to 16, and the timing delays associated with memory cell 430 to T3 ms, T4 ms, T5 ms, and T6 ms (for W2R delay, W2W delay, R2R delay, and R2W delay, respectively).

[0065] Figure 6Table 600, according to some embodiments, shows an instance performance level 602 and a corresponding performance parameter 608. Table 600 maps each performance level 602 to a corresponding value of performance parameter 608. Performance parameter 608 includes host I / O queue depth 610, maximum number of parallel jobs 612, and timing latency 614. Performance limiting component 113 can reduce the performance of memory subsystem 110 by setting the performance parameter 410 of memory cell 430 to a value corresponding to parameter 608 at a reduced performance level 606. Furthermore, performance limiting component 113 can improve the performance of memory subsystem 110 to a normal level by setting the performance parameter 410 of memory cell 430 to a value corresponding to parameter 608 at a normal performance level 604.

[0066] Table 600 specifies example values ​​for performance parameters 608 for normal performance level 604 and reduced performance level 606. For normal performance level 604, instance performance parameters include a host I / O queue depth of 28, a maximum number of concurrent jobs of 8, and a timing (W2R latency) value of T1 milliseconds. For reduced performance level 606, instance performance parameters include a host I / O queue depth of 8, a maximum number of concurrent jobs of 4, and a timing (W2R latency) value of T2 milliseconds.

[0067] Figure 7 Table 700 illustrates, according to some embodiments, an instance performance level 702 and a corresponding elapsed power-off time threshold 716 and performance parameters 708. Table 700 also specifies a performance metric 708 representing the expected number of I / O operations per second and a power consumption 720 representing the expected power consumption for each performance level 702. Performance levels include a normal performance level 704, a first reduced performance level 706A, and a second reduced performance level 706B. The performance limiting component 113 can select performance parameters 708 based on the elapsed power-off time. Longer elapsed power-off times correspond to lower performance levels, which have lower performance metric values ​​718 and lower power consumption 720. Therefore, each reduced performance level 706 corresponds to a different range of elapsed power-off times, with lower performance levels 706 corresponding to a higher range of elapsed power-off times.

[0068] Normal performance level 704 has instance performance parameters 708, which include host I / O queue depth 64, maximum parallel jobs 16, and timings (W2R latency, W2W latency, R2R latency, and R2W latency) of T3 ms, T4 ms, T5 ms, and T6 ms, respectively. Normal performance level 704 also has a performance metric of 5000 I / O operations per second (IOPS) 718 and a power consumption of P1 milliwatts (mW) 720.

[0069] The first reduced performance level 706A corresponds to the performance reduction of the normal performance level 704, and the second reduced performance level 706B corresponds to the performance reduction of the first reduced performance level 706A. The first reduced performance level 706A meets the first threshold criterion when the elapsed power outage time is within a first range specified by lower and upper thresholds 716 of 24 hours and 120 hours, respectively. The second reduced performance level 706A meets the second threshold criterion when the elapsed power outage time is within a second range specified by lower and upper thresholds 716 of 120 hours and an infinite number of hours, respectively.

[0070] When the elapsed power outage time is within a first range, the performance limiting component 113 can reduce the performance of the memory subsystem to a first reduction level 706A. For a longer elapsed power outage time, when the elapsed power outage time is within a second range, the performance limiting component 113 can reduce the performance to a second reduction level 706B.

[0071] The performance limiting component 113 can reduce the performance of the memory subsystem 110 to a first reduced performance level 706A by setting the performance parameter 410 of the memory cell 430 to a parameter value 708 corresponding to a first reduced performance level 706A. The instance performance parameter values ​​708 of the first reduced performance level 706A are host I / O queue depth 28, maximum parallel jobs 8, and timings (W2R latency, W2W latency, R2R latency, and R2W latency) of T7 ms, T8 ms, T9 ms, and T10 ms. The first reduced performance level 706A is also characterized by a performance metric 718 of 2500 IOPS and a power consumption of P2 milliwatts (mW) 720.

[0072] The performance limiting component 113 can reduce the performance of the memory subsystem 110 to a second reduced performance level 706B by setting the performance parameter 410 of the memory cell 430 to a parameter value 708 corresponding to the second reduced performance level 706B. The instance performance parameter values ​​708 of the second reduced performance level 706B are host I / O queue depth 8, maximum parallel jobs 2, and timings (W2R latency, W2W latency, R2R latency, and R2W latency) of T11 ms, T12 ms, T13 ms, and T14 ms, respectively. The second reduced performance level 706B is also characterized by a performance metric 718 of 1000 I / O operations per second (IOPS) and a power consumption of P3 milliwatts (mW) 720.

[0073] Figure 8 An example machine of computer system 800 is shown, within which a set of instructions is executable to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 800 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to execute commands corresponding to...). Figure 1 (Performance limiting component 113 operation). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0074] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch or bridge, or non-digital circuit system, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should also be considered to include any collection of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0075] The example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 818, which communicate with each other via a bus 830.

[0076] Processing device 802 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 802 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 802 is configured to execute instructions 826 for performing the operations and steps discussed herein. Computer system 800 may further include a network interface device 808 communicating via network 820.

[0077] The data storage system 818 may include a machine-readable storage medium 824 (also referred to as a computer-readable medium) on which one or more instruction sets 826 or software embodying any or more of the methods or functions described herein are stored. The instructions 826 may also reside wholly or at least partially in main memory 804 and / or processing device 802 during execution by computer system 800, the main memory 804 and processing device 802 also constituting machine-readable storage media. The machine-readable storage medium 824, the data storage system 818, and / or main memory 804 may correspond to... Figure 1 The memory subsystem 110.

[0078] In one embodiment, instruction 826 includes instructions for implementing a component corresponding to the read voltage adjustment (e.g., Figure 1 The performance-limiting component 113) has instructions that restrict its functionality. Although machine-readable storage medium 824 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. The term "machine-readable storage medium" may include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0079] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0080] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data representing physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0081] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0082] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0083] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0084] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A system comprising: a memory device; and a processing device operatively coupled to the memory device to perform operations comprising: receiving a request to perform a write operation on a memory cell of the memory device; determining whether the memory cell has been written at least once previously since a power-up of the memory device; in response to determining that the memory cell has not been written at least once previously since the power-up of the memory device: determining an elapsed power-down time based on a difference between a time at which the power-up occurred and a time at which a previous power-down of the memory device occurred; determining whether the elapsed power-down time satisfies an elapsed time threshold criterion; in response to determining that the elapsed power-down time satisfies the elapsed time threshold criterion: changing a performance parameter associated with the memory cell of the memory device to a first parameter value corresponding to a reduced performance level; and performing the write operation on the memory cell of the memory device in accordance with the first parameter value corresponding to the reduced performance level.

2. The system of claim 1, wherein the write operation is a first write operation performed on the memory cell after the power-up of the memory device.

3. The system of claim 1, the operations further comprising: in response to completion of the write operation, changing the performance parameter associated with the memory cell to a second parameter value corresponding to a normal performance level.

4. The system of claim 3, wherein the reduced performance level is associated with a reduced power consumption level that is lower than a normal power consumption level associated with the normal performance level.

5. The system of claim 3, wherein the performance parameter comprises one or more of: a number of memory operations that can be performed in parallel, a memory operation queue depth, or a timing delay between consecutive memory operations.

6. The system of claim 5, wherein the timing delay comprises one or more of: a write-to-read (W2R) delay, a write-to-write (W2W) delay, a read-to-write (R2W) delay, or a read-to-read (R2R) delay between the consecutive memory operations.

7. The system of claim 1, the operations further comprising: determining the first parameter value corresponding to the reduced performance level as a function of the elapsed power-down time.

8. The system of claim 7, wherein the first parameter value corresponding to the reduced performance level is determined using a mapping table that maps elapsed power-down times to performance parameter values, wherein the mapping table maps each elapsed power-down time to a corresponding performance parameter value.

9. The system of claim 8, wherein the mapping table comprises a plurality of records, each record comprising an elapsed power-down time threshold criterion and one or more corresponding performance parameter values, wherein determining the first parameter value corresponding to the reduced performance level comprises: identifying, in the mapping table, a record that includes a passed power-off time threshold criterion corresponding to the passed power-off time, wherein the identified record further includes the first parameter value corresponding to the reduced performance level.

10. A method comprising: receiving, by a processing device, a request to perform a write operation on a memory cell of a memory device; determining whether the memory cell has been written at least once previously since a power-up of the memory device; in response to determining that the memory cell has not been written at least once previously since the power-up of the memory device: determining a passed power-off time of the memory device based on a time difference between the power-up of the memory device and a power-off of the memory device prior to the power-up; identifying one or more performance parameter values corresponding to the passed power-off time; setting one or more performance parameters associated with the memory cell of the memory device to respective identified performance parameter values; and performing the write operation on the memory cell of the memory device in accordance with the identified performance parameter values.

11. The method of claim 10, further comprising: in response to completion of the write operation, setting the one or more performance parameters of the memory cell to respective values corresponding to a normal performance level.

12. The method of claim 10, wherein the one or more performance parameters comprise one or more of: a number of memory operations that can be performed in parallel, a memory operation queue depth, or a timing delay between consecutive memory operations.

13. The method of claim 12, wherein the timing delay comprises one or more of a write-to-read (W2R) delay, a write-to-write (W2W) delay, a read-to-write (R2W) delay, or a read-to-read (R2R) delay between the consecutive memory operations.

14. A non-transitory computer-readable medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: receiving a request to perform a write operation on a memory cell of a memory device; determining whether the memory cell has been written at least once previously since a power-up of the memory device; in response to determining that the memory cell has not been written at least once previously since the power-up of the memory device: determining a passed power-off time based on a difference between a time at which the power-up occurred and a time at which a previous power-off of the memory device occurred; determining whether the passed power-off time satisfies a passed time threshold criterion; in response to determining that the passed power-off time satisfies the passed time threshold criterion: changing a performance parameter associated with the memory cell of the memory device to a first parameter value corresponding to a reduced performance level; and performing the write operation on the memory cell of the memory device in accordance with the first parameter value corresponding to the reduced performance level.

15. The non-transitory computer-readable medium of claim 14, wherein the write operation is a first write operation performed on the memory cell after the power-up of the memory device.

16. The non-transitory computer-readable medium of claim 14, the operations further comprising: in response to completion of the write operation, changing the performance parameter associated with the memory cell to a second parameter value corresponding to a normal performance level.

17. The non-transitory computer-readable medium of claim 16, wherein the performance parameter comprises one or more of: a number of memory operations that can be performed in parallel, a memory operation queue depth, or a timing delay between consecutive memory operations.

18. The non-transitory computer-readable medium of claim 17, wherein the timing delay comprises one or more of: a write-to-read (W2R) delay, a write-to-write (W2W) delay, a read-to-write (R2W) delay, or a read-to-read (R2R) delay between the consecutive memory operations.

19. The non-transitory computer-readable medium of claim 14, the operations further comprising: determining the first parameter value corresponding to the reduced performance level as a function of the elapsed power-down time.

20. The non-transitory computer-readable medium of claim 19, wherein the first parameter value corresponding to the reduced performance level is determined using a mapping table that maps elapsed power-down times to performance parameter values, wherein the mapping table maps each elapsed power-down time to a corresponding performance parameter value. ​ ​

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