Charge loss compensation during read operations in memory devices

Abstract

This disclosure relates to charge loss compensation during read operations in a memory device. Control logic in the memory device initiates a read operation on the memory array of the memory device and performs a calibration operation to detect a change in the series resistance in the memory array. The control logic determines whether the change in series resistance is attributable to charge loss in the memory array, and in response to determining that the change in series resistance is attributable to charge loss in the memory array, performs the read operation using a calibrated read voltage level to read data from the memory array.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to charge loss compensation during read operations in a memory device. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0003] In one aspect, this disclosure provides a memory device comprising: a memory array including a plurality of word lines; and control logic operatively coupled to the memory array to perform operations including: initiating a read operation on the memory array; performing a calibration operation to detect a change in series resistance in the memory array; determining whether the change in series resistance is attributable to charge loss in the memory array; and, in response to determining that the change in series resistance is attributable to charge loss in the memory array, performing the read operation using a calibrated read voltage level to read data from the memory array.

[0004] In another aspect, this disclosure provides a method comprising: initiating a read operation on a memory array of a memory device; performing a calibration operation to detect a change in series resistance in the memory array; determining whether the change in series resistance is attributable to charge loss in the memory array; and, in response to determining that the change in series resistance is attributable to charge loss in the memory array, performing the read operation using a calibrated read voltage level to read data from the memory array.

[0005] In another aspect, this disclosure provides a memory device comprising: a memory array including a plurality of word lines; and control logic operatively coupled to the memory array to perform operations including: determining a first magnitude of a voltage applied to the selected word line among the plurality of word lines at a first time after a selected word line among the plurality of word lines has been programmed, when a first change in the output voltage of the memory array is equal to a first preset amount; determining a second magnitude of the voltage applied to the selected word line among the plurality of word lines at a second time before the selected word line among the plurality of word lines is read, when a second change in the output voltage of the memory array is equal to the first preset amount; determining whether the second magnitude is less than the first magnitude; and determining, in response to determining that the second magnitude is less than the first magnitude, that a charge loss has occurred on at least one memory cell associated with the selected word line. Attached Figure Description

[0006] This disclosure will be more fully understood in light of the detailed description provided below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2A This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to an embodiment.

[0009] Figure 2B This is a schematic diagram illustrating a string of memory cells in a data block of a memory device in a memory subsystem according to some embodiments of the present disclosure.

[0010] Figure 3 This is a schematic diagram of a portion of a memory cell array (e.g., a NAND memory array) of a memory device in a memory subsystem according to some embodiments of the present disclosure.

[0011] Figure 4 This is a flowchart of an example method for compensating for charge loss during a read operation in a memory device according to some embodiments of the present disclosure.

[0012] Figure 5 This is a timing diagram of the operation of a memory device for implementing charge loss compensation during a read operation in the memory device, according to some embodiments of the present disclosure.

[0013] Figure 6 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0014] This disclosure relates to charge loss compensation during read operations in a memory device within a memory subsystem. The memory subsystem may be a memory device, a memory module, or a combination of both. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0015] A memory subsystem may contain high-density non-volatile memory devices where data retention is required when no power is supplied to the memory device. For example, NAND memory, such as 3D flash NAND memory, provides storage in a compact, high-density configuration. A non-volatile memory device is a package of one or more dies, each die containing one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane consists of a set of physical blocks. Each block contains a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Hereinafter, a block refers to a cell of a memory device used to store data and may contain groups of memory cells, groups of word lines, word lines, or individual memory cells. Each block may contain several sub-blocks, each sub-block being defined by an associated pillar (e.g., a vertical conductive trace) extending from a shared bit line. A memory page (also referred to herein as a “page”) stores one or more bits of binary data corresponding to data received from a host system. To achieve high density, strings of memory cells in non-volatile memory devices can be configured to comprise several memory cells comprising pillars at least partially surrounding a polysilicon channel material (i.e., the channel region). The memory cells can be coupled to access lines, often referred to as "word lines," which are typically fabricated together with the memory cells to form a string array within a memory block. The compact nature of certain non-volatile memory devices, such as 3D flash NAND flash memory, means that word lines are common for a large number of memory cells within a memory block.

[0016] During a programming operation, a selected memory cell is programmed by applying a programming voltage to a selected word line. In some cases, a series of incremental voltage programming pulses are applied to the selected word line to increase the charge level of each memory cell connected to that word line, thereby increasing the threshold voltage of each memory cell. After each programming pulse, or after several programming pulses, a programming verification operation is performed to determine whether the threshold voltage of the memory cell has increased to the desired programming level. After the programming operation is complete, the programmed memory cell may experience various forms of charge loss, which may lead to defects in the data retention characteristics of the memory cell, such as unity charge loss, intrinsic charge loss, and fast charge loss. Fast charge loss (QLC) is a result of electron trapping in the tunnel oxide layer (also referred to herein as the “bandgap engineering (BE)” layer) after the applied programming pulse moves back into the channel region of the memory cell string. When the cell passes the programming verification operation, the programmed threshold voltage appears higher due to the charge trapped in the tunnel oxide layer. However, when the memory cell is read later after the programming operation has been completed, the cell may have a threshold voltage lower than the threshold voltage obtained during the programming verification operation. This is attributed to charge leakage from the tunnel oxide layer to the channel region. This may require increasing the threshold voltage distribution to accommodate all possible threshold voltages for a given state, and could result in a higher error rate during any subsequent read operation.

[0017] Certain memory devices attempt to detect fast charge loss by measuring changes in string resistance and calibrating the selected and unselected word line voltages applied during read operations to compensate for it. This technique works when the block being read from the memory device is fully programmed (i.e., a “closed” block). However, introducing zone namespace (ZNS) features into a particular memory device can create incompletely programmed blocks (i.e., “open” blocks). Open blocks are partially programmed. The string resistance in an open block can differ from that of a fully programmed block due to the presence of erased memory cells. Many fast charge loss detection techniques cannot detect whether a change in string resistance is due to fast charge loss or the presence of an open block. Therefore, the memory device can incorrectly calibrate a threshold voltage shift attributed to fast charge loss when the string resistance change is actually due to the open block (which does not require voltage compensation). Performing read operations with incorrectly calibrated voltage signals applied to the selected and unselected word lines can affect the reliability of the memory device, leading to higher error rates and performance degradation.

[0018] This disclosure addresses the above and other drawbacks by providing a detection scheme that measures the change in string resistance of a block of memory devices and determines whether the change in string resistance is attributable to rapid charge loss of memory cells in the string or to the presence of open blocks. After determining that the change in string resistance is attributable to rapid charge loss, the memory device can immediately determine the associated offset of selected word line voltages and unselected word line voltages applied to the memory device during a read operation. In one embodiment, the memory array of the memory device includes a bit line precharge path connected to a current supply. An output voltage (i.e., “vreg2”) on this path can be applied to a comparator and compared to a reference voltage (i.e., “vref”) to raise a flag when the output voltage reaches the reference voltage. During calibration, if the string resistance in the block decreases due to rapid charge loss or the presence of open blocks, then the output voltage also decreases. In one embodiment, to perform the detection and make the determination, the memory device scales the voltages applied to all word lines of the block to a specific voltage (e.g., the unselected word line voltage) and slowly and gradually increases the reference voltage until it reaches the output voltage and raises a flag (e.g., from high to low). After the flag is raised, the memory device gradually increases the reference voltage by a large fixed amount (independent of the serial characteristics) and then begins to ramp down the voltage applied to the selected word line until the flag is raised again. If the voltage applied to the selected word line during the second flag raising differs from the expected value (e.g., a value measured immediately after the block is programmed), the memory device can determine that a rapid charge loss has occurred in the block and can compensate for this rapid charge loss by adjusting the read voltage. If the voltage applied to the selected word line during the second flag raising is the same as the expected value (e.g., within a threshold amount), the memory device can determine that no read voltage compensation is needed.

[0019] The advantages of this method include, but are not limited to, improvements in memory device performance. In the manner described herein, the memory device can successfully identify cases of rapid charge loss and distinguish them from cases where only open blocks exist. This allows the memory device to appropriately compensate for rapid charge loss by modifying the voltages applied to selected and unselected word lines during subsequent read operations. This reduces error rates and improves reliability and data retention within the memory device. Consequently, the overall quality of service level of the memory subsystem is improved.

[0020] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0021] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0022] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., computer contained in a vehicle, industrial equipment or networked commercially available device), or such computing device that includes memory and processing power.

[0023] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intervening component), whether wired or wireless, including connections such as electrical, optical, and magnetic connections.

[0024] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses, for example, memory subsystem 110 to write data to and read data from memory subsystem 110.

[0025] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access memory components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0026] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0027] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory. The crosspoint array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0028] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0029] While non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0030] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0031] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0032] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although in Figure 1 The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but instead may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0033] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0034] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0035] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory system controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device 130 having on-die control logic (e.g., local controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device. For example, memory device 130 may represent a single die having some control logic embodied thereon (e.g., local media controller 135). In some embodiments, one or more components of memory subsystem 110 may be omitted.

[0036] In one embodiment, the memory subsystem 110 includes a memory device programming management component 113 that can monitor, control, and / or manage data access operations (e.g., read operations) performed on a non-volatile memory device (e.g., memory device 130) of the memory subsystem 110. The access management component 113 is responsible for applying (or indicating which voltages are applied) specific voltages to the memory device 130 during access operations. Additionally, the access management component 113 may perform associated calibration operations to determine the appropriate voltages to be applied during access operations. For example, before performing a read operation on the memory device 130, the access management component 113 may perform a calibration operation to measure changes in string resistance in blocks of the array of memory device 130 and determine whether the change in string resistance is attributable to rapid charge loss in the memory cells of the string or to the presence of open blocks. After determining that the change in string resistance is attributable to rapid charge loss, the access management component 113 may immediately determine the associated offset (i.e., calibrated read voltage level) of the selected word line voltage and the unselected word line voltage applied to the memory array during the read operation. If it is determined that the change in series resistance is not attributable to rapid charge loss but to the presence of an open block, then the access management component can determine that no read voltage compensation is required and that read operations can be performed using the default voltage level.

[0037] In one embodiment, access management component 113 determines a first magnitude of voltage applied to the selected word line among the plurality of word lines at a first time after the selected word line among the plurality of word lines has been programmed, when a first change in the output voltage (e.g., vreg2) of the memory array equals a first set amount. Access management component 113 further determines a second magnitude of voltage applied to the selected word line among the plurality of word lines at a second time before the selected word line among the plurality of word lines has been read, when a second change in the output voltage (e.g., vreg2) of the memory array equals the first set amount. Additionally, access management component 113 determines whether the second magnitude is less than the first magnitude, and in response to determining whether the second magnitude is less than the first magnitude, determines that charge loss has occurred on at least one memory cell associated with the selected word line. Further details regarding the operation of access management component 113 are described below.

[0038] Figure 2A The first device, in the form of a memory device 130, and the memory subsystem controller 115, in the form of a memory subsystem, are, according to the embodiment, (e.g., Figure 1 A simplified block diagram of communication between a second device and a memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and the like. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0039] Memory device 130 includes an array 204 of memory cells logically arranged in rows and columns. Memory cells arranged in logical rows are typically connected to the same access line (e.g., a word line), while memory cells arranged in logical columns are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 204 ( Figure 2A (Not shown in the image) can be programmed to one of at least two target data states.

[0040] Row decoding circuitry 208 and column decoding circuitry 210 are provided to decode address signals. Address signals are received and decoded to access memory cell array 204. Memory device 130 also includes input / output (I / O) control circuitry 260, which manages inputs of commands, addresses, and data to memory device 130, as well as outputs of data and status information from memory device 130. Address register 214 communicates with I / O control circuitry 260, row decoding circuitry 208, and column decoding circuitry 210 to latch address signals before decoding. Command register 224 communicates with I / O control circuitry 260 and local media controller 135 to latch incoming commands.

[0041] A controller (e.g., a local media controller 135 within memory device 130) controls access to memory cell array 204 in response to commands and generates status information for external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, programming operations, and / or erase operations) on memory cell array 204. The local media controller 135 communicates with row decoding circuitry system 208 and column decoding circuitry system 210 to control them in response to addresses. In one embodiment, the local media controller 134 includes an access management component 113 that can implement tests and calibrations for charge loss compensation during read operations within the memory device of memory device 130.

[0042] The local media controller 135 also communicates with cache register 218. Cache register 218 latches incoming or outgoing data, such as data initiated by the local media controller 135, to temporarily store data while the memory cell array 204 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 218 to data register 270 for transmission to memory cell array 204; new data can then be latched from I / O control circuitry 260 into cache register 218. During read operations, data can be transferred from cache register 218 to I / O control circuitry 260 for output to memory subsystem controller 115; new data can then be transferred from data register 270 to cache register 218. Cache register 218 and / or data register 270 may form a page buffer (e.g., a portion thereof) of memory device 130. The page buffer may additionally include sensing devices ( Figure 2A(Not shown in the diagram), it is used to sense the data status of the memory cells, for example, by sensing the status of the data lines connected to the memory cell array 204. The status register 222 can communicate with the I / O control circuitry system 260 and the local memory controller 135 to latch status information for output to the memory subsystem controller 115.

[0043] Memory device 130 receives control signals from local media controller 135 at memory subsystem controller 115 via control link 232. For example, control signals may include chip enable signal CE#, command latch enable signal CLE, address latch enable signal ALE, write enable signal WE#, read enable signal RE#, and write protection signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may also be received via control link 232. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 236, and outputs data to memory subsystem controller 115 via I / O bus 236.

[0044] For example, commands can be received at I / O control circuitry 260 via input / output (I / O) pins [7:0] of I / O bus 236 and then written to command register 224. Addresses can be received at I / O control circuitry 236 via input / output (I / O) pins [7:0] of I / O bus 260 and then written to address register 214. Data can be received at I / O control circuitry 260 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and then written to cache register 218. The data can then be written to data register 270 for programming memory cell array 204.

[0045] In this embodiment, the cache register 218 may be omitted, and data may be written directly to the data register 270. Data may also be output on the input / output (I / O) pins [7:0] for an 8-bit device or the input / output (I / O) pins [15:0] for a 16-bit device. While references may be made to the I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to the memory device 130 via an external device (e.g., the memory subsystem controller 115).

[0046] Those skilled in the art should understand that additional circuitry and signals can be provided and have been simplified. Figure 2A The memory device 130. It should be understood that, reference Figure 2A The functionality of the various block components described may not necessarily be separate from different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 2A The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 2A The functionality of a single block component. Furthermore, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0047] Figure 2B This is a schematic diagram illustrating a string 200 of memory cells in a data block of a memory device in a memory subsystem according to some embodiments of the present disclosure. In one embodiment, string 200 represents, for example, a portion of a memory device 130 from memory cell array 204, such as... Figure 2A As shown. String 200 includes a plurality of memory cells 212 (i.e., charge storage devices), for example, up to 32 memory cells (or more) in some embodiments. String 200 includes a source-side select transistor, referred to as source-select gate 220 (SGS) (typically an n-channel transistor), coupled between the memory cells 212 and a common source 226 at one end of string 200. The common source 226 may comprise, for example, a co-doped semiconductor material and / or other conductive material. At the other end of string 200, a drain-side select transistor, referred to as drain-select gate 230 (SGD) (typically an n-channel transistor), and a gate-induced drain leakage (GIDL) generator 240 (GG) (typically an n-channel transistor) are coupled between one of the memory cells 212 and a data line 234, which is typically referred to as a "bit line" in this art. The common source 226 can be coupled to a reference voltage (e.g., ground voltage or simply "ground" [Gnd]) or a voltage source (e.g., a charge pump circuit or power supply, which may be selectively configured to a specific voltage suitable for optimizing programming operations).

[0048] Each memory cell 212 may include, for example, a floating gate transistor or a charge-retaining transistor, and may include a single-level memory cell or a multi-level memory cell. The floating gate may be referred to as charge storage structure 235. The memory cell 212, source-select gate 220, drain-select gate 230, and GIDL generator 240 may be controlled by signals on their respective control gates 250.

[0049] For example, a control signal may be applied to a select line (not shown) to select a string, or to an access line (not shown) to select a memory cell 212, either through or under the guidance of the access management component 113. In some cases, a control gate may be formed part of a select line (for selecting a device) or an access line (for a cell). A drain select gate 230 receives a voltage that causes the drain select gate 230 to select or deselect the string 200. In one embodiment, each corresponding control gate 250 is connected to a separate word line (i.e., an access line), such that each device or memory cell can be controlled individually.

[0050] In one embodiment, to detect charge loss in one or more memory devices forming a portion of string 200, access management component 113 may perform a calibration operation prior to operation to measure a change in the string resistance of string 200 and determine whether the change in string resistance is attributable to rapid charge loss in the memory cells of string 200 or to the presence of open blocks. The specific application of a signal to string 200 may vary depending on the embodiment, as described in more detail below.

[0051] Figure 3 According to the embodiments, as referenced Figure 2A This is a schematic diagram of a portion of a memory cell array 204 (e.g., a NAND memory array) that can be used in a memory device of the described type. The memory array 204 includes access lines, such as word lines 3020 to 3024, and data lines, such as bit lines. Word lines 302 can be connected to global access lines (e.g., global word lines) in a many-to-one relationship. Figure 3 Not shown in the diagram. In some embodiments, the memory array 204 may be formed over a semiconductor, which may be conductively doped to have a conductivity type, such as p-type conductivity, for example forming a p-well, or n-type conductivity, for example forming an n-well.

[0052] Memory array 204 may be arranged in rows (each row corresponding to word lines 302) and columns (each column corresponding to bit lines). Each column may contain a string of memory cells (e.g., non-volatile memory cells) connected in series, such as one of NAND strings 2060 to 2063. Each NAND string 206 may be connected (e.g., selectively connected) to a common source (SRC) 316 and may contain a plurality of memory cells. Memory cells may represent non-volatile memory cells used for data storage. The memory cells of each NAND string 206 may be connected in series between the select gate (e.g., a field-effect transistor) of a source select transistor (typically referred to as a select gate-source (SGS)) and the select gate of a drain select transistor (typically referred to as a select gate-drain (SGD)). The source select gate may be commonly connected to select line 3024, such as a source select line (SGS), and the drain select gate may be commonly connected to select line 3020, such as a drain select line (SGD). Although depicted as a conventional field-effect transistor, the select gate can utilize a structure similar to (e.g., identical to) a memory cell. The select gate can represent several select gates connected in series, each configured to receive the same or independent control signal.

[0053] The source of each select gate can be connected to a common source 316. The drain of each source select gate can be connected to a memory cell of the corresponding NAND string 306. Therefore, each source select gate can be configured to selectively connect the corresponding NAND string 306 to the common source 316. The drain of each drain select gate can be connected to a bit line of the corresponding NAND string 206. The source of each drain select gate can be connected to a memory cell of the corresponding NAND string 206. Therefore, each drain select gate can be configured to selectively connect the corresponding NAND string 206 to the corresponding bit line.

[0054] Figure 3 The memory array 204 can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 316, NAND string 306, and bit lines extend in a generally parallel plane. Alternatively, Figure 3 The memory array 204 in the memory array can be a three-dimensional memory array, for example, in which the NAND string 206 can extend substantially perpendicular to the plane containing the common source 316 and substantially parallel to the plane containing the bit lines containing the common source 316.

[0055] A typical construction of a memory cell includes a data storage structure (e.g., a floating gate, a charge trap, etc.) that determines the data state of the memory cell (e.g., through changes in a threshold voltage), and a control gate, such as... Figure 3As shown. The data storage structure may include both conductive and dielectric structures, while the control gate is typically formed of one or more conductive materials. In some cases, the memory cell may additionally have defined source and drain terminals. The control gate of the memory cell is connected to (and in some cases, forms) word line 302.

[0056] A column of memory cells may be one or more NAND strings 306 selectively connected to a given word line 302. A row of memory cells may (but does not need to) contain all memory cells that are commonly connected to a given word line 302. A row of memory cells may often be divided into one or more physical page groups of memory cells, and a physical page of memory cells often contains every other memory cell that is commonly connected to a given word line 302. For example, a memory cell that is commonly connected to word line 3021 and selectively connected to an even number of bit lines may be a physical page of memory cells (e.g., an even number of memory cells), while a memory cell that is commonly connected to word line 3021 and selectively connected to an odd number of bit lines may be another physical page of memory cells (e.g., an odd number of memory cells).

[0057] Other groups of memory cells commonly connected to a given word line 302 may also define physical pages of the memory cells. For some memory devices, all memory cells commonly connected to a given word line may be considered physical pages of the memory cells. A portion of a physical page of a memory cell (in some embodiments, it may still be an entire row) that is read during a single read operation or programmed during a single programmable operation (e.g., the upper or lower page of the memory cell) may be considered a logical page of the memory cell. A block of memory cells may contain those memory cells configured to be erased together, such as all memory cells connected to word line 302 (e.g., all NAND strings 206 sharing a common word line 202). Unless explicitly distinguished, reference to a page of a memory cell herein refers to a memory cell that is a logical page of the memory cell. This is in conjunction with the discussion of NAND flash memory. Figure 3 Examples are provided, but the embodiments and concepts described herein are not limited to a particular array architecture or structure and may include other structures (e.g., SONOS, phase-change, ferroelectric, etc.) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0058] In one embodiment, the output voltage (i.e., vreg2) at the drain terminal of each of the memory strings 306 is collected and provided to one input of comparator 320. A reference voltage (i.e., vref) is provided to the other input of comparator 320. The comparator output (i.e., flag) of comparator 320 changes state when the output voltage (i.e., vreg2) reaches the reference voltage (i.e., vref). For example, if the comparator output (i.e., flag) is currently in a high state and the output voltage (i.e., vreg2) is currently higher than the reference voltage (i.e., vref), then once the output voltage (i.e., vreg2) decreases and / or the reference voltage (i.e., vref) increases to make the output voltage (i.e., vreg2) equal to or less than the reference voltage (i.e., vref), the comparator output (i.e., flag) can switch to a low state. Once the output voltage (i.e., vreg2) increases again and / or the reference voltage (i.e., vref) decreases again so that the output voltage (i.e., vreg2) is equal to or greater than the reference voltage (i.e., vref) again, the comparator output (i.e., the flag) can switch back to the high state voltage.

[0059] Figure 4 This is a flowchart of an example method for compensating for charge loss during a read operation in a memory device according to some embodiments of the present disclosure. Method 400 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1 The access management component 113 executes. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0060] At operation 405, the word line voltage is ramped up. For example, processing logic (e.g., access management component 113) can cause the voltage applied to word lines of the memory array, such as word lines 3020-3024 of memory array 204 of memory device 130, to ramp up to a specific voltage, such as an unselected word line voltage. Figure 5As shown, voltage signal 502 is applied to each of the word lines in memory array 204, including both selected word lines (i.e., word lines to which memory access operations (e.g., read operations) will be performed) and unselected word lines (i.e., the remaining word lines to which memory access operations will not be performed). In one embodiment, the voltage of the unselected word line is a pass voltage (i.e., Vpass), although the specific value may vary.

[0061] At operation 410, the output voltage is sampled. For example, the processing logic may sample the first output voltage (i.e., vreg2) of memory array 204. As described above, the output voltage (i.e., vreg2) may represent the bit line voltage in memory array 204 and may be sampled at nodes connected to each of multiple memory strings (e.g., strings 3060-3063 in memory array 204). Figure 5 As shown, the output voltage (i.e., vreg2) signal 504 can vary depending on the state of the block being read. For example, signal 504a can represent the output voltage (i.e., vreg2) of a closed block (i.e., a block that has been fully written), signal 504b can represent the output voltage of an open block (i.e., a block that has only been partially written), and signal 504c can represent the output voltage of a closed block that has experienced rapid charge loss (QCL). However, the magnitude of the output voltage signal 504 alone does not indicate the state of the block being read.

[0062] At operation 415, the reference voltage is ramped up. For example, the processing logic may cause the reference voltage (i.e., vref) to change incrementally (e.g., ramping up or ramping down) over a first time period. In one embodiment, the reference voltage (i.e., vref) is received from a voltage source inside or outside the memory device 130 and is applied as input to comparator 320 along with the output voltage (i.e., vreg2) sampled at operation 410. Figure 5 As shown, the magnitude of the reference voltage signal 510 can periodically increase in fixed increments. In other embodiments, the reference voltage signal may start at a higher level and periodically decrease over time.

[0063] At operation 420, a determination is made. For example, the processing logic may determine whether the reference voltage (i.e., vref) is equal to the output voltage (i.e., vreg2). In one embodiment, when the inputs are equal, the output of comparator 320 will change state (e.g., from a high state to a low state), thereby raising a "flag" signal to notify access management component 113. Figure 5As shown, when the output voltage signal 504 equals the reference voltage signal 510, the flag signal 514 will change state. Depending on whether the output voltage (i.e., vref2) is 504a, 504b, or 504c, the flag signal will change state at the corresponding time, as indicated by flag signals 514a, 514b, or 514c. If the reference voltage (i.e., vref) is not equal to the output voltage (i.e., vreg2), then the processing logic continues at operation 415 to cause the reference voltage to ramp up incrementally.

[0064] If the reference voltage (i.e., vref) equals the output voltage (i.e., vreg2), then at operation 425, the reference voltage is changed. For example, the processing logic can cause the reference voltage to change (e.g., increase or decrease) by a fixed step size. Figure 5 As shown, without considering the voltage magnitude when the reference voltage signal 510 reaches any of the output voltage signals 504a, 504b, or 504c, the reference voltage signal 510 is subsequently incremented by the same fixed step size, as indicated by the resulting reference voltage signals 510a, 510b, or 510c. In one embodiment, the fixed step size is greater than the increment used to ramp up the reference voltage signal 510 at operation 415 (e.g., greater than 4×). In one embodiment, the fixed step size is used to ensure that a comparison can be made when the change in the output voltage of the memory array is equal to a set amount for different states of the block being read (e.g., a closed block, an open block, or a closed block with a QCL). In other embodiments, instead of increasing the reference voltage by a fixed step size, the processing logic may alternatively decrease the reference voltage by a fixed step size.

[0065] At operation 430, the word line voltage is ramped down. For example, processing logic can cause the voltage applied to a selected word line to ramp down. Figure 5 As shown, the voltage signal 5022 applied to the selected word line (e.g., word line 3022) of the memory array 204 slopes down to a lower value, while the voltage signal 5021 applied to the unselected word lines (e.g., word lines 3021 and 3023) remains at the unselected word line voltage.

[0066] At operation 435, the output voltage is sampled. For example, the processing logic may sample the second output voltage (i.e., vreg2) of memory array 204 after the selected word line voltage signal 5022 has ramped down. As described above, the output voltage (i.e., vreg2) may represent the bit line voltage in memory array 204 and may be sampled at nodes connected to each of multiple memory strings (e.g., strings 3060-3063 in memory array 204). Figure 5 As shown, the output voltage (i.e., vreg2) signals 504a, 504b, or 504c can vary depending on the state of the block being read.

[0067] At operation 440, a determination is made. For example, the processing logic may determine whether a reference voltage (i.e., vref) increased by a fixed step is equal to the output voltage (i.e., vreg2). In one embodiment, when the inputs are equal, the output of comparator 320 will change state (e.g., from a high state to a low state), thereby raising a "flag" signal to notify access management component 113. Figure 5 As shown, when the output voltage signals 504a, 504b, or 504c are equal to the reference voltage signals 510a, 510b, or 510c with a fixed step size, the corresponding flag signals 514a, 514b, or 514c will change state. If the reference voltage with a fixed step size (i.e., vref) is not equal to the output voltage (i.e., vreg2), then the processing logic continues to cause the word line voltage signal 5022 to slope down at operation 430.

[0068] If the reference voltage (i.e., vref) increased by a fixed step amount equals the output voltage (i.e., vreg2), then at operation 445, the magnitude is determined. For example, the processing logic can determine the magnitude of the voltage applied to the selected word line at the time when the reference voltage (i.e., vref) increased by a fixed step amount equals the output voltage (i.e., vreg2). Figure 5 As shown, the time when the reference voltage (i.e., vref) increased by a fixed step size equals the output voltage (i.e., vreg2) varies depending on the state of the block being read, just as the magnitude of voltage signal 5022 does. For example, when the magnitude of voltage signal 5022 is V1, reference voltage signal 510a equals output voltage 504a and reference voltage signal 510c equals output voltage 504c, but when the magnitude of voltage signal 5022 is a lower voltage V2, reference voltage signal 510b equals output voltage 504b.

[0069] At operation 450, a determination is made. For example, the processing logic may determine whether the magnitude of the voltage signal 5022 applied to the selected word line 3022 at the time when the reference voltage (i.e., vref) increased by a fixed step amount equals the output voltage (i.e., vreg2) is lower than a expected magnitude. In one embodiment, the expected magnitude is voltage V1 and is determined based on the magnitude of the voltage signal 5022 at an earlier time immediately after the selected word line is programmed, when the reference voltage increased by a fixed step amount equals the output voltage of the memory array. Since a finite amount of time has elapsed since the selected word line was programmed, there has not yet been enough time for rapid charge loss to occur.

[0070] Therefore, if the magnitude of voltage signal 5022 is determined to be equal to (i.e., not less than) the expected magnitude (e.g., V1), then at operation 455, the processing logic can determine that no charge loss has occurred. In one embodiment, access management component 113 may use a default read voltage level to perform a read operation to read data from memory array 204.

[0071] However, if the magnitude of voltage signal 5022 (e.g., V2) is determined to be less than the expected magnitude (e.g., V1), then at operation 460, the processing logic can determine that a rapid charge loss has occurred. In one embodiment, access management component 113 can determine that the magnitude of the voltage applied to a selected word line at a time when a reference voltage with a fixed step size is changed equal to a second output voltage of the memory array is less than the expected magnitude (e.g., V1-V2) and determine a voltage offset corresponding to said magnitude. For example, access management component 113 can query a lookup table maintained in memory device 130 containing multiple entries, each of which maps a corresponding difference to a corresponding voltage offset.

[0072] At operation 465, a read operation is performed. For example, the processing logic could cause a read voltage with a magnitude based on a voltage offset to be applied to the selected word line to perform the read operation. Figure 5 As shown, the voltage offset determined at operation 460 can be used to calibrate both the voltage applied to the selected word line (i.e., the read voltage) and the voltage applied to the unselected word line (i.e., the pass voltage).

[0073] Figure 6 An example machine is described as a computer system 600, within which a set of instructions is executable to cause the machine to perform any or more of the methods discussed herein. In some embodiments, the computer system 600 may correspond to including, coupled to, or using a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., to execute the operating system to perform operations corresponding to...). Figure 1 The operation of the access management component 113) of the host system (e.g., Figure 1 (Host system 120). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0074] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should also be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0075] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0076] Processing device 602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communication via network 620.

[0077] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium) on which one or more instruction sets 626 or software embodying any or more of the methods or functions described herein are stored. Instructions 626 may also reside wholly or at least partially in main memory 604 and / or processing device 602 during execution by computer system 600, the main memory 604 and processing device 602 also constituting machine-readable storage medium. Machine-readable storage medium 624, data storage system 618 and / or main memory 604 may correspond to... Figure 1 The memory subsystem 110.

[0078] In one embodiment, instruction 626 includes instructions for implementing the corresponding Figure 1The access management component 113 provides functional instructions. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. The term "machine-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0079] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0080] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0081] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0082] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0083] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0084] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications can be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory device comprising: A memory array that includes multiple word lines; and Control logic, which is operatively coupled to the memory array to perform operations including: Initiate a read operation on the memory array; Performing a calibration operation to detect changes in the series resistance in the memory array, wherein performing the calibration operation includes: This causes the voltage applied to the plurality of word lines to ramp up to the voltage of the unselected word line; The first output voltage of the memory array is sampled; This causes the reference voltage to change incrementally during the first time period; and The reference voltage is determined to be equal to the first output voltage of the memory array; Determine whether the change in series resistance can be attributed to charge loss in the memory array; and In response to determining that the change in the series resistance is attributable to charge loss in the memory array, the read operation is performed using a calibrated read voltage level to read data from the memory array.

2. The memory device of claim 1, wherein performing the calibration operation further comprises: Change the reference voltage by a fixed step size; This causes a voltage ramp-down applied to a selected word line among the plurality of word lines; The second output voltage of the memory array is sampled; and The reference voltage, which has been changed by the fixed step size, is determined to be equal to the second output voltage of the memory array.

3. The memory device of claim 2, wherein determining whether the change in series resistance is attributable to charge loss in the memory array comprises: Determine the amount of voltage applied to the selected word line at the time when the reference voltage, which has been changed by the fixed step size, is equal to the second output voltage of the memory array; Determine whether the amount of voltage applied to the selected word line at the time when the reference voltage, which has been changed by the fixed step size, is equal to the second output voltage of the memory array is lower than the expected amount; and In response to determining that the magnitude of the voltage applied to the selected word line at the time when the reference voltage, which has been changed by the fixed step size, is equal to the second output voltage of the memory array is lower than the expected magnitude, it is determined that the change in the series resistance can be attributed to charge loss in the memory array.

4. The memory device of claim 3, wherein performing the read operation to read data from the memory array using a calibrated read voltage level comprises: Determine the amount by which the voltage applied to the selected word line at the time when the reference voltage, which has been changed by the fixed step size, is equal to the second output voltage of the memory array is lower than the expected amount; Determine the voltage offset corresponding to the stated amount; and This causes a read voltage with a value based on the voltage offset to be applied to the selected word line to perform the read operation.

5. The memory device of claim 3, wherein the expected value is based on the value of the voltage applied to the selected word line at an earlier time immediately after the selected word line is programmed, when the reference voltage, which changes by the fixed step size, is equal to the third output voltage of the memory array.

6. The memory device of claim 1, wherein the control logic further performs operations including: In response to determining that the change in the series resistance is not attributable to charge loss in the memory array, the read operation is performed using the default read voltage level to read the data from the memory array.

7. A method comprising: Initiate a read operation on the memory array of the memory device; Performing a calibration operation to detect changes in the series resistance in the memory array, wherein performing the calibration operation includes: This causes the voltage applied to multiple word lines of the memory array to ramp up to the voltage of an unselected word line; The first output voltage of the memory array is sampled; This causes the reference voltage to change incrementally during the first time period; and The reference voltage is determined to be equal to the first output voltage of the memory array; Determine whether the change in series resistance can be attributed to charge loss in the memory array; and In response to determining that the change in the series resistance is attributable to charge loss in the memory array, the read operation is performed using a calibrated read voltage level to read data from the memory array.

8. The method of claim 7, wherein performing the calibration operation further comprises: Change the reference voltage by a fixed step size; This causes a voltage ramp-down applied to a selected word line among the plurality of word lines; The second output voltage of the memory array is sampled; and The reference voltage, which has been changed by the fixed step size, is determined to be equal to the second output voltage of the memory array.

9. The method of claim 8, wherein determining whether the change in series resistance is attributable to charge loss in the memory array comprises: Determine the amount of voltage applied to the selected word line at the time when the reference voltage, which has been changed by the fixed step size, is equal to the second output voltage of the memory array; Determine whether the amount of voltage applied to the selected word line at the time when the reference voltage, which has been changed by the fixed step size, is equal to the second output voltage of the memory array is lower than the expected amount; and In response to determining that the magnitude of the voltage applied to the selected word line at the time when the reference voltage, which has been changed by the fixed step size, is equal to the second output voltage of the memory array is lower than the expected magnitude, it is determined that the change in the series resistance can be attributed to charge loss in the memory array.

10. The method of claim 9, wherein performing the read operation using a calibrated read voltage level to read data from the memory array comprises: Determine the amount by which the voltage applied to the selected word line at the time when the reference voltage, which has been changed by the fixed step size, is equal to the second output voltage of the memory array is lower than the expected amount; Determine the voltage offset corresponding to the stated amount; and This causes a read voltage with a value based on the voltage offset to be applied to the selected word line to perform the read operation.

11. The method of claim 9, wherein the expected value is based on the value of the voltage applied to the selected word line at an earlier time immediately after the selected word line is programmed, when the reference voltage, which has been changed by the fixed step size, is equal to the third output voltage of the memory array.

12. The method of claim 7, further comprising: In response to determining that the change in the series resistance is not attributable to charge loss in the memory array, the read operation is performed using the default read voltage level to read the data from the memory array.

13. A memory device comprising: A memory array that includes multiple word lines; and Control logic, which is operatively coupled to the memory array to perform operations including: Determine a first value of the voltage applied to the selected word line among the plurality of word lines at a first time after the selected word line among the plurality of word lines has been programmed, when a first change in the output voltage of the memory array is equal to a first set amount. Determine a second value of the voltage applied to the selected word line among the plurality of word lines at a second time prior to the selected word line being read, when a second change in the output voltage of the memory array is equal to a first preset amount, wherein determining the second value of the voltage applied to the selected word line includes: This causes the voltage applied to the plurality of word lines to ramp up to the voltage of the unselected word line; The output voltage of the memory array is sampled; This causes the reference voltage to change incrementally during the first time period; and The reference voltage is determined to be equal to the output voltage of the memory array; Determine whether the second value is less than the first value; and In response to determining that the second value is less than the first value, it is determined that charge loss has occurred on at least one memory cell associated with the selected word line.

14. The memory device of claim 13, wherein determining the second magnitude of the voltage applied to the selected word line comprises: Change the reference voltage by a fixed step size; This causes a voltage sag applied to the selected word line among the plurality of word lines; The output voltage of the memory array is sampled; and At the second time, it is determined that the reference voltage, which has changed by the fixed step size, is equal to the output voltage of the memory array.

15. The memory device of claim 13, wherein the control logic further performs operations including: Determine the amount by which the second value is lower than the first value; Determine the voltage offset corresponding to the stated amount; and This causes a read voltage with a value based on the voltage offset to be applied to the selected word line to perform a read operation.

16. The memory device of claim 13, wherein the control logic further performs operations including: In response to determining that the second value is equal to the first value, it is determined that no charge loss has occurred on any memory cell associated with the selected word line.

17. The memory device of claim 16, wherein the control logic further performs operations including: In response to determining that no charge loss has occurred on at least one memory cell associated with the selected word line, a read voltage with a default value is applied to the selected word line to perform a read operation.

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