A semiconductor structure and a method for manufacturing the same

Abstract

An embodiment of the present invention discloses a semiconductor structure, comprising: a substrate and a through hole located in the substrate; a conductive pillar located in the through hole, wherein the conductive pillar has a groove extending from the upper surface of the conductive pillar towards the inside; a core layer located in the groove; wherein the Young's modulus of the core layer is less than the Young's modulus of the conductive pillar.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] As the feature size of integrated circuits continues to shrink and the device interconnection density continues to increase, traditional two-dimensional packaging can no longer meet the needs of the industry. The vertical interconnection stacked packaging method based on the Through Silicon Via (TSV) interconnection technology, with its advantages of short-distance interconnection and high-density integration, has gradually led the trend of the development of packaging technology.

[0003] However, the existing through-silicon vias are prone to protruding outside the substrate after thermal expansion, affecting the flatness of the substrate. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a semiconductor structure and a manufacturing method thereof to solve at least one problem in the background art.

[0005] To achieve the above object, the technical solution of the present invention is implemented as follows:

[0006] Embodiments of the present invention provide a semiconductor structure, including:

[0007] A substrate and a through hole located in the substrate;

[0008] A conductive pillar located in the through hole, and the conductive pillar has a groove extending from the upper surface of the conductive pillar towards the inside;

[0009] A core layer located in the groove; wherein, the Young's modulus of the core layer is less than that of the conductive pillar.

[0010] In the above solution, the material of the core layer includes polysilicon.

[0011] In the above solution, the conductive pillar extends in a direction perpendicular to the substrate, the extending direction of the core layer is the same as that of the conductive pillar, and the core layer is located on the central axis of the conductive pillar.

[0012] In the above solution, the core layer is a circular pillar, and the diameter of the circular pillar is between and ; or, the core layer is a rectangular pillar, and the side length of the rectangular pillar is between and ;

[0013] In the above solution, the semiconductor structure further includes at least one buffer layer located between the substrate and the conductive pillar, and the Young's modulus of the buffer layer is less than that of the substrate.

[0014] In the above solution, the number of the buffer layers is between 1 and 3, and the thickness of each layer of the buffer layer is between and .

[0015] In the above solution, the material of the buffer layer is the same as that of the core layer.

[0016] In the above solution, the number of the buffer layers is multiple; the semiconductor structure further includes: a first insulating layer located between any two adjacent layers of the multiple buffer layers.

[0017] In the above solution, the semiconductor structure further includes: a second insulating layer disposed in the through hole; wherein, the second insulating layer is located between the substrate and the buffer layer.

[0018] In the above solution, the thickness of the second insulating layer is to

[0019] In the above solution, the semiconductor structure further includes: a barrier layer disposed in the through hole, and the barrier layer is located between the buffer layer and the conductive pillar.

[0020] In the above solution, the material of the barrier layer includes at least one of tantalum or titanium.

[0021] An embodiment of the present invention further provides a manufacturing method of a semiconductor structure, including:

[0022] Providing a substrate, and performing an etching process on the substrate to form a through hole in the substrate;

[0023] Forming a conductive pillar with a groove in the through hole, and the groove extends from the upper surface of the conductive pillar to the inside of the conductive pillar;

[0024] Forming a core layer in the groove; wherein, the Young's modulus of the core layer is less than that of the conductive pillar.

[0025] In the above solution, the substrate includes an active surface and a back surface opposite to the active surface;

[0026] Performing an etching process on the substrate to form a through hole in the substrate, including:

[0027] Etching from the active surface into the substrate to form the through hole that does not penetrate the substrate;

[0028] After forming the core layer in the conductive pillar, the method further includes:

[0029] Starting from the back surface, a thinning process is performed on the substrate until the conductive pillars are exposed.

[0030] In the above solution, the substrate includes an active surface and a back surface opposite to the active surface, and metal pads are arranged on the active surface;

[0031] Performing an etching process on the substrate to form a through hole in the substrate, including:

[0032] Etching the substrate from the back surface to form the through hole penetrating the substrate, and the through hole exposes the metal pads.

[0033] In the above solution, before forming the conductive pillars in the through hole, the method further includes:

[0034] Forming at least one buffer layer between the substrate and the conductive pillars, and the Young's modulus of the buffer layer is less than that of the substrate.

[0035] In the above solution, the number of the buffer layers is multiple; the method further includes:

[0036] Forming a first insulating layer between any two adjacent layers of the multiple buffer layers;

[0037] Forming a second insulating layer between the substrate and the buffer layer.

[0038] In the above solution, after forming at least one buffer layer between the substrate and the conductive pillars, it further includes: forming a barrier layer between the buffer layer and the conductive pillars.

[0039] In the above solution, forming a conductive pillar with a groove in the through hole, including:

[0040] Depositing a conductive material in the through hole, controlling the deposition time of the conductive material so that the conductive material does not completely fill the through hole, and obtaining the conductive pillar with a groove.

[0041] In the above solution, forming a conductive pillar with a groove in the through hole, including:

[0042] Depositing a conductive material in the through hole, and the conductive material completely fills the through hole;

[0043] Removing part of the conductive material by etching to obtain the conductive pillar with a groove.

[0044] The semiconductor structure and its manufacturing method provided by the embodiments of the present invention, wherein the semiconductor structure includes: a substrate and a through hole located in the substrate; a conductive pillar located in the through hole, the conductive pillar having a groove extending from the upper surface towards the inside; a core layer located in the groove; wherein, the Young's modulus of the core layer is less than that of the conductive pillar. Thus, the core layer can relieve the stress generated by the conductive pillar during thermal expansion, thereby reducing the degree of outward protrusion of the conductive pillar when heated and improving the flatness of the substrate.

[0045] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be understood through the practice of the present invention. Description of the Drawings

[0046] Figure 1 Schematic diagram of a semiconductor structure provided in the related art;

[0047] Figure 2a Schematic diagram of a semiconductor structure provided by an embodiment of the present invention;

[0048] Figure 2b Schematic diagram of a semiconductor structure provided by another embodiment of the present invention;

[0049] Figure 3 Flow chart of a manufacturing method of a semiconductor structure provided by an embodiment of the present invention;

[0050] Figures 4a - 4e Process flow chart of a manufacturing method of a semiconductor structure provided by an embodiment of the present invention;

[0051] Figures 5a - 5c Process flow chart of a manufacturing method of a semiconductor structure provided by another embodiment of the present invention. Detailed Embodiments

[0052] The exemplary embodiments disclosed by the present invention will be described in more detail below with reference to the drawings. Although the exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present invention can be more thoroughly understood and the scope of the present invention disclosed can be fully communicated to those skilled in the art.

[0053] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention; that is, not all features of actual embodiments are described herein, and well-known functions and structures are not described in detail.

[0054] In the drawings, for the sake of clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. Like reference numerals throughout the drawings denote like elements.

[0055] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another. Thus, a first element, component, region, layer, or section discussed below may be denoted as a second element, component, region, layer, or section without departing from the teachings of the present invention. And when a second element, component, region, layer, or section is discussed, it does not necessarily imply the existence of a first element, component, region, layer, or section in the present invention.

[0056] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein for convenience in describing the relationship of one element or feature to another element or feature shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "over" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0057] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0058] The vertical interconnection stacked packaging method based on the Through Silicon Via (TSV) interconnection technology stacks two or more semiconductor chips together and realizes signal transmission between the semiconductor chips through the through-silicon vias.

[0059] Figure 1 FIG. is a schematic diagram of a semiconductor structure provided in the related art. As shown in the figure, the semiconductor structure includes a substrate 10 and a through hole 11 located in the substrate 10; an insulating layer 12 covering the side wall of the through hole 11; a conductive pillar 13 formed in the through hole 11 and isolated from the substrate 10 by the insulating layer 12; a redistribution layer 14 formed on one side of the substrate 10; and a metal pad 15 formed in the redistribution layer 14 and electrically connected to the conductive pillar 13. When the semiconductor structure is bonded to other structures, the conductive pillar 13 can provide vertical interconnection between the semiconductor structure and the other structures.

[0060] However, when the semiconductor structure is bonded to other structures, the semiconductor structure is heated. During this process, the conductive pillar 13 expands due to heat, and the expansion generates a large stress on the surrounding environment. The stress reacts on the conductive pillar 13, and finally causes the conductive pillar 13 to protrude outward from the substrate 10, reducing the flatness of the substrate 10 and making the performance of the semiconductor structure possibly deteriorate.

[0061] Based on this, the following technical solutions of the embodiments of the present invention are proposed:

[0062] The embodiments of the present invention provide a semiconductor structure, including: a substrate and a through hole located in the substrate; a conductive pillar located in the through hole, and the conductive pillar has a groove extending from the upper surface of the conductive pillar to the inside; a core layer located in the groove; wherein, the Young's modulus of the core layer is less than the Young's modulus of the conductive pillar.

[0063] In this way, the core layer can relieve the stress generated by the conductive pillars when they expand due to heat, thereby reducing the degree to which the conductive pillars protrude outward when heated, improving the flatness of the substrate, and improving the overall performance of the semiconductor structure.

[0064] To make the above-mentioned objects, features, and advantages of the present invention more clearly understood, the following detailed description of the specific embodiments of the present invention is given in conjunction with the accompanying drawings. When describing the embodiments of the present invention in detail, for ease of explanation, the schematic diagrams may be partially enlarged according to the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention.

[0065] Figure 2a A schematic diagram of a semiconductor structure provided in an embodiment of the present invention. As shown, the semiconductor structure includes a substrate 20 and a through-hole 21 within the substrate 20; a conductive pillar 23 within the through-hole 21, each having a groove T extending inward from the upper surface of the conductive pillar 23; and a core layer 26 within the groove T. The Young's modulus of the core layer 26 is smaller than that of the conductive pillar 23.

[0066] In some embodiments, the substrate may be a silicon substrate. In other embodiments, the substrate may include other semiconductor elements, such as germanium; or semiconductor compounds, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; or other semiconductor alloys, such as silicon germanium, gallium arsenic phosphide, indium aluminum arsenide, gallium aluminum arsenide, indium gallium arsenide, indium gallium phosphide, and / or indium gallium arsenide phosphide, or combinations thereof. In a preferred embodiment, the substrate has a thickness between 40 and 70 μm.

[0067] The substrate 20 includes an active surface S and a back surface opposite to the active surface S. A device is disposed within the substrate 20 near the active surface S. In one embodiment, the device may be a memory, such as a dynamic random access memory (DRAM); however, the present invention is not limited thereto. In other embodiments, the device may be a logic chip, etc.

[0068] In one embodiment, a redistribution layer 24 is provided on the active surface S of the substrate 20. A metal pad 25 is provided within the redistribution layer 24. The metal pad 25 is located at one end of the conductive pillar 23 and is electrically connected to the conductive pillar 23. In an actual process, the through hole 21 is etched from the active surface S of the substrate 20 toward the back surface, and the redistribution layer 24 is formed after the core layer 26 is formed.

[0069] In one embodiment, the shape of the opening of the through hole 21 may be circular, but not limited thereto, in other embodiments, the shape of the opening of the through hole 21 may also be elliptical, polygonal, or the like.

[0070] The conductive pillar 23 extends in a direction perpendicular to the substrate 20, and the material of the conductive pillar 23 includes at least one of copper and tungsten. In some embodiments, the width of the conductive pillar 23 is between 2 - 10 μm, and the depth is between 5 - 100 μm.

[0071] In one embodiment, the extending direction of the core layer 26 is the same as that of the conductive pillar 23, and the core layer 26 is located on the central axis of the conductive pillar 23. Thus, the core layer 26 can more evenly relieve the stress generated when the conductive pillar 23 expands due to heat. In a specific embodiment, the material of the core layer 26 includes polysilicon. However, it is not limited thereto, and any material with a Young's modulus meeting the above requirements can be used as the core layer 26 in the embodiments of the present invention.

[0072] In one embodiment, the core layer 26 extends from the upper surface of the conductive pillar 23 into the conductive pillar 23 but does not penetrate the bottom of the conductive pillar 23, as Figure 2a shown. However, it is not limited thereto. In other embodiments, the core layer 26 extends from the upper surface of the conductive pillar 23 to the bottom surface of the conductive pillar 23, that is, it penetrates the conductive pillar 23.

[0073] In one embodiment, the core layer 26 is a circular pillar, and the diameter of the circular pillar is between and . However, it is not limited thereto. In other embodiments, the core layer 26 can also be a rectangular pillar, and the side length of the rectangular pillar is between and .

[0074] In one embodiment, the semiconductor structure further includes at least one buffer layer 27 located between the substrate 20 and the conductive pillar 23, and the Young's modulus of the buffer layer 27 is less than that of the substrate 20. The buffer layer 27 can effectively release the stress exerted on the substrate 20 when the conductive pillar 23 expands due to heat, thereby reducing the influence of the stress in the substrate 20 on the performance of the devices distributed around the through hole 21.

[0075] In one embodiment, the material of the buffer layer 27 is the same as that of the core layer 26. However, it is not limited thereto, and any material satisfying the above Young's modulus can be used as the buffer layer 27 in the embodiments of the present invention.

[0076] Figure 2aThe number of buffer layers 27 in the semiconductor structure shown is 2, namely buffer layer 27a and buffer layer 27b. However, it is not limited thereto. In other embodiments, the number of the buffer layers 27 can also be other values. It can be understood that the more layers the buffer layer 27 has, the greater the stress release effect it can achieve; however, too many layers will increase the complexity of the process, so the number of layers of the buffer layer 27 should not be too many. In some specific embodiments, the number of the buffer layers 27 is between 1 and 3, and the thickness of each layer of the buffer layer 27 is in to between.

[0077] In some embodiments, the number of the buffer layers 27 is multiple layers; the semiconductor structure further includes: a first insulating layer 28, the first insulating layer 28 is located between any two adjacent layers of the multiple buffer layers 27, and the first insulating layer 28 is used to isolate the adjacent buffer layers 27 to improve the stress release effect of the buffer layer 27. The material of the first insulating layer 28 includes but is not limited to oxides.

[0078] In one embodiment, the semiconductor structure further includes: a second insulating layer 22 disposed in the through hole 21; wherein, the second insulating layer 22 is located between the substrate 20 and the buffer layer 27. The second insulating layer 22 is used to electrically isolate the substrate 20 from any conductive material in the through hole 21 and prevent the conductive material from migrating into the substrate 20. The second insulating layer 22 includes but is not limited to oxides. The thickness of the second insulating layer 22 is to

[0079] In one embodiment, the semiconductor structure further includes: a barrier layer 29 disposed in the through hole 21, the barrier layer 29 is located between the buffer layer 27 and the conductive pillar 23, and the barrier layer 29 covers the outer wall of the conductive pillar 23. The barrier layer 29 is used to block the conductive material in the conductive pillar 23 from migrating into the substrate 20. The material of the barrier layer 29 includes at least one of tantalum or titanium.

[0080] It can be understood that a preset area around the through hole 21 is usually set as a Keep Out Zone (KOZ) 31, and no semiconductor devices such as transistors are formed in the zone 31. The purpose of setting the zone 31 in the substrate 20 is to prevent the semiconductor devices distributed near the through hole 21 from being adversely affected by the stress in the substrate 20. By disposing the core layer 26 and the buffer layer 27 in the through hole 21 in the embodiments of the present invention, the stress in the substrate 20 can be effectively relieved, so the area of the zone 31 can be effectively reduced and the utilization rate of the substrate 20 can be improved.

[0081] Figure 2a The through hole 21 shown is etched from the active surface S of the substrate 20 to the back surface. In other embodiments of the present invention, the through hole 21 may also be etched from the back surface of the substrate 20 to the active surface S, as Figure 2b shown. In this embodiment, before forming the through hole 21, a redistribution layer 24 is first formed on the active surface S of the substrate 20; then, the through hole 21 is etched from the back surface of the substrate 20 to the active surface S; then, a second insulating layer 22, a buffer layer 27b, a first insulating layer 28, a buffer layer 27a, a barrier layer 29, a conductive pillar 23, and a core layer 26 are sequentially formed in the through hole 21. The above layers have been introduced in the previous embodiments and will not be elaborated here.

[0082] An embodiment of the present invention also provides a manufacturing method of a semiconductor structure, as Figure 3 shown, the method includes the following steps:

[0083] Step 301, provide a substrate, and perform an etching process on the substrate to form a through hole in the substrate;

[0084] Step 302, form a conductive pillar with a groove in the through hole, and the groove extends from the upper surface of the conductive pillar to the inside of the conductive pillar;

[0085] Step 303, form a core layer in the groove; wherein, the Young's modulus of the core layer is less than that of the conductive pillar.

[0086] Next, in combination with Figures 4a - 4e , Figures 5a - 5c the manufacturing method of the semiconductor structure of the embodiment of the present invention will be further described in detail.

[0087] First, perform step 301, provide a substrate 20, and perform an etching process on the substrate 20 to form a through hole 21 in the substrate 20, as Figure 4a shown.

[0088] The substrate may be a silicon substrate. In some other embodiments, the substrate may include other semiconductor elements, such as: germanium, or include semiconductor compounds, such as: silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, or other semiconductor alloys, such as: silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, indium gallium phosphide, and / or indium gallium phosphide arsenide, or a combination thereof. In a preferred embodiment, the thickness of the substrate is 40-70 μm.

[0089] The substrate 20 includes an active surface S and a back surface opposite to the active surface S, and devices are disposed in the substrate 20 near the active surface S. In one embodiment, the device may be a memory, such as a dynamic random access memory (DRAM). However, it is not limited thereto. In other embodiments, the device may be a logic chip or the like.

[0090] Please refer to Figure 4a , in one embodiment, performing an etching process on the substrate 20 to form the through hole 21 includes:

[0091] Forming a patterned mask (not shown in the figure) on the active surface S of the substrate 20, and performing an etching process on the substrate 20 using the patterned mask as an etching mask, etching from the active surface S into the interior of the substrate 20 to form the through hole 21 that does not penetrate the substrate 20.

[0092] In some embodiments, the shape of the opening of the through hole 21 may be circular. However, it is not limited thereto. In other embodiments, the shape of the opening of the through hole 21 may be oval, polygonal, or the like.

[0093] Next, step 302 is performed to form a conductive column 23 having a groove T in the through hole 21, and the groove T extends from the upper surface of the conductive column 23 to the interior of the conductive column 23, as Figures 4b - 4c shown.

[0094] In one embodiment, before forming the conductive column 23 in the through hole 21, the method further includes: forming at least one buffer layer 27 between the substrate 20 and the conductive column 23, as Figure 4b shown. The Young's modulus of the buffer layer 27 is less than that of the substrate 20, and it can effectively release the stress generated by the thermal expansion of the conductive column 23 on the substrate 20, thereby reducing the influence of the stress in the substrate 20 on the performance of the devices distributed around the through hole 21.

[0095] The number of layers of the buffer layer is one layer or multiple layers; it can be understood that the more layers of the buffer layer, the greater the stress release effect it can achieve; however, too many layers will increase the complexity of the process, so the number of layers of the buffer layer should not be too many. In some specific embodiments, the number of the buffer layers is between 1 and 3, and the thickness of each layer of the buffer layer is between and between.

[0096] In one embodiment, the material of the buffer layer includes polysilicon. However, it is not limited thereto. Any material that satisfies the above Young's modulus can be used as the buffer layer in the embodiments of the present invention.

[0097] In one embodiment, the number of the buffer layers 27 is multiple layers, such as buffer layer 27a and buffer layer 27b; the method further includes: forming a first insulating layer 28 between any two adjacent layers of the multiple buffer layers 27, as Figure 4b shown. The first insulating layer 28 is used to isolate the adjacent buffer layers 27 to improve the stress release effect of the buffer layers 27. The material of the first insulating layer 28 includes but is not limited to oxides.

[0098] In one embodiment, before forming at least one buffer layer 27 between the substrate 20 and the conductive pillar 23, it further includes: forming a second insulating layer 22 between the substrate 20 and the buffer layer 27, as Figure 4b shown. The second insulating layer 22 is used to electrically isolate the substrate 20 from any conductive material in the via 21 and prevent the conductive material from migrating into the substrate 20. The material of the second insulating layer 22 includes but is not limited to oxides. The thickness of the second insulating layer 22 is to

[0099] In one embodiment, after forming at least one buffer layer 27 between the substrate 20 and the conductive pillar 23, it further includes: forming a barrier layer 29 between the buffer layer 27 and the conductive pillar 23, as Figure 4b shown. The barrier layer 29 is used to prevent the conductive material in the conductive pillar 23 from migrating into the substrate 20. The material of the barrier layer 29 includes at least one of tantalum or titanium.

[0100] Continuing to refer to Figure 4b , in a specific embodiment, the second insulating layer 22, the buffer layer 27b, the first insulating layer 28, the buffer layer 27a, and the barrier layer 29 are sequentially formed on the sidewall and bottom surface of the via 21. The above-mentioned layers are formed using one or more thin film deposition processes; specifically, the formation processes of each layer structure include but are not limited to chemical vapor deposition (CVD) process, plasma enhanced chemical vapor deposition (PECVD) process, atomic layer deposition (ALD) process, or a combination thereof.

[0101] In one embodiment, forming the conductive pillar 23 having the groove T in the via 21 includes: depositing a conductive material in the via 21 and controlling the deposition time of the conductive material so that the conductive material does not completely fill the via 21, thereby obtaining the conductive pillar 23 having the groove T.

[0102] In one embodiment, forming the conductive column 23 with the groove T in the through hole 21 includes: depositing a conductive material in the through hole 21, the conductive material completely filling the through hole 21; removing part of the conductive material by etching to obtain the conductive column 23 with the groove T.

[0103] In a specific embodiment, the conductive material is formed by physical vapor deposition (PVD) process or chemical vapor deposition (CVD) process. However, it is not limited thereto. In other embodiments, the conductive material can also be formed by electroplating.

[0104] The conductive column 23 extends in a direction perpendicular to the substrate 20, and the material of the conductive column 23 includes at least one of copper or tungsten. In some embodiments, the width of the conductive column 23 is 2 - 10 μm, and the depth is 5 - 100 μm.

[0105] In one embodiment, the groove T extends from the upper surface of the conductive column 23 into the conductive column 23 but does not penetrate the bottom of the conductive column 23. However, it is not limited thereto. In other embodiments, the groove T extends from the upper surface of the conductive column 23 to the bottom surface of the conductive column 23, that is, penetrates the conductive column 23.

[0106] Next, perform step 303 to form the core layer 26 in the groove T, please refer to Figure 4d ; wherein, the Young's modulus of the core layer 26 is less than that of the conductive column 23.

[0107] The core layer 26 completely fills the groove T. The forming process of the core layer 26 includes but is not limited to chemical vapor deposition (CVD) process, plasma enhanced chemical vapor deposition (PECVD) process, atomic layer deposition (ALD) process or a combination thereof.

[0108] In some embodiments, the core layer 26 is a circular column, and the diameter of the circular column is between and . However, it is not limited thereto. In other embodiments, the core layer 26 can also be a rectangular column, and the side length of the rectangular column is between and . The material of the core layer 26 includes polysilicon. However, it is not limited thereto. Any material with a Young's modulus meeting the above requirements can be used as the core layer 26 in the embodiments of the present invention.

[0109] In one embodiment, the extending direction of the core layer 26 is the same as that of the conductive column 23, and the core layer 26 is located on the central axis of the conductive column 23. Thus, the core layer 26 can more evenly relieve the stress generated when the conductive column 23 expands due to heat.

[0110] Please refer to Figure 4e , in one embodiment, after forming the core layer 26 in the conductive pillar 23, the method further includes: forming a redistribution layer 24 on the active surface S, a metal pad 25 is disposed in the redistribution layer 24, the metal pad 25 is deposited on the active surface S and is electrically connected to the conductive pillar 23.

[0111] In one embodiment, after forming the core layer 26 in the conductive pillar 23, the method further includes: starting from the back surface opposite to the active surface S, performing a thinning process on the substrate 20 until the conductive pillar 23 is exposed, and the finally formed semiconductor structure is as Figure 2a shown.

[0112] Figures 4a to 4e The through hole 21 shown is etched from the active surface S of the substrate 20 to the back surface. In another embodiment of the present invention, the through hole 21 can also be etched from the back surface of the substrate 20 to the active surface S, as Figures 5a - 5c shown.

[0113] Refer to Figure 5a , performing an etching process on the substrate 20 to form the through hole 21 includes: etching from the back surface of the substrate 20 to the active surface S to form the through hole 21 penetrating the substrate 20.

[0114] Specifically, before forming the through hole 21 in the substrate 20, the method further includes: forming a redistribution layer 24 on the active surface S, a metal pad 25 is disposed in the redistribution layer 24, the metal pad 25 is deposited on the active surface S, and the through hole 21 exposes the metal pad 25.

[0115] Next, as Figure 5b shown, the second insulating layer 22, the buffer layer 27b, the first insulating layer 28, the buffer layer 27a, and the barrier layer 29 are sequentially formed on the sidewall of the through hole 21 in the same manner as the foregoing embodiment, which will not be elaborated herein.

[0116] Next, as Figure 5c shown, a conductive pillar 23 having a groove T is formed in the through hole 21, and the groove T extends from the upper surface of the conductive pillar 23 to the inside of the conductive pillar 23.

[0117] Finally, a core layer 26 is formed in the groove T, and the finally formed semiconductor structure is as Figure 2b shown.

[0118] The above are only the preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate and a through-hole located within the substrate; A conductive pillar, located within the through-hole, the conductive pillar having a groove extending from the upper surface of the conductive pillar towards the interior; A core layer, located within the groove; wherein, the Young's modulus of the core layer is less than the Young's modulus of the conductive pillar; Wherein, the semiconductor structure further includes at least one buffer layer located between the substrate and the conductive pillar, the Young's modulus of the buffer layer being less than the Young's modulus of the substrate; Wherein, the material of the buffer layer is the same as the material of the core layer.

2. The semiconductor structure according to claim 1, wherein The material of the core layer includes polysilicon.

3. The semiconductor structure according to claim 1, wherein The conductive pillar extends in a direction perpendicular to the substrate, the core layer extends in the same direction as the conductive pillar, and the core layer is located on the central axis of the conductive pillar.

4. The semiconductor structure according to claim 1, wherein The core layer is a circular pillar, the diameter of the circular pillar being between 100 Å and 1000 Å; or, the core layer is a rectangular pillar, the side length of the rectangular pillar being between 100 Å and 1000 Å.

5. The semiconductor structure according to claim 1, wherein The number of the buffer layers is between 1 and 3, and the thickness of each layer of the buffer layer is between 100 Å and 500 Å.

6. The semiconductor structure according to claim 1, wherein The number of the buffer layers is multiple; the semiconductor structure further includes: a first insulating layer, the first insulating layer being located between any two adjacent layers of the multiple buffer layers.

7. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes: a second insulating layer disposed within the through-hole; wherein, the second insulating layer is located between the substrate and the buffer layer.

8. The semiconductor structure according to claim 7, wherein, The thickness of the second insulating layer is between 2000 Å and 5000 Å.

9. The semiconductor structure according to claim 1, wherein The semiconductor structure further includes: a barrier layer disposed within the through-hole, the barrier layer being located between the buffer layer and the conductive pillar.

10. The semiconductor structure according to claim 9, wherein The material of the barrier layer includes at least one of tantalum or titanium.

11. A manufacturing method of a semiconductor structure, characterized in that, The method includes: Providing a substrate, performing an etching process on the substrate to form a through-hole within the substrate; Forming a conductive pillar with a groove within the through-hole, the groove extending from the upper surface of the conductive pillar to the interior of the conductive pillar; Forming a core layer within the groove; wherein, the Young's modulus of the core layer is less than the Young's modulus of the conductive pillar; Wherein, before forming the conductive pillar within the through-hole, further included is: Forming at least one buffer layer between the substrate and the conductive pillar, the Young's modulus of the buffer layer being less than the Young's modulus of the substrate; Wherein, the material of the buffer layer is the same as the material of the core layer.

12. The manufacturing method according to claim 11, characterized in that, The substrate includes an active surface and a back surface opposite to the active surface; Performing an etching process on the substrate to form a through-hole within the substrate, including: Etching from the active surface towards the interior of the substrate to form the through-hole that does not penetrate the substrate; After forming the core layer within the conductive pillar, the method further includes: Starting from the back surface, performing a thinning process on the substrate until the conductive pillar is exposed.

13. The manufacturing method according to claim 11, characterized in that, The substrate includes an active surface and a back surface opposite to the active surface, and a metal pad is disposed on the active surface; Performing an etching process on the substrate to form a through-hole within the substrate, including: Etching the substrate from the back surface to form the through-hole that penetrates the substrate, the through-hole exposing the metal pad.

14. The manufacturing method according to claim 11, characterized in that, The number of the buffer layers is multiple; the method further includes: forming a first insulating layer between any two adjacent ones of the multiple buffer layers; forming a second insulating layer between the substrate and the buffer layer.

15. The manufacturing method according to claim 11, characterized in that, After forming at least one buffer layer between the substrate and the conductive pillar, it further includes: forming a barrier layer between the buffer layer and the conductive pillar.

16. The manufacturing method according to claim 11, characterized in that, Forming a conductive pillar with a groove in the through hole includes: depositing a conductive material in the through hole, controlling the deposition time of the conductive material so that the conductive material does not completely fill the through hole, to obtain the conductive pillar with a groove.

17. The manufacturing method according to claim 11, characterized in that, Forming a conductive pillar with a groove in the through hole includes: depositing a conductive material in the through hole, and the conductive material completely fills the through hole; removing part of the conductive material by etching to obtain the conductive pillar with a groove.

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