Semiconductor packaging structure

Abstract

This invention relates to a semiconductor packaging structure. The semiconductor packaging structure includes: a first substrate interposer layer located between an upper substrate and a lower substrate; and an inductor circuit, at least a portion of which is located within the first substrate interposer layer. The inductor circuit has multiple contacts, at least one of which is a pseudo-electrical connection to the upper substrate or the lower substrate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor packaging structure. Background Technology

[0002] In semiconductor packaging structures, in order to enable the power module to provide a stable voltage, the inductor components in the current power module packaging structure (such as SiP structure) are relatively large and tall, which often makes it impossible for the overall packaging structure design to meet the height and size requirements of customers. Summary of the Invention

[0003] To address the problem that semiconductor packaging structures in related technologies cannot meet design requirements due to the large size of power supply components, this invention proposes a semiconductor packaging structure.

[0004] According to one aspect of the present invention, a semiconductor package structure is provided, comprising: a first substrate interlayer located between an upper substrate and a lower substrate; and an inductor circuit, at least a portion of which is located within the first substrate interlayer. The inductor circuit has a plurality of contacts, at least one of which is a pseudo-electrical connection to the upper substrate or the lower substrate.

[0005] In some embodiments, a signal connection via is provided in the first substrate interposer layer, and the signal connection via and the inductor circuit are disposed in physically separated regions.

[0006] In some embodiments, the first substrate interlayer has a length direction, and signal connection vias and inductor circuits are disposed in two different regions arranged side by side in the length direction.

[0007] In some embodiments, the inductor circuit is arranged within the first substrate interlayer around an axis parallel to the length direction.

[0008] In some embodiments, a plurality of first signal connection vias are located in a first region, and a plurality of second signal connection vias are located in a second region different from the first region, wherein the first region and the second region are physically separated by an inductor circuit.

[0009] In some embodiments, the first region and the second region are arranged side by side in the width direction of the first substrate interposer, and the inductor circuit is arranged in the first substrate interposer around an axis parallel to the width direction.

[0010] In some embodiments, the semiconductor package structure further includes a second substrate interlayer located between the upper substrate and the lower substrate and physically spaced apart from the first substrate interlayer.

[0011] In some embodiments, a first portion of the inductor circuit is located within a first substrate interlayer, and a second portion of the inductor circuit is located within a second substrate interlayer. A third portion of the inductor circuit extends between the first and second substrate interlayers and connects the first and second portions of the inductor circuit.

[0012] In some embodiments, the third portion of the inductor circuit is located in the non-featured areas of the upper and lower substrates.

[0013] In some embodiments, the third portion of the inductor circuit is located in a layable region between the circuit layers of the upper and lower substrates.

[0014] According to one aspect of the present invention, a semiconductor package structure is provided, comprising: an upper substrate and a lower substrate; a first substrate interlayer located between the upper substrate and the lower substrate; and an inductor circuit located between the upper substrate and the lower substrate, wherein at least a portion of the inductor circuit is located within the first substrate interlayer, and the inductor circuit is arranged around an axis parallel to the upper substrate and the lower substrate.

[0015] In some embodiments, the inductor circuit includes a plurality of contacts, wherein at least one of the plurality of contacts is a pseudo-electrical connection that protrudes from the surface of the first substrate interlayer and is connected to the upper substrate or the lower substrate.

[0016] In some embodiments, a first via is provided in the first substrate interposer, wherein the first via is configured as part of an inductor circuit.

[0017] In some embodiments, the first substrate interposer layer also has additional vias serving as signal connection vias, and the additional vias and inductor circuits are disposed in different regions physically spaced apart from each other in the length direction of the first substrate interposer layer.

[0018] In some embodiments, the inductor circuit is arranged within the first substrate interlayer around an axis parallel to the length direction.

[0019] In some embodiments, the semiconductor package structure further includes: a second substrate interlayer located between the upper substrate and the lower substrate and physically spaced apart from the first substrate interlayer; a first via in the first substrate interlayer being configured as a first portion of an inductor circuit; and a second via in the second substrate interlayer being configured as a second portion of an inductor circuit. A third portion of the inductor circuit extends between the first substrate interlayer and the second substrate interlayer and connects the first via and the second via.

[0020] In some embodiments, the third portion of the inductor circuit is located in the non-mounted area of ​​the upper and lower substrates, or in the layable area between the circuit layers of the upper and lower substrates. Attached Figure Description

[0021] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industrial practice, the components are not drawn to scale. In fact, the dimensions of the components may be arbitrarily increased or decreased for clarity of discussion.

[0022] Figure 1A This is a perspective view of a semiconductor package structure according to an embodiment of the present invention.

[0023] Figure 1B From Figure 1A A side view of the semiconductor package structure viewed from direction D1.

[0024] Figure 1C From Figure 1A A side view of the semiconductor package structure viewed from direction D2.

[0025] Figure 2 This is a schematic diagram of the traditional intermediary layer structure.

[0026] Figure 3 This is a perspective view of a semiconductor package structure according to another embodiment of the present invention.

[0027] Figure 4 This is a side view of a semiconductor package structure viewed along the length of the first substrate interposer, according to some embodiments of the present invention.

[0028] Figure 5 This is a perspective view of a semiconductor package structure according to yet another embodiment of the present invention. Specific Implementation

[0029] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the invention. These are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various instances. Such repetition is for brevity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0030] Figure 1A This is a perspective view of a semiconductor package structure according to an embodiment of the present invention. Figure 1B From Figure 1A A side view of the semiconductor package structure viewed from direction D1. Figure 1C From Figure 1AA side view of the semiconductor package structure viewed from direction D2.

[0031] refer to Figures 1A to 1C As shown, the semiconductor package structure 100 provided by the present invention includes a first substrate interposer 110, with an upper substrate 120 (first substrate) and a lower substrate 130 (second substrate) connected above and below the first substrate interposer 110, respectively. An inductor circuit 150 is formed within the first substrate interposer 110. The present invention utilizes the interposer between the upper and lower substrates to fabricate inductor components that affect the overall package structure size and thickness. The circuit components in the interposer can achieve functions such as energy storage and voltage regulation of the inductor components, thereby forming a 3D inductor and reducing the overall package structure size and thickness.

[0032] Figure 2 This is a schematic diagram of a traditional intermediary layer structure. (Example:) Figure 2 As shown, the vias 112' in the interposer layer 110' are disposed in the central region of the interposer layer 110', and each via 112' is spaced apart from the edge of the interposer layer 110' by a certain distance.

[0033] Return to reference Figure 1A The semiconductor package structure 100 shown has a first through-hole 1121 within the first substrate interposer layer 110. In addition to the first through-hole 1121, the first substrate interposer layer 110 may also have another through-hole 1122. Figure 2 In contrast, vias 1121 and 1122 are disposed at the edge of the first substrate interposer 110. An inductor circuit 150 is formed through the first via 1121 within the first substrate interposer 110, and the first via 1121 is configured to form a part of the inductor circuit 150. The vias 1121 are interconnected by connectors parallel to the surface of the upper substrate 120 or the lower substrate 130 to collectively form the inductor circuit 150.

[0034] The first substrate interposer 110 has a length direction L. The inductor circuit 150 is configured to be arranged around an axis AX parallel to the length direction L between the upper substrate 120 and the lower substrate 130. The semiconductor package structure 100 of the present invention utilizes the interposer in a 3D stacked structure to wind the inductor circuit within the interposer, which can reduce the thickness of the package module and also save on the cost of inductor components.

[0035] refer to Figure 1B and Figure 1CAs shown, the inductor circuit 150 may have multiple contacts 180 on the surface of the first substrate interposer 110. The inductor circuit 150 is connected to the upper substrate 120 and the lower substrate 130 through the multiple contacts 180. At least one of the multiple contacts 180 is a dummy electrical connector 181 connected to the upper substrate 120 or the lower substrate 130. The dummy electrical connector 181 is not connected to any other signal. By providing the dummy electrical connector 181, it is easier to assemble the 3D inductor without affecting the 3D inductor function. Similarly, the upper substrate 120 or the lower substrate 130 also has (dummy) pads for connecting the dummy electrical connector 181. That is, the pads are not electrically connected to the circuitry within the upper substrate 120 or the lower substrate 130, but are only exposed on the surface of the upper substrate 120 or the lower substrate 130 for connecting the dummy electrical connector 181 through the electrical connector 182 (e.g., solder).

[0036] In addition, the plurality of contacts 180 may also include electrical connectors 182 for connecting signals. In some embodiments, the electrical connectors 182 may be electrical connectors disposed at the start and end ends of the inductor circuit 150. Figure 1B In the example shown, the electrical connectors 182 at both the start and end of the inductor loop 150 are connected to the upper substrate 120. However, in other embodiments, the two electrical connectors 182 may be connected to the upper substrate 120 and the lower substrate 130 respectively, or both electrical connectors 182 may be connected to the lower substrate 130. In some embodiments, a plurality of contacts 180 may protrude from the surface of the first substrate interposer layer 110. The contacts 180 may include solder and conductive pads.

[0037] refer to Figure 1A and Figure 1B As shown, in addition to the first via 1121 used to form the inductor circuit 150, the first substrate interposer layer 110 may also have another via 1122 for signal connection. Along the length L of the first substrate interposer layer 110, the other via 1122 and the inductor circuit 150 are disposed in two different regions arranged side-by-side and physically separated; that is, the other via 1122 for signal connection is located outside the region where the inductor circuit 150 is located.

[0038] Figure 3 This is a perspective view of a semiconductor package structure 300 according to another embodiment of the present invention. Figure 3 In the middle, to and Figures 1A to 1C Similar components in the text use the same reference numerals, and their detailed descriptions are omitted.

[0039] exist Figure 3In the semiconductor package structure 300, an inductor circuit 150 is also formed within the first substrate interposer layer 110. In this embodiment, two rows of vias 112 are provided within the first substrate interposer layer 110, with each row of vias 112 arranged along the length direction L of the first substrate interposer layer 110. The vias 112 are located at the edge of the first substrate interposer layer 110. The inductor circuit 150 is located in the central region of the first substrate interposer layer 110 and between the two rows of vias 112.

[0040] The inductor circuit 150 is arranged around an axis AX that is parallel to the upper substrate 120 and the lower substrate 130 and perpendicular to the length direction L. In other words, the inductor circuit 150 can be arranged around an axis AX that is parallel to the width direction of the first substrate interposer 110.

[0041] Figure 4 This is a side view of a semiconductor package structure viewed along the length of a first substrate interposer, according to some embodiments of the present invention. In some embodiments, such as Figure 4 As shown, a second substrate interposer 115, opposite to the first substrate interposer 110, may also be provided between the upper substrate 120 and the lower substrate 130. The second substrate interposer 115 may be similar to the first substrate interposer 110. An inductor circuit 150 may not be formed in the second substrate interposer 115, such as... Figure 4 As shown. In other embodiments, the above reference may also be formed in the second substrate interposer layer 115. Figures 1A to 1C and Figure 3 The described inductor circuit is 150.

[0042] Figure 5 This is a perspective view of a semiconductor package structure 500 according to yet another embodiment of the present invention. Figure 5 In the middle, to and Figures 1A to 1C and Figure 3 Similar components in the text use the same reference numerals, and their detailed descriptions are omitted.

[0043] exist Figure 5 In the semiconductor package structure 500, a second substrate interposer 115 is disposed between the upper substrate 120 and the lower substrate 130. The second substrate interposer 115 is opposite to and physically spaced from the first substrate interposer 110. The second substrate interposer 115 has a second through-hole 1221. Furthermore, with... Figure 1A Similarly, the first substrate interposer 110 may have additional vias 1122 for signal connection, and the second substrate interposer 115 may have additional vias 1222 for signal connection.

[0044] In this embodiment, the inductor circuit 150 has a first portion 151 formed using a first via 1121 in the first substrate interposer layer 110. The inductor circuit 150 also has a second portion 152 formed using a second via 1221 in the second substrate interposer layer 115. A third portion 153 of the inductor circuit 150 extends parallel between the first substrate interposer layer 110 and the second substrate interposer layer 115, and the third portion 153 connects the first portion 151 and the second portion 152 of the inductor circuit 150. Thus, an inductor circuit 150 with a 3D inductor structure is formed using the first via 1121 in the first substrate interposer layer 110 and the second via 1222 in the second substrate interposer layer 115.

[0045] The third portion 153 of the inductor circuit 150 may be located in a non-placement area of ​​the upper substrate 120 and the lower substrate 130. Alternatively, the third portion 153 of the inductor circuit 150 may be located in a placeable area between the circuit layers of the upper substrate 120 and the lower substrate 130.

[0046] Figure 5 The semiconductor packaging structure 500 in the stacked structure utilizes the non-placement or layoutable areas of the two substrate interlayers 110 and 115 and the upper and lower substrates 120 and 130 to wind the inductor circuit of the 3D inductor, which reduces the thickness of the packaging module and also saves the cost of inductor components.

[0047] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that they can be modified, substituted, and altered in various ways within the invention without departing from its spirit and scope.

Claims

1. A semiconductor packaging structure, characterized in that, include: The first substrate interlayer is located between the upper substrate and the lower substrate; An inductor circuit, at least a portion of which is located within the first substrate interposer layer; The second substrate interlayer is located between the upper substrate and the lower substrate and is physically spaced apart from the first substrate interlayer. The inductor circuit has multiple contacts, and at least one of the multiple contacts is a pseudo-electrical connector connected to the upper substrate or the lower substrate. Wherein, the first via in the first substrate interposer is configured as the first part of the inductor circuit, the second via in the second substrate interposer is configured as the second part of the inductor circuit, and the third part of the inductor circuit physically separates the first substrate interposer and the second substrate interposer. The third part is located in the non-mounted area of ​​the upper substrate and the lower substrate or in the layable area between the circuit layers of the upper substrate and the lower substrate. The third part extends parallel across the gap between the first substrate interposer and the second substrate interposer. The third part directly connects the upper end of the portion of the first via facing the second part of the first part of the inductor circuit and the upper end of the portion of the second via facing the first part of the second part of the second part. The third part also directly connects the lower end of the portion of the first via facing the second part of the first part and the lower end of the portion of the second via facing the first part of the second part of the second part. The first substrate interposer and the second substrate interposer also have signal connection vias.

2. The semiconductor packaging structure according to claim 1, characterized in that, The signal connection via and the inductor circuit are located in physically separated areas.

3. The semiconductor packaging structure according to claim 2, characterized in that, The first substrate interposer has a length direction, and the signal connection via and the inductor circuit are disposed in two different regions arranged side by side in the length direction.

4. The semiconductor packaging structure according to claim 3, characterized in that, The inductor circuit is arranged within the first substrate interlayer around an axis parallel to the length direction.

5. The semiconductor packaging structure according to claim 2, characterized in that, A plurality of first signal connection vias are located in a first region, and a plurality of second signal connection vias are located in a second region different from the first region. The first region and the second region are physically separated by the inductor circuit.

6. The semiconductor packaging structure according to claim 5, characterized in that, The first region and the second region are arranged side by side in the width direction of the first substrate interposer, and the inductor circuit is arranged in the first substrate interposer around an axis parallel to the width direction.

7. A semiconductor packaging structure, characterized in that, include: Upper substrate and lower substrate; A first substrate interposer layer is located between the upper substrate and the lower substrate; An inductor circuit is located between the upper substrate and the lower substrate, at least a portion of the inductor circuit is located within the interlayer of the first substrate, and the inductor circuit is arranged around an axis parallel to the upper substrate and the lower substrate. The second substrate interlayer is located between the upper substrate and the lower substrate and is physically spaced apart from the first substrate interlayer. Wherein, the first via in the first substrate interposer is configured as the first part of the inductor circuit, the second via in the second substrate interposer is configured as the second part of the inductor circuit, and the third part of the inductor circuit physically separates the first substrate interposer and the second substrate interposer. The third part is located in the non-mounted area of ​​the upper substrate and the lower substrate or in the layable area between the circuit layers of the upper substrate and the lower substrate. The third part extends parallel across the gap between the first substrate interposer and the second substrate interposer. The third part directly connects the upper end of the portion of the first via facing the second part of the first part and the upper end of the portion of the second via facing the first part of the second part of the second part. The third part also directly connects the lower end of the portion of the first via facing the second part of the first part and the lower end of the portion of the second via facing the first part of the second part of the second part. The first substrate interposer and the second substrate interposer also have additional vias used as signal connection vias.

8. The semiconductor packaging structure according to claim 7, characterized in that, The inductor circuit includes a plurality of contacts, wherein at least one of the plurality of contacts is a pseudo-electrical connector that protrudes from the surface of the first substrate interlayer and is connected to the upper substrate or the lower substrate.

9. The semiconductor packaging structure according to claim 7, characterized in that, The additional vias and the inductor circuits are located in different regions physically spaced apart along the length of the first substrate interposer layer.

10. The semiconductor packaging structure according to claim 9, characterized in that, The inductor circuit is arranged within the first substrate interlayer around an axis parallel to the length direction.

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