Silicon carbide semiconductor device and power conversion device

Abstract

Provided is a silicon carbide semiconductor device capable of suppressing discharge occurring when a reverse bias is applied. A silicon carbide semiconductor device (100) has an n-type epitaxial layer (2) provided on a SiC substrate (1), a surface electrode (10) provided on the epitaxial layer (2), and a p-type electric field relaxation region (3) provided in an upper layer portion of the epitaxial layer (2) in a terminal region. A first protective film composed of an interlayer insulating film (23) covering at least a portion of the electric field relaxation region (3) and a protective oxide film (24) is provided on the epitaxial layer (2). A second protective film composed of a polyimide protective film (12) is provided so as to cover at least a portion of the surface electrode (10) outside, the first protective film, and the epitaxial layer (2) with a silicon nitride film (81) interposed therebetween. The silicon nitride film (81) extends beyond the second protective film at both an inside end portion and an outside end portion of the second protective film.

Description

Technical Field

[0001] This invention relates to silicon carbide semiconductor devices. Background Technology

[0002] Semiconductor devices are known to have an end region formed outside the element region where a semiconductor element is formed, and this end region has an electric field mitigation region such as a protective ring. For example, Patent Document 1 discloses a technique for suppressing the movement of various mobile ions present in an interlayer insulating film disposed above the end region. Furthermore, Patent Document 2 discloses a technique that improves the moisture resistance of a semiconductor device by providing a protective film made of polyimide film on top of the chip of the semiconductor device, separated by a silicon nitride (SiN) film with high moisture resistance.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2020-170788

[0004] Patent Document 2: International Publication No. 2011 / 027523

[0005] As described in Patent Document 2, a structure in which a protective film is placed on top of a semiconductor device chip through a SiN film can improve the moisture resistance of the semiconductor device. However, in silicon carbide (SiC) semiconductor devices, this may increase the risk of discharge. Silicon carbide semiconductor devices exhibit superior breakdown voltage (approximately 10 times stronger insulation breakdown electric field) compared to silicon (Si) semiconductor devices, and low resistance can be achieved through thin-film fabrication. However, the electric field in the chip's end regions becomes stronger as a result, necessitating research to ensure breakdown voltage and suppress discharge in these end regions. The risk of discharge is particularly high in the end regions, which are miniaturized by incorporating electric field mitigation areas.

[0006] Furthermore, in modules housing semiconductor devices, the top of the semiconductor chip is encapsulated by encapsulation materials such as gel or resin to ensure insulation. However, the stress generated between the encapsulation material and the chip may cause the protective film on the chip to peel off (peeling at the interface between the polyimide film and the SiN film). If the protective film peels off, the risk of surface discharge along the interface between the protective film and the SiN film increases due to the high electric field generated when reverse bias is applied to the semiconductor device. Summary of the Invention

[0007] The present invention was proposed to solve the problems mentioned above, and its purpose is to provide a silicon carbide semiconductor device capable of suppressing discharge that occurs when a reverse bias is applied.

[0008] The silicon carbide semiconductor device of the present invention comprises: a semiconductor substrate made of silicon carbide; a semiconductor layer of a first conductivity type disposed on the semiconductor substrate; a first main electrode disposed on the semiconductor layer; a second main electrode disposed on the back side of the semiconductor substrate; an electric field mitigation region of a second conductivity type disposed on an upper portion of the semiconductor layer at an outer end region of an element region through which a main current flows; a first protective film disposed on the semiconductor layer, covering at least a portion of the electric field mitigation region; a silicon nitride film covering an outer end of the first main electrode, the first protective film, and at least a portion of the semiconductor layer further outer than the first protective film; and a second protective film disposed on the silicon nitride film, the silicon nitride film extending relative to the second protective film at both an inner end and an outer end.

[0009] The effects of the invention

[0010] According to the present invention, by extending the area covered by the SiN film further than the polyimide, the surface discharge distance is lengthened, thereby suppressing the risk of discharge occurring when a reverse bias is applied. Therefore, a highly reliable end structure with suppressed discharge is obtained. Attached Figure Description

[0011] Figure 1 This is a top view of the silicon carbide semiconductor device according to Embodiment 1.

[0012] Figure 2 This is a cross-sectional view of the silicon carbide semiconductor device according to Embodiment 1.

[0013] Figure 3 This is a diagram illustrating a modified example of the silicon carbide semiconductor device according to Embodiment 1.

[0014] Figure 4 This is a diagram illustrating a modified example of the silicon carbide semiconductor device according to Embodiment 1.

[0015] Figure 5 This is a cross-sectional view of the silicon carbide semiconductor device according to Embodiment 2.

[0016] Figure 6 This is a top view of the silicon carbide semiconductor device according to Embodiment 3.

[0017] Figure 7 This is a cross-sectional view of the silicon carbide semiconductor device according to Embodiment 3.

[0018] Figure 8 This is a block diagram showing the structure of a power conversion system that uses the power conversion device described in Embodiment 4. Detailed Implementation

[0019] <Implementation Method 1>

[0020] Figure 1 This is a top view of the silicon carbide semiconductor device 100, i.e., MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) (SiC-MOSFET), according to Embodiment 1. Figure 2 It is along Figure 1 A cross-sectional view along line AA. (e.g.) Figure 1 As shown, a component region 50 and a terminal region 60 are defined at the chip location of the silicon carbide semiconductor device 100. Additionally, in Figure 2 The sectional view includes the boundaries of the component region 50 and the end region 60.

[0021] Component region 50 is the region where a semiconductor component structure is formed and where it operates as a semiconductor component. In this embodiment, a MOSFET structure is formed in component region 50, and component region 50 operates as a MOSFET. Terminal region 60 is provided in a manner that surrounds component region 50 and is the region that bears the voltage withstand capability of silicon carbide semiconductor device 100.

[0022] Here, the region through which the main current flows in the silicon carbide semiconductor device 100 when it is in the ON state is referred to as the "active region". Basically, the component region 50 is equivalent to the active region, but for example, when control pads for controlling the silicon carbide semiconductor device 100 are provided within the component region 50, since no main current flows in the area of ​​the control pads, the portion of the component region 50 excluding the area of ​​the control pads becomes the active region. Examples of control pads include, for instance, gate pads connected to the gate electrode of the MOSFET, and current sensing pads for measuring the main current flowing through the MOSFET.

[0023] like Figure 2 As shown, the silicon carbide semiconductor device 100 is formed using a semiconductor substrate, namely a SiC substrate 1, made of n-type (first conductivity type) SiC. An n-type epitaxial layer 2 with a lower peak concentration of impurities than the SiC substrate 1 is formed on the SiC substrate 1. The SiC substrate 1 contains n-type impurities at a relatively high concentration. + The epitaxial layer 2 is a semiconductor layer containing n-type impurities at a relatively low concentration. - The semiconductor layer is of the type. Preferably, the thickness of the SiC substrate 1 is greater than or equal to 50 μm and less than or equal to 400 μm, and the thickness of the epitaxial layer 2 is greater than or equal to 3 μm and less than or equal to 100 μm.

[0024] In the upper part of the epitaxial layer 2 in the terminal region 60, a p-type (second conductivity type) electric field mitigation region 3 is selectively formed in such a way as to surround the active region. The electric field mitigation region 3 is a region containing p-type impurities with a thickness greater than or equal to 0.2 μm and less than or equal to 2.0 μm.

[0025] In this embodiment, the electric field mitigation region 3 includes an impurity region 31 and an impurity region 32 formed on the outer side compared to the impurity region 31. The cross-sectional area of ​​the impurity region 31 is larger than that of the impurity region 32, and multiple impurity regions 32 are provided at intervals between each other. The number and spacing of the impurity regions 32 are designed based on the specifications of the silicon carbide semiconductor device 100.

[0026] In the upper layer of the epitaxial layer 2 of the element region 50, a p-type well region 4 is selectively formed in the active region. The well region 4 is a region containing p-type impurities with a thickness greater than or equal to 0.2 μm and less than or equal to 2.0 μm. Furthermore, in... Figure 2 Only one well region 4 is shown, but multiple well regions 4 are arranged at intervals between each other in the active region. That is, Figure 2 The trap region 4 shown is the outermost trap region 4 located in the active region among multiple trap regions 4.

[0027] In the upper part of the trap region 4, a p-type trap contact region 6 is selectively formed, with a higher peak concentration of impurities than that in the trap region 4. The trap contact region 6 contains p-type impurities at a relatively high concentration. + In addition, an n-type source region 5 is selectively formed in the upper part of the well region 4, sandwiching the well contact region 6. The source region 5 contains n-type impurities at a relatively high concentration. + The source region 5 and the well contact region 6 are formed to be thinner than the well region 4.

[0028] The well contact region 6 is provided to stabilize the switching characteristics of the MOSFET by making the potentials of the source region 5 and the well region 4 the same. Additionally, in this embodiment, the well contact region 6 is also provided within the impurity region 31 of the electric field mitigation region 3. However, the well contact region 6 is not an essential structural element. That is, the well contact region 6 can be omitted.

[0029] A protective oxide film 24 is provided on the epitaxial layer 2 of the end region 60 in such a way that it covers at least a portion of the electric field mitigation region 3. The protective oxide film 24 is formed, for example, from silicon oxide using TEOS, and has a thickness greater than or equal to 0.3 μm and less than or equal to 3.0 μm.

[0030] A gate insulating film 21 is formed on the epitaxial layer 2 of the element region 50, covering the source region 5 within the well region 4 from the region between adjacent well regions 4. A gate electrode 22 is formed on the gate insulating film 21. The thickness of the gate insulating film 21 is set to be greater than or equal to 2 nm and less than or equal to 200 nm. The gate insulating film 21 and the gate electrode 22 can also be as follows: Figure 2 As shown, it is arranged such that the source region 5 in the trap region 4 at the outermost periphery of the element region 50 covers the end of the impurity region 31 in the end region 60.

[0031] The gate insulating film 21, the gate electrode 22, and the protective oxide film 24 are covered by an interlayer insulating film 23. The thickness of the interlayer insulating film 23 is greater than or equal to 0.3 μm and less than or equal to 3.0 μm. Contact holes reaching the source region 5 and the well contact region 6 are formed in the interlayer insulating film 23.

[0032] A first main electrode, namely a surface electrode 10, which functions as the source electrode of a MOSFET, is formed on the interlayer insulating film 23. The surface electrode 10 is connected to the source region 5 and the well contact region 6 through contact holes formed in the interlayer insulating film 23. The surface electrode 10 is a metal, such as Al or AlSi. Alternatively, the surface electrode 10 can also be connected to the impurity region 31 through contact holes (not shown) in the end region 60 through which the interlayer insulating film 23 and the protective oxide film 24 pass.

[0033] The protective oxide film 24 and the interlayer insulating film 23 extend further outward than the electric field mitigation region 3, but do not reach the edge of the silicon carbide semiconductor device 100 chip. At the edge of the chip, the epitaxial layer 2 is exposed from the protective oxide film 24 and the interlayer insulating film 23. Hereinafter, the laminated films composed of the protective oxide film 24 and the interlayer insulating film 23 are sometimes collectively referred to as the "first protective film". Alternatively, the protective oxide film 24 and the interlayer insulating film 23 can be made of the same material, and the first protective film can be a single-layer structure. In this case, the protective oxide film 24 and the interlayer insulating film 23 can be made of insulating films; for example, silicon oxide can be used.

[0034] A silicon nitride film 81 is formed to cover the outer end of the surface electrode 10, the interlayer insulating film 23, and the epitaxial layer 2 at the chip end. An organic film or a polyimide protective film 12 is disposed on the silicon nitride film 81. An opening (hereinafter referred to as a "pad opening") is formed in the silicon nitride film 81 and the polyimide protective film 12, exposing the central portion of the surface electrode 10, which serves as an electrode pad for wire bonding, etc. In addition, the silicon nitride film 81 covers at least a portion of the epitaxial layer 2 exposed from the protective oxide film 24 and the interlayer insulating film 23 at the chip end of the silicon carbide semiconductor device 100. Hereinafter, the polyimide protective film 12 is sometimes referred to as a "second protective film".

[0035] A second main electrode, namely the back electrode 11, which functions as the drain electrode of a MOSFET, is formed on the back side of the SiC substrate 1 (the side opposite to the surface electrode 10). The surface electrode 10 and the back electrode 11 can be made of, for example, Al, Cu, etc.

[0036] When the silicon carbide semiconductor device 100 is in the ON state, a main current flows between the surface electrode 10 and the back electrode 11. That is, the silicon carbide semiconductor device 100 is a vertical type semiconductor device in which a main current flows in the thickness direction of the SiC substrate 1.

[0037] Here, the silicon nitride film 81 will be described. The silicon nitride film 81 is insulating and is formed with a width wider than the polyimide protective film 12. That is, the silicon nitride film 81 extends relative to the polyimide protective film 12 at both its inner end (on the element region 50 side) and its outer end (on the end region 60 side).

[0038] In this way, by extending the silicon nitride film 81 from both ends of the polyimide protective film 12, the surface distance of the silicon nitride film 81 is increased compared to the existing structure where the silicon nitride film 81 does not extend from the polyimide protective film 12. As a result, the surface discharge distance is increased, thus suppressing discharge when reverse bias is applied. For example, in the case of actually using a module that encapsulates the silicon carbide semiconductor device 100 with encapsulation material, if the polyimide protective film 12 peels off due to stress generated between the encapsulation material and the silicon carbide semiconductor device 100, the risk of discharge can be reduced compared to the existing structure. Furthermore, the reverse bias state of the MOSFET refers to the state in which the source electrode (surface electrode 10) is biased to a positive potential and the drain electrode (back electrode 11) is biased to a negative potential.

[0039] Furthermore, it is assumed that the electric field applied to the end region 60 of the silicon carbide semiconductor device 100 is stronger than that of the silicon semiconductor device. Therefore, if the moisture contained in the polyimide protective film 12 reaches the surface electrode 10, electrolysis of the moisture occurs. Due to the volume expansion of the reaction products formed on the surface of the surface electrode 10 and the epitaxial layer 2, peeling of the protective films (the first protective film and the second protective film) may occur. However, in the case of the silicon carbide semiconductor device 100, by providing a silicon nitride film 81 with a width wider than the polyimide protective film 12 below the polyimide protective film 12, it is possible to prevent the moisture contained in the polyimide protective film 12 from reaching the surface electrode 10, thereby preventing the peeling of the protective films.

[0040] In addition, by extending the silicon nitride film 81 relative to the polyimide protective film 12, the polyimide protective film 12, which has poor adhesion to the epitaxial layer 2, is prevented from contacting the epitaxial layer 2. Therefore, the effect of suppressing the peeling of the polyimide protective film 12 can also be obtained, which can also help extend the life of the silicon carbide semiconductor device 100.

[0041] Preferably, the extension (length of the silicon nitride film 81) relative to the polyimide protective film 12 is greater than or equal to 5 μm and less than or equal to 20 μm, but a greater extension is also permissible as long as the required area of ​​the pad openings exposing the surface electrode 10 is ensured. Additionally, in Figure 2 The diagram shows an example where the silicon nitride film 81 extending outward from the polyimide protective film 12 does not reach the chip end of the silicon carbide semiconductor device 100, but as... Figure 3 As shown, the silicon nitride film 81 can also reach the chip end of the silicon carbide semiconductor device 100. In Figure 3 In the structure, with Figure 2 Compared to the previous structure, the silicon nitride film 81 has a longer surface distance, and on this basis, the peeling of the polyimide protective film 12 is suppressed due to the stress between the encapsulation material and the silicon carbide semiconductor device 100.

[0042] In addition, such as Figure 4 As shown, the extension of the silicon nitride film 81 from the inner end of the polyimide protective film 12 can be made shorter than the extension of the silicon nitride film 81 from the outer end of the polyimide protective film 12. This ensures a larger area for the pad openings exposing the surface electrode 10, improving the ease of assembly such as wire bonding. Furthermore, the stress generated between the packaging material and the silicon carbide semiconductor device 100 is stronger closer to the chip end. Therefore, by making the distance from the chip end to the polyimide protective film 12 longer, the stress applied to the polyimide protective film 12 is reduced, and peeling of the polyimide protective film 12 from the chip end side can be suppressed.

[0043] <Implementation Method 2>

[0044] Figure 5 This is a cross-sectional view of the silicon carbide semiconductor device 101, i.e., a MOSFET (SiC-MOSFET), according to Embodiment 2. Figure 5 In the middle, to and Figure 2 Structural elements that are identical to those shown are labeled with the same reference numerals. Therefore, descriptions of structural elements that are identical to those described in Embodiment 1 are omitted here.

[0045] like Figure 5As shown, in the silicon carbide semiconductor device 101 according to Embodiment 2, the side surface of the end of the surface electrode 10 covered by the silicon nitride film 81 is inclined, so that the silicon nitride film 81 is not bent into a right angle above the end of the surface electrode 10. The stress generated between the packaging material and the silicon carbide semiconductor device 101 tends to concentrate at the end of the surface electrode 10, but this structure alleviates the stress concentration at the end of the surface electrode 10 and suppresses the formation of cracks in the silicon nitride film 81.

[0046] If cracks occur in the silicon nitride film 81, moisture contained in the polyimide protective film 12 can easily reach the surface electrode 10. As described above, due to the reaction products formed by the electrolysis of moisture, peeling of the protective films (the first and second protective films) is possible. In this embodiment, since cracks are prevented from occurring in the silicon nitride film 81, peeling of the aforementioned protective films can be prevented, which helps to improve the reliability of the silicon carbide semiconductor device 101.

[0047] <Implementation Method 3>

[0048] Figure 6 This is a top view of the silicon carbide semiconductor device 102, i.e., MOSFET (SiC-MOSFET), according to Embodiment 3. Figure 7 It is along Figure 6 A cross-sectional view along line AA. Figure 6 and Figure 7 In the middle, to and Figure 2 Structural elements that are identical to those shown are labeled with the same reference numerals. Therefore, descriptions of structural elements that are identical to those described in Embodiment 1 are omitted here.

[0049] like Figure 6 and Figure 7 As shown, in Embodiment 3, the silicon carbide semiconductor device 102 is provided with an electrode 82 (hereinafter referred to as the "frame electrode") that appears frame-shaped when viewed from above, covering the outer end of a first protective film composed of an interlayer insulating film 23 and a protective oxide film 24. A silicon nitride film 81 is configured to cover the frame electrode 82. The frame electrode 82 extends to cover the entire circumference of the outer edge of the first protective film when viewed from above. Furthermore, in... Figure 6 For ease of explanation, only the surface electrode 10, the protective oxide film 24 (first protective film), and the border electrode 82 are shown; illustrations of other structures are omitted. The material of the border electrode 82 can be the same as that of the surface electrode 10, such as Al or AlSi. In this case, the border electrode 82 can be formed using the same process as the surface electrode 10.

[0050] like Figure 7As shown, since the frame electrode 82 covers the end of the first protective film, it has a stepped shape with a step at the position corresponding to the end of the first protective film. Therefore, the cross-sectional shape of the silicon nitride film 81 covering the frame electrode 82 is bent along this stepped shape, and correspondingly, the surface distance of the silicon nitride film 81 becomes longer. Therefore, the surface discharge distance can be set to be longer without increasing the width of the end region 60, thereby improving the effect of suppressing discharge when reverse bias is applied.

[0051] Furthermore, in embodiments 1 to 3, a MOSFET is shown as a silicon carbide semiconductor device, but the silicon carbide semiconductor device is not limited to a MOSFET; for example, it could also be an IGBT (Insulated-Gate Bipolar Transistor), an SBD (Schottky Barrier Diode), a JBS (Junction Barrier Diode), a pn junction diode, a JFET (junction field-effect transistor), etc. Also, in the above description, the first conductivity type is defined as n-type and the second conductivity type as p-type, but it is also possible to reverse this, defining the first conductivity type as p-type and the second conductivity type as n-type.

[0052] <Implementation Method 4>

[0053] This embodiment applies the semiconductor device described in Embodiments 1 to 3 to a power conversion device. The application of the semiconductor device described in Embodiments 1 to 3 is not limited to a specific power conversion device, but in Embodiment 4, a three-phase inverter is shown as an example of a power conversion device.

[0054] Figure 8 This is a block diagram showing the structure of a power conversion system that uses the power conversion device described in this embodiment.

[0055] Figure 8 The power conversion system shown consists of a power source 150, a power conversion device 200, and a load 300. The power source 150 is a DC power source that supplies DC power to the power conversion device 200. The power source 150 can be composed of various power sources, such as a DC system, solar cells, or batteries, or it can be composed of a rectifier circuit connected to an AC system or an AC / DC converter. Alternatively, the power source 150 can also be composed of a DC / DC converter that converts DC power output from a DC system into a specific type of power.

[0056] The power conversion device 200 is a three-phase inverter connected between the power source 150 and the load 300, which converts the DC power supplied from the power source 150 into AC power and supplies the AC power to the load 300. For example... Figure 8 As shown, the power conversion device 200 includes: a main conversion circuit 201 that converts DC power into AC power for output; and a control circuit 203 that outputs a control signal to the main conversion circuit 201 to control the main conversion circuit 201.

[0057] Load 300 is a three-phase motor driven by AC power supplied from power conversion device 200. Furthermore, load 300 is not limited to a specific application; it is a motor mounted on various electrical equipment, such as motors used in hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0058] The details of the power conversion device 200 will be described below. The main conversion circuit 201 includes switching elements and freewheeling diodes (not shown). By switching the switching elements on and off, it converts the DC power supplied from the power source 150 into AC power and supplies it to the load 300. The specific circuit structure of the main conversion circuit 201 varies, but the main conversion circuit 201 in this embodiment is a two-level three-phase full-bridge circuit, which can be composed of six switching elements and six freewheeling diodes connected in anti-parallel to the switching elements. At least one of the switching elements and freewheeling diodes in the main conversion circuit 201 is composed of a semiconductor module 202 equivalent to any of the embodiments 1 to 3 described above. The six switching elements are connected in series in pairs to form upper and lower bridge arms, and each upper and lower bridge arm constitutes a phase (U phase, V phase, W phase) of the full-bridge circuit. Furthermore, the output terminals of each upper and lower bridge arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0059] Additionally, the main converter circuit 201 includes a drive circuit (not shown) for driving each switching element. However, this drive circuit can be integrated into the semiconductor module 202 or it can be a separate drive circuit from the semiconductor module 202. The drive circuit generates drive signals to drive the switching elements of the main converter circuit 201 and supplies them to the control electrodes of the switching elements. Specifically, according to the control signal from the control circuit 203 (described later), drive signals that turn the switching element on and drive signals that turn the switching element off are output to the control electrodes of each switching element. When the switching element is maintained in the on state, the drive signal is a voltage signal greater than or equal to the threshold voltage of the switching element (on signal); when the switching element is maintained in the off state, the drive signal is a voltage signal less than or equal to the threshold voltage of the switching element (off signal).

[0060] The control circuit 203 controls the switching elements of the main converter circuit 201 to supply the desired power to the load 300. Specifically, it calculates the time (on-time) during which each switching element of the main converter circuit 201 should be in the on state based on the power to be supplied to the load 300. For example, the main converter circuit 201 can be controlled by PWM control, which modulates the on-time of the switching elements in accordance with the voltage to be output. Furthermore, a control command (control signal) is output to the drive circuit of the main converter circuit 201 so that an on signal is output to the switching element that should be in the on state at each time point, and an off signal is output to the switching element that should be in the off state. The drive circuit outputs the on signal or off signal as a drive signal to the control electrode of each switching element according to the control signal.

[0061] In the power conversion device according to this embodiment, since the semiconductor module according to any of the embodiments 1 to 3 is used as the switching element and freewheeling diode of the main conversion circuit 201, the discharge when reverse bias is applied can be suppressed, thereby improving reliability.

[0062] In this embodiment, an example of applying any of Embodiments 1 to 3 to a 2-level three-phase inverter has been described, but it is not limited to this and can be applied to various power conversion devices. In this embodiment, a 2-level power conversion device is used, but it can also be a 3-level or multi-level power conversion device. When supplying power to a single-phase load, Embodiments 1 to 3 can also be applied to a single-phase inverter. In addition, when supplying power to DC loads, etc., any of Embodiments 1 to 3 can also be applied to DC / DC converters and AC / DC converters.

[0063] Furthermore, the power conversion device that applies any of the embodiments 1 to 3 is not limited to the case where the load is an electric motor. For example, it can also be used as a power supply device for electrical discharge machining, laser processing machine, induction heating cooker, non-contact power supply system, and can also be used as a power regulator for solar power generation system, energy storage system, etc.

[0064] Furthermore, the various implementation methods can be freely combined, and appropriate modifications or omissions can be made to each implementation method.

[0065] Explanation of the label

[0066] 1 SiC substrate, 2 epitaxial layer, 3 electric field mitigation region, 4 well region, 5 source region, 6 well contact region, 10 surface electrode, 11 back electrode, 12 polyimide protective film, 21 gate insulating film, 22 gate electrode, 23 interlayer insulating film, 24 protective oxide film, 31, 32 impurity regions, 50 device region, 60 end region, 81 silicon nitride film, 82 frame electrode, 100-102 silicon carbide semiconductor device, 150 power supply, 200 power conversion device, 201 main conversion circuit, 202 semiconductor module, 203 control circuit, 300 load.

Claims

1. A silicon carbide semiconductor device, comprising: Semiconductor substrates made of silicon carbide; A first conductivity type semiconductor layer is disposed on the semiconductor substrate; The first main electrode is disposed on the semiconductor layer; The second main electrode is disposed on the back side of the semiconductor substrate; The electric field mitigation region of the second conductivity type is provided in the upper part of the semiconductor layer at the end region outside the element region through which the main current flows. A first protective film is disposed on the semiconductor layer, covering at least a portion of the electric field mitigation region; A silicon nitride film covering at least a portion of the outer end of the first main electrode, the first protective film, and the semiconductor layer further outer than the first protective film; and A second protective film is disposed on the silicon nitride film. The silicon nitride film extends relative to the second protective film at both the inner and outer ends of the second protective film.

2. The silicon carbide semiconductor device according to claim 1, wherein, The length of the silicon nitride film extending from the inner end of the second protective film is shorter than the length of the silicon nitride film extending from the outer end of the second protective film.

3. The silicon carbide semiconductor device according to claim 1 or 2, wherein, The silicon nitride film extends to the chip end of the silicon carbide semiconductor device.

4. The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein, The side of the end of the first main electrode covered by the silicon nitride film is inclined.

5. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein, It also has a stepped edge electrode that covers the outer end of the first protective film and has a step corresponding to the outer end of the first protective film. The silicon nitride film covers the border electrode.

6. A power conversion device, comprising: A main converter circuit having a silicon carbide semiconductor device as described in any one of claims 1 to 5, the main converter circuit converting the input power to an output; and The control circuit outputs control signals to the main conversion circuit to control the main conversion circuit.

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