Wide bandgap semiconductor bipolar charge-trap nonvolatile memory with single insulating layer and method of manufacturing the same

Abstract

The present application provides a wide bandgap semiconductor bipolar charge trapping (BCT) non-volatile memory structure with only one single insulating layer and a method of fabricating the same. The present application also provides a monolithic integrated enhancement-mode (E-mode) n-channel and p-channel field effect transistors (n-FET and p-EFT) for gallium nitride (GaN) based complementary logic (CL) gates based on the proposed memory structure, a method of fabricating the field effect transistors in a single process run, and various logic circuits incorporating one or more of the GaN based CL gates.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 232,661, filed August 13, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This invention relates to a charge-trapping semiconductor device, and more particularly to a wide-bandgap (WBG) semiconductor BCT non-volatile memory device or structure with only a single insulating layer, and a method for manufacturing the same. The invention also relates to a method for constructing monolithic enhancement-mode n-FETs and p-FETs for various logic circuits on a single substrate using the proposed structure. Background Technology

[0004] Charge-trapping memory is a representative semiconductor-based non-volatile memory characterized by a gate stack with gate electrodes, blocking oxide (BO), charge-trapping layer (TL), tunnel oxide (TO), and semiconductor channel[1]-[4]. It is suitable for high-density 3D integration and has sufficient retention time, thus it is widely used in flash memory and solid-state drives. However, deploying such non-volatile memory near control processing units (CPUs) with high-speed, high-throughput data exchange remains challenging, mainly due to the still relatively slow program / erase (P / E) speed and low endurance. In most modern computers, the first and second layers of the memory hierarchy are still volatile memories that can be written and read more than trillions of times in sub-nanoseconds, such as static / dynamic random access memory (SRAM and DRAM).

[0005] Traditional charge-trap memory (CTMB) faces a trilemma of high endurance, high speed, and long hold time. During the hold phase, the TO layer acts as a barrier between the TL and semiconductor channel to confine the stored charge. A large bandgap between TO and TL is beneficial for long hold times. During the P / E phase, the TO layer resists charge transfer between the TL and semiconductor channel. Therefore, high P / E speeds require thin TO layers and high P / E voltages, which imposes excessive electrical stress on the TO layer and is detrimental to high endurance. For these reasons, current CTMB flash memory technology exhibits long P / E times ranging from 10 microseconds to 10 nanoseconds, with a maximum P / E cycle of 10. 5 It maintains a lifespan of over 10 years [1-4].

[0006] Several solutions have been proposed to address the issues of P / E speed and / or endurance for charge-trapping-based memory devices. Semi-floating gate memories have been shown to achieve ultrafast P / E times [5]. By deploying semiconductor junction diodes connected to the charge storage layer, the electrical connection of the charge storage layer is switched from floating to semi-floating, thereby achieving ultrafast P / E times of several nanoseconds. However, due to the narrow bandgap of silicon semiconductors (approximately 1.1 eV), a significant compromise must be made on the hold time.

[0007] Therefore, there is a need for an improved non-volatile memory structure to achieve high P / E speed while having high durability and long retention time, which at least reduces or essentially eliminates the aforementioned drawbacks and problems.

[0008] References

[0009] The following references are cited in this article and are incorporated herein by reference:

[0010] [1] CHLee, KI Choi, MK Cho, YHSong, KCPark and K. Kim, “A novel SiO2 / SiN / Al2O3 SONOS structure with TaN metal gate for multi-giga bit flash memories”, IEEE International Electron Devices Meeting (IEDM), 2003, pp. 26.5.1-26.5.4, doi:10.1109 / IEDM.2003.1269356.

[0011] [2] HTLue, SYWang, EKLai, YHShih, SCLai, LWYang, KCChen, J.Ku, KYHsieh, R.Liu and CYLu, “BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability”, IEEE International Electron Devices Conference (IEDM), 2005, pp. 547-550, doi:10.1109 / IEDM.2005.1609404.

[0012] [3] M. Ishiduki, Y. Fukuzumi, R. Katsumata, M. Kito, M. Kido, H. Tanaka, Y. Komori, Y. Nagata, T. Fujiwara, T. Maeda, Y. Mikajiri, S. Oota, M. Honda, Y. Iwata, R. Kirisawa, H. Aochi and A. Nitayama, “Optimal Device Structure for Pipe-shaped BiCS Flash Memory for Ultra High Density Storage Device with Excellent Performance and Reliability”, IEEE International Electron Devices Meeting (IEDM), 2009, pp. 27.3.1-27.3.4, doi:10.1109 / IEDM.2009.5424261.

[0013] [4] S. Tsuda, Y. Kawashima, K. Sonoda, A. Yoshitomi, T. Mihara, S. Narumi, M. Inoue, S. Muranaka, T. Maruyama, T. Yamashita, Y. Yamaguchi and D. Hisamoto, “First Demonstration of FinFET Split-Gate MONOS for High-Speed ​​and Highly-Reliable Embedded Flash in 16 / 14nm-node and beyond”, IEEE International Electron Devices Meeting (IEDM), 2016, pp. 11.1.1-11.1.4, doi:10.1109 / IEDM.2016.7838393.

[0014] [5] P. Wang, X. Lin, L. Liu, Q. Sun, P. Zhou, X. Liu, W. Liu, Y. Gong, DW Zhang, “A Semi-Floating Gate Transistor for Low-Voltage Ultrafast Memory and Sensing Operation”, Science, Vol. 334, No. 6146, pp. 640-643, August 2013, doi:10.1126 / science.1240961.

[0015] [6] Z. Zheng, L. Zhang, W. Song, S. Feng, H. Xu, J. Sun, S. Yang, T. Chen, J. Wei and K. J. Chen, “Gallium nitride-based complementary logic integrated circuits”, Nat. Electron., July 2021, doi:10.1038 / s41928-021-00611-y.

[0016] [7] Z. Zheng, W. Song, L. Zhang, S. Yang, J. Wei, K. J. Chen, “High ION and ION / IOFF ratio enhancement-mode buried p-channel GaN MOSFETs on p-GaN gate power HEMT platform”, IEEE Electron Device Lett., Vol. 41, No. 1, January 2020, pp. 26-29, doi:10.1109 / LED.2019.2954035. Summary of the Invention

[0017] This disclosure proposes a wide-bandgap (WBG) semiconductor bipolar charge trapping (BCT) nonvolatile memory with only a single insulating layer. Specifically, the proposed WBG semiconductor BCT nonvolatile memory structure utilizes wide-bandgap semiconductor materials, including but not limited to gallium nitride (GaN), to enhance data retention and the bipolar charge trapping process, thereby improving data P / E speed while enhancing durability. Preferably, the proposed WBG semiconductor BCT nonvolatile memory structure is fabricated based on GaN-based heterojunction or planar GaN heterojunction-based high electron mobility transistors (HEMTs). The proposed WBG semiconductor BCT nonvolatile memory structure provides sufficient barrier height for hole and electron injection and trapping in the absence of intrinsically TO conditions within the semiconductor. In the proposed structure, only an external bias voltage is needed during the P / E stage to reduce the potential barrier in the wide-bandgap semiconductor junction for electron injection and hole diffusion. Furthermore, in the proposed structure, since the external bias voltage compensates for the built-in potential, significant carrier transport occurs as the electric field decreases, thus ensuring high durability. Using the proposed structure, P / E speeds up to sub-nanosecond levels and speeds exceeding 10⁻⁶ are achievable. 8 The proposed structure exhibits P / E operation over 10 cycles and a retention time of over 10 years. It can be fabricated on a commercially available gallium nitride-on-silicon (GaN-on-Si) platform where peripheral write / read circuitry is readily available and can be integrated with other existing or emerging GaN-based electronic or optoelectronic devices [6-7].

[0018] Therefore, a first aspect of the present invention provides a charge trapping semiconductor device comprising a structure having a lower wide bandgap semiconductor channel layer and one or more corresponding ohmic contact regions, an upper wide bandgap semiconductor channel layer and one or more corresponding ohmic contact regions, one or more insulating layers disposed on one or both of the upper wide bandgap semiconductor channel layer and the lower wide bandgap semiconductor channel layer, one or more charge trapping layers disposed between the upper wide bandgap semiconductor channel layer / lower wide bandgap semiconductor channel layer and their respective insulating layers, and one or more control gates in contact with the corresponding insulating layers.

[0019] In some embodiments, the upper wide bandgap semiconductor channel layer is n-type doped, and the lower wide bandgap semiconductor channel is p-type doped.

[0020] In some embodiments, the upper wide bandgap semiconductor channel layer is p-type doped, and the lower wide bandgap semiconductor channel is n-type doped.

[0021] In some embodiments, one or both of the upper wide-bandgap semiconductor channel layer and the lower wide-bandgap semiconductor layer are undoped.

[0022] In some embodiments, at least one of the charge trapping layers is disposed on the upper wide bandgap semiconductor channel layer; one of the insulating layers is disposed on the charge trapping layer; and one of the control gates is disposed on the insulating layer, forming a top gate structure.

[0023] In some embodiments, at least one of the charge trapping layers is disposed under the lower wide bandgap semiconductor channel layer; one of the insulating layers is disposed under the charge trapping layer; and one of the control gates is disposed under the insulating layer, forming a bottom gate or buried gate structure.

[0024] In other embodiments, an upper charge trapping layer is disposed on the upper wide bandgap semiconductor channel layer; an upper insulating layer is disposed on the upper charge trapping layer; and the top control gate is disposed on the upper insulating layer to form a top gate structure; while a lower charge trapping layer is disposed below the lower wide bandgap semiconductor channel layer, a lower insulating layer is disposed below the lower charge trapping layer, and the bottom control gate is disposed below the lower insulating layer to form a bottom gate or buried gate structure.

[0025] In some embodiments, a barrier layer (or potential barrier layer) is disposed between the lower wide bandgap semiconductor channel and the upper wide bandgap semiconductor channel, including but not limited to a semiconductor material having a wider bandgap than the lower wide bandgap semiconductor channel layer or the upper wide bandgap semiconductor channel layer, or other semiconductor materials forming a heterojunction structure with the lower wide bandgap semiconductor channel layer or the upper wide bandgap semiconductor channel layer.

[0026] In some embodiments, the p-type doped wide bandgap semiconductor channel layer is made of a p-type doped wide bandgap semiconductor, including but not limited to p-type gallium nitride (GaN), p-type silicon carbide (SiC), p-type aluminum nitride (AlN), p-type gallium oxide (Ga2O3), and p-type diamond; or it is made of a wide bandgap semiconductor heterojunction structure, including but not limited to AlGaN / GaN and AlN / GaN structures.

[0027] In some embodiments, the n-type doped wide bandgap semiconductor channel is made of an n-type doped wide bandgap semiconductor, including but not limited to n-type gallium nitride (GaN), n-type silicon carbide (SiC), n-type aluminum nitride (AlN), n-type gallium oxide (Ga2O3), and n-type diamond; or it is made of a wide bandgap semiconductor heterojunction structure, including but not limited to AlGaN / GaN and AlN / GaN structures.

[0028] In some embodiments, the undoped wide bandgap semiconductor channel is made of an undoped wide bandgap semiconductor, including but not limited to undoped gallium nitride (GaN), undoped silicon carbide (SiC), undoped aluminum nitride (AlN), undoped gallium oxide (Ga2O3), and undoped diamond; or it is made of a wide bandgap semiconductor heterojunction structure, including but not limited to AlGaN / GaN and AlN / GaN structures.

[0029] In some embodiments, the control gate is made of one or more of a metal, a metal alloy, a metal oxide, a metal nitride, and a heavily doped semiconductor.

[0030] Preferably, the control gate is made of one or more of the following materials: nickel, titanium, aluminum, silver, gold, tungsten, chromium, titanium nitride, titanium tungsten, indium tin oxide, and polycrystalline silicon.

[0031] In some embodiments, the insulating layer is made of an oxide, a nitride dielectric material, or a semiconductor material having a bandgap wider than that of the lower or upper wide bandgap semiconductor channel layer.

[0032] Preferably, the insulating layer is made of a barrier oxide (BO), including silicon oxide (SiO), aluminum oxide (AlO), gallium oxide (GaO), zirconium oxide (ZrO), hafnium oxide (HfO), or hafnium zirconium oxide (HfZrO); or it is made of a nitride dielectric material, including silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxynitride (AlON), or gallium oxynitride (GaON).

[0033] In some embodiments, the lower wide bandgap semiconductor channel layer and the upper wide bandgap semiconductor channel layer are made of group III nitrides, including aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), silicon compounds, or silicon carbide (SiC).

[0034] In some embodiments, the upper wide bandgap semiconductor channel layer or the lower wide bandgap semiconductor channel layer has at least two ohmic contact regions arranged on two opposite sides where a control gate is disposed.

[0035] In some embodiments, the charge trapping layer is a modified semiconductor surface of an n-type, p-type, or undoped wide-bandgap semiconductor channel layer that is in direct contact with the insulating layer.

[0036] In other embodiments, the charge trapping layer is an additional semiconductor layer with a band gap smaller than that of the n-type, p-type, or undoped wide bandgap semiconductor channel layer.

[0037] In some other embodiments, the charge trapping layer is a metal layer.

[0038] In some other embodiments, the charge trapping layer is a heavily doped semiconductor layer.

[0039] In some embodiments, the lower wide bandgap semiconductor channel layer and the upper wide bandgap semiconductor channel layer are made of the same material to form a wide bandgap semiconductor pn junction.

[0040] In other embodiments, one of the wide bandgap semiconductor channel layers is made of a heterogeneous semiconductor material or a multilayer structure to form a heterojunction with another wide bandgap semiconductor channel layer.

[0041] In some embodiments, the lower wide bandgap semiconductor channel layer or the upper wide bandgap semiconductor channel layer is also the substrate of the device.

[0042] In other embodiments, the lower wide bandgap semiconductor channel layer or the upper wide bandgap semiconductor channel layer has other substrate materials disposed thereunder.

[0043] Preferably, at least one ohmic contact region of the lower wide bandgap semiconductor channel layer or the upper wide bandgap semiconductor channel layer has an independent electrode.

[0044] In some embodiments, at least one ohmic contact region of one of the wide bandgap semiconductor layers is shorted to one of at least two ohmic contact regions of another wide bandgap semiconductor channel layer via an interconnect metal.

[0045] In some embodiments, at least one ohmic contact region is a pair of n-type ohmic contact regions disposed on a barrier layer disposed on a lower wide bandgap semiconductor layer, wherein an upper wide bandgap semiconductor channel layer disposed on the barrier layer is selectively removed to partially expose the barrier layer, and disposed on two opposite sides of the remaining upper wide bandgap semiconductor channel layer, wherein a control gate is provided.

[0046] In some embodiments, the charge-trapping semiconductor device is a buried p-channel gallium nitride (GaN) field-effect transistor (p-FET) charge-trapping memory device, which can be mainly divided into two parts, namely, a p-channel part and an n-channel part.

[0047] In some embodiments, the p-FET charge trapping memory device includes a substrate, a buffer layer disposed on the substrate, an n-type wide bandgap semiconductor channel layer disposed on the buffer layer, a barrier layer disposed on the n-type wide bandgap semiconductor channel layer, a p-type doped GaN (p-GaN) forming a p-type wide bandgap semiconductor channel layer disposed on the barrier layer, and a gate structure disposed on a recess in the p-GaN channel layer.

[0048] In some embodiments, an n-type heterojunction channel region is formed on the p-GaN channel layer by selectively removing a portion of the p-GaN channel layer from the barrier layer.

[0049] In some embodiments, at least one n-type ohmic contact region is formed on the n-type heterojunction channel region.

[0050] In some embodiments, a pair of p-type ohmic contacts, which serve as source and drain contacts respectively, are formed on two opposite sides of the location where the gate structure will be arranged on the recess of the p-GaN channel.

[0051] In some embodiments, the gate structure includes a charge trapping layer (TL), a dielectric layer disposed on the TL as a barrier oxide (BO) layer, and a gate electrode disposed on the BO layer.

[0052] In some embodiments, the substrate is selected from silicon, sapphire, diamond, silicon carbide (SiC), aluminum nitride (AlN), or gallium nitride (GaN).

[0053] In some embodiments, the buffer layer is selected from aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), or any alloy thereof.

[0054] According to certain embodiments described herein, a second aspect of the present invention provides a method for manufacturing a charge-trapping semiconductor device, the method comprising:

[0055] A structure is provided comprising at least a substrate, a buffer layer, a lower wide-bandgap semiconductor layer, a barrier layer, and an upper wide-bandgap semiconductor layer;

[0056] Partially remove the upper wide bandgap semiconductor channel layer to partially expose the barrier layer, leaving an active region of the upper wide bandgap semiconductor channel layer on the barrier layer for subsequent bonding with the gate structure;

[0057] A pair of identical ohmic contact regions are provided on two opposite sides of a region in the barrier layer where the upper wide-bandgap semiconductor channel layer has been removed;

[0058] A pair of ohmic contact regions are provided on two opposite sides of the active region that will be bonded to the gate structure in the upper wide bandgap semiconductor channel layer.

[0059] A groove is provided in the active region of the upper wide bandgap semiconductor channel layer for bonding with the gate structure;

[0060] A charge trapping layer is provided above the surface of the groove of the upper wide-bandgap semiconductor layer;

[0061] An insulating layer is provided on the ohmic contact region, charge trapping layer, and other regions besides the region where the ohmic contact is provided on the upper wide bandgap semiconductor channel layer and barrier layer;

[0062] A gate electrode is provided on a groove of an upper wide bandgap semiconductor channel layer to cover at least a gate foot region, wherein an insulating layer is provided on a charge trapping layer in the groove at the gate foot region;

[0063] Selectively remove the insulating layer from the horizontal surface covering the ohmic contact region and the insulating layer partially covering its vertical surface, such that the upper wide-bandgap semiconductor channel layer remains insulated by the insulating layer, while the contact window of the corresponding ohmic contact region is opened; and

[0064] Pad metal is deposited on the gate electrode and ohmic contact area to form pads thereon.

[0065] In some embodiments, a silicon wafer is chosen as the substrate. Other possible candidate materials may also be selected, such as sapphire, diamond, silicon carbide (SiC), aluminum nitride (AlN), and gallium nitride (GaN).

[0066] In some embodiments, the buffer layer is selected from aluminum nitride (AlN), gallium nitride (GaN), or indium nitride (InN), or alloys thereof.

[0067] In some embodiments, a GaN channel layer is selected as the lower wide bandgap semiconductor channel layer.

[0068] In some embodiments, the GaN channel layer, which serves as the lower wide bandgap semiconductor channel layer, is unintentionally doped with magnesium.

[0069] In some embodiments, an aluminum gallium nitride (AlGaN) barrier layer is selected as the barrier layer. Other possible barrier layer materials may be selected from aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), or any alloy thereof.

[0070] In some embodiments, the barrier layer may be a single-layer or multi-layer structure.

[0071] In some embodiments, the upper wide bandgap semiconductor channel layer is made of the same material as the lower wide bandgap semiconductor channel layer.

[0072] In some embodiments, the lower wide bandgap semiconductor channel layer is n-type doped, and the upper wide bandgap semiconductor channel layer is p-type doped.

[0073] In some embodiments, the lower wide bandgap semiconductor channel layer is p-type doped, and the upper wide bandgap semiconductor channel layer is n-type doped.

[0074] In some embodiments, one or both of the lower wide bandgap semiconductor channel layer and the upper wide bandgap semiconductor channel layer are undoped.

[0075] In some embodiments, the n-type doped wide bandgap semiconductor channel layer is made of an n-type wide bandgap semiconductor, including but not limited to n-type gallium nitride (GaN), n-type silicon carbide (SiC), n-type aluminum nitride (AlN), n-type gallium oxide (Ga2O3), and n-type diamond; or it is made of a wide bandgap semiconductor heterojunction structure, including but not limited to AlGaN / GaN and AlN / GaN structures.

[0076] In some embodiments, the p-type doped wide bandgap semiconductor channel layer is made of a p-type wide bandgap semiconductor, including but not limited to p-type gallium nitride (GaN), p-type silicon carbide (SiC), p-type aluminum nitride (AlN), p-type gallium oxide (Ga2O3), and p-type diamond; or it is made of a wide bandgap semiconductor heterojunction structure, including but not limited to AlGaN / GaN and AlN / GaN structures.

[0077] In some embodiments, the partial removal of the upper wide bandgap semiconductor channel layer to partially expose the barrier layer and leave an active region for bonding with the gate structure is performed by dry etching, such as plasma dry etching or digital etching, or a combination thereof.

[0078] In some embodiments, the pair of identical ohmic contact regions on two opposite sides of a region in the barrier layer where the upper wide-bandgap semiconductor channel layer has been removed are made from metals, metal alloys, metal oxides, metal nitrides, heavily doped semiconductors by epitaxial growth using chemical vapor deposition, molecular beam epitaxy, sputtering, atomic layer deposition or evaporation or similar processes.

[0079] In some embodiments, the pair of distinct ohmic contact regions on two opposite sides of the active region of the gate structure to be received in the upper wide bandgap semiconductor channel layer are formed from metals, metal alloys, metal oxides, metal nitrides, heavily doped semiconductors by epitaxial growth using chemical vapor deposition, molecular beam epitaxy, sputtering, atomic layer deposition or evaporation or similar processes.

[0080] In some embodiments, the grooves in the upper wide-bandgap semiconductor channel layer are provided by dry etching, digital etching, or a combination thereof.

[0081] In some embodiments, the charge trapping layer is provided by plasma treatment (including oxygen plasma treatment) of the upper wide bandgap semiconductor channel layer or by epitaxial growth using chemical vapor deposition, molecular beam epitaxy, sputtering, atomic layer deposition or evaporation or similar processes.

[0082] In some embodiments, the insulating layer is provided by epitaxial growth to form a dielectric layer using chemical vapor deposition, molecular beam epitaxy, sputtering, atomic layer deposition, evaporation, or similar processes.

[0083] In some embodiments, the gate electrode is made of a metal, metal alloy, metal oxide, metal nitride, or heavily doped semiconductor, and is provided by epitaxial growth using chemical vapor deposition, molecular beam epitaxy, sputtering, atomic layer deposition, evaporation, or similar processes.

[0084] In some embodiments, the selective removal of the insulating layer from the upper wide bandgap semiconductor channel layer to form the contact window of the corresponding ohmic contact region is performed by dry etching, such as plasma dry etching, digital etching, or a combination thereof.

[0085] In some embodiments, a pad window is formed by probing the contact window of the corresponding ohmic contact region with pad metal, and the ohmic contact region includes both a source contact region and a drain contact region.

[0086] In some embodiments, the pad metal includes one or more of nickel, titanium, aluminum, silver, gold, tungsten, chromium, and any alloy thereof.

[0087] A third aspect of the invention provides monolithically integrated enhancement-mode (E-mode) n-channel and p-channel field-effect transistors (n-FETs and p-FETs) for wide-bandgap semiconductor-based complementary logic (CL) gates formed on a single substrate, and a method for manufacturing said transistors in a single process execution, the method comprising:

[0088] A substrate is provided, on which a buffer layer is provided.

[0089] The lower wide bandgap semiconductor channel layer is arranged on the buffer layer.

[0090] A barrier layer disposed on the lower wide bandgap semiconductor channel layer, and

[0091] A wide-bandgap semiconductor channel layer disposed on a barrier layer;

[0092] A hard mask is provided on the upper wide bandgap semiconductor channel layer for masking during subsequent patterning;

[0093] Selectively remove the unmasked upper wide bandgap semiconductor layer from the gate region of the n-FET and the region outside the p-FET;

[0094] The hard mask is removed from the location where the upper wide bandgap semiconductor channel is selectively removed, and then a surface passivation layer is deposited on the p-FET and n-FET regions;

[0095] Corresponding ohmic contact regions are provided on the n-FET and p-FET respectively by opening contact windows in corresponding regions on the surface passivation layer;

[0096] Remove the surface passivation layer on the gate region of the p-FET, and then create a groove on the upper wide bandgap semiconductor channel layer to form a recessed p-FET gate region;

[0097] The recessed p-FET gate region is surface-treated, and then a dielectric layer is deposited on both the n-FET and p-FET.

[0098] The n-FET and p-FET are isolated by multi-level ion implantation;

[0099] The base layer is selectively removed from the corresponding ohmic contact region and gate region of the n-FET;

[0100] Gate electrodes are provided on the corresponding gate regions of the n-FET and p-EFT, respectively; and

[0101] Pad metal is deposited on the gate electrode and ohmic contact area to form pads thereon.

[0102] In some embodiments, a silicon wafer is chosen as the substrate. Other possible candidate materials may also be selected, such as sapphire, diamond, silicon carbide (SiC), aluminum nitride (AlN), and gallium nitride (GaN).

[0103] In some embodiments, the buffer layer is selected from aluminum nitride (AlN), gallium nitride (GaN), or indium nitride (InN), or alloys thereof.

[0104] In some embodiments, an aluminum gallium nitride (AlGaN) barrier layer is selected as the barrier layer. Other possible barrier layer materials may be selected from aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), or any alloy thereof.

[0105] In some embodiments, a GaN channel layer is selected as the lower wide bandgap semiconductor channel layer.

[0106] In some embodiments, the lower wide bandgap semiconductor channel layer is n-type doped, and the upper wide bandgap semiconductor channel layer is p-type doped.

[0107] In some embodiments, the lower wide bandgap semiconductor channel layer is p-type doped, and the upper wide bandgap semiconductor channel layer is n-type doped.

[0108] In some embodiments, the lower wide bandgap semiconductor channel layer and / or the upper wide bandgap semiconductor channel layer are undoped.

[0109] In some embodiments, the n-type wide bandgap semiconductor channel layer is made of an n-type wide bandgap semiconductor, including but not limited to n-type gallium nitride (GaN), n-type silicon carbide (SiC), n-type aluminum nitride (AlN), n-type gallium oxide (Ga2O3), and n-type diamond; or it is made of a wide bandgap semiconductor heterojunction structure, including but not limited to AlGaN / GaN and AlN / GaN structures.

[0110] In some embodiments, the p-type wide bandgap semiconductor channel layer is made of a p-type wide bandgap semiconductor, including but not limited to p-type gallium nitride (GaN), p-type silicon carbide (SiC), p-type aluminum nitride (AlN), p-type gallium oxide (Ga2O3), and p-type diamond; or it is made of a wide bandgap semiconductor heterojunction structure, including but not limited to AlGaN / GaN and AlN / GaN structures.

[0111] In some embodiments, the dielectric layer is made of an oxide, nitride dielectric material, or a semiconductor material having a band gap wider than that of a wide band gap semiconductor channel layer.

[0112] In some embodiments, the dielectric layer is made of silicon oxide (SiO), aluminum oxide (AlO), gallium oxide (GaO), zirconium oxide (ZrO), hafnium oxide (HfO) or hafnium zirconium oxide (HfZrO), or is made of a nitride dielectric material, including silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxynitride (AlON) or gallium oxynitride (GaON).

[0113] In some embodiments, both the hard mask and the surface passivation layer are made of silicon oxide.

[0114] In some embodiments, the surface passivation layer is made of silicon oxide (SiO), aluminum oxide (AlO), gallium oxide (GaO), zirconium oxide (ZrO), hafnium oxide (HfO), or hafnium zirconium oxide (HfZrO); or it is made of a nitride dielectric material, including silicon nitride (SiN), aluminum nitride (AlN), silicon oxynitride (SiON), aluminum oxynitride (AlON), or gallium oxynitride (GaON); or it is made of a bilayer or multilayer dielectric material, including but not limited to AlN / SiN, AlN / SiO, AlN / AlO, AlON / AlN / SiN, AlON / AlN / SiO, or AlON / AlN / AlO.

[0115] In some embodiments, the surface treatment of the recessed p-GaN gate region is carried out by plasma treatment, including but not limited to oxygen plasma, hydrogen plasma, and nitrogen plasma; or by solvent treatment, including but not limited to diluted or undiluted hydrochloric acid, hydrosulfuric acid, hydrofluoric acid, piranha solution, tetramethylammonium hydroxide solution, and ammonia solution.

[0116] In some embodiments, the multi-level ion implantation is selected from fluorine ion implantation.

[0117] In some embodiments, the corresponding gates of the n-FET and p-FET have a gate aspect ratio of 1:10.

[0118] In some embodiments, the ohmic contact regions of each of the n-FET and p-FET are source contact regions and drain contact regions.

[0119] In some embodiments, the pad metal includes one or more of nickel, titanium, aluminum, silver, gold, tungsten, chromium, and any alloy thereof.

[0120] Other aspects of the invention include an integrated GaN complementary logic (CL) gate prepared by using the method described in the third aspect, and a single-level or multi-level logic circuit incorporating one or more integrated GaN CL gates, wherein the single-level logic circuit includes, but is not limited to, inverters, NOR gates, NAND gates, and transmission gates; and the multi-level logic circuit includes, but is not limited to, latch units and ring oscillators having up to 15 levels of complementary logic gates.

[0121] This "Summary of the Invention" section provides a brief overview of some concepts that will be further described in the "Detailed Description" section below. This "Summary of the Invention" section is not intended to identify key or essential features of the subject matter to be protected, nor is it intended to help determine the scope of the subject matter to be protected. Other aspects of the invention are disclosed in the embodiments described below. Attached Figure Description

[0122] The same reference numerals in the accompanying drawings denote the same elements or elements that are functionally similar. The drawings include graphics of certain embodiments to further illustrate and explain the above and other aspects, advantages, and features of the invention. It should be understood that these drawings illustrate only some embodiments of the invention and are not intended to limit the scope of the invention. The invention will now be described and explained with more features and details using the accompanying drawings, in which:

[0123] Figure 1A A top view of a charge-trapping semiconductor device on a GaN heterojunction according to certain embodiments of the present invention is shown;

[0124] Figure 1B It shows Figure 1A The cross-sectional view (A-A') of the device for the p-channel portion is shown;

[0125] Figure 1C It shows Figure 1A Another cross-sectional view (B-B') of the device for the n-channel portion is shown;

[0126] Figure 2 A flowchart illustrating a method for fabricating a charge-trapping semiconductor device on a GaN heterojunction according to certain embodiments of the present invention is shown;

[0127] Figure 3 A series of cross-sectional views depicting a manufacturing method according to certain embodiments of the present invention are shown, the cross-sections of the p-channel portion and the n-channel portion respectively;

[0128] Figure 4A Quasi-static transfer curves of a charge-trapping semiconductor device according to certain embodiments of the present invention are shown;

[0129] Figure 4B Pulse-mode transfer curves of a charge-trapping semiconductor device according to certain embodiments of the present invention are shown, illustrating two storage states and a storage window of 2.2 volts;

[0130] Figure 5A This shows the effect of using different erase pulse widths (t). E ) and a fixed erase voltage of -10 volts (V E The transfer curves of the charge-trapping semiconductor device according to certain embodiments of the present invention, measured after an erasure operation; the curves enclosed by dashed lines represent curves that have been effectively erased;

[0131] Figure 5B This shows the effect of using different programmed pulse widths (t) P ) and a fixed programming voltage of 20 volts (V PThe transfer curves of the charge trapping semiconductor device according to certain embodiments of the present invention, measured after programming operations; the curves enclosed by dashed lines represent curves that have been effectively programmed.

[0132] Figure 6A The diagram shows the transfer curves of a charge-trapping semiconductor device according to certain embodiments of the invention, measured after P / E operation with varying delay times for retention characteristic measurements; the two distinct dashed circles represent retention performance measurements at a fixed erase voltage and a fixed programming voltage, respectively.

[0133] Figure 6B It shows from Figure 6A The V value extracted from the retention characteristic measurement value enclosed by the corresponding dashed line in the figure. TH ;

[0134] Figure 7A The diagram shows the charge trapping semiconductor device according to certain embodiments of the invention, measured after P / E cycles for durability measurements; the two distinct dashed circles represent the charges at a fixed erase voltage (V). E ) and fixed programming voltage (V P Durability characteristic measurement values ​​at ( ) location;

[0135] Figure 7B It shows from such Figure 7A The durability characteristic measurement value extracted by the dashed line shown is V. TH V P =20 volts and V E = -10 volts;

[0136] Figure 8A The diagram shows the charge trapping semiconductor device according to certain embodiments of the invention, measured after different P / E cycles for durability measurements; the two different dashed circles represent the charge trapping semiconductor device at a fixed erase voltage (V). E ) and fixed programming voltage (V P Durability characteristic measurement values ​​at ( ) location;

[0137] Figure 8B It shows from such Figure 8A The durability characteristic measurement value extracted by the dashed line shown is V. TH V P =10 volts and V E = -10 volts;

[0138] Figure 9 A method for manufacturing an integrated GaN complementary logic (CL) inverter according to certain embodiments of the present invention is schematically depicted;

[0139] Figure 10A A schematic depiction according to Figure 9A perspective view of an integrated GaN CL inverter fabricated by the method shown in the diagram;

[0140] Figure 10B The circuit diagrams of the integrated GaN CL inverter in two static logic states are schematically depicted, in which only one FET is turned on in each static state;

[0141] Figure 10C The energy band diagrams of the n-FET and p-FET of the integrated GaN CL inverter are schematically depicted under different logic inputs, illustrating how they generate greatly suppressed static power dissipation; "br" and "ox" refer to the blocking layer and oxide dielectric layer, respectively; "E" Fn "and "E Fp "Represents the quasi-Fermi levels of electrons and holes in a non-equilibrium system, respectively;

[0142] Figure 10D The SEM image of the integrated GaN CL inverter is shown in grayscale; the passive regions of both the n-FET and p-FET are defined by fluorine ion implantation (a planar isolation technique) to make the device appear as a planar structure without obvious mesa-trench.

[0143] Figure 11A The gate capacitances of the n-FET and p-FET of an integrated GaN CL inverter according to certain embodiments of the present invention are shown; V S V G and V D These represent the voltages applied to the source, gate, and drain of the inverter, respectively.

[0144] Figure 11B The following is illustrated using a logarithmic scale: Figure 11A The transfer characteristics of n-FET and p-FET are shown;

[0145] Figure 11C The output characteristics (IV) of an integrated GaN CL inverter with n-FET and p-FET according to certain embodiments of the present invention are shown;

[0146] Figure 12A GaN CL inverters according to certain embodiments of the present invention are shown at different supply voltages (V). dd Input-output voltage (V) under ) in -V out Transfer characteristics;

[0147] Figure 12B A GaN CL inverter according to certain embodiments of the present invention is shown through different V in and V dd The quasi-static power consumption generated by drawing current from the power supply;

[0148] Figure 12C GaN CL inverters according to certain embodiments of the present invention are shown at different V... in and V dd Voltage gain under;

[0149] Figure 12D A GaN CL inverter according to certain embodiments of the present invention is shown at 5 volts. dd The noise margin is (1201); 1201 represents the conversion window region; 1203 represents the boundary of the conversion window defined at the unity gain point; the inset shows an image of the inverter obtained by testing using a three-dimensional confocal laser microscope;

[0150] Figure 12E Voltage transfer curves of a GaN CL inverter according to certain embodiments of the present invention are shown at different temperatures ranging from room temperature to 200°C.

[0151] Figure 12F Output voltage according to logic "low" and "high" (represented as V respectively). OL and V OH Lower and higher input conversion voltages (represented as V) IL and V IH ) and the conversion threshold (V TH This summarizes GaN CL inverters according to certain embodiments of the present invention at 5V. dd Noise margin at different temperatures;

[0152] Figure 12G A GaN CL inverter according to certain embodiments of the present invention is shown at 5 volts. dd V under continuous switching operation with varying drive frequencies from 100kHz to 2MHz in and V out The waveform;

[0153] Figure 12H A GaN CL inverter according to certain embodiments of the present invention is shown at its average V IH V TH and V IL (n=50) transfer characteristics; Ave: average; Dev.: deviation;

[0154] Figure 13A Confocal laser microscope grayscale images of NAND gates prepared according to certain embodiments of the present invention are shown;

[0155] Figure 13B It shows Figure 13A Circuit diagram of NAND gates in the circuit;

[0156] Figure 13C It shows Figure 13A Input-output waveforms of NAND gates in a computer;

[0157] Figure 13D Confocal laser microscope grayscale images of NOR gates prepared according to certain embodiments of the present invention are shown;

[0158] Figure 13E It shows Figure 13D The circuit diagram of the NOR gate in the image;

[0159] Figure 13F It shows Figure 13D Input-output waveforms of a NOR gate in a computer;

[0160] Figure 13G The image shows a confocal laser microscope grayscale image of a transmission gate prepared according to certain embodiments of the present invention;

[0161] Figure 13H It shows Figure 13G The circuit diagram of the transmission gate in the diagram;

[0162] Figure 13I As shown Figure 13G The input-output waveform of the transmission gate is shown, where the transmission gate is blocked and the output mode is high impedance (high Z).

[0163] Figure 14A A circuit diagram of a latch unit consisting of two cross-coupled inverters according to certain embodiments of the present invention is shown.

[0164] Figure 14B It shows according to Figure 14A The confocal laser microscope grayscale image of the latch unit prepared from the circuit diagram;

[0165] Figure 14C The results measured at different input voltages are shown. Figure 14B The input-output waveform of the latch unit in the image, where the switch “S” is closed intermittently to load the input signal (gray shaded area);

[0166] Figure 14D The figure shows the measurement under long-term bias after loading the logic state and turning on switch "S". Figure 14B The input-output waveforms of the latch unit in the image;

[0167] Figure 15A A circuit diagram of an oscillator (OSC) prepared according to certain embodiments of the present invention is shown;

[0168] Figure 15B It shows according to Figure 15AA confocal laser microscope grayscale image of a 15-stage ring oscillator fabricated from a circuit diagram;

[0169] Figure 15C This shows the output buffer inverter (with 5 volts) dd The output monitored at the ) such as Figure 15B The single oscillation period (T) of the ring oscillator in osc The output waveform (above) of the gray shaded area, and the corresponding power spectrum (P) with a fundamental frequency of 502 kHz and subsequent harmonic peaks of, for example, 1.004 MHz. out (See image below);

[0170] Figure 15D As shown Figure 15B The fundamental oscillation frequency (f) of the ring oscillator in the middle osc The power supply voltage dependence of the stage (top figure) and the power delay product of each stage (bottom figure);

[0171] Figure 15E It shows Figure 15D The ring oscillator shown in the figure f osc Temperature dependence (top figure) and power-delay product of each stage (bottom figure);

[0172] Figure 15F Examples of inverter stages with different numbers (N) are shown. Figure 15B The corresponding f of the ring oscillator in osc (Above image) and oscillation period (T) osc ), where T osc A linear fit to N yielded an average propagation delay (τ) of 61 nanoseconds per stage. pd ).

[0173] Those skilled in the art will understand that the elements in the accompanying drawings are shown for the purpose of simplicity and clarity and are not necessarily drawn to scale. Detailed Implementation

[0174] It will be apparent to those skilled in the art that various modifications, including additions and / or substitutions, can be made without departing from the scope and spirit of the invention. Specific details may be omitted to avoid obscuring the invention; however, this disclosure is intended to enable those skilled in the art to practice the teachings herein without requiring excessive experimentation.

[0175] Please go to Figure 1A A preferred structure of the device is depicted in a top view, the structure comprising at least:

[0176] The trenches (in the channel layer arranged on the upper wide bandgap semiconductor, p-type doped GaN (p-GaN)) are perpendicular to the channel layer. Figure 1AThe control gate (G) is shown in the rectangular area defined by the two parallel dashed lines in the top view.

[0177] Arranged on two opposite sides of the control gate and in contact with the p-GaN channel layer (e.g.) Figure 1B The cross-section of the image shows the two source (S) contact regions and the drain (D) contact regions.

[0178] Arranged on the other two opposite sides of the control gate and in contact with the AlGaN barrier layer (e.g.) Figure 1C The other two identical source (S) contact regions (shown in cross-section);

[0179] In addition to the source contact region and the drain contact region, an insulating layer (e.g., a barrier oxide (BO) layer) is disposed on the p-GaN channel layer including the recessed trench region under the control gate;

[0180] A charge trapping layer (TL) is disposed at the horizontal surface of a recessed trench on which a control gate of the p-GaN channel is disposed between the insulating layer and the p-GaN channel layer; and

[0181] A lower wide-bandgap semiconductor n-type channel layer (e.g., GaN channel) disposed under an AlGaN barrier layer.

[0182] The control gate (G) includes a gate electrode formed of one or more of a metal, metal alloy, metal oxide, metal nitride, and heavily doped semiconductor, wherein the metal, metal alloy, metal oxide, metal nitride, and heavily doped semiconductor include, but are not limited to, nickel (Ni), titanium (Ti), aluminum (Al), silver (Ag), gold (Au), tungsten (W), chromium (Cr), titanium nitride (TiN), titanium tungsten (TiW), indium tin oxide (ITO), and polycrystalline silicon.

[0183] Barrier oxides (BO) that form insulating layers include, but are not limited to, silicon oxide (SiO), aluminum oxide (AlO), gallium oxide (GaO), zirconium oxide (ZrO), hafnium oxide (HfO), and hafnium zirconium oxide (HfZrO). Other potential materials for fabricating insulating layers include nitride dielectric materials or semiconductor materials with a bandgap wider than that of wide-bandgap semiconductor channel layers, such as silicon oxynitride (SiON), aluminum oxynitride (AlON), and gallium oxynitride (GaON).

[0184] In addition to gallium nitride (GaN), the upper wide bandgap semiconductor channel layer and the lower wide bandgap semiconductor channel layer can also be made of silicon carbide (SiC), gallium oxide (Ga2O3), aluminum nitride (AlN), diamond, or made of a wide bandgap semiconductor heterojunction structure, including but not limited to AlGaN / GaN and AlN / GaN structures.

[0185] like Figure 1B As shown (the diagram is along) Figure 1A The top view of the structure (a cross-sectional view taken from the A-A' plane) shows that the upper wide-bandgap semiconductor channel layer (p-GaN) can have at least two ohmic contact regions, which are represented by D and S respectively, and are arranged on both sides of the control gate.

[0186] The charge trapping layer (TL) can be a modified semiconductor surface of a wide bandgap semiconductor channel layer that is in direct contact with the insulating layer, or another semiconductor layer or metal layer that has a smaller bandgap than the wide bandgap semiconductor channel layer.

[0187] The lower wide bandgap semiconductor channel layer can be made of the same material as the upper wide bandgap semiconductor channel layer, but with a different doping type, to form a pn junction with the wide bandgap semiconductor channel; or it can be made of a heterogeneous semiconductor material or a multilayer material to form a heterojunction with the wide bandgap semiconductor channel.

[0188] When the lower wide-bandgap semiconductor channel layer is made of the same material as the upper wide-bandgap semiconductor channel layer, a preferred embodiment is gallium nitride (GaN). Other possible materials may be silicon carbide (SiC), group III nitrides, gallium oxide (Ga2O3), or diamond.

[0189] The doping types of the upper wide-bandgap semiconductor channel layer and the lower wide-bandgap semiconductor channel layer can be the same or different.

[0190] In some embodiments, the lower wide bandgap semiconductor channel layer is also the substrate of the device.

[0191] In other embodiments, the lower wide bandgap semiconductor channel layer has other substrate materials disposed thereunder.

[0192] When the lower wide-bandgap semiconductor channel layer has at least one ohmic contact region, it can be a standalone electrode, or as... Figure 1C As shown (the diagram is along) Figure 1A (A top view of the structure taken from the B-B' plane, or a cross-sectional view of the structure, or shorted to one of the other two ohmic contact areas through one or more interconnecting metal layers.)

[0193] If the lower wide-bandgap semiconductor channel layer is not the substrate of the device, one or more other substrate materials, such as buffer layers, nucleation layers and / or silicon wafers, may be disposed thereunder.

[0194] Please go to Figure 2 The diagram shows a flowchart of a method for fabricating a WBG semiconductor BCT nonvolatile memory structure on a GaN-based heterojunction according to certain embodiments. Figure 3A corresponding diagram is provided, which is based on Figure 2 Each step shown is illustrated with a corresponding cross-sectional view (to be shown separately). Figure 1B and 1C The A-A' and B-B' planes in the diagram depict the geometric changes in the p-channel and n-channel portions of the device. The method includes initially providing a buffer layer disposed on a substrate, a GaN channel layer disposed on the buffer layer, an AlGaN barrier layer disposed on the GaN channel layer, and finally a p-GaN layer disposed on the AlGaN barrier layer (s201, 301a, 301b). This initial step is performed if the lower wide-bandgap semiconductor channel layer is not the substrate of the device. An n-type heterojunction channel region (s202, 302a, 302b) is then formed by selectively etching the p-GaN layer therefrom. An n-type ohmic contact region (s203, 303b) is then formed on the n-type heterojunction channel. A p-type ohmic source / drain contact region (s204, 304a) is then formed on the p-GaN layer on two opposite sides of the defined p-GaN gate region. The p-GaN layer is then selectively recessed to define the p-GaN gate region (s205, 305a, 305b). Subsequently, a charge trapping layer (TL) and a barrier oxide (BO) layer (s206, 306a, 306b) are sequentially deposited on the p-GaN gate region. After the BO layer is formed, a gate contact region (e.g., gate electrode) is further formed on the BO layer in the p-GaN gate region (s207, 307a, 307b). The source and drain contact regions are opened by removing the corresponding BO layers from the source and drain contact regions (s208, 308a, 308b), and then pads are formed thereon by probing the pad metal on the source, drain, and gate contact regions (s209, 309a, 309b). Further details for performing each step of this method will be provided in other embodiments or examples described below.

[0195] Please go to Figure 4A and 4B The large hysteresis window demonstrates the excellent suitability of the proposed WBG semiconductor BCT non-volatile memory device for memory applications.

[0196] Please go to Figure 5A and 5B The -10V erase voltage with a 100-nanosecond erase pulse width and the 20V programming voltage with a programming time as short as 20 nanoseconds are sufficient for effective programming and erasing, thus demonstrating that the proposed device can achieve ultrafast P / E speeds.

[0197] Please go to Figure 6A and 6B The proposed device is shown to be capable of 10 4The program / erase state is maintained after a 10-second hold period. The 10-year lifespan is calculated based on measurement results and maintains a good storage window of 1.5 volts after the 10-year hold period.

[0198] Please go to Figure 7A and 7B The proposed device is shown to withstand more than 10 6 No significant degradation occurred after several P / E cycles.

[0199] Please go to Figure 8A and 8B The proposed device exhibits enhanced durability, capable of withstanding over 10... 8 P / E cycle 2.

[0200] The following examples will illustrate how the proposed structure, which includes an upper wide-bandgap semiconductor channel and a lower wide-bandgap semiconductor channel, can be applied to various integrated circuits including various complementary logic (CL) gates, as well as their corresponding manufacturing methods.

[0201] Example

[0202] (A) Monolithic integration of enhancement-mode (E-mode) N-channel and P-channel GaN field-effect transistors (N-FETs and P-FETs) on a single substrate for complementary logic (CL) gates.

[0203] Gallium nitride (GaN)-based planar heterojunction high electron mobility transistors (HEMTs) fabricated as power switching devices on large silicon substrates require peripheral circuitry for drive, control, sensing, and protection modules. Therefore, monolithic integration is necessary to achieve on-chip functionality, enhance robustness, and facilitate miniaturization of power conversion systems. The planar configuration of GaN HEMTs (i.e., source, gate, and drain located on the top surface) is advantageous for high-density integration; however, most conventional GaN integrated circuits are currently based on n-channel devices where electrons are the majority carriers. Furthermore, the typical peripheral circuitry for GaN power devices consists of a large number of logic blocks. Complementary metal-oxide-semiconductor (CMOS) topology dominates in silicon-based logic circuits because it offers the most energy-efficient solution for very large-scale integrated circuits (VLSI) and mixed-signal ICs. However, in conventional GaN-CMOS circuits, there is no suitable integration strategy to combine both enhancement-mode n-FETs and p-EFTs on a single substrate.

[0204] By using the fabrication methods described herein, integrated CMOS basic logic gates, such as inverters, NOR gates, NAND gates, and transmission gates, as well as multi-level logic circuits, such as two-stage latches and ring oscillators, with rail-to-rail operation and ultra-low quiescent power consumption, were fabricated. Commercially available gallium nitride-on-silicon (GaN-on-Si) wafers designed for power electronic devices characterized by p-GaN / AlGaN / GaN epitaxial stacks can be used as “substrates” for IC fabrication. Oxygen plasma processing (OPT) is used to form buried p-channel enhancement-type FETs with characteristics for complementary logic (CL) circuitry. For example, inverters fabricated using this method exhibit well-balanced transition thresholds and sharp transition regions, providing good noise margin and robustness for multi-level logic gate integration; two-stage latches and ring oscillators with up to 15 stages can be fabricated.

[0205] GaN HEMTs are typically fabricated based on heterojunctions of wurtzite GaN and its alloys (e.g., AlGaN / GaN heterojunctions). The non-centrosymmetric wurtzite structure and the significant electronegativity difference between nitrogen and group III elements (e.g., gallium, aluminum, indium) induce significant polarization effects in group III nitride compounds, where strain caused by lattice mismatch between dissimilarly stacked alloy layers induces additional piezoelectric polarization. High-density polarization charge (approximately 10⁻⁶) at the AlGaN / GaN heterojunction interface is observed. 13 cm -2 This creates a sharp potential well, in which electrons with very high mobility (approximately 2000 cm⁻¹) are formed. 2 Two-dimensional electron gas (2DEG) of / Vs.

[0206] Since GaN HEMTs are naturally depletion-mode (D-mode) transistors, in order to achieve enhancement-mode operation, a layer of p-GaN (usually heavily doped) is placed in the gate region above the AlGaN layer to deplete the underlying 2DEG.

[0207] Complementary devices to GaN HEMTs (such as p-channel GaN FETs) are not common because the hole mobility in GaN material is quite low compared to the electron mobility (<50 cm⁻¹ at room temperature). 2 / V·s, typically about 15cm 2The electron mobility (V·s) inherently stems from the valence band structure and intrinsically strong phonon scattering. While significant improvements have been made to the p-FET platform to enhance hole mobility or current density, the intrinsic mobility mismatch does not support GaN as a suitable candidate for advanced CMOS technology for low-power, high-speed logic circuits. On the other hand, the desire to monolithically integrate peripheral circuitry with GaN power switches operating at mid-frequency offers an attractive and easy opportunity for GaN complementary CL circuits. Typical operating frequencies are in the 100kHz–10MHz range, which is technically achievable and cost-effective for GaN CL circuits. Therefore, this device starts with mainstream GaN power platforms (p-GaN / AlGaN / GaN-on-Si) rather than with other specific epitaxial structures designed to maximize the current density of GaN p-FETs.

[0208] The locations for the n-FET (at the AlGaN / GaN heterojunction) and p-FET (in the p-GaN layer) coexist naturally and are inherently decoupled because the p-GaN layer and the thin AlGaN barrier layer are designed to deplete the underlying 2DEG n-channel. The enhancement-mode n-FET required in the CL circuit can be implemented using the same process as that used for normally-off p-GaN gate power HEMTs, with a shorter gate-drain distance. Dense epitaxial growth and process optimization have yielded high-quality p-GaN layers on such a commercial platform. Hall measurements show a hole density of approximately 1.23 × 10⁻⁶ at room temperature. 13 cm -2 The hole mobility is approximately 10.2 cm. 2 / V·s, which is in the same range as data extracted from other platforms. Substantial enhancement-mode operation of the p-FET can be achieved through a buried channel structure used to maintain a reasonable hole current density.

[0209] (B) Epitaxial structure and fabrication of integrated GaN CL inverters

[0210] All integrated GaN logic circuits described herein are preferably fabricated on a gallium nitride-on-silicon (GaN-on-Si) wafer in a single process run. In this example, the n-FET is characterized by a configuration having a gate-source spacing of 2 micrometers (L). GS ), 3.5 micrometer gate length (L) G ), 2 micrometer gate-drain spacing (L) GD ) and a gate width of 10 micrometers (W G ); L of p-FET GS / L G / L GD / W GThe dimensions are 3 / 1.5 / 3 / 100 micrometers, respectively. Group III nitride epitaxial layers are grown on p-type low-resistivity silicon wafers via metal-organic chemical vapor deposition (MOCVD). They consist of a 4-micrometer transition / buffer layer, an unintentionally doped GaN channel layer, a 12-nanometer AlGaN barrier layer, and a layer with a nominal magnesium doping concentration of approximately 3 × 10⁻⁶. 19 cm -3 The sample consists of an 85 nm p-GaN layer. Prior to device fabrication, the sample underwent a wet solution-based cleaning process, including ultrasonic treatment in acetone and immersion in buffered oxide etchant (BOE) to remove surface contaminants and native oxides. Subsequently, the sample was loaded into a plasma-enhanced chemical vapor deposition (PECVD) chamber to deposit an approximately 70 nm thick silicon dioxide layer as a hard mask for dry etching of the p-GaN.

[0211] All patterning was performed using photolithography. The first patterning step involved removing p-GaN from the area reserved for the p-FET and outside the p-GaN gate of the n-FET. A hard mask was opened using reactive ion etching (RIE) with a CHF3 / O2 mixed gas, followed by p-GaN etching using BCl3 plasma via an inductively coupled plasma reactive ion etching (ICP-RIE) system. The etching depth was controlled by a pre-calibrated etching time and detected by atomic force microscopy (AFM). After dry etching, the hard mask was removed by immersion in a BOE. Another 70 nm silicon dioxide layer was then deposited as a surface passivation layer. The ohmic contact region of the n-FET was then formed by opening contact windows on the passivation layer, electron beam evaporation of a Ti / Al / Ni / Au metal stack (20 / 150 / 50 / 80 nm), stripping, and rapid thermal annealing (RTA) at 850 °C for 30 seconds in a nitrogen atmosphere. The ohmic contact region of the p-FET was formed in a similar manner, but the metal stack was changed to Ni / Au (both 20 nm thick), and annealed at 550 °C for 10 minutes in an oxygen atmosphere. The contact resistance of the p-FET was extracted to be 61 Ω·mm using the transfer length method (TLM).

[0212] The channel region of the p-FET is defined by a recessed trench formed by passivation layer opening using RIE and p-GaN etching using ICP-RIE. Approximately 30 nm (total thickness 85 nm) of p-GaN layer is retained as the channel region. To achieve enhancement-mode operation, the etched p-channel surface is subjected to in-situ oxygen plasma treatment (OPT) in an ICP chamber using low-power oxygen plasma. The coil power and platen power of the ICP plasma are 50 W and 30 W, respectively. The chamber pressure is set to 10 mTorr and the oxygen flow rate is set to 10 sccm. The treatment time is 1 minute. X-ray photoelectron spectroscopy (XPS) was used to characterize the p-GaN surfaces after OPT and without OPT.

[0213] Following OPT, the sample is loaded into an atomic layer deposition (ALD) system to deposit the gate dielectric layer for the p-FET. Approximately 20 nm of aluminum oxide is used as the gate dielectric. Subsequently, device isolation is achieved via multi-level (up to 110 keV) fluorine ion implantation. This planar isolation technique eliminates leakage sidewalls in step-trench based schemes and effectively suppresses leakage current. In the n-FET, the gate metal forms a direct Schottky contact with p-GaN. The gate electrodes and probe pads for both the n-FET and p-FET are simultaneously formed by electron beam deposition and stripping of Ni / Au. Figure 9 A schematic diagram depicting the manufacturing process of this example is shown, and Figure 10A and 10D Schematic perspective view and SEM image of an integrated GaN CL inverter fabricated according to this manufacturing process are shown respectively.

[0214] Please go to Figure 10B and 10C The p-GaN layer is used as part of the gate stack in the n-FET channel, which raises the energy band to deplete the underlying 2DEG channel under thermal equilibrium. As a result, when the inverter input is logic '0', the voltage from the power supply (V...)... dd The current path to ground (GND) is blocked by the n-FET. Figure 10B -(i)). Under positive gate bias, the energy band bends downward and electrons are induced into the 2DEG channel to conduct current ( Figure 10C -(ii)), while in the p-FET channel, the p-GaN under the gate serves as the p-channel and is thinned so that it can be effectively controlled by the gate. Oxygen plasma treatment (OPT) is performed after moderate trench etching to transform the top portion of the remaining p-GaN into a pore-free region, as oxygen compensates for magnesium doping or passivates magnesium by forming magnesium-oxygen complexes. Such an OPT process promotes the depletion of the p-channel under thermal equilibrium. Figure 10C -(iv)). Therefore, the p-FET channel is configured in enhancement mode (E-mode) and utilizes the logic '1' input to block the signal from V. dd Current path to GND ( Figure 10B -(ii)). Due to its relative position to the source (which is connected to V), dd The negative gate bias of the p-channel pulls the energy band upward, and the buried p-channel begins to form. Figure 10C -(iii)). In this conduction state, holes are located in the buried channel, i.e., in the p-GaN region far from the interface between the dielectric and the semiconductor layer, where significant disorder / interface scattering occurs. The buried p-channel has higher crystal quality compared to the interface region and is less affected by the adverse effects from the interface, where the damage caused by groove etching is more concentrated. Therefore, a reasonable hole current density is achieved through enhancement-mode operation, enabling the inverter output to reach V in both logic states. dd And the power rails of GND.

[0215] (C) Quasi-static device characterization of discrete n-FET and p-FET channels

[0216] Please go to Figure 11A The figure shows the gate capacitance-gate voltage (C) G -V G The differences in characteristics reveal the different operating principles of n-FET and p-FET channels. For n-FET channels, the drain current (Id) is significantly different. D The Ic is tunable by adjusting the electron density in the 2DEG channel. Since all charge carriers are confined within a 2D thin layer, they are coupled to the charge in the gate metal via parallel-plate capacitance, and thus the CV curve of the n-FET channel generally exhibits a plateau when the device is turned on. For buried p-FET channels, Ic is tunable over the operating gate voltage range (e.g., 0 to -5 V). D This is tunable by controlling the thickness of the non-depleted p-GaN layer (i.e., the channel). Therefore, the variable depletion boundary leads to a V-dependent... G C G .

[0217] Please go to Figure 11BThe logarithmically scaled transition curves show that both the n-FET and p-FET channels are true enhancement-mode with nearly symmetrical threshold voltages, significantly suppressing gate current and drain leakage in the off-state. Both channels exhibit high on / off ratios, very low leakage current, and suppressed gate current due to the MOS gate stack in the p-FET and the Schottky p-GaN / AlGaN / GaN gate stack in the n-FET. This results in high quasi-static / static input impedance for GaN complementary logic modules, ensuring rail-to-rail operation in multi-level logic circuits, while ultra-low off-state leakage current ensures low quiescent power consumption in both logic states.

[0218] Please go to Figure 11C The output current-voltage (IV) characteristics of the n / p-FET channels indicate a significant mismatch in their current densities due to the inherent mismatch between electron and hole mobilities in the GaN material. Therefore, careful configuration of the gate width ratio of the n-FET and p-FET is necessary to address this mismatch. Preferably, in this invention, the gate width ratio of the n-FET to the p-FET is 1:10.

[0219] Unlike conventional silicon-based CMOS circuits where both p-FETs and n-FETs have 'metal-oxide-semiconductor (MOS)' gate stacks, according to certain embodiments of the invention, only the p-FET has a 'MOS' structure, while the n-FET is essentially a heterojunction field-effect transistor (HFET). Therefore, a more appropriate interpretation of the circuitry in this inverter should be a 'complementary logic (CL) circuit' with 'CMOS-like' behavior, rather than 'CMOS'. However, it should be noted that in the gate stack of the enhancement-type n-FET of the present invention, an additional p-GaN layer is present on the AlGaN / GaN heterostructure. Therefore, the gate IV characteristics are significantly different from those of a conventional HFET, thus forming a more MOSFET-like n-FET. The n-FET of the present invention is characterized by having a p-GaN gate stack, which can be modeled as a series connection of a pin junction (i.e., a p-GaN / AlGaN / GaN junction) and a gate metal / p-GaN Schottky junction. Schottky junctions are reverse biased under a positive gate bias, which suppresses gate leakage, makes the gate forward breakdown voltage greater than 10 volts, and increases the gate voltage swing. All of these are crucial for the operation of GaN complementary ICs using a standard 5-volt supply voltage.

[0220] (D) Characterization of GaN CL inverters

[0221] Please go to Figure 12A At different power supply voltages (V) dd Under these conditions, the output voltage level of logic '1' is always equal to V.dd The logic '0' output is always 0 volts, meaning the inverter's output changes from V... dd The orbit swings to the GND orbit (rail-to-rail), indicating that rail-to-rail operation has been achieved. Typically in V... in =V out Lower limit of conversion threshold (V) TH Located in V dd Half of that, because the threshold voltages of n-FETs and p-FETs are symmetrical. At V dd At only 2 volts, the GaN CL inverter exhibits tri-state behavior because at V in At approximately 1 volt, both the n-FET and p-FET are in the off state.

[0222] Please go to Figure 12B The diagram shows that the power consumption of the GaN CL inverter occurs during the switching state, but it exhibits strong enhancement-mode operation and a high on / off current ratio (approximately 10) in both n-FET and p-FET. 7 When ), compared to the transition state, in the two static states (V) in =0 volts or V dd The power consumption was significantly reduced by up to three orders of magnitude (depending on V). dd The static power consumption characteristic of the GaN CL inverter of this invention is equivalent to the most important characteristic of CMOS circuits (i.e., low static power consumption), and in terms of efficiency, this static power consumption characteristic is superior to other conventional logic circuit schemes, such as resistor-transistor logic (RTL) or direct-coupled FET logic (DCFL) structures. With V dd As the voltage increases, the conversion window narrows, while the voltage gain increases, particularly at 5 volts. dd The maximum peak gain was recorded at 80 volts. Figure 12C ).

[0223] In GaN power electronics, a 5-volt power supply is typically used for the logic control sub-circuits. This inverter is also suitable for use at such a 5-volt voltage. dd Go to work. Figure 12D This shows the noise margin of this inverter analyzed according to the voltage transfer relationship of the cross-coupled inverter, where the logic 'low' level (V IL –V OL The noise margin is 2.1 volts, while the logic 'high' level (V) OH –V IH The noise margin is 2.6 volts, which indicates that both noise margins are large enough that this inverter is shown to have high immunity to various noises, such as electromagnetic interference generated by high-frequency power switching.

[0224] Please go to Figure 12EThe voltage transfer of this GaN CL inverter, measured at elevated temperatures from room temperature to up to 200°C, is shown, from which characteristic transition voltages are extracted and summarized. Figure 12F In the middle. Although the conversion window and V at high temperatures. TH The deviation increased slightly, but the excellent characteristics of GaN CL inverters (such as rail-to-rail operation, wide noise margin, and fast logic state transitions) were well preserved. At high temperatures up to 350°C (in... Figure 12E (Not shown in the image), although the output swing is slightly compressed, good noise margin (approximately 1.83 volts) and voltage gain (approximately 18.1 volts / volt) are still achieved. In contrast, due to the relatively narrow bandgap of silicon (approximately 1.1 eV), the operating temperature of conventional bulk silicon CMOS circuits is typically limited to 125°C, or 175°C in some special applications, because silicon MOSFETs cannot be effectively turned off, and thermally induced junction leakage currents can easily lead to latch-up and failure. CMOS circuits based on silicon-on-insulator (SOI) and silicon carbide (SiC) have been developed for operation at higher temperatures. SOI CMOS circuits do not have latch-up problems and suppress bulk leakage currents, thus enabling operation at temperatures up to 300°C. SiC CMOS's operating temperature is further increased to 400°C and above due to its wider bandgap of 3.26 eV. On the other hand, GaN has a wider bandgap of approximately 3.4 eV and provides a favorable platform for developing devices and circuits for high-temperature applications. Furthermore, the heterojunction-based epitaxial structure employed in this invention naturally eliminates the latch-up process because it lacks parasitic thyristor structures. The GaN CL inverters described herein have demonstrated remarkable high-temperature durability, indicating their potential for deployment in harsh environments.

[0225] Please go to Figure 12G The waveform of the inverter of the present invention was measured under continuous switching operation with a varying drive frequency of up to 2 MHz, where its rise time is limited by the p-FET. However, the p-FET in this example has not yet reached the inherent limit of mobility. With further optimization of the channel trench etching and oxidation processes, the current density of the p-FET at the same device size is expected to increase, and thus the operating frequency will increase by several megahertz. Furthermore, due to the limitations of the photolithography technology used, the gate length of the p-FET in this example is 1.5 micrometers. By reasonably scaling the device to simultaneously reduce channel resistance and gate capacitance, the speed of the p-FET can be greatly increased to several megahertz. By using an 8-inch production line to manufacture GaN power HEMT devices, submicron photolithography can reduce the gate length (L) to several megahertz. GThe size can be reduced to 180–250 nanometers. Considering the buried p-channel structure, power supply voltage level, and short-channel effect, a 250-nanometer L-channel can be used. G To enable operation at frequencies of several megahertz in current GaN CL circuits.

[0226] Please go to Figure 12H For 50 inverters, each with a surface area of ​​2×2 square centimeters, the average boundary input voltage (V) is... IL V IH ) and conversion threshold (V TH The transfer characteristics in terms of n-FET were characterized. V, related to the conduction process of the n-FET, was also analyzed. IL The tight distribution indicates that the manufactured n-FET has good consistency. Since the p-FET in this invention is manufactured by dry etching, fluctuations in etching depth may lead to variations in V... TH and V IH The distribution is slightly coarse. However, all the inverters described in this paper demonstrate the ability to operate with sufficient noise margin, and their consistency is expected to improve significantly during large-scale industrial production.

[0227] (E) Application in monolithic GaN CL gates

[0228] In addition to its use in integrated GaN CL inverters, this device structure is also suitable for forming other basic CL gates as fundamental building blocks of logic circuits.

[0229] Please go to Figure 13A-13I It provides images of NAND gates taken using a confocal laser microscope. Figure 13A ), NOR gate ( Figure 13D ) and transmission gate ( Figure 13G The grayscale images of ) and their respective circuit diagrams (which are respectively Figure 13B , 13E and 13H) and operation waveforms (respectively) Figure 13C , 13FThe corresponding logic states are shown in the diagram (13I). In this example, both the NAND and NOR gates exhibit correct logic operations according to their truth tables and provide rail-to-rail outputs at sub-MHz operating frequencies. The two input signals fed into the NAND gate are both 0.5MHz with a 90° phase shift, which drives the output signal to switch at an equivalent frequency of 1MHz. However, because the two p-FETs of the NOR gate are connected in series, the NOR gate exhibits a slower switching speed. Therefore, it is characterized by an input signal of 0.25MHz. The device ratio can be further adjusted in different logic gates to produce optimal performance. A transmission gate with complementary n-FETs and p-FETs in parallel allows signals to pass through in the on state without being truncated and effectively blocks signals in the off state, because both the n-FET and p-FET are capable of switching at V... GS Completely shut off when the voltage is 0 volts.

[0230] (F) Multilevel logic circuits – latches and ring oscillators

[0231] Please go to Figure 14A and 14B To demonstrate the feasibility of applying this device in multi-level logic circuits, a latching cell consisting of two cross-coupled GaN CL inverters as described herein is provided, in which one bit of information can be stored in the latching cell as illustrated in this example. Different input voltages are applied to node Q of the latching cell by intermittently closing switch 'S'. At 5 volts... dd In this case, due to the high noise margin in the inverter, the latch cell maintains its logic state even when an input voltage deviates by 2 volts from its static state. Figure 14C ).like Figure 14D As shown, the logic state can be rapidly switched by external pulses, but remains for a long time. The ability to store data enables the implementation of memory cells (e.g., static random access memory (SRAM)) and sequential logic circuits. This example demonstrates that the present invention is suitable for constructing finite state machines or microprocessors using group III nitrides (e.g., GaN).

[0232] Please go to Figure 15A and 15B The second example provided is a multi-level logic circuit, namely a ring oscillator having 15 stages of inverters cascaded in a ring and additional inverters arranged outside the ring as output buffers serving as internal oscillation nodes. Figure 15C The oscillation waveform of the ring oscillator (top) and the corresponding power spectrum (bottom) are shown, with the oscillation period of 1.99 microseconds and the fundamental frequency of 502 kHz shown respectively. Figure 15D The product of the fundamental frequency and power delay of each stage of the ring oscillator versus the supply voltage (V) is shown. ddThe dependency of ) is increased by increasing the V of this type of CL gate. dd The circuit's transmission speed is increased, but dynamic power consumption is sacrificed at the same time. This differs from conventional DCFL circuits, where increasing V... dd It doesn't necessarily lead to higher speeds. Figure 15E The temperature dependence of the ring oscillator at temperatures up to 200°C is further demonstrated, wherein the ring oscillator exhibits a stable oscillation frequency and power-delay product over a wide temperature range, because the inverter of the present invention has satisfactory thermal stability. More ring oscillators composed of varying numbers of inverters have also been fabricated and characterized, such as... Figure 15F As shown. In Figure 15F In this process, a linear fitting method can be used to extract the average delay of 61 nanoseconds per stage. Even with the manufacturing method and interface optimization of this invention, there is still significant room for improvement in speed, reducing the propagation delay to the sub-nanosecond level to meet the switching requirements of power electronic devices at MHz frequencies. The successful implementation of the GaN CL inverter of this invention in the construction of a CMOS ring oscillator demonstrates the practical application of this invention in the fabrication of GaN-based complementary logic ICs.

[0233] As described in the examples, single-stage logic inverters and multi-stage logic circuits based on the structure proposed in this invention exhibit rail-to-rail operation, significantly suppressed quiescent power consumption, a suitable switching threshold, a narrow switching window with high voltage gain and good noise margin, and good thermal stability, indicating that this invention is suitable for applications in harsh environments. The monolithically integrated energy-efficient peripheral circuitry based on the proposed GaN CL inverter structure, capable of driving, controlling, and protecting GaN devices, is suitable for high-frequency / high-power-density applications or applications in harsh environments.

[0234] While the invention has been described with reference to certain embodiments, other embodiments that will be apparent to those skilled in the art are also within the scope of the invention. Therefore, the scope of the invention should be defined only by the appended claims.

Claims

1. A charge-trapping semiconductor memory device, comprising: Lower wide-bandgap semiconductor channel layer; A barrier layer disposed on the lower wide bandgap semiconductor channel layer; An upper wide bandgap semiconductor channel layer disposed on the barrier layer, wherein the upper wide bandgap semiconductor channel layer includes an active region formed for bonding with a gate electrode, and a groove is provided at the active region; A pair of identical ohmic contact regions disposed on two opposite sides of the region where the upper wide bandgap semiconductor channel layer has been removed, on the barrier layer; A pair of different ohmic contact regions are arranged on two opposite sides of the active region; A charge trapping layer disposed on the bottom horizontal surface of the groove; An insulating layer, excluding the ohmic contact region, disposed on the upper wide-bandgap semiconductor channel layer, the barrier layer, and the charge trapping layer; and The gate electrode is disposed in the active region and formed on the insulating layer. The barrier layer is a semiconductor material with a wider bandgap than either the lower or upper wide bandgap semiconductor channel layer, thereby forming heterojunctions with both the lower and upper wide bandgap semiconductor channel layers. In the absence of a tunnel oxide layer, the charge-trapping semiconductor memory device is provided with a barrier by the blocking layer.

2. The device according to claim 1, wherein: The upper wide-bandgap semiconductor channel layer is n-type doped, and the lower wide-bandgap semiconductor channel layer is p-type doped; or The upper wide bandgap semiconductor channel layer is p-type doped, and the lower wide bandgap semiconductor channel layer is n-type doped.

3. The device according to claim 1, further comprising: A lower charge trapping layer disposed beneath the lower wide bandgap semiconductor channel layer; A lower insulating layer disposed beneath the lower charge trapping layer; and The bottom gate electrode is arranged under the lower insulating layer to form a dual-gate structure.

4. The device according to claim 1, wherein the insulating layer is made of a barrier oxide selected from silicon oxide (SiO), aluminum oxide (AlO), gallium oxide (GaO), zirconium oxide (ZrO), hafnium oxide (HfO), or hafnium zirconium oxide (HfZrO), or is made of a nitride dielectric material selected from silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxynitride (AlON), or gallium oxynitride (GaON).

5. The device of claim 1, wherein the charge trapping layer is selected from a modified semiconductor surface of either the upper wide bandgap semiconductor channel layer or the lower wide bandgap semiconductor channel layer that is in direct contact with the insulating layer, a layer separate from either the upper wide bandgap semiconductor channel layer or the lower wide bandgap semiconductor channel layer, a heavily doped semiconductor layer, or a metal layer.

6. The device according to claim 1, wherein, The materials constituting the barrier layer include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or other semiconductor materials capable of forming the heterojunction with the upper wide bandgap semiconductor channel layer or the lower wide bandgap semiconductor channel layer.

7. The device according to claim 2, wherein: The material constituting the upper wide bandgap semiconductor channel layer or the lower wide bandgap semiconductor channel layer of the p-type doped layer is selected from p-type GaN, p-type SiC, p-type AlN, p-type Ga2O3, and p-type diamond. The material constituting the upper wide bandgap semiconductor channel layer or the lower wide bandgap semiconductor channel layer of the n-type doped layer is selected from n-type GaN, n-type SiC, n-type AlN, n-type Ga2O3, and n-type diamond. The structure constituting the heterojunction is selected from AlGaN / GaN, AlN / AlGaN / GaN, AlGaN / AlN / GaN, AlN / AlGaN / AlN / GaN, or AlN / GaN structure.

8. The device according to claim 1, further comprising: A buffer layer disposed beneath the lower wide-bandgap semiconductor channel layer; and The substrate disposed under the buffer layer, The material constituting the substrate is selected from silicon, sapphire, diamond, silicon carbide (SiC), aluminum nitride (AlN), or gallium nitride (GaN). The material constituting the buffer layer is selected from aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), or any alloy thereof.

9. A complementary logic circuit comprising the charge trapping semiconductor memory device according to claim 1.

10. A method of manufacturing a charge-trapping semiconductor memory device according to claim 1, comprising: A structure is provided comprising at least a substrate, a buffer layer, the lower wide bandgap semiconductor channel layer, the barrier layer, and the upper wide bandgap semiconductor channel layer; The upper wide bandgap semiconductor channel layer is partially removed to partially expose the barrier layer, leaving an active region of the upper wide bandgap semiconductor channel layer on the barrier layer for subsequent bonding with the gate electrode; The pair of identical ohmic contact regions are provided on two opposite sides of the region of the barrier layer where the upper wide bandgap semiconductor channel layer has been removed; The pair of distinct ohmic contact regions are provided on two opposite sides of the active region of the upper wide bandgap semiconductor channel layer; The groove is provided in the active region for engaging with the gate electrode; A charge trapping layer is provided above the bottom horizontal surface of the groove; The insulating layer is provided on the ohmic contact region on the upper wide bandgap semiconductor channel layer and the barrier layer, the charge trapping layer, and other regions besides the regions where ohmic contacts are provided; A gate electrode is provided on the groove to cover at least the gate foot region, where the insulating layer is disposed on the charge trapping layer in the groove. The insulating layer is selectively removed from the horizontal surface covering the ohmic contact area and the insulating layer that partially covers its vertical surface, so that the upper wide bandgap semiconductor channel layer remains insulated by the insulating layer, while the contact window of the corresponding ohmic contact area is opened. as well as Pad metal is deposited on the gate electrode and ohmic contact area to form pads thereon.

11. The method of claim 10, wherein the charge trapping layer is provided by plasma treatment of the upper wide bandgap semiconductor channel layer or by epitaxial growth using chemical vapor deposition, molecular beam epitaxy, sputtering, atomic layer deposition or evaporation processes, wherein the plasma treatment includes oxygen plasma treatment.

12. A method for fabricating monolithically integrated enhancement-mode E-mode n-channel field-effect transistors (n-FETs) and p-channel field-effect transistors (p-FETs) for wide-bandgap semiconductor-based complementary logic (CL) gates on a single substrate in a single process run, comprising: A substrate is provided, on which a buffer layer is provided. A lower wide bandgap semiconductor channel layer disposed on the buffer layer, A barrier layer disposed on the lower wide bandgap semiconductor channel layer, and A wide-bandgap semiconductor channel layer disposed on the barrier layer; A hard mask is provided on a wide bandgap semiconductor channel layer with a second doping type for masking during subsequent patterning; Selectively remove the unmasked upper wide bandgap semiconductor channel layer from the gate region of the n-FET and the region outside the p-FET; The hard mask is removed from the location where the upper wide bandgap semiconductor channel layer is selectively removed, and then a surface passivation layer is deposited on the p-FET and n-FET regions; Corresponding ohmic contact regions are provided on the n-FET and p-FET respectively by opening contact windows in the corresponding regions on the surface passivation layer; Remove the surface passivation layer on the gate region of the p-FET, and then create a groove on the upper wide bandgap semiconductor channel layer to form a recessed p-FET gate region; The recessed p-FET gate region is surface-treated, and then a dielectric layer is deposited on both the n-FET and the p-FET. The n-FET and p-FET are isolated by multi-level ion implantation; The dielectric layer is selectively removed from the corresponding ohmic contact region and gate region of the n-FET; Gate electrodes are provided on the corresponding gate regions of the n-FET and p-FET, respectively; as well as Pad metal is deposited on the gate electrode and ohmic contact area to form pads thereon.

13. The method according to claim 12, wherein: The lower wide bandgap semiconductor channel layer and the upper wide bandgap semiconductor channel layer are made of gallium nitride (GaN), silicon carbide (SiC), aluminum nitride (AlN), gallium oxide (Ga2O3), or diamond.

14. The method according to claim 12, wherein, The dielectric layer is made of silicon oxide (SiO), aluminum oxide (AlO), gallium oxide (GaO), zirconium oxide (ZrO), hafnium oxide (HfO), or hafnium zirconium oxide (HfZrO), or is made of a nitride dielectric material, including silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxynitride (AlON), or gallium oxynitride (GaON).

15. The method according to claim 12, wherein, The surface passivation layer is made of silicon oxide (SiO), aluminum oxide (AlO), gallium oxide (GaO), zirconium oxide (ZrO), hafnium oxide (HfO), or hafnium zirconium oxide (HfZrO); or it is made of a nitride dielectric material, including silicon nitride (SiN), aluminum nitride (AlN), silicon oxynitride (SiON), aluminum oxynitride (AlON), or gallium oxynitride (GaON); or it is made of a double-layer or multi-layer dielectric material, including AlN / SiN, AlN / SiO, AlN / AlO, AlON / AlN / SiN, AlON / AlN / SiO, or AlON / AlN / AlO.

16. The method according to claim 12, wherein, The surface treatment of the recessed p-FET gate region is carried out by plasma treatment, including but not limited to oxygen plasma, hydrogen plasma and nitrogen plasma; or by solvent treatment, including but not limited to diluted or undiluted hydrochloric acid, hydrosulfuric acid, hydrofluoric acid, piranha solution, tetramethylammonium hydroxide solution and ammonia solution.

17. The method according to claim 12, wherein, The corresponding gates of the n-FET and p-FET have a gate aspect ratio of 1:

10.

18. An integrated gallium nitride-based complementary logic gate prepared by the method according to claim 12.

19. A single-level logic circuit or a multi-level logic circuit, comprising one or more integrated gallium nitride-based complementary logic gates according to claim 18, wherein the single-level logic circuit comprises an inverter, a NOR gate, a NAND gate, and a transmission gate; and the multi-level logic circuit comprises a latch unit and a ring oscillator.

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