Semiconductor structure preparation method and semiconductor structure
By forming a concave-convex surface on the outer layer of the active column of the semiconductor structure and increasing the specific surface area of the gate oxide layer, the problem of performance degradation caused by weakening of the transistor gate control ability is solved, and the overall performance of the semiconductor structure is improved.
Patent Information
- Application Number
- CN202110926631.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-08-12
- Publication Date
- 2025-10-03
- Estimated Expiration
- 2041-08-12
AI Technical Summary
As the feature size of DRAM devices decreases, the gate control capability of transistors weakens and the short channel effect becomes significant, resulting in reduced performance of semiconductor structures.
A concave-convex surface is formed on the outer surface of the active column to increase the specific surface area of the gate oxide layer, thereby improving the control ability of the gate.
By increasing the specific surface area of the gate oxide layer, the performance of the semiconductor structure is improved, and the control capability of the gate and the short channel effect are improved.
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Figure CN115707231B_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art
[0002] Dynamic Random Access Memory (DRAM) offers compact size, high integration, low power consumption, and is faster than all other Read-Only Memory (ROM) devices. With the development of the semiconductor industry, optimizing integration has become a primary goal of circuit design. However, as the feature sizes of devices like DRAM continue to shrink, transistors are also shrinking, weakening their gate control capabilities and increasing the short-channel effect, significantly reducing the performance of semiconductor structures. Summary of the Invention
[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.
[0004] The present disclosure provides a method for preparing a semiconductor structure and a semiconductor structure.
[0005] A first aspect of an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising:
[0006] providing a substrate;
[0007] forming a plurality of active pillars on the substrate, wherein the plurality of active pillars are arranged in an array, wherein the outer surface of each active pillar has a concave-convex surface;
[0008] forming a gate oxide layer on the substrate to cover the top surface of the substrate and the sidewalls and top surfaces of the active pillars, wherein a filling region is formed between adjacent active pillars in the same row;
[0009] forming a word line and a first dielectric layer in sequence in the filling area;
[0010] removing a portion of the first dielectric layer and a portion of the gate oxide layer to expose the top surface of the active pillar;
[0011] forming a contact layer on a top surface of the active pillar;
[0012] A capacitor structure is formed on the contact layer.
[0013] According to some embodiments of the present disclosure, along the first direction, the concave-convex surface includes a plurality of annular arc-shaped protrusions connected in sequence.
[0014] According to some embodiments of the present disclosure, after the step of providing a substrate and before the step of forming a plurality of active pillars on the substrate, the preparation method further includes:
[0015] A plurality of bit lines are formed in the substrate. The plurality of bit lines are arranged in the substrate at intervals along a row direction of the active pillars, wherein top surfaces of the bit lines are flush with a top surface of the substrate.
[0016] According to some embodiments of the present disclosure, the step of forming a plurality of bit lines in the substrate includes:
[0017] forming a plurality of first grooves in the substrate and arranged at intervals along a row direction of the active pillars;
[0018] forming an insulating dielectric layer in the first groove, wherein a top surface of the insulating dielectric layer is flush with a top surface of the substrate, wherein an area between adjacent insulating dielectric layers constitutes an active area;
[0019] Ion doping is performed on the active region by using an ion implantation technique to form the bit line.
[0020] According to some embodiments of the present disclosure, the step of forming a plurality of active pillars on the substrate includes:
[0021] forming an etching sacrificial layer and a photoresist layer stacked in sequence on the substrate;
[0022] removing a portion of the photoresist layer and a portion of the etching sacrificial layer, and forming a plurality of second grooves spaced apart from each other in the remaining photoresist layer and the etching sacrificial layer, wherein each second groove exposes a top surface of the bit line;
[0023] An active pillar is formed in the second groove, wherein a top surface of the active pillar is flush with a top surface of the etched sacrificial layer.
[0024] According to some embodiments of the present disclosure, the step of removing a portion of the photoresist layer and a portion of the etched sacrificial layer to form a plurality of second grooves spaced apart, each second groove exposing a top surface of the bit line, includes:
[0025] removing a portion of the photoresist layer, and forming a plurality of third grooves spaced apart from each other in the remaining photoresist layer, wherein each of the third grooves exposes a top surface of the etched sacrificial layer;
[0026] The etching sacrificial layer exposed in the third groove is removed, and the remaining etching sacrificial layer forms the second groove.
[0027] According to some embodiments of the present disclosure, the step of removing the etched sacrificial layer exposed in the third groove to form the second groove includes:
[0028] removing the etched sacrificial layer exposed to a predetermined height in the third groove to form a recess, wherein the recess is in the shape of a semi-elliptical groove;
[0029] forming a barrier layer in the recess;
[0030] removing the barrier layer at the bottom of the recess, and forming a first opening with the remaining barrier layer, wherein the bottom surface of the first opening exposes the etching sacrificial layer;
[0031] removing the etched sacrificial layer exposed at a predetermined height in the first opening to form a second opening, wherein a top surface of the etched sacrificial layer in the second opening is higher than a top surface of the substrate;
[0032] The etching sacrificial layer having a predetermined height in the second opening is repeatedly removed multiple times until the top surface of the bit line is exposed, and the remaining etching sacrificial layer forms a concave-convex inner wall on the inner wall of the second groove.
[0033] According to some embodiments of the present disclosure, the step of forming an active pillar in the second groove includes:
[0034] forming active pillars along the concave-convex inner wall by silicon epitaxial growth;
[0035] The photoresist layer and the etching sacrificial layer that are retained are removed, so that the outer surface of the active pillar forms the concave-convex surface.
[0036] According to some embodiments of the present disclosure, after the step of removing a portion of the first dielectric layer and a portion of the gate oxide layer to expose the top surface of the active pillar and before the step of forming a contact layer on the top surface of the active pillar, the preparation method further includes:
[0037] forming an initial metal layer on the top surface of the retained first dielectric layer and the top surface of the active pillar;
[0038] removing a portion of the initial metal layer and retaining the initial metal layer corresponding to the top surface of the active pillar to form a metal layer;
[0039] The metal layer is subjected to high temperature tempering treatment to form the contact layer.
[0040] According to some embodiments of the present disclosure, the metal layer includes at least one of a cobalt layer, a nickel layer, or a platinum layer;
[0041] The contact layer includes at least one of a cobalt compound, a nickel compound, or a platinum compound.
[0042] A second aspect of the present disclosure provides a semiconductor structure, which is prepared by the above-mentioned semiconductor structure preparation method, and the semiconductor structure includes:
[0043] substrate;
[0044] A plurality of active pillars are arranged in an array on the substrate, wherein the outer surface of each active pillar has a concave-convex surface.
[0045] According to some embodiments of the present disclosure, along the first direction, the concave-convex surface includes a plurality of annular arc-shaped protrusions connected in sequence.
[0046] According to some embodiments of the present disclosure, the annular arc-shaped protrusion includes a protruding portion and a first connecting portion and a second connecting portion arranged on both sides of the protruding portion, the projection area of the protruding portion on the substrate is larger than the projection area of the first connecting portion and the second connecting portion on the substrate, and the first connecting portion of one of the annular arc-shaped protrusions is connected to the second connecting portion of the adjacent annular arc-shaped protrusion.
[0047] According to some embodiments of the present disclosure, a projection of the first connecting portion on the substrate coincides with a projection of the second connecting portion on the substrate.
[0048] According to some embodiments of the present disclosure, the semiconductor structure further includes a plurality of bit lines in the substrate, the plurality of bit lines are arranged at intervals along a row direction of the active pillars, and the top surfaces of the bit lines are connected to the bottom surfaces of the active pillars.
[0049] According to some embodiments of the present disclosure, the semiconductor structure further includes a plurality of word lines spaced apart along a column direction of the active pillars, each word line connecting a plurality of the active pillars in the same row.
[0050] According to some embodiments of the present disclosure, a contact layer is provided on the top surface of the active pillar, and a capacitor structure is connected to the contact layer.
[0051] In the semiconductor structure preparation method and semiconductor structure provided by the embodiments of the present disclosure, a concave-convex surface is formed on the outer layer of the active column, thereby increasing the specific surface area of the gate oxide layer, improving the control capability of the gate, and thus improving the performance of the semiconductor structure.
[0052] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0053] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0054] Figure 1 The figure is a flow chart of a method for preparing a semiconductor structure according to an exemplary embodiment.
[0055] Figure 2 It is a schematic diagram of forming a first groove in a substrate in a method for preparing a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0056] Figure 3 FIG. 1 is a schematic diagram of forming an insulating dielectric layer in a method for preparing a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0057] Figure 4 FIG. 1 is a schematic diagram of forming a bit line in a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0058] Figure 5 FIG. 1 is a schematic diagram of forming an etched sacrificial layer in a method for preparing a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0059] Figure 6 It is a schematic diagram of forming a third groove and a recess in a method for preparing a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0060] Figure 7 FIG. 1 is a schematic diagram of forming a barrier layer in a method for preparing a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0061] Figure 8 1 is a schematic diagram of forming a first opening in a method for preparing a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0062] Figure 9 1 is a schematic diagram of forming a second opening in a method for preparing a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0063] Figure 10 It is a schematic diagram of forming a second groove in a method for preparing a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0064] Figure 11 It is a schematic diagram of forming an active pillar in a method for preparing a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0065] Figure 12FIG. 1 is a schematic diagram of an active pillar in a method for preparing a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0066] Figure 13 FIG. 1 is a schematic diagram of forming a gate oxide layer in a method for preparing a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0067] Figure 14 FIG. 1 is a schematic diagram of forming a word line in a method for preparing a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0068] Figure 15 FIG. 1 is a schematic diagram of forming a first dielectric layer in a method for preparing a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0069] Figure 16 The diagram is a schematic diagram of removing a portion of the gate oxide layer and a portion of the first dielectric layer in a method for preparing a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0070] Figure 17 FIG. 1 is a schematic diagram of forming an initial metal layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0071] Figure 18 FIG. 1 is a schematic diagram of forming a metal layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0072] Figure 19 FIG. 1 is a schematic diagram of forming a contact layer and a capacitor structure in a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0073] Figure 20 FIG. 1 is a schematic diagram of a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0074] Figure 21 The figure is a flow chart of a method for preparing a semiconductor structure according to an exemplary embodiment. Description of the drawings:
[0076] 10. substrate; 20. bit line;
[0077] 30. Insulating dielectric layer; 40. Etching sacrificial layer;
[0078] 50. Photoresist layer; 60. Barrier layer;
[0079] 70. Active pillar; 71. Annular arc-shaped protrusion;
[0080] 80. Gate oxide layer; 90. Word line;
[0081] 100. First dielectric layer; 101. First groove;
[0082] 110. Metal layer; 111. Initial metal layer;
[0083] 120. Contact layer; 130. Capacitor structure;
[0084] 401, second groove; 402, depression;
[0085] 501, third groove; 601, first opening;
[0086] 602, second opening; 701, filling area;
[0087] 711. Raised portion; 712. First connecting portion;
[0088] 713. Second connecting portion. DETAILED DESCRIPTION
[0089] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure. It should be noted that, in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.
[0090] In related technologies, as the feature sizes of devices such as DRAM continue to decrease, the size of transistors is also getting smaller and smaller, their gate control capabilities are weakened, and the short channel effect is becoming more and more obvious, which in turn leads to a significant reduction in the performance of the semiconductor structure.
[0091] In response to the above technical problems, the semiconductor structure preparation method and semiconductor structure provided by the embodiments of the present disclosure increase the specific surface area of the gate oxide layer by forming a concave and convex surface on the outer layer of the active column, thereby improving the control ability of the gate and thus improving the performance of the semiconductor structure.
[0092] In an exemplary embodiment of the present disclosure, a method for preparing a semiconductor structure is provided, such as Figure 1 shown. Figure 1 A flow chart of a method for preparing a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figure 2-Figure 20 The following is a schematic diagram of the various stages of the method for preparing a semiconductor structure. Figure 2-Figure 20 The preparation method of semiconductor structure is introduced.
[0093] This embodiment does not limit the semiconductor structure. The semiconductor structure will be described below using a dynamic random access memory (DRAM) as an example, but this embodiment is not limited thereto. The semiconductor structure in this embodiment may also be other structures.
[0094] like Figure 1 As shown, an embodiment of the present disclosure provides a method for preparing a semiconductor structure, comprising the following steps:
[0095] Step S100: providing a substrate.
[0096] Step S110 : forming a plurality of active pillars on a substrate, wherein the plurality of active pillars are arranged in an array, wherein an outer surface layer of each active pillar has a concave-convex surface.
[0097] Step S120: forming a gate oxide layer on the substrate to cover the top surface of the substrate and the sidewalls and top surfaces of the active pillars, wherein a filling region is formed between adjacent active pillars in the same row.
[0098] Step S130 : sequentially forming word lines and a first dielectric layer in the filling region.
[0099] Step S140: removing a portion of the first dielectric layer and a portion of the gate oxide layer to expose the top surface of the active pillar.
[0100] Step S150 : forming a contact layer on the top surface of the active pillar.
[0101] Step S160: forming a capacitor structure on the contact layer.
[0102] For example, in step S100, Figure 2 As shown, the substrate 10 serves as a support component of the storage device, and is used to support other components disposed thereon. The substrate 10 may be made of a semiconductor material, which may be one or more of silicon, germanium, a silicon-germanium compound, and a silicon-carbon compound.
[0103] In step S110, Figure 5 and Figure 6 As shown, a stacked etching sacrificial layer 40 and a photoresist layer 50 may be sequentially formed on a substrate 10. In some embodiments, the stacked etching sacrificial layer 40 and the photoresist layer 50 may be formed on the substrate 10 by an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process. The etching sacrificial layer 40 may be made of a material such as silicon oxide.
[0104] Reference Figure 6As shown, a portion of the photoresist layer 50 is first removed, and the remaining photoresist layer 50 forms a plurality of spaced third grooves 501, each of which exposes the top surface of the etched sacrificial layer 40. The plurality of third grooves 501 are arranged in an array to facilitate the subsequent formation of active pillars.
[0105] like Figure 10 As shown, after the third groove 501 is formed, the retained photoresist layer 50 is used as a mask to repeatedly remove the etching sacrificial layer 40 exposed in the third groove 501. Each time, the etching sacrificial layer 40 of a predetermined height in the third groove 501 is removed, and the retained etching sacrificial layer 40 forms a second groove 401. Each second groove 401 exposes the top surface of the substrate 10, so that the inner wall of the second groove 401 forms a concave and convex inner wall.
[0106] In some embodiments, Figures 7 to 10 As shown, the formation process of the second groove 401 is as follows:
[0107] The etched sacrificial layer 40 exposed to a predetermined height in the third groove 501 is first removed to form a recess 402 on the top surface of the etched sacrificial layer 40. In some embodiments, the recess 402 has a semi-elliptical shape in a longitudinal section perpendicular to the top surface of the substrate 10.
[0108] A barrier layer 60 is formed in the recess 402. For example, Figure 7 As shown, oxygen gas may be introduced into the third groove 501 to oxidize the etched sacrificial layer 40 on the surface of the recess 402 to form an oxide layer, or a silicon nitride layer may be deposited on the surface of the recess 402. The oxide layer or the silicon nitride layer constitutes the barrier layer 60.
[0109] The barrier layer 60 at the bottom of the recess 402 is removed, and the remaining barrier layer 60 forms a first opening 601, and the bottom surface of the first opening 601 exposes the etching sacrificial layer 40. In some embodiments, the barrier layer 60 at the bottom of the recess 402 can be anisotropically etched using a plasma etching gas containing a chlorofluoride compound to form the first opening 601, and the bottom of the first opening 601 stays on the upper surface of the etching sacrificial layer 40, as shown in FIG. Figure 8 shown.
[0110] The etched sacrificial layer 40 exposed to a predetermined height in the first opening 601 is removed to form a second opening 602. The depths of the first opening 601 and the second opening 602 may be the same or different, and the top surface of the etched sacrificial layer 40 in the second opening 602 is higher than the bottom surface of the substrate 10.
[0111] In some embodiments, as Figure 9As shown, the etching sacrificial layer 40 in the first opening 601 can be etched using a plasma etching gas of a chlorine compound and a bromine compound. The upper surface of the etching sacrificial layer 40 in the first opening 601 is used as the etching starting point, and the sidewalls and bottom of the etching sacrificial layer 40 are anisotropically etched in a direction toward the substrate 10, thereby forming a second opening 602.
[0112] For example, Figure 10 As shown, the process of removing the etched sacrificial layer 40 of a predetermined height in the above embodiment is repeated, wherein it should be noted that each time the etched sacrificial layer 40 of a predetermined height is removed, the recess 402 formed on the top surface of the etched sacrificial layer 40 retained last time is used as a starting point, until the top surface of the substrate 10 is exposed, the retained etched sacrificial layer 40 forms a plurality of second grooves 401 arranged in an array, and the retained etched sacrificial layer 40 forms a concave and convex inner wall on the inside of the second groove 401.
[0113] After repeatedly removing the predetermined height of the etched sacrificial layer 40 in the second opening 602 until the top surface of the substrate 10 is exposed, hydrofluoric acid or phosphoric acid is introduced into the second opening 602 to perform wet etching to remove the barrier layer 60 retained on the surface of the first opening 601 .
[0114] like Figure 11 As shown, an active pillar 70 is formed in the second groove 401. The top surface of the active pillar 70 is flush with the top surface of the etched sacrificial layer 40. In some embodiments, the active pillar 70 can be formed by silicon epitaxial growth along the concave-convex inner wall of the second groove 401. The outer layer of the active pillar 70 has a concave-convex surface along the concave-convex inner wall of the second groove 401. In a projection of the active pillar 70 on a longitudinal section perpendicular to the top surface of the substrate 10, the concave-convex surface includes a plurality of sequentially connected annular arc-shaped protrusions 71 along the height extension direction of the active pillar 70.
[0115] Then, the remaining photoresist layer 50 is removed and the sacrificial layer is etched, so that the outer surface of the active pillar 70 forms a concave-convex surface, as shown in FIG. Figure 12 As shown, by forming a concave-convex surface on the outer layer of the active pillar 70, the specific surface area of the gate oxide layer formed subsequently is increased to improve the gate control capability and short channel control performance of the semiconductor structure, thereby improving the performance of the semiconductor.
[0116] For example, in step S120, Figure 13As shown, a silicon dioxide layer can be formed on the sidewalls and top surfaces of the active pillars 70 and the surface of the substrate 10, wherein the silicon dioxide layer can be formed by a chemical vapor deposition process. Then, a portion of the silicon dioxide layer is removed by wet etching, and finally, the top surfaces and sidewalls of the active pillars 70 are dry oxidized to form a gate oxide layer 80. At the same time, a filling region 701 is formed between adjacent active pillars 70 in the same row.
[0117] For example, in step S130, Figure 14 and Figure 15 As shown, word lines 90 are formed on the surface of gate oxide layer 80, i.e., in filling region 701. Word lines 90 are a metal layer comprising at least one of a tungsten layer, a copper layer, or a titanium nitride layer. The top surface of word lines 90 is formed to be lower than the top surface of active pillars 70.
[0118] A first dielectric layer 100 is formed on the word line 90, wherein the first dielectric layer 100 covers the top surface of the word line 90 and the top surface and sidewalls of the gate oxide layer 80. The material of the first dielectric layer 100 includes silicon dioxide and other materials.
[0119] For example, in step S140, Figure 16 As shown, a portion of the first dielectric layer 100 and a portion of the gate oxide layer 80 are removed by chemical mechanical polishing, and the top surface of the active pillar 70 is exposed.
[0120] For example, in step S150, Figure 17 and Figure 18 As shown, an initial metal layer 111 is formed on the top surface of the retained first dielectric layer 100 and the top surface of the active pillar 70 by using a physical vapor deposition process.
[0121] A portion of the initial metal layer 111 is removed, and the initial metal layer 111 corresponding to the top surface of the active pillar 70 is retained to form a metal layer 110 .
[0122] like Figure 19 As shown, the metal layer 110 is subjected to high temperature annealing to form a metal silicide, namely the contact layer 120. The metal layer 110 includes at least one of a cobalt layer, a nickel layer or a platinum layer. The contact layer 120 includes at least one of a cobalt compound, a nickel compound or a platinum compound.
[0123] For example, in step S160, Figure 19 As shown, a capacitor structure 130 is formed on the contact layer 120 , wherein the capacitor structure may include a columnar capacitor structure, a cup capacitor structure, or a trench capacitor structure.
[0124] In the method for preparing the semiconductor structure provided by the embodiment of the present disclosure, a concave-convex surface is formed on the outer layer of the active pillar to increase the specific surface area of the gate oxide layer, thereby improving the control capability of the gate and further improving the performance of the semiconductor structure.
[0125] like Figure 21 As shown, an embodiment of the present disclosure provides a method for preparing a semiconductor structure, comprising the following steps:
[0126] Step S200: providing a substrate.
[0127] Step S210: forming a plurality of bit lines in a substrate.
[0128] Step S220: forming a plurality of active pillars on the substrate, wherein the plurality of active pillars are arranged in an array, wherein the outer surface of each active pillar has a concave-convex surface.
[0129] Step S230: forming a gate oxide layer on the substrate to cover the top surface of the substrate and the sidewalls and top surfaces of the active pillars, wherein a filling region is formed between adjacent active pillars in the same row.
[0130] Step S240: forming a word line and a first dielectric layer in sequence in the filling region.
[0131] Step S250: removing a portion of the first dielectric layer and a portion of the gate oxide layer to expose the top surface of the active pillar.
[0132] Step S260: forming a contact layer on the top surface of the active pillar.
[0133] Step S270: forming a capacitor structure on the contact layer.
[0134] For example, in step S210, Figures 2 to 4 As shown, a mask layer may be formed on the substrate 10 by a deposition process, and then the mask layer may be patterned to form a plurality of mask openings arranged at intervals along the row direction of the active pillars 70 on the mask layer.
[0135] A first photoresist layer can be formed on the mask layer, and a mask pattern can be formed on the first photoresist layer by exposure or development etching. The first photoresist layer with the mask pattern is used as a mask to remove part of the mask layer to form a plurality of mask openings arranged at intervals.
[0136] In this embodiment, the mask pattern can be transferred to the mask layer, and then the mask layer is used as a mask to etch the substrate 10, thereby improving the accuracy of pattern transfer and the performance of the semiconductor structure.
[0137] After the mask openings are formed, an etching solution or an etching gas is used to remove the substrate 10 exposed in each mask opening, so as to form a plurality of first grooves 101 on the substrate 10 .
[0138] After forming the plurality of first grooves 101 , the mask layer remaining on the top surface of the substrate 10 is removed.
[0139] An insulating dielectric layer 30 is then formed in the first recess 101 by physical vapor deposition, chemical vapor deposition, spin coating, or a combination thereof. The top surface of the insulating dielectric layer 30 is flush with the top surface of the substrate 10. The insulating dielectric layer 30 may be made of, for example, silicon oxide, silicon oxynitride, or other suitable insulating materials (e.g., organic polymer compounds), or a combination thereof. The region between adjacent insulating dielectric layers 30 constitutes the active region.
[0140] Then, dopant ions may be implanted into the active region by ion implantation technology. The dopant ions include nitrogen ions, phosphorus ions, boron ions, germanium ions, and the like, thereby forming the bit line 20 .
[0141] In this embodiment, the active pillar 70 formed subsequently is formed on the top surface of the bit line 20 , that is, the bottom of the active pillar 70 is connected to the top of the bit line 20 .
[0142] It should be noted that step S200 in this embodiment is the same as step S100 in the above embodiment, and steps S220 to S270 in this embodiment are the same as steps S110 to S160 in the above embodiment, which will not be elaborated herein.
[0143] In the method for preparing the semiconductor structure provided by the embodiment of the present disclosure, a concave-convex surface is formed on the outer layer of the active column to form a gate oxide layer with a large specific surface area, thereby improving the control capability of the gate and thereby improving the performance of the semiconductor structure.
[0144] like Figure 20 As shown, the embodiment of the present disclosure further provides a semiconductor structure. The semiconductor structure includes a substrate 10 and a plurality of active pillars 70, wherein the plurality of active pillars 70 are arranged in an array on the substrate 10, wherein the outer surface of each active pillar 70 has a concave-convex surface, referring to Figure 20 As shown, along the first direction Figure 20 In the Y direction shown in FIG, the concave-convex surface includes a plurality of annular arc-shaped protrusions 71 connected in sequence.
[0145] In some embodiments, the annular arc-shaped protrusion 71 includes a protruding portion 711 and a first connecting portion 712 and a second connecting portion 713 provided on both sides of the protruding portion 711. The projected area of the protruding portion 711 on the substrate 10 is larger than the projected areas of the first connecting portion 712 and the second connecting portion 713 on the substrate 10. The first connecting portion 712 of one annular arc-shaped protrusion 71 is connected to the second connecting portion 713 of its adjacent annular arc-shaped protrusion 71. The projection of the first connecting portion 712 on the substrate 10 coincides with the projection of the second connecting portion 713 on the substrate 10. By sequentially connecting multiple annular arc-shaped protrusions 71, the specific surface area of the outer surface of the active pillar 70 is effectively increased, thereby increasing the specific surface area of the gate oxide layer 80 formed subsequently, thereby improving the control capability of the gate of the semiconductor structure, and further improving the performance of the semiconductor structure.
[0146] In some embodiments, the semiconductor structure further includes a plurality of bit lines 20 in the substrate 10, and the plurality of bit lines 20 are arranged at intervals along the row direction of the active pillars 70, that is, Figure 20 The X direction is shown in FIG. , wherein the top surface of the bit line 20 is connected to the bottom surface of the active pillar 70 .
[0147] It should be noted that, in this embodiment, the row direction of the active pillars 70 can be Figure 20 The first direction can be the X direction shown in Figure 20 Y direction shown in .
[0148] In some embodiments, the semiconductor structure further includes a plurality of word lines 90 spaced apart along the columns of the active pillars 70, each word line 90 connecting multiple active pillars 70 in the same row. A gate oxide layer 80 is disposed between the word lines 90 and the active pillars 70, and an insulating dielectric layer 30 is disposed between the gate oxide layer 80 and the substrate 10.
[0149] In some embodiments, a contact layer 120 is disposed on the top surface of the active pillar 70 , and a capacitor structure 130 is connected to the contact layer 120 .
[0150] In the semiconductor structure provided by the embodiment of the present disclosure, the outer layer of the active column has a concave-convex surface to increase the specific surface area of the gate oxide layer formed subsequently, thereby improving the gate control capability and short channel control performance of the semiconductor structure, thereby improving the performance of the semiconductor.
[0151] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.
[0152] In the description of this specification, reference to terms such as "one embodiment", "some embodiments", "illustrative embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.
[0153] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in any one or more embodiments or examples.
[0154] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.
Claims
1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a plurality of active pillars on the substrate, wherein the plurality of active pillars are arranged in an array, wherein the outer surface of each active pillar has a concave-convex surface; forming a gate oxide layer on the substrate to cover the top surface of the substrate and the sidewalls and top surfaces of the active pillars, wherein a filling region is formed between adjacent active pillars in the same row; forming a word line and a first dielectric layer in sequence in the filling area; removing a portion of the first dielectric layer and a portion of the gate oxide layer to expose the top surface of the active pillar; forming a contact layer on a top surface of the active pillar; forming a capacitor structure on the contact layer; Along a first direction, the concave-convex surface includes a plurality of annular arc-shaped protrusions connected in sequence; the first direction is a direction perpendicular to the substrate.
2. The method for preparing a semiconductor structure according to claim 1, wherein: After the step of providing a substrate and before the step of forming a plurality of active pillars on the substrate, the preparation method further includes: A plurality of bit lines are formed in the substrate. The plurality of bit lines are arranged in the substrate at intervals along a row direction of the active pillars, wherein top surfaces of the bit lines are flush with a top surface of the substrate.
3. The method for preparing a semiconductor structure according to claim 2, wherein: The step of forming a plurality of bit lines in the substrate includes: forming a plurality of first grooves in the substrate and arranged at intervals along a row direction of the active pillars; forming an insulating dielectric layer in the first groove, wherein a top surface of the insulating dielectric layer is flush with a top surface of the substrate, wherein an area between adjacent insulating dielectric layers constitutes an active area; Ion doping is performed on the active region by using an ion implantation technique to form the bit line.
4. The method for preparing a semiconductor structure according to claim 3, wherein: The step of forming a plurality of active pillars on the substrate includes: forming an etching sacrificial layer and a photoresist layer stacked in sequence on the substrate; removing a portion of the photoresist layer and a portion of the etching sacrificial layer, and forming a plurality of second grooves spaced apart from each other in the remaining photoresist layer and the etching sacrificial layer, wherein each second groove exposes a top surface of the bit line; An active pillar is formed in the second groove, wherein a top surface of the active pillar is flush with a top surface of the etched sacrificial layer.
5. The method for preparing a semiconductor structure according to claim 4, wherein: The step of removing a portion of the photoresist layer and a portion of the etched sacrificial layer to form a plurality of second grooves spaced apart, each second groove exposing a top surface of the bit line, comprises: removing a portion of the photoresist layer, and forming a plurality of third grooves spaced apart from each other in the remaining photoresist layer, wherein each of the third grooves exposes a top surface of the etched sacrificial layer; The etching sacrificial layer exposed in the third groove is removed, and the remaining etching sacrificial layer forms the second groove.
6. The method for preparing a semiconductor structure according to claim 5, wherein: The step of removing the etching sacrificial layer exposed in the third groove to form the second groove includes: removing the etched sacrificial layer exposed to a predetermined height in the third groove to form a recess, wherein the recess is in the shape of a semi-elliptical groove; forming a barrier layer in the recess; removing the barrier layer at the bottom of the recess, and forming a first opening in the remaining barrier layer, wherein the bottom surface of the first opening exposes the etching sacrificial layer; removing the etched sacrificial layer exposed at a predetermined height in the first opening to form a second opening, wherein a top surface of the etched sacrificial layer in the second opening is higher than a top surface of the substrate; The etching sacrificial layer having a predetermined height in the second opening is repeatedly removed multiple times until the top surface of the bit line is exposed, and the remaining etching sacrificial layer forms a concave-convex inner wall on the inner wall of the second groove.
7. The method for preparing a semiconductor structure according to claim 6, wherein: The step of forming an active pillar in the second groove includes: forming active pillars along the concave-convex inner wall by silicon epitaxial growth; The photoresist layer and the etching sacrificial layer that are retained are removed, so that the outer surface of the active pillar forms the concave-convex surface.
8. The method for preparing a semiconductor structure according to claim 1, wherein: After the step of removing a portion of the first dielectric layer and a portion of the gate oxide layer to expose the top surface of the active pillar and before the step of forming a contact layer on the top surface of the active pillar, the preparation method further includes: forming an initial metal layer on the top surface of the retained first dielectric layer and the top surface of the active pillar; removing a portion of the initial metal layer and retaining the initial metal layer corresponding to the top surface of the active pillar to form a metal layer; The metal layer is subjected to high temperature tempering treatment to form the contact layer.
9. The method for preparing a semiconductor structure according to claim 8, wherein: The metal layer includes at least one of a cobalt layer, a nickel layer or a platinum layer; The contact layer includes at least one of a cobalt compound, a nickel compound, or a platinum compound.
10. A semiconductor structure, characterized in that The method is obtained by the preparation method according to any one of claims 1 to 9, which comprises: substrate; A plurality of active pillars, wherein the plurality of active pillars are arranged in an array on the substrate, wherein the outer surface of each active pillar has a concave-convex surface; Along a first direction, the concave-convex surface includes a plurality of annular arc-shaped protrusions connected in sequence, and the first direction is a direction perpendicular to the substrate.
11. The semiconductor structure according to claim 10, wherein: The annular arc-shaped protrusion includes a protruding portion and a first connecting portion and a second connecting portion arranged on both sides of the protruding portion. The projection area of the protruding portion on the substrate is larger than the projection area of the first connecting portion and the second connecting portion on the substrate. The first connecting portion of one of the annular arc-shaped protrusions is connected to the second connecting portion of the adjacent annular arc-shaped protrusion.
12. The semiconductor structure according to claim 11, wherein: A projection of the first connecting portion on the substrate coincides with a projection of the second connecting portion on the substrate.
13. The semiconductor structure according to claim 10, wherein: The semiconductor structure further includes a plurality of bit lines in the substrate, the plurality of bit lines are arranged at intervals along a row direction of the active pillars, and the top surfaces of the bit lines are connected to the bottom surfaces of the active pillars.
14. The semiconductor structure according to claim 10, wherein: The semiconductor structure further includes a plurality of word lines spaced apart along a column direction of the active pillars, and each word line connects a plurality of the active pillars in the same row.
15. The semiconductor structure according to any one of claims 10 to 14, characterized in that: A contact layer is provided on the top surface of the active column, and a capacitor structure is connected to the contact layer.
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