Defect detection in memory based on active monitoring of read operations

Abstract

Embodiments of the present application relate to defect detection in memory based on active monitoring of read operations. A first error rate is obtained based on a first read operation performed on a memory device. Individual data units of the memory device that satisfy a first threshold criterion associated with defect candidates are determined. A defect verification operation is performed on the individual data units to obtain a second error rate. The individual data units that satisfy a second threshold criterion associated with defects are determined.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to defect detection in memory based on active monitoring of read operations. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, the host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] According to an aspect of this application, a system is provided. The system may include: a memory device; and a processing device. The processing device is operatively coupled to the memory device to perform operations including: obtaining a first error rate associated with individual data cells of the memory device based on a first read operation performed on the memory device; determining that the first error rate satisfies a first threshold criterion associated with a defect candidate; in response to determining that the first error rate associated with the individual data cell satisfies the first threshold criterion, performing a defect verification operation on the individual data cell to obtain a second error rate; determining that the second error rate satisfies a second threshold criterion associated with a defect; and in response to determining that the second error rate satisfies the second threshold criterion, marking the individual data cell as defective.

[0004] According to another aspect of this application, a method is provided. The method may include: obtaining a first error rate associated with individual data cells of the memory device based on a first read operation performed on a memory device; determining that the first error rate satisfies a first threshold criterion associated with a defect candidate; in response to determining that the first error rate associated with the individual data cell satisfies the first threshold criterion, performing a defect verification operation on the individual data cell to obtain a second error rate; determining that the second error rate satisfies a second threshold criterion associated with a defect; and in response to determining that the second error rate satisfies the second threshold criterion, marking the individual data cell as defective.

[0005] According to another aspect of this application, a non-transitory computer-readable storage medium including instructions is provided. When executed by a processing device, the instructions cause the processing device to perform operations including: performing a read operation to read data from individual data cells of a memory device; determining whether the individual data cell of the memory device is a defect candidate based on a first error rate associated with the read operation; performing a defect verification operation on the individual data cell in response to determining that the individual data cell is a defect candidate; and determining whether the individual data cell is defective based on a second error rate associated with the defect verification operation. Attached Figure Description

[0006] This disclosure will become more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are merely for explanation and understanding.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This is a flowchart of an example method for actively monitoring potential defects in a memory device according to some embodiments of the present disclosure.

[0009] Figure 3 This is a flowchart of an example method for defect verification in a memory device according to some embodiments of the present invention.

[0010] Figure 4 This is a flowchart of another example method for proactively monitoring potential defects in memory devices.

[0011] Figure 5 This is a flowchart of another example method for proactively monitoring potential defects in memory devices.

[0012] Figure 6 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0013] This disclosure relates to defect detection in memory based on active monitoring of read operations. The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0014] The memory subsystem may include high-density non-volatile memory devices where it is desirable to retain data when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. Memory devices at the memory subsystem may have specific properties that pose challenges during the operation of the memory subsystem. For example, some non-volatile memory devices may have limited endurance. For instance, some memory devices may be written to, read from, or erased a limited number of times before they begin to physically degrade or wear out and eventually fail.

[0015] Conventional memory subsystems detect whether a read failure has occurred on a data cell of a memory device. A data cell refers to a specific number of memory units in the memory device, such as pages or blocks. In some embodiments, the memory subsystem declares a data cell defective once a read failure is detected. In some examples, read failures are attributed to intrinsic and / or extrinsic factors. Extrinsic factors are factors that cause transient failures during a read operation, such as time, temperature, read interference, and / or write interference. Intrinsic factors are physical degradation or wear of the data cell caused by the read and write operations performed on it. Conventional memory subsystems typically declare a data cell defective only after it has suffered a read failure, resulting in data loss. Once a conventional memory subsystem marks a data cell as defective, it retires the defective data cell to prevent further data loss. A defective data cell is a data cell in the memory device that cannot retain data or has already experienced data loss. Therefore, conventional memory subsystems cannot detect defects in data cells in advance.

[0016] A specific problem with current approaches to conventional memory subsystems is the inability to distinguish between data cells marked as defective due to intrinsic factors and those marked as defective due to extrinsic factors. Therefore, in conventional memory subsystems, the memory subsystem controller frequently misidentifies data cells as defective, thus impairing system performance. This misidentification occurs when a read failure is caused by an extrinsic factor rather than an intrinsic one, and is subsequently marked as defective. Since read failures caused by such extrinsic factors are transient, and the underlying data cells remain functional and will be usable in the future, it is undesirable to mark such data cells as defective. Therefore, conventional memory subsystem controllers cannot accurately identify potential defects in data cells and may unnecessarily mark otherwise good data cells as defective.

[0017] This disclosure addresses the aforementioned and other defects by enabling the memory subsystem controller to proactively monitor read operations to identify data cells (e.g., defect candidates) before a read failure occurs in a potentially defective data cell. A potentially defective data cell is one that is undergoing a higher level of wear and is therefore tending towards failure. The memory subsystem controller performs memory access operations (e.g., read operations) on the data cells to retrieve data. Therefore, the memory subsystem controller determines the error rate of the read operations. The error rate corresponds to the total number of errors occurring during a read operation (i.e., the total number of bit errors in the read data, or a percentage / fraction of the total number of bits experiencing bit errors in the read data). In some embodiments, the memory subsystem controller may use a directional failure bit count (e.g., directional bit error), defined as the number of faulty bits in a given direction (e.g., bits written as logic 0 but read as logic 1, or bits written as logic 1 but read as logic 0). In some embodiments, it may be assumed that the number of logic 0s and logic 1s is balanced across the set of data cells, and the directional error rate may be largely equivalent to the directional failure bit count. The memory subsystem controller can determine whether a data cell is a defect candidate based on whether the error rate of the current read operation meets defect candidate criteria (e.g., meets or exceeds a threshold defect candidate value). Depending on the embodiment, the threshold defect candidate value (e.g., error rate 12 or directional error rate 8) can be predefined or tuned according to the behavior of the memory device.

[0018] In response to determining that the error rate of the current read operation meets the defect candidate criteria (e.g., error rate >= 12 or directed error rate >= 8), the memory subsystem controller performs a defect verification operation on the data cell. Otherwise, the memory subsystem controller determines that the data cell is not a defect candidate. While performing the defect verification operation on the data cell, the memory subsystem controller performs a rewrite operation on the data cell (e.g., rewriting the data read from the cell back to the data cell). After the data cell has been rewritten, the memory subsystem controller waits for a predetermined time period (e.g., 1 ms) and performs another read operation (i.e., a second read) on the rewritten data cell. The predetermined time period refers to the time between when a write operation is performed on the data cell and when a second read operation is performed on the data cell to reduce and / or eliminate read failures attributed to external factors.

[0019] The memory subsystem controller can determine whether a data cell is defective based on whether the error rate of the rewritten data cell meets a defect criterion (e.g., meets or exceeds a threshold defect value). Depending on the embodiment, the threshold defect value (e.g., an error rate of 6 or a directed error rate of 4) may be predefined or tuned according to a defect verification operation. In response to determining that the error rate of the rewritten data cell meets the defect criterion (e.g., an error rate >= 6 or a directed error rate >= 4), the memory subsystem controller marks the data cell as defective. Since the predetermined time period (e.g., 1 ms) between rewriting and reading the data cell is typically much shorter than the time period between the initial write and first read of the data cell, in some embodiments, the defect candidate criterion may be greater than the defect criterion to account for a reduction in the error rate due to external factors. If the error rate of the rewritten data cell does not meet the defect criterion, then the memory subsystem controller determines that the data cell is not defective.

[0020] Depending on the embodiments described, the memory subsystem controller may determine whether to place a data unit on a defect monitoring list in response to determining that the error rate of the rewritten data unit meets defect monitoring criteria and that the data unit is not defective (e.g., exceeding a threshold defect monitoring value but less than a threshold defect value). Depending on the embodiments, the threshold defect monitoring value (e.g., error rate 2 or directional error rate 1) may be predefined and / or tuned according to defect verification operations. In some embodiments, the threshold defect monitoring value may be a range (e.g., an error rate between 2 and 5 or a directional error rate between 1 and 3). In response to determining that the error rate of the rewritten data unit meets defect monitoring criteria, the memory subsystem controller adds the data unit to the defect monitoring list. The defect monitoring list contains a set of data units that meet defect candidate criteria but do not meet defect criteria and can therefore be pre-monitored to avoid data loss. In some embodiments, periodic defect verification may be performed on the data units on the defect monitoring list.

[0021] The advantages of this disclosure include, but are not limited to, early detection of potentially defective data units to prevent future data loss. By actively monitoring read operations, the memory subsystem controller identifies data units as defect candidates. Therefore, data units as defect candidates are detected before a read failure. Subsequently, the memory subsystem controller performs a defect verification operation on the defect candidates. Thus, the memory subsystem advantageously distinguishes between data units that are defect candidates due to external factors and those that are defect candidates due to internal factors. Therefore, the defect verification operation avoids over-detection of defects in data units attributable to external factors. This process improves the performance of the memory subsystem and maintains the available capacity for storing host data.

[0022] Figure 1This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0023] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash memory drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0024] The computing system 100 may be, for example, a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, drone, train, car or other means of transport), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment or networked commercial device), or a computing device that includes memory and processing devices.

[0025] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0026] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110 (for example) to write data to and read data from memory subsystem 110.

[0027] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect (PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Double Data Rate (DDR) memory buses, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM slot interfaces supporting Double Data Rate (DDR)), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple individual communication connections, and / or combinations of communication connections.

[0028] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (such as memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0029] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-situ write memory, such as a three-dimensional crosspoint (“3D crosspoint”) memory device, which is a crosspoint array of non-volatile memory cells. The crosspoint array of non-volatile memory cells can perform bit storage based on changes in volume resistance in conjunction with a stackable cross-grid data access array. Furthermore, in contrast to many flash-based memories, crosspoint non-volatile memories can perform in-situ write operations, where the non-volatile memory cells can be programmed without previously erasing them. NAND flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0030] Each of the memory devices 130 may include one or more arrays of memory cells. For example, one type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include SLC portions and MLC portions, TLC portions, QLC portions, or PLC portions of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0031] Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND-type flash memories (e.g., 2D NAND, 3D NAND) have been described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0032] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0033] The memory subsystem controller 115 may include processing means configured to execute instructions stored in local memory 119, and may include one or more processors (e.g., processor 117). In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines (including handling communication between the memory subsystem 110 and the host system 120) for controlling the operation of the memory subsystem 110.

[0034] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although already... Figure 1 The instance memory subsystem 110 is described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0035] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations, such as wear leveling, scrap item collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical block addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130, and also translate responses associated with the memory device 130 into information for the host system 120.

[0036] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0037] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0038] Memory subsystem 110 includes a defect detection component 113 that actively detects potentially defective data units in memory devices 130, 140 during operation of memory subsystem 110. In some embodiments, memory subsystem controller 115 includes at least a portion of defect detection component 113. For example, memory subsystem controller 115 may include processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, defect detection component 113 is part of host system 110, an application, or an operating system. In other embodiments, local media controller 135 includes at least a portion of defect detection component 113 and is configured to perform the functionality described herein.

[0039] Defect detection component 113 facilitates defect detection operations at data units (e.g., blocks, pages, etc.) in memory devices 130, 140. Defect detection component 113 obtains the error rate associated with read operations performed on the data unit. Defect detection component 113 determines whether a data unit is a defect candidate based on the error rate satisfying defect candidate criteria. In response to determining that a data unit is a defect candidate, defect detection component 113 performs a defect verification operation on the data unit. Defect detection component 113 obtains the error rate associated with the defect verification operation performed on the data unit. Defect detection component 113 determines whether a data unit is defective based on the error rate associated with the defect verification operation satisfying defect criteria. In response to determining that a data unit is defective, defect detection component 113 may mark the data unit as defective to prevent the data unit from being used to store host data in the future. As previously described, a defective data unit refers to a data unit in the memory device that cannot retain data or has experienced data loss. Further details regarding the operation of defect detection component 113 are described below.

[0040] Figure 2This is a flowchart of an example method 200 for determining whether a data cell of a memory device is defective, according to some embodiments of the present disclosure. Method 200 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 200 is performed by… Figure 1 The defect detection component 113 performs the operation. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0041] In operation 202, the processing logic obtains an error rate (e.g., a first error rate) based on a first read operation performed on a data cell of the memory device. As previously described, the error rate corresponds to the total number of errors or orientation bit errors that occur during the first read operation.

[0042] In operation 204, the processing logic determines whether the defect candidate criterion is met. As previously described, if the first error rate obtained in operation 202 meets or exceeds the defect candidate threshold (e.g., the first threshold), then the defect candidate criterion (e.g., the first threshold criterion) is met. In response to determining that the defect candidate criterion is met, the processing logic continues to operation 206.

[0043] In operation 206, the processing logic performs a defect verification operation on individual data units to obtain a second error rate. As previously described, while performing the defect verification operation on individual data units, the processing logic performs a rewrite operation on the individual data units (e.g., defect candidates). In response to rewriting the individual data units, the processing logic performs a second read operation on the individual data units after a predetermined time period (e.g., 1 ms). Therefore, the processing logic returns a second error rate (e.g., a second error rate) based on the second read operation on the individual data units.

[0044] In operation 208, the processing logic determines whether a defect criterion (e.g., a second defect criterion) is met. As previously described, if the second error rate obtained in operation 206 meets or exceeds a defect threshold (e.g., a second threshold), then the defect criterion is met. In response to determining that a defect candidate criterion is met, the processing logic continues to operation 210.

[0045] In operation 210, the processing logic marks individual data units as defective. As previously described, in response to marking an individual data unit as defective, the processing logic may remove the individual data unit from further use, thereby preventing data loss on the defective data unit.

[0046] Figure 3 This is a flowchart of an example method 300 for performing defect verification operations on individual units, for example, according to operation 206 of method 200 or operation 406 of method 400. Method 300 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, special-purpose logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 300 is performed by… Figure 1 The defect detection component 113 performs the operation. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0047] In operation 302, the processing logic performs a write operation to rewrite the data of individual data cells in the memory device that satisfy a first threshold criterion. Depending on the embodiment, an error correction code operation is performed on the individual data cells that are defect candidates. As previously described, an individual data cell is considered a defect candidate because the first error rate associated with the first read operation satisfies the defect candidate criterion. Therefore, the data in the individual data cell contains errors that need to be corrected before the data is rewritten to the individual data cell.

[0048] In operation 304, the processing logic obtains a predetermined time period associated with the time period during which transient failures are filtered out. Depending on the embodiment, the predetermined time period may be defined or modified based on external factors. As previously described, external factors such as time, temperature, read interference, and / or write interference can cause transient failures during a read operation. By obtaining the predetermined time period, transient errors can be reduced, and time can be eliminated as an external factor. Furthermore, by defining or modifying the predetermined time period, other external factors such as temperature, read interference, and / or write interference can be made negligible by reducing the amount of time spent by external factors causing transient errors during a read operation.

[0049] In operation 306, the processing logic waits for a predetermined period of time. As previously described, after a write operation, the processing logic waits for a predetermined period of time before performing a read operation on an individual data unit.

[0050] In operation 308, the processing logic performs a second read operation on individual cells after a predetermined time period.

[0051] In operation 310, the processing logic obtains an error rate associated with an individual data cell of the memory device based on the second read operation performed on the memory device. As previously described, for example, the error rate corresponds to the total number of errors that occurred during the second read operation (i.e., the total number of bit errors in the read data, or the percentage / fraction of the total number of bits in the read data that experienced bit errors).

[0052] Figure 4 This is a flowchart of an example method 400 for determining whether a data cell of a memory device is defective, according to some embodiments of the present disclosure. Method 400 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1 The defect detection component 113 performs the operation. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0053] In operation 402, the processing logic performs a read operation to read data from individual data cells of the memory device.

[0054] In operation 404, the processing logic determines whether an individual data cell of the memory device is a defect candidate based on a first error rate associated with the read operation. As previously described, the first error rate corresponds to the total number of errors or orientation bit errors that occur during the read operation. If the first error rate associated with the first read operation meets the defect candidate criterion, then the individual data cell is a defect candidate. If the first error rate is greater than or equal to a defect candidate threshold, then the defect candidate criterion is met. In response to determining that the defect candidate criterion is met, the processing logic proceeds to operation 406.

[0055] In operation 406, the processing logic performs defect verification operations on individual data units. As previously stated... Figure 3The description states that, in response to performing a defect verification operation, the processing logic performs a rewrite operation on individual data units identified as defect candidates. In response to rewriting the data of the individual data units, the processing logic performs a second read operation on the individual data units after a predetermined time period (e.g., 1 ms). In response to the second read operation, the processing logic obtains a second error rate associated with the second read operation on the individual data units and continues to operation 408.

[0056] In operation 408, the processing logic determines whether an individual data cell is defective based on a second error rate associated with the defect verification operation. As previously described, the second error rate corresponds to the total number of errors or orientation bit errors that occur during the read operation. If the second error rate associated with the second read operation meets the defect verification criterion associated with the defect, then the individual data cell is defective. If the second error rate is greater than or equal to a threshold defect value, then the defect verification criterion is met. In response to determining that the defect verification criterion is not met, the processing logic determines that the individual data cell is not defective. In response to determining that the defect verification criterion is met, the processing logic determines that the individual data cell is defective.

[0057] Figure 5 This is a flowchart of an example method 500 for determining whether a data cell of a memory device is defective or whether an individual data cell is placed on a monitoring list, according to some embodiments of this disclosure. Method 500 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figure 1 The defect detection component 113 performs the operation. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0058] In operation 502, the processing logic obtains an error rate (e.g., a first error rate) based on a first read operation performed on a data cell of the memory device. As previously described, the error rate corresponds to the total number of errors or orientation bit errors that occur during the first read operation.

[0059] In operation 504, the processing logic determines whether the defect candidate criterion is met. As previously described, if the first error rate obtained in operation 502 meets or exceeds the defect candidate threshold, then the defect candidate criterion is met. In response to determining that the defect candidate criterion is not met, the processing logic proceeds to operation 512. In response to determining that the defect candidate criterion is met, the processing logic proceeds to operation 506.

[0060] In operation 506, the processing logic performs a defect verification operation on individual data units to obtain a second error rate. As previously described, the processing logic may use the error rate associated with the read operation of the defect verification operation as the second error rate.

[0061] In operation 508, the processing logic determines whether the defect criteria are met. As previously described, if the second error rate obtained in operation 506 meets or exceeds the defect threshold, then the defect criteria are met. In response to determining that the defect criteria are not met, the processing logic proceeds to operation 510. In response to determining that the defect candidate criteria are met, the processing logic proceeds to operation 516.

[0062] In operation 510, the processing logic determines whether a defect monitoring criterion is met. As previously described, if the second error rate obtained in operation 506 is within a defect monitoring threshold, then the defect monitoring criterion is met. Depending on the embodiment, if the second error rate falls within a range of the defect monitoring threshold (e.g., an error rate equal to or greater than 6), which is less than the defect threshold (e.g., an error rate between 2 and 5), then the defect monitoring criterion is met. In response to determining that the defect monitoring criterion is not met, the processing logic continues to operation 512. In operation 512, the processing logic determines that the individual data unit is not defective. In response to determining that the candidate defect monitoring criterion is met, the processing logic continues to operation 514.

[0063] In operation 514, the processing logic adds individual data units to a defect monitoring list. Depending on the embodiment, in response to adding individual data units to the defect monitoring list, the processing logic may periodically perform defect verification on the individual data units to proactively monitor for defects in the individual data units. In some embodiments, based on the individual data units included in the monitoring list, the processing logic may modify a defect threshold to be more sensitive to defect detection. Individual data units may be removed from the defect monitoring list by the processing logic based on a second error rate associated with the second read operation that falls outside the range of the defect monitoring threshold.

[0064] In operation 516, the processing logic marks individual data units as defective. As previously described, in response to marking an individual data unit as defective, the processing logic may remove the individual data unit from further use, thereby preventing data loss on the defective data unit.

[0065] Figure 6An example machine of computer system 600 is described, within which a set of instructions is executed to cause the machine to perform any or more of the methodologies discussed herein. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110, or may be used to perform controller operations (e.g., execute an operating system to perform operations corresponding to...). Figure 1 (Operation of the defect detection component 113). In an alternative embodiment, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer-to-peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0066] The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, while a single machine is described, the term "machine" should also be considered to include any collection of machines that individually or collectively execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0067] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.) and a data storage system 618, which communicate with each other via a bus 630.

[0068] Processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or multiple processors implementing combinations of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communication via network 620.

[0069] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which one or more sets of instructions 626 or software embodying any or more of the methodologies or functions described herein are stored. The instructions 626 may also reside wholly or at least partially in main memory 604 and / or processing device 602 during execution by computer system 600, which also constitute machine-readable storage media. The machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to... Figure 1 The memory subsystem 110.

[0070] In one embodiment, instruction 626 includes instructions for implementing a defect detection component (e.g., Figure 1 The defect detection component 113) contains functional instructions. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include (but is not limited to) solid-state memory, optical media, and magnetic media.

[0071] Certain portions of the foregoing detailed description have been presented based on algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Here, an algorithm is generally considered as a self-consistent sequence of operations that leads to a desired result. These operations are those that require physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient, and sometimes, for customary use, these signals are referred to in principle as bits, values, elements, symbols, characters, items, numbers, or the like.

[0072] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure may relate to the operation and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) numbers in the registers and memories of the computer system into physical quantities similarly represented as those in the computer system's memory or registers or other such information storage systems.

[0073] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specially constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0074] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used in conjunction with the programs taught herein, or it may prove convenient to construct more specialized devices to implement the methods. Structures for various such systems will appear as described below. Furthermore, this disclosure is not described with reference to any particular programming language. It will be understood that various programming languages ​​can be used to implement the teachings of this disclosure as described herein.

[0075] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine (e.g., computer) readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0076] In the foregoing description, embodiments thereof have been described with reference to specific examples of the present disclosure. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure set forth in the appended claims. Therefore, the description and drawings should be regarded in an illustrative rather than restrictive sense.

Claims

1. A memory subsystem comprising: Memory devices; and A processing device operatively coupled to the memory device to perform operations including: A first error rate associated with an individual data cell of the memory device is obtained based on a first read operation performed on the memory device; Determine that the first error rate satisfies a first threshold criterion associated with defect candidates; In response to determining that the first error rate associated with the individual data unit satisfies the first threshold criterion, a defect verification operation is performed on the individual data unit to obtain a second error rate; The second error rate is determined to satisfy a second threshold criterion associated with defects; and In response to determining that the second error rate meets the second threshold criterion, the individual data unit is marked as defective. Performing the defect verification operation on the individual data unit includes: Rewrite the data into the individual data units; Perform a second read operation on the individual data units after a predetermined time period; and Return the second error rate.

2. The memory subsystem of claim 1, wherein if the first error rate is greater than or equal to the first threshold, then the first threshold criterion is satisfied.

3. The memory subsystem of claim 2, wherein if the second error rate is greater than or equal to the second threshold, then the second threshold criterion is satisfied.

4. The memory subsystem of claim 3, wherein the first threshold is configured to be greater than the second threshold based on a predetermined time period.

5. The memory subsystem of claim 4, wherein the predetermined time period is configured to eliminate external factors acting on the memory device.

6. The memory subsystem of claim 1, wherein the first error rate and the second error rate correspond to a plurality of orientation bit errors.

7. The memory subsystem of claim 1, wherein marking the individual data unit as defective includes removing the individual data unit to prevent further use.

8. A method for operating a memory subsystem, comprising: A first error rate associated with an individual data cell of the memory device is obtained based on a first read operation performed on the memory device; Determine that the first error rate satisfies a first threshold criterion associated with defect candidates; In response to determining that the first error rate associated with the individual data unit satisfies the first threshold criterion, a defect verification operation is performed on the individual data unit to obtain a second error rate; The second error rate is determined to satisfy a second threshold criterion associated with defects; and In response to determining that the second error rate meets the second threshold criterion, the individual data unit is marked as defective. Performing the defect verification operation on the individual data unit includes: Rewrite the data into the individual data units; Perform a second read operation on the individual data units after a predetermined time period; and Return the second error rate.

9. The method of claim 8, wherein if the first error rate is greater than or equal to the first threshold, then the first threshold criterion is satisfied.

10. The method of claim 9, wherein if the second error rate is greater than or equal to the second threshold, then the second threshold criterion is satisfied.

11. The method of claim 10, wherein the first threshold is configured to be greater than the second threshold based on a predetermined time period.

12. The method of claim 11, wherein the predetermined time period is configured to eliminate external factors acting on the memory device.

13. The method of claim 8, wherein the first error rate and the second error rate correspond to a plurality of orientation bit errors.

14. The method of claim 8, wherein marking the individual data unit as defective includes removing the individual data unit to prevent further use.

15. A non-transitory computer-readable storage medium comprising, when executed by a processing means, instructions that cause the processing means to perform operations including: Perform a read operation to read data from an individual data cell of the memory device; Whether the individual data cell of the memory device is a defect candidate is determined based on a first error rate associated with the read operation; In response to determining that the individual data unit is a defect candidate, a defect verification operation is performed on the individual data unit; and Whether the individual data unit is defective is determined based on a second error rate associated with the defect verification operation. Performing the defect verification operation on the individual data unit includes: Rewrite the data of the individual data units; Perform a second read operation on the individual data units after a predetermined time period; and Return the second error rate.

16. The non-transitory computer-readable storage medium of claim 15, wherein determining whether the individual data cell of the memory device is a defect candidate comprises: Determine whether the first error rate associated with the read operation meets the defect candidate criteria.

17. The non-transitory computer-readable storage medium of claim 15, wherein determining whether the individual data unit is defective comprises: Determine whether the second error rate associated with the second read operation meets the defect criteria.

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