A 1394B bus node that can be disconnected from the network online

Abstract

The present invention belongs to the technical field of the security and reliability design of embedded computer systems, and particularly relates to a 1394B bus node capable of online network withdrawal, including a physical layer protocol chip, a physical layer port communicating with the protocol layer chip, and a bypass physical layer port communicating with the physical layer chip; the present invention maximally suppresses abnormal events in the physical layer of the 1394B bus node from causing the entire network to fall into a "reset storm" and unable to work properly, so that the 1394B bus can be safely applied in systems with high security and high reliability requirements.

Description

Technical Field

[0001] The invention belongs to the technical field of security and reliability design of embedded computer systems, and in particular relates to a 1394B bus node capable of being disconnected from the network online. Background Art

[0002] The 1394B serial bus has a notable feature: it can form a physical ring path connection. After identifying a ring path, it automatically disconnects the loop. If other nodes experience network disconnection during real-time operation, the physical layer can reset and restart, re-establishing the network topology using the original ring connection segments to ensure communication integrity among all nodes, thus providing single-fault fault tolerance. While 1394B has single-fault fault tolerance, it still has shortcomings for embedded applications with higher reliability and security requirements. Specifically, it lacks the ability to suppress abnormal physical layer resets. Even the AS5643 protocol, optimized for the 1394B bus protocol, does not effectively address this issue. When the physical layer protocol chip or port experiences abnormally frequent disconnections, it can cause a network-wide "reset storm" of continuous reset operations, preventing nodes from effectively utilizing their single-fault fault tolerance capabilities. Summary of the Invention

[0003] In view of this, the present invention proposes a 1394B bus node that can be disconnected from the network online, which can maximally suppress abnormal events at the physical layer of the 1394B bus node that cause the entire network to fall into a "reset storm" and become unable to work normally, so that the 1394B bus can be safely used in systems with high security and high reliability requirements.

[0004] In order to achieve the above technical objectives, the specific technical solutions adopted by the present invention are:

[0005] A 1394B bus node capable of online network exit comprises a physical layer protocol chip, a physical layer port communicating with the protocol layer chip, and a bypass physical layer port communicating with the physical layer chip;

[0006] The physical layer port is connected to the 1394B bus and is used to convert the bus signal of the 1394B bus into an electrical signal that can be recognized by the physical layer protocol chip, and is also used to convert the electrical signal into a bus signal;

[0007] The physical layer protocol chip is used to perform protocol decoding, data identification and data forwarding on the electrical signal;

[0008] The bus node also includes power supply control logic, port monitoring logic, processor circuit, power supply switch and isolation switch;

[0009] The processor circuit communicates with the 1394B bus and determines whether the 1394B bus node is normal according to the information of the 1394B bus;

[0010] The port monitoring logic communicates with the physical layer port, determines whether the physical layer port is normal based on information of the physical layer port, and outputs an indication signal if it is abnormal; the isolation switch disconnects the information transmission between the physical layer port and the 1394B bus based on the indication signal;

[0011] The power supply control logic communicates with the port monitoring logic, and controls the power supply switch to cut off the power supply to the physical layer protocol chip when all the physical layer ports in the 1394B bus node are abnormal;

[0012] The power supply control logic communicates with the processor circuit and controls the power supply switch to cut off the power supply to the physical layer protocol chip when the 1394B bus node is abnormal.

[0013] Furthermore, the physical layer protocol chip is a 1394B bus node physical layer protocol chip D1;

[0014] The port monitoring logic includes port 0 monitoring logic D2-1 and port 1 monitoring logic D2-2;

[0015] The power supply control logic is the power supply control logic D2-3;

[0016] The physical layer port is a 1394B bus node physical layer port interface N1;

[0017] The bypass physical layer port is a 1394B bus node physical layer port interface N2;

[0018] The isolation switch includes an isolation driver N3, an isolation driver N4, an isolation driver N5, an isolation driver N6 and an isolation driver N7;

[0019] The isolating switch includes switch K1, switch K2, switch K3 and switch K4;

[0020] The power supply switch is switch K5.

[0021] Furthermore, the 1394B bus node physical layer protocol chip D1, port 0 monitoring logic D2-1, port 1 monitoring logic D2-2, power supply control logic D2-3, 1394B bus node physical layer port interface N1, 1394B bus node physical layer port interface N2, isolation driver N3, isolation driver N4, isolation driver N5, isolation driver N6, isolation driver N7, switch K1, switch K2, switch K3, switch K4, switch K5 and processor circuit are connected as follows:

[0022] The physical layer protocol chip D1 of the 1394B bus node, the port monitoring logic D2-1, is connected to the pins TPA+, TPA-, TPB+, and TPB- of the 1394B bus node physical layer port interface N1;

[0023] The physical layer protocol chip of the 1394B bus node, the port monitoring logic D2-1, is connected to the pins TPA+, TPA-, TPB+, and TPB- of the 1394B bus node physical layer port interface N2;

[0024] The pin 1 of the switch K1 is defined as connected to 0_TPA+, the pin 2 of K1 is connected to the port_TPA+ pin of the 1394B bus node physical layer port interface N1, and the port_TPA+ pin is associated with its TPA+ pin inside the 1394B bus node physical layer port interface N1; the pin 4 of the switch K1 is defined as connected to 0_TPA-, the pin 5 of K1 is connected to the port 0_TPA- pin of the 1394B bus node physical layer port interface N1, and the port 0_TPA- pin is associated with its TPA- pin inside the 1394B bus node physical layer port interface N1; the pins 3 and 6 of K1 are left vacant;

[0025] The pin 1 of the switch K2 is defined as connected to 0_TPB+, the pin 2 of K2 is connected to the port_TPB+ pin of the 1394B bus node physical layer port interface N1, and the port_TPB+ pin is associated with its TPB+ pin inside the 1394B bus node physical layer port interface N1; the pin 4 of the switch K2 is defined as connected to _TPB-, the pin 5 of K2 is connected to the port 0_TPB- pin of the 1394B bus node physical layer port interface N1, and the port_TPB- pin is associated with its TPB- pin inside the 1394B bus node physical layer port interface N1; the pins 3 and 6 of K2 are left vacant;

[0026] The pin 1 of the switch K3 is defined as connected to 0_TPA+, the pin 2 of K3 is connected to the port_TPA+ pin of the 1394B bus node physical layer port interface N2, and the port_TPA+ pin is associated with its TPA+ pin inside the 1394B bus node physical layer port interface N2; the pin 4 of the switch K3 is defined as connected to 1_TPA-, the pin 5 of K3 is connected to the port_TPA- pin of the 1394B bus node physical layer port interface N2, and the port_TPA- pin is associated with its TPA- pin inside the 1394B bus node physical layer port interface N2; the pins 3 and 6 of K3 are left vacant;

[0027] The pin 1 of switch K4 is defined to connect to 1_TPB+. The pin 2 of K4 connects to the pin 1_TPB+ of port 1_TPB+ of the physical layer port interface N2 of the 1394B bus node. The port 1_TPB+ pin is associated with its TPB+ pin inside the physical layer port interface N2 of the 1394B bus node. The pin 4 of switch K4 is defined to connect to 1_TPB-. The pin 5 of K4 connects to the pin 1_TPB- of port 1_TPB- of the physical layer port interface N2 of the 1394B bus node. The port 1_TPB- pin is associated with its TPB- pin inside the physical layer port 1 interface of the 1394B bus node. The pins 3 and 6 of K4 are vacant.

[0028] The 0-port monitoring logic D2-1 outputs a 0-port valid signal and, at the same time, connects to isolation driver N3, connects to isolation driver N4, and connects to power supply control logic D2-3.

[0029] The 0-port monitoring logic D2-1 outputs a 0-port valid signal and, at the same time, connects to isolation driver N3, connects to isolation driver N4, and connects to power supply control logic D2-3.

[0030] The 1-port monitoring logic D2-2 outputs a 1-port valid signal and, at the same time, connects to isolation driver N5, connects to isolation driver N6, and connects to power supply control logic D2-3.

[0031] In the 0-port monitoring logic, the output is invalid if any of the following conditions is met: the software instruction from the bus requires invalidation, the determination message is invalid.

[0032] In the 1-port monitoring logic, the output is invalid if any of the following conditions is met: the software instruction from the bus requires invalidation, the determination message is invalid.

[0033] In the power supply control logic, the output of allowing power supply is invalid if any of the following conditions is met: the software instruction from the bus does not allow power supply, all port valid signals are invalid.

[0034] The allowing power supply signal output by the power supply control logic is output to connect to the pin 4 of switch K5 after passing through isolation driver N7. The power supply is connected to the normally open contact pin 2 of switch K5. The pin 3 of K5 is vacant. The pin 1 of K5 connects to the power supply pin of the physical layer protocol chip D1 of the 1394B bus node.

[0035] When the allowing power supply signal is in the valid state, the pin 1 of K5 is connected to the normally open contact pin 2. When the allowing power supply signal is in the invalid state, the pin 1 of K5 is connected to the normally closed contact pin 3.

[0036] The bus signals led out by the processor circuit are connected to the 0-port monitoring logic D2-1, the 1-port monitoring logic D2-2, and the power supply control logic D2-3, for reading the internal state and outputting software control instructions.

[0037] The receiving 0 port of the isolation driver N3 receives the connection signal and connects to pin 7 of K1; the sending 0 port of the isolation driver N4 sends the connection signal and connects to pin 7 of K1; the receiving 1 port of the isolation driver N5 receives the connection signal and connects to pin 7 of K1; the sending 1 port of the isolation driver N6 sends the connection signal and connects to pin 7 of K1;

[0038] Further, when the receiving 0 port receives the connection signal indicating the effective state, inside the switch K1, pin 1 is connected to the internal normally open contact pin 2, otherwise it is connected to the internal normally closed contact pin 3; inside the switch K1, pin 4 is connected to the internal normally open contact pin 5, otherwise it is connected to the internal normally closed contact pin 6;

[0039] Further, when the sending 0 port sends the connection signal indicating the effective state, inside the switch K2, pin 1 is connected to the internal normally open contact pin 2, otherwise it is connected to the internal normally closed contact pin 3; inside the switch K2, pin 4 is connected to the internal normally open contact pin 5, otherwise it is connected to the internal normally closed contact pin 6;

[0040] Further, when the receiving 1 port receives the connection signal indicating the effective state, inside the switch K3, pin 1 is connected to the internal normally open contact pin 2, otherwise it is connected to the internal normally closed contact pin 3; inside the switch K3, pin 4 is connected to the internal normally open contact pin 5, otherwise it is connected to the internal normally closed contact pin 6;

[0041] Further, when the sending 1 port sends the connection signal indicating the effective state, inside the switch K4, pin 1 is connected to the internal normally open contact pin 2, otherwise it is connected to the internal normally closed contact pin 3; inside the switch K4, pin 4 is connected to the internal normally open contact pin 5, otherwise it is connected to the internal normally closed contact pin 6. Brief Description of the Drawings

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0043] Figure 1 It is the principle structure diagram of a 1394B bus node that can be online retired in the specific embodiment of the present invention. Detailed Embodiment

[0044] The embodiments of the present disclosure will be described in detail below with reference to the drawings.

[0045] The following describes the embodiments of the present disclosure through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts belong to the scope of protection of the present disclosure.

[0046] It should be noted that the following describes various aspects of the embodiments within the scope of the appended claims. It should be obvious that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is illustrative only. Based on the present disclosure, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement a device and / or practice a method. Additionally, this device and / or method can be implemented using other structures and / or functionality in addition to one or more of the aspects described herein.

[0047] It should also be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present disclosure schematically. The diagrams only show the components related to the present disclosure and are not drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in its actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0048] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0049] In an embodiment of the present invention, a 1394B bus node capable of online network disconnection is proposed, including a physical layer protocol chip, a physical layer port communicating with the protocol layer chip, and a bypass physical layer port communicating with the physical layer chip;

[0050] The physical layer port is connected to the 1394B bus, and is used to convert the bus signals of the 1394B bus into electrical signals that can be recognized by the physical layer protocol chip, and is also used to convert electrical signals into bus signals;

[0051] The physical layer protocol chip is used to perform protocol decoding, data identification, and data forwarding on electrical signals;

[0052] The bus node also includes a power supply control logic, a port monitoring logic, a processor circuit, a power supply switch, and an isolation switch;

[0053] The processor circuit communicates with the 1394B bus, and determines whether the 1394B bus node is normal according to the information of the 1394B bus;

[0054] The port monitoring logic communicates with the physical layer port, and determines whether the physical layer port is normal based on the information of the physical layer port. If it is not normal, an indication signal is output; The isolation switch disconnects the information transmission between the physical layer port and the 1394B bus based on the indication signal;

[0055] The power supply control logic communicates with the port monitoring logic, and controls the power supply switch to disconnect the power supply of the physical layer protocol chip when all the physical layer ports in the 1394B bus node are not normal;

[0056] The power supply control logic communicates with the processor circuit, and controls the power supply switch to disconnect the power supply of the physical layer protocol chip when the 1394B bus node is not normal.

[0057] In this embodiment, as Figure 1 shown, the physical layer protocol chip is the physical layer protocol chip D1 of the 1394B bus node;

[0058] The port monitoring logic includes a port 0 monitoring logic D2-1 and a port 1 monitoring logic D2-2;

[0059] The power supply control logic is the power supply control logic D2-3;

[0060] The physical layer port is the physical layer port interface N1 of the 1394B bus node;

[0061] The bypass physical layer port is the physical layer port interface N2 of the 1394B bus node;

[0062] The isolation switch includes isolation drivers N3, N4, N5, N6, and N7;

[0063] The isolation switch includes switches K1, K2, K3, and K4;

[0064] The power supply switch is switch K5.

[0065] In this embodiment, as Figure 1As shown, the connection method of the 1394B bus node physical layer protocol chip D1, 0-port monitoring logic D2-1, 1-port monitoring logic D2-2, power supply control logic D2-3, 1394B bus node physical layer port interface N1, 1394B bus node physical layer port interface N2, isolation drivers N3, N4, N5, N6, N7, switches K1, K2, K3, K4, K5, and the processor circuit is as follows:

[0066] The 1394B bus node physical layer protocol chip D1 and 0-port monitoring logic D2-1 are connected to the pins TPA+, TPA-, TPB+, and TPB- of the 1394B bus node physical layer port interface N1.

[0067] The 1394B bus node physical layer protocol chip and 1-port monitoring logic D2-1 are connected to the pins TPA+, TPA-, TPB+, and TPB- of the 1394B bus node physical layer port interface N2.

[0068] The pin 1 of switch K1 is defined as connected to 0_TPA+, the pin 2 of K1 is connected to the port_TPA+ pin of the 1394B bus node physical layer port interface N1, and the port_TPA+ pin is associated with its TPA+ pin inside the 1394B bus node physical layer port interface N1; the pin 4 of switch K1 is defined as connected to 0_TPA-, the pin 5 of K1 is connected to the port 0_TPA- pin of the 1394B bus node physical layer port interface N1, and the port 0_TPA- pin is associated with its TPA- pin inside the 1394B bus node physical layer port interface N1; pins 3 and 6 of K1 are left vacant.

[0069] The pin 1 of switch K2 is defined as connected to 0_TPB+, the pin 2 of K2 is connected to the port_TPB+ pin of the 1394B bus node physical layer port interface N1, and the port_TPB+ pin is associated with its TPB+ pin inside the 1394B bus node physical layer port interface N1; the pin 4 of switch K2 is defined as connected to _TPB-, the pin 5 of K2 is connected to the port 0_TPB- pin of the 1394B bus node physical layer port interface N1, and the port_TPB- pin is associated with its TPB- pin inside the 1394B bus node physical layer port interface N1; pins 3 and 6 of K2 are left vacant.

[0070] Pin 1 of switch K3 is named and defined as connection 0_TPA+, and pin 2 of K3 is connected to the port_TPA+ pin of the 1394B bus node physical layer port interface N2. The port_TPA+ pin is associated with its TPA+ pin inside the 1394B bus node physical layer port interface N2. Pin 4 of switch K3 is named and defined as connection 1_TPA-, and pin 5 of K3 is connected to the port_TPA- pin of the 1394B bus node physical layer port interface N2. The port_TPA- pin is associated with its TPA- pin inside the 1394B bus node physical layer port interface N2. Pins 3 and 6 of K3 are vacant.

[0071] Pin 1 of switch K4 is defined as connection 1_TPB+, and pin 2 of K4 is connected to the port 1_TPB+ pin of the 1394B bus node physical layer port interface N2. The port 1_TPB+ pin is associated with its TPB+ pin inside the 1394B bus node physical layer port interface N2. Pin 4 of switch K4 is defined as connection 1_TPB-, and pin 5 of K4 is connected to the port 1_TPB- pin of the 1394B bus node physical layer port interface N2. The port 1_TPB- pin is associated with its TPB- pin inside the 1394B bus node physical layer port 1 interface. Pins 3 and 6 of K4 are vacant.

[0072] The 0-port monitoring logic D2-1 outputs a valid signal for the 0-port. At the same time, it is connected to the isolation driver N3, the isolation driver N4, and the power supply control logic D2-3.

[0073] The 0-port monitoring logic D2-1 outputs a valid signal for the 0-port. At the same time, it is connected to the isolation driver N3, the isolation driver N4, and the power supply control logic D2-3.

[0074] The port monitoring logic D2-2 outputs a port valid signal and is connected to the isolation driver N5, the isolation driver N6, and the power supply control logic D2-3.

[0075] In the port 0 monitoring logic, the output is invalid if one of the following conditions is met: the software instruction request from the bus is invalid, the judgment message is invalid;

[0076] 1. In the port monitoring logic, the output is invalid if one of the following conditions is met: the software instruction request from the bus is invalid, or the judgment message is invalid;

[0077] In the power supply control logic, if one of the following conditions is met, the output power enable is invalid: the software instruction from the bus does not allow power supply, and all port valid signals are invalid;

[0078] The power supply enabling signal output by the power supply control logic is output after being isolated and driven by N7 and is connected to pin 4 of switch K5. The power supply is connected to the normally open contact pin 2 of switch K5. Pin 3 of K5 is left unconnected. Pin 1 of K5 is connected to the power supply pin of the 1394B bus node physical layer protocol chip D1.

[0079] When the power supply enabling signal is in the valid state, pin 1 of K5 is connected to the normally open contact pin 2. When the power supply enabling signal is in the invalid state, pin 1 of K5 is connected to the normally closed contact pin 3.

[0080] The bus signals led out by the processor circuit are connected to the 0-port monitoring logic D2-1, the 1-port monitoring logic D2-2, and the power supply control logic D2-3, for reading the internal status and outputting software control instructions.

[0081] The isolation driver N3 outputs the 0-port receive connection signal and is connected to pin 7 of K1; the isolation driver N4 outputs the 0-port transmit connection signal and is connected to pin 7 of K1; the isolation driver N5 outputs the 1-port receive connection signal and is connected to pin 7 of K1; the isolation driver N6 outputs the 1-port transmit connection signal and is connected to pin 7 of K1.

[0082] In this embodiment, when there is a valid 0-port receive connection signal, inside switch K1, pin 1 is connected to the internal normally open contact pin 2, otherwise it is connected to the internal normally closed contact pin 3; inside switch K1, pin 4 is connected to the internal normally open contact pin 5, otherwise it is connected to the internal normally closed contact pin 6.

[0083] In this embodiment, when there is a valid 0-port transmit connection signal, inside switch K2, pin 1 is connected to the internal normally open contact pin 2, otherwise it is connected to the internal normally closed contact pin 3; inside switch K2, pin 4 is connected to the internal normally open contact pin 5, otherwise it is connected to the internal normally closed contact pin 6.

[0084] In this embodiment, when there is a valid 1-port receive connection signal, inside switch K3, pin 1 is connected to the internal normally open contact pin 2, otherwise it is connected to the internal normally closed contact pin 3; inside switch K3, pin 4 is connected to the internal normally open contact pin 5, otherwise it is connected to the internal normally closed contact pin 6.

[0085] In this embodiment, when there is a valid 1-port transmit connection signal, inside switch K4, pin 1 is connected to the internal normally open contact pin 2, otherwise it is connected to the internal normally closed contact pin 3; inside switch K4, pin 4 is connected to the internal normally open contact pin 5, otherwise it is connected to the internal normally closed contact pin 6.

[0086] As described above, it is only the specific implementation manner of the present disclosure. However, the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed by the present disclosure should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A 1394B bus node capable of online network withdrawal, characterized in that including a physical layer protocol chip, which is respectively communicatively connected to a physical layer port and a bypass physical layer port. Among them, the physical layer port is connected to the 1394B bus, and is used to convert the bus signals of the 1394B bus into electrical signals recognizable by the physical layer protocol chip, and is also used to convert the electrical signals into bus signals; the physical layer protocol chip is used to perform protocol decoding, data recognition, and data forwarding on the electrical signals; the bus node further includes a power supply control logic, a port monitoring logic, a processor circuit, a power supply switch, and an isolation switch; the processor circuit communicates with the 1394B bus and determines whether the 1394B bus node is normal according to the information of the 1394B bus; the port monitoring logic communicates with the physical layer port, and determines whether the physical layer port is normal based on the information of the physical layer port. If it is not normal, an indication signal is output; the isolation switch disconnects the information transmission between the physical layer port and the 1394B bus based on the indication signal; the power supply control logic communicates with the port monitoring logic, and controls the power supply switch to disconnect the power supply of the physical layer protocol chip when all the physical layer ports in the 1394B bus node are not normal; the power supply control logic communicates with the processor circuit, and controls the power supply switch to disconnect the power supply of the physical layer protocol chip when the 1394B bus node is not normal; the physical layer protocol chip is the 1394B bus node physical layer protocol chip D1; the port monitoring logic includes the 0-port monitoring logic D2-1 and the 1-port monitoring logic D2-2; the power supply control logic is the power supply control logic D2-3; the physical layer port is the 1394B bus node physical layer port interface N1; the bypass physical layer port is the 1394B bus node physical layer port interface N2; the isolation switch includes isolation drivers N3, N4, N5, N6, N7 and switches K1, K2, K3, and K4; the power supply switch is switch K5; the 0-port monitoring logic D2-1 outputs a 0-port valid signal, and at the same time, is connected to the isolation driver N3, the isolation driver N4, and the power supply control logic D2-3; the 1-port monitoring logic D2-2 outputs a 1-port valid signal, and at the same time, is connected to the isolation driver N5, the isolation driver N6, and the power supply control logic D2-3.

2. The 1394B bus node capable of online network disconnection according to claim 1, wherein, The connection manners of the 1394B bus node physical layer protocol chip D1, the 0-port monitoring logic D2-1, the 1-port monitoring logic D2-2, the power supply control logic D2-3, the 1394B bus node physical layer port interface N1, the 1394B bus node physical layer port interface N2, the isolation drivers N3, N4, N5, N6, N7, the switches K1, K2, K3, K4, K5, and the processor circuit are as follows: The physical layer protocol chip of the 1394B bus node, the monitoring logic D2-1 of port 0 is connected to the pins TPA+, TPA-, TPB+ and TPB- of the physical layer port interface N1 of the 1394B bus node; The physical layer protocol chip of the 1394B bus node, the monitoring logic D2-1 of port 1 is connected to the pins TPA+, TPA-, TPB+ and TPB- of the physical layer port interface N2 of the 1394B bus node; The pin 1 name definition of the switch K1 is connected to 0_TPA+, the pin 2 of K1 is connected to the port_TPA+ pin of the physical layer port interface N1 of the 1394B bus node, and the port_TPA+ pin is associated with its TPA+ pin inside the physical layer port interface N1 of the 1394B bus node; the pin 4 name definition of the switch K1 is connected to 0_TPA-, the pin 5 of K1 is connected to the port_TPA- pin of the physical layer port interface N1 of the 1394B bus node, and the port_TPA- pin is associated with its TPA- pin inside the physical layer port interface N1 of the 1394B bus node; the pins 3 and 6 of K1 are vacant; The pin 1 name definition of the switch K2 is connected to 0_TPB+, the pin 2 of K2 is connected to the port_TPB+ pin of the physical layer port interface N1 of the 1394B bus node, and the port_TPB+ pin is associated with its TPB+ pin inside the physical layer port interface N1 of the 1394B bus node; the pin 4 name definition of the switch K2 is connected to _TPB-, the pin 5 of K2 is connected to the port_TPB- pin of the physical layer port interface N1 of the 1394B bus node, and the port_TPB- pin is associated with its TPB- pin inside the physical layer port interface N1 of the 1394B bus node; the pins 3 and 6 of K2 are vacant; The pin 1 name definition of the switch K3 is connected to 1_TPA+, the pin 2 of K3 is connected to the port_TPA+ pin of the physical layer port interface N2 of the 1394B bus node, and the port_TPA+ pin is associated with its TPA+ pin inside the physical layer port interface N2 of the 1394B bus node; the pin 4 name definition of the switch K3 is connected to 1_TPA-, the pin 5 of K3 is connected to the port_TPA- pin of the physical layer port interface N2 of the 1394B bus node, and the port_TPA- pin is associated with its TPA- pin inside the physical layer port interface N2 of the 1394B bus node; the pins 3 and 6 of K3 are vacant; The pin 1 name definition of the switch K4 is connected to 1_TPB+, the pin 2 of K4 is connected to the port 1_TPB+ pin of the physical layer port interface N2 of the 1394B bus node, and the port_TPB+ pin is associated with its TPB+ pin inside the physical layer port interface N2 of the 1394B bus node; the pin 4 name definition of the switch K4 is connected to 1_TPB-, the pin 5 of K4 is connected to the port_TPB- pin of the physical layer port interface N2 of the 1394B bus node, and the port_TPB- pin is associated with its TPB- pin inside the physical layer port 1 interface of the 1394B bus node; the pins 3 and 6 of K4 are vacant; In the 0-port monitoring logic, the output is invalid if any of the following conditions is met: the software instruction from the bus requests invalidation, or the judgment message is invalid; In the 1-port monitoring logic, the output is invalid if any of the following conditions is met: the software instruction from the bus requests invalidation, or the judgment message is invalid; In the power supply control logic, the output of allowing power supply is invalid if any of the following conditions is met: the software instruction from the bus does not allow power supply, or all port valid signals are invalid; The signal of allowing power supply output by the power supply control logic is output and connected to pin 4 of switch K5 after being isolated and driven by N7. The power supply is connected to the normally open contact pin 2 of switch K5. Pin 3 of K5 is left vacant, and pin 1 of K5 is connected to the power supply pin of the 1394B bus node physical layer protocol chip D1. When the signal of allowing power supply is in the valid state, pin 1 of K5 is connected to the normally open contact pin 2. When the signal of allowing power supply is in the invalid state, pin 1 of K5 is connected to the normally closed contact pin 3. The bus signals led out by the processor circuit are connected to the 0-port monitoring logic D2-1, the 1-port monitoring logic D2-2, and the power supply control logic D2-3, for reading the internal state and outputting software control instructions. The isolation driver N3 outputs the 0-port receive connection signal and connects it to pin 7 of K1; the isolation driver N4 outputs the 0-port transmit connection signal and connects it to pin 7 of K2; the isolation driver N5 outputs the 1-port receive connection signal and connects it to pin 7 of K3; the isolation driver N6 outputs the 1-port transmit connection signal and connects it to pin 7 of K4.

3. The 1394B bus node capable of online network disconnection according to claim 2, characterized in that, When there is a valid 0-port receive connection signal, switch K1 internally connects pin 1 to the internal normally open contact pin 2, otherwise to the internal normally closed contact pin 3; switch K1 internally connects pin 4 to the internal normally open contact pin 5, otherwise to the internal normally closed contact pin 6.

4. The 1394B bus node capable of online network withdrawal according to claim 3, wherein When there is a valid 0-port transmit connection signal, switch K2 internally connects pin 1 to the internal normally open contact pin 2, otherwise to the internal normally closed contact pin 3; switch K2 internally connects pin 4 to the internal normally open contact pin 5, otherwise to the internal normally closed contact pin 6.

5. The 1394B bus node capable of online network disconnection according to claim 4, wherein When there is a valid 1-port receive connection signal, switch K3 internally connects pin 1 to the internal normally open contact pin 2, otherwise to the internal normally closed contact pin 3; switch K3 internally connects pin 4 to the internal normally open contact pin 5, otherwise to the internal normally closed contact pin 6.

6. The 1394B bus node capable of online network withdrawal according to claim 5, wherein When there is a valid 1-port transmit connection signal, switch K4 internally connects pin 1 to the internal normally open contact pin 2, otherwise to the internal normally closed contact pin 3; switch K4 internally connects pin 4 to the internal normally open contact pin 5, otherwise to the internal normally closed contact pin 6.

Images