SiC Heterojunction Thyristor with Dual-Wavelength Light Control Function and Preparation Method

Abstract

The present invention discloses a SiC heterogeneous crystallization transistor with dual-wavelength light control function, which is provided with a boss-shaped p + SiC emitter region and p + The NiO emitter region can be turned on under the control of 365nm ultraviolet light and maintain the on state after the 365nm light is removed; + The SiC emitter region, p-type short base region, and i-type Ga2O3 commutation region terminate internal positive feedback under the control of 254nm ultraviolet light and switch to the off state after the 254nm light is removed. The present invention also discloses a method for preparing a SiC heterogeneous crystal thyristor with dual-wavelength light control. This invention solves the existing problems of SiC LTTs, which have led to difficulty in autonomous shutdown, increased operating costs, and reduced electromagnetic interference resistance of the circuit system.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a SiC heterogeneous crystal thyristor with a dual-wavelength light control function. The present invention also relates to a preparation method of the SiC heterogeneous crystal thyristor with a dual-wavelength light control function. Background Art

[0002] SiC light-triggered thyristors (LTTs) boast high blocking voltage, low conduction losses, and strong resistance to electromagnetic interference (EMI). They hold great promise for application in ultra-high voltage direct current (UHVDC) transmission, high-power pulse power supplies, and electromagnetic weapon platforms. Because the internal equivalent pnp and npn transistors couple to form positive feedback when the SiC LTT is on, the LTT maintains its self-on state after the triggering light is removed. However, the inability of SiC LTTs to self-shut off has severely hampered their widespread application. To switch the SiC LTT from the on state to the off state, specialized control circuits are often required to implement voltage commutation or emission current limiting. While specialized control circuits can achieve controlled shutdown of the LTT, they increase its size and complexity, increasing its cost and reducing the circuit system's resistance to EMI. Summary of the Invention

[0003] The purpose of the present invention is to provide a SiC heterogeneous crystalline transistor with dual-wavelength light control function, which solves the problems in the prior art that SiC LTT is difficult to shut down independently, has increased usage costs, and has reduced anti-electromagnetic interference ability of the circuit system.

[0004] Another object of the present invention is to provide a method for preparing a SiC heterogeneous crystal thyristor with dual-wavelength light control function.

[0005] The first technical solution adopted by the present invention is that the SiC heterogeneous crystalline transistor with dual-wavelength light control function includes n - Substrate, n - One side of the substrate is made with n + Buffer layer, p + SiC emitter, anode ohmic contact metal, anode PAD metal, p + The side of the SiC emitter region that contacts the anode ohmic contact metal is a number of evenly distributed bosses, with p-type convex plates set between adjacent bosses. + NiO emitter region, n - A p-type short base region is formed on the other side of the substrate. The p-type short base region is away from the n - Several n + SiC emitter region and i-type Ga2O3 commutation region, n +SiC emitter regions and i-type Ga2O3 commutation regions are distributed alternately, and the adjacent n + A passivation layer is set between the SiC emitter region and the i-type Ga2O3 commutation region. Several dielectric layers are evenly distributed on the side of the i-type Ga2O3 commutation region away from the p-type short base region. The longitudinal section of the passivation layer is T-shaped, and the vertical part of the passivation layer is adjacent to the n-type Ga2O3 commutation region. + The sidewalls of the SiC emitter region and the i-type Ga2O3 commutation region, the horizontal portion of the passivation layer covers part of the n + A cathode ohmic contact metal is provided between the upper surfaces of the SiC emitter region and the i-type Ga2O3 commutation region and the horizontal portion of the passivation layer, and a cathode PAD metal is provided on the upper surface of the cathode ohmic contact metal.

[0006] The first technical solution of the present invention is also characterized in that:

[0007] n - The substrate material is 4H-SiC, the thickness is 100-300 μm, and the donor impurity concentration is 2.0×10 13 cm -3 ~2.0×10 14 cm -3 ;n + The buffer layer thickness is 0.5 μm to 3.0 μm, and the donor impurity concentration is 5.0×10 16 cm -3 ~5.0×10 17 cm -3 .

[0008] p + The thickness of the SiC emitter is 1.0 to 3.0 μm, the width is 3.0 to 9.0 μm, and the acceptor impurity concentration is 5.0×10 18 cm -3 ~5.0×10 19 cm -3 ;p + The NiO emitter region has a thickness of 1.0 to 3.0 μm, a width of 3.0 to 9.0 μm, and an acceptor impurity concentration of 1.0×10 18 cm -3 ~1.0×10 19 cm -3 ;

[0009] The thickness of the p-type short base region is 2.0 to 3.0 μm, and the acceptor impurity concentration is 5.0×10 16 cm -3 ~5.0×10 17 cm -3 ;n + The SiC emitter region has a thickness of 1.0 to 3.0 μm, a width of 15 to 100 μm, and a donor impurity concentration of 1.0×1018 cm -3 ~1.0×10 19 cm -3 The i-type Ga2O3 commutation region has a thickness of 1.0 to 3.0 μm, a width of 15 to 100 μm, and an impurity concentration of 1.0×10 6 cm -3 ~1.0×10 8 cm -3 ;

[0010] The material of the passivation layer is a combination of one or more of SiO2, AlN, and Si3N4, and the overall thickness of the passivation layer is 500nm~2μm; the material of the dielectric layer is a combination of one or more of SiO2, AlN, and Si3N4, and the overall thickness of the dielectric layer is 500nm~2μm, and the width is 1.0μm~10μm; the material of the cathode ohmic contact metal is a combination of one or more of Ti, Ni, Al, Cu, and Au, and the overall thickness of the cathode ohmic contact metal is 200nm~500nm; the material of the anode ohmic contact metal is a combination of one or more of Ti, Ni, W, Al, and Ta, and the overall thickness of the anode ohmic contact metal is 200nm~500nm; the material of the cathode PAD metal is a combination of one or more of Ti, Al, Cu, and Au, and the overall thickness of the cathode PAD metal is 2.0~10μm; the material of the anode PAD metal is a combination of one or more of Ti, Ag, Ni, and Au, and the overall thickness of the anode PAD metal is 1.0~2.0μm.

[0011] The second technical solution adopted by the present invention is a method for preparing a SiC heterogeneous crystalline transistor with dual-wavelength light control function, which is specifically implemented according to the following steps:

[0012] Step 1: Prepare n-type 4H-SiC by physical vapor transport (PVT) - substrate;

[0013] Step 2: Chemical vapor deposition (CVD) - Epitaxially growing the surface of one side of the substrate upward to prepare an n+ buffer layer;

[0014] Step 3: Chemical vapor deposition (CVD) + Buffer layer surface upward epitaxial preparation p + SiC emitter region;

[0015] Step 4: Etch the p by photolithography plus dry etching process + SiC emitter region (3), making p + The surface of the SiC emitter region presents several convex terraces;

[0016] Step 5: Sputtering or CVD method on p + p-type SiC emitter is prepared between the protrusions + NiO emitter region;

[0017] Step 6: Flip the wafer and deposit it on n - The other side of the substrate 1 is epitaxially grown upward to prepare a p-type short base region;

[0018] Step 7: Prepare n-type epitaxial growth on the surface of the p-type short base region 5 by CVD method. + SiC emitter region;

[0019] Step 8: Etch n by photolithography plus dry etching process + SiC emitter region;

[0020] Step 9: CVD method + The i-type Ga2O3 commutation region is epitaxially prepared between the SiC emitter regions and on the surface of the p-type short base region;

[0021] Step 10: Combine CVD method with photolithography and etching method to form a + A passivation layer is formed on the upper surface edge and sidewall of the SiC emitter region and the i-type Ga2O3 commutation region;

[0022] Step 11: fabricating a dielectric layer on the upper surface of the i-type Ga2O3 commutation region by a CVD method combined with photolithography and etching;

[0023] Step 12: Photolithography and vacuum evaporation are used to form a passivation layer between the passivation layers and the n + Cathode ohmic contact metal is made on the surface of the SiC emitter region, between the dielectric layers, and on the surface of the i-type Ga2O3 commutation region;

[0024] Step 13: vacuum evaporation and rapid thermal annealing + SiC emitter region 3 and p + Anode ohmic contact metal is made on the surface of NiO emitter region 4;

[0025] Step 14: forming cathode PAD metal on the passivation layer and the cathode ohmic contact metal surface by vacuum evaporation and etching;

[0026] Step 15: forming an anode PAD metal on the surface of the anode ohmic contact metal by vacuum evaporation;

[0027] The manufacture of SiC heterogeneous thyristors with dual-wavelength light control function is achieved through dotting, scribing and packaging.

[0028] The second technical solution of the present invention is also characterized in that:

[0029] In step 1, the growth temperature of the physical vapor transport (PVT) method is 2100° C. to 2200° C., the reaction pressure is 0.5 Pa to 1.5 Pa, and the argon gas flow rate is 100 sccm to 500 sccm.

[0030] The deposition temperature of the chemical vapor deposition (CVD) method in step 2 is 1500° C. to 1600° C.; the deposition temperature of the chemical vapor deposition (CVD) method in step 3 is 1500° C. to 1600° C.; the pressure range of the sputtering or CVD method in step 5 is 0.8 Pa to 2.0 Pa; the deposition temperature of the chemical vapor deposition (CVD) method in step 6 is 1500° C. to 1600° C.; the deposition temperature of the chemical vapor deposition (CVD) method in step 7 is 1500° C. to 1600° C.; the deposition temperature of the chemical vapor deposition (CVD) method in step 9 is 850° C. to 1100° C.; the deposition temperature of the chemical vapor deposition (CVD) method in steps 10 and 11 is room temperature to 600° C.

[0031] The atmosphere of the dry etching process in step 4 is CF4 and SF6, and the pressure range is 1.0Pa~10Pa; the atmosphere of the dry etching process in step 8 is CF4 and SF6, and the pressure range is 1.0Pa~10Pa.

[0032] The background vacuum pressure of the vacuum evaporation method in steps 12, 13, 14 and 15 is 5×10 -5 Pa~5×10 -4 Pa; the annealing temperature of the rapid thermal annealing in step 13 is 900°C to 1100°C.

[0033] The beneficial effects of the present invention are: 1) by setting the boss-shaped p + SiC emitter region 3 and p + NiO emission region 4, the present invention has a dual-wavelength light control function of the SiC heterogeneous crystal transistor can be turned on under the control of 365nm ultraviolet light, and maintain the on state after the 365nm light is withdrawn; 2) by setting a boss-shaped n + The SiC emitter region 6, the p-type short base region 5, and the i-type Ga2O3 commutation region 7, the SiC heterogeneous crystalline transistor with dual-wavelength light control function of the present invention ends the internal positive feedback under the control of 254nm ultraviolet light, and turns to the off state after the 254nm light is withdrawn. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 1 is a schematic cross-sectional view of a SiC heterogeneous crystal thyristor with dual-wavelength light control function according to embodiment 1 of the present invention;

[0035] Figure 2 is n in Example 1 of the present invention - A schematic cross-sectional structure diagram of substrate 1;

[0036] Figure 3 The invention is the embodiment 1 of the invention to manufacture n + Schematic diagram of the cross-sectional structure of the buffer layer 2;

[0037] Figure 4 The p is manufactured in Example 1 of the present invention + Schematic diagram of the cross-sectional structure of the SiC emitter region 3;

[0038] Figure 5 The etching process of the embodiment 1 of the present invention is + Schematic diagram of the cross-sectional structure of the SiC emitter region 3;

[0039] Figure 6 The p is manufactured in Example 1 of the present invention + Schematic diagram of the cross-sectional structure of the NiO emitter region 4;

[0040] Figure 7 1 is a schematic cross-sectional view of the p-type short base region 5 manufactured in Example 1 of the present invention;

[0041] Figure 8 The invention is the embodiment 1 of the invention to produce n + Schematic diagram of the cross-sectional structure of the SiC emitter region 6;

[0042] Figure 9 is the etching n in Example 1 of the present invention + Schematic diagram of the cross-sectional structure of the SiC emitter region 6;

[0043] Figure 10 Schematic diagram of the cross-sectional structure of the i-type Ga2O3 commutation region 7 manufactured in Example 1 of the present invention;

[0044] Figure 11 Schematic diagram of the cross-sectional structure of the passivation layer 8 and the dielectric layer 9 manufactured in Example 1 of the present invention;

[0045] Figure 12 1 is a schematic cross-sectional view of the cathode ohmic contact metal 10 manufactured in Example 1 of the present invention;

[0046] Figure 13 1 is a schematic cross-sectional view of the anode ohmic contact metal 11 manufactured in Example 1 of the present invention;

[0047] Figure 14 1 is a schematic cross-sectional view of the cathode PAD metal 12 manufactured in Example 1 of the present invention;

[0048] Figure 15 Schematic diagram of the cross-sectional structure of the anode PAD metal 13 manufactured in Example 1 of the present invention;

[0049] Figure 16These are the light-triggered turn-on and turn-off waveforms of a SiC heterojunction thyristor with dual-wavelength light control function in Example 1 of the present invention.

[0050] In the figure, 1.n - Substrate, 2.n + Buffer layer, 3.p + SiC emitter region, 4. + NiO emitter region, 5.p-type short base region, 6.n + SiC emitter region, 7. i-type Ga2O3 commutation region, 8. passivation layer, 9. dielectric layer, 10. cathode ohmic contact metal, 11. anode ohmic contact metal, 12. cathode PAD metal, 13. anode PAD metal. DETAILED DESCRIPTION

[0051] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0052] The SiC heterogeneous crystal transistor with dual wavelength light control function of the present invention has a structure as follows Figure 1 As shown, including n - Substrate 1, n - One side of the substrate 1 is formed with n + Buffer layer 2, p + SiC emitter region 3, anode ohmic contact metal 11, anode PAD metal 13, p + The side of the SiC emitter region 3 that contacts the anode ohmic contact metal 11 is a number of evenly distributed bosses, with p-type convex plates arranged between adjacent bosses. + NiO emitter 4, n - The other side of the substrate 1 is formed with a p-type short base region 5, which is away from the n-type short base region 5. - Several n + SiC emitter region 6 and i-type Ga2O3 commutation region 7, n + SiC emitter regions 6 and i-type Ga2O3 commutation regions 7 are distributed alternately, and the adjacent n + A passivation layer 8 is provided between the SiC emitter region 6 and the i-type Ga2O3 commutation region 7. Several dielectric layers 9 are evenly distributed on the side of the i-type Ga2O3 commutation region 7 away from the p-type short base region 5. The longitudinal section of the passivation layer 8 is T-shaped. The vertical part of the passivation layer 8 is adjacent to the n-type Ga2O3 commutation region 7. + The sidewalls of the SiC emitter region 6 and the i-type Ga2O3 commutation region 7, and the horizontal portion of the passivation layer 8 cover part of the n + A cathode ohmic contact metal 10 is provided between the upper surfaces of the SiC emitter region 6 and the i-type Ga2O3 commutation region 7 and the horizontal portion of the passivation layer 8, and a cathode PAD metal 12 is provided on the upper surface of the cathode ohmic contact metal 10.

[0053] n- The material of substrate 1 is 4H-SiC, the thickness is 100-300 μm, and the donor impurity concentration is 2.0×10 13 cm -3 ~2.0×10 14 cm -3 ;n + The buffer layer 2 has a thickness of 0.5 μm to 3.0 μm and a donor impurity concentration of 5.0×10 16 cm -3 ~5.0×10 17 cm -3 .

[0054] p + The thickness of the SiC emitter region 3 is 1.0 to 3.0 μm, the width of the convex platform is 3.0 to 9.0 μm, and the acceptor impurity concentration is 5.0×10 18 cm -3 ~5.0×10 19 cm -3 ;p + The NiO emitter region 4 has a thickness of 1.0 to 3.0 μm, a width of 3.0 to 9.0 μm, and an acceptor impurity concentration of 1.0×10 18 cm -3 ~1.0×10 19 cm -3 ;

[0055] The thickness of the p-type short base region 5 is 2.0 to 3.0 μm, and the acceptor impurity concentration is 5.0×10 16 cm -3 ~5.0×10 17 cm -3 ;n + The SiC emitter region 6 has a thickness of 1.0 to 3.0 μm, a width of 15 to 100 μm, and a donor impurity concentration of 1.0×10 18 cm -3 ~1.0×10 19 cm -3 The i-type Ga2O3 commutation region 7 has a thickness of 1.0 to 3.0 μm, a width of 15 to 100 μm, and an impurity concentration of 1.0×10 6 cm -3 ~1.0×10 8 cm -3 ;

[0056] The material of the passivation layer 8 is a combination of one or more of SiO2, AlN, and Si3N4, and the overall thickness of the passivation layer 8 is 500nm to 2μm; the material of the dielectric layer 9 is a combination of one or more of SiO2, AlN, and Si3N4, and the overall thickness of the dielectric layer 9 is 500nm to 2μm, and the width is 1.0μm to 10μm; the material of the cathode ohmic contact metal 10 is a combination of one or more of Ti, Ni, Al, Cu, and Au, and the overall thickness of the cathode ohmic contact metal 10 is 200nm to 500nm; The material of the anode ohmic contact metal 11 is a combination of one or more of Ti, Ni, W, Al, and Ta, and the overall thickness of the anode ohmic contact metal 11 is 200nm to 500nm; the material of the cathode PAD metal 12 is a combination of one or more of Ti, Al, Cu, and Au, and the overall thickness of the cathode PAD metal 12 is 2.0 to 10μm; the material of the anode PAD metal 13 is a combination of one or more of Ti, Ag, Ni, and Au, and the overall thickness of the anode PAD metal 13 is 1.0 to 2.0μm.

[0057] The preparation method of the SiC heterogeneous crystal thyristor with dual-wavelength light control function is specifically implemented according to the following steps:

[0058] Step 1: Prepare n-type 4H-SiC by physical vapor transport (PVT) - Substrate 1, such as Figure 2 In step 1, the growth temperature of the physical vapor transport PVT method is 2100°C to 2200°C, the reaction pressure is 0.5Pa to 1.5Pa, and the argon gas flow rate is 100sccm to 500sccm.

[0059] Step 2: Chemical vapor deposition (CVD) - The n+ buffer layer 2 is formed by epitaxial growth on one side of the substrate 1. Figure 3 As shown; the deposition temperature of the chemical vapor deposition CVD method in step 2 is 1500 ℃ ~ 1600 ℃; the deposition temperature of the chemical vapor deposition CVD method in step 3 is 1500 ℃ ~ 1600 ℃;

[0060] Step 3: Chemical vapor deposition (CVD) + Buffer layer 2 surface upward epitaxial preparation p + SiC emitter region 4, such as Figure 4 As shown;

[0061] Step 4: Etch the p by photolithography plus dry etching process + SiC emitter region 3, making p + The surface of the SiC emitter region 3 is formed into several convex platforms, such as Figure 5As shown; the atmosphere of the dry etching process in step 4 is CF4 and SF6, and the pressure range is 1.0Pa~10Pa;

[0062] Step 5: Sputtering or CVD method on p + The p-type SiC emitter is prepared between the protrusions of the SiC emitter region 3. + NiO emitter region 4, such as Figure 6 As shown; the pressure range of the sputtering or CVD method in step 5 is 0.8Pa~2.0Pa;

[0063] Step 6: Flip the wafer and deposit it on n - The other side of the substrate 1 is epitaxially grown upward to prepare a p-type short base region 5, such as Figure 7 As shown; the deposition temperature of the chemical vapor deposition CVD method in step 6 is 1500°C to 1600°C;

[0064] Step 7: Prepare n-type epitaxial growth on the surface of the p-type short base region 5 by CVD method. + SiC emitter region 6, such as Figure 8 As shown; the deposition temperature of the chemical vapor deposition CVD method in step 7 is 1500°C to 1600°C;

[0065] Step 8: Etch n by photolithography plus dry etching process + SiC emitter region 6, such as Figure 9 As shown; the atmosphere of the dry etching process in step 8 is CF4 and SF6, and the pressure range is 1.0Pa~10Pa.

[0066] Step 9: CVD method + The i-type Ga2O3 commutation region 7 is epitaxially prepared between the SiC emitter regions 6 and on the surface of the p-type short base region 5, such as Figure 10 As shown; the deposition temperature of the chemical vapor deposition CVD method in step 9 is 850°C to 1100°C;

[0067] Step 10: Combine CVD method with photolithography and etching method to form a + A passivation layer 8 is formed on the upper surface edge and sidewall of the SiC emitter region 6 and the i-type Ga2O3 commutation region 7;

[0068] Step 11: A dielectric layer 9 is formed on the upper surface of the i-type Ga2O3 commutation region 7 by a CVD method combined with photolithography and etching. Figure 11 As shown; the deposition temperature of the chemical vapor deposition CVD method in step 10 and step 11 is room temperature to 600°C;

[0069] Step 12: Photolithography and vacuum evaporation are used to form a passivation layer between the passivation layer 8 and the n +The cathode ohmic contact metal 10 is made on the surface of the SiC emitter region 6, between the dielectric layers 9, and on the surface of the i-type Ga2O3 commutation region 7, as shown in FIG. Figure 12 As shown;

[0070] Step 13: vacuum evaporation and rapid thermal annealing + SiC emitter region 3 and p + Anode ohmic contact metal 11 is made on the surface of NiO emitter region 4, such as Figure 13 As shown;

[0071] Step 14: Form cathode PAD metal 12 on the surface of passivation layer 8 and cathode ohmic contact metal 10 by vacuum evaporation and etching. Figure 14 As shown;

[0072] Step 15: Make the anode PAD metal 13 on the surface of the anode ohmic contact metal 11 by vacuum evaporation. Figure 15 As shown;

[0073] The background vacuum pressure of the vacuum evaporation method in steps 12, 13, 14 and 15 is 5×10 -5 Pa~5×10 -4 Pa; the annealing temperature of the rapid thermal annealing in step 13 is 900°C to 1100°C.

[0074] The manufacture of SiC heterogeneous thyristors with dual-wavelength light control function is achieved through dotting, scribing and packaging.

[0075] Example 1

[0076] like Figure 1 The structure of the SiC heterogeneous crystal thyristor with dual wavelength light control function is as follows: - Substrate 1, thickness is 100, donor impurity concentration is 2.0×10 14 cm -3 ;

[0077] n - One side of the substrate 1 is made with n + Buffer layer 2, thickness is 0.5 μm, and the donor impurity concentration is 5.0×10 17 cm -3 ;

[0078] n + The surface of the buffer layer 2 is made with a convex platform + SiC emitter region 3, the platform thickness is 1.0 μm, the platform width is 3.0 μm, and the acceptor impurity concentration is 5.0×10 18 cm -3 ;

[0079] Two adjacent convex-shaped p + SiC emitter regions 3 are embedded with p + NiO emitter 4, p + The NiO emitter region 4 has a thickness of 1.0 μm, a width of 3.0 μm, and an acceptor impurity concentration of 1.0×10 18 cm -3 ;

[0080] n - On the other side of the substrate 1, a p-type short base region 5 is formed upward, with a thickness of 2.0 μm and an acceptor impurity concentration of 5.0×10 17 cm -3 ;

[0081] The surface of the p-type short base region 5 is formed with a convex platform n + SiC emitter 6, convex platform n + The SiC emitter region 6 has a thickness of 1.0 μm, a width of 15 μm, and a donor impurity concentration of 1.0×10 18 cm -3 ;

[0082] Two adjacent bosses n + An i-type Ga2O3 commutation region 7 is fabricated on the surface of the p-type short base region 5 between the SiC emitter regions 6. The i-type Ga2O3 commutation region 7 has a thickness of 1.0 μm, a width of 15 μm, and an impurity concentration of 1.0×10 6 cm -3 ;

[0083] n + A passivation layer 8 is formed on the edge and sidewalls of the SiC emitter region 6. The passivation layer 8 is also formed on the edge and sidewalls of the i-type Ga2O3 commutation region 7. The passivation layer 8 is made of SiO2 and has a thickness of 500 nm.

[0084] A convex platform dielectric layer 9 is formed on the upper surface of the i-type Ga2O3 commutation region 7. The material of the convex platform dielectric layer 9 is SiO2, with a thickness of 500nm and a width of 1.0μm.

[0085] Between the passivation layer 8 n + A cathode ohmic contact metal 10 is made on the surface of the SiC emitter region 6 and the surface of the i-type Ga2O3 commutation region 7 between the dielectric layers 9. The cathode ohmic contact metal 10 is made of a combination of Ti, Ni, and Al and has a thickness of 200 nm.

[0086] p + SiC emitter region 3 and p + An anode ohmic contact metal 11 is made on the surface of the NiO emitter region 4. The material of the anode ohmic contact metal 11 is a combination of Ti, Ni, and W, and has a thickness of 200 nm.

[0087] A cathode PAD metal 12 is formed on the surface of the passivation layer 8 and the cathode ohmic contact metal 10. The cathode PAD metal 12 is made of a combination of Ti, Al, and Au, and has a thickness of 2.0 μm.

[0088] An anode PAD metal 13 is formed on the surface of the anode ohmic contact metal 11. The material of the anode PAD metal 13 is a combination of Ti and Ag, and the thickness is 1.0 μm.

[0089] like Figure 2-Figure 15 The present invention provides a method for preparing a SiC heterogeneous crystal thyristor with dual-wavelength light control function, which is implemented according to the following steps:

[0090] The n-SiC material was prepared by PVT method - Substrate 1, growth temperature is 2200℃, reaction pressure is 1.5Pa, argon gas flow rate is 500sccm; Figure 2 Show;

[0091] By CVD method - The n+ buffer layer 2 is formed by epitaxial growth on one side of the substrate 1 at a temperature of 1600°C. Figure 3 As shown;

[0092] The p-type epitaxial layer is prepared by CVD on the surface of n+ buffer layer 2. + SiC emitter region 3, the temperature is 1600℃, such as Figure 4 As shown;

[0093] The p + The SiC emitter region 3 makes p + The SiC emitter region 3 is in the shape of several convex platforms, and the atmosphere is SF6 with a pressure of 1.0 Pa. Figure 5 As shown;

[0094] By sputtering method, the convex p + SiC emitter region 3 is prepared between p + NiO emission region 4, the pressure is 0.8Pa, such as Figure 6 As shown;

[0095] Flip the wafer and deposit it on n - The other side of the substrate 1 is epitaxially grown upward to prepare a p-type short base region 5 at a temperature of 1600°C. Figure 7 As shown;

[0096] The n-type short base region 5 is epitaxially grown upwards by CVD. + SiC emitter region 6, the temperature is 1600℃, such as Figure 8 As shown;

[0097] Etch n by photolithography plus dry etching process + The SiC emitter region 6 makes n + The SiC emitter region 6 is in the shape of a convex platform, and the atmosphere is CF4 with a pressure of 10Pa. Figure 9 As shown;

[0098] By CVD method + Between the SiC emitter regions 6, an i-type Ga2O3 commutation region 7 is epitaxially prepared on the surface of the p-type short base region 5 at a temperature of 850°C. Figure 10 As shown;

[0099] By combining CVD method with photolithography and etching, + A passivation layer 8 is formed on the upper surface edge and sidewall of the SiC emitter region 6 and the i-type Ga2O3 commutation region 7 at a temperature of 200°C;

[0100] The dielectric layer 9 is formed on the upper surface of the i-type Ga2O3 commutation region 7 by a CVD method combined with photolithography and etching at a temperature of 200°C. Figure 11 As shown;

[0101] By photolithography and vacuum evaporation method, n + The cathode ohmic contact metal 10 is made on the surface of the SiC emitter region 6 and the surface of the i-type Ga2O3 commutation region 7 between the dielectric layers 9. The background vacuum pressure is 5×10 -5 Pa, such as Figure 12 As shown;

[0102] By vacuum evaporation and rapid thermal annealing method, the + SiC emitter region 3 and p + The anode ohmic contact metal 11 is made on the surface of the NiO emitter region 4, and the background vacuum pressure is 5×10 -5 Pa, annealing temperature is 900℃, such as Figure 13 As shown;

[0103] The cathode PAD metal 12 is formed on the surface of the passivation layer 8 and the cathode ohmic contact metal 10 by vacuum evaporation and etching. The background vacuum pressure is 5×10 -5 Pa, such as Figure 14 As shown;

[0104] The anode PAD metal 13 is formed on the surface of the anode ohmic contact metal 11 by vacuum evaporation, and the background vacuum pressure is 5×10 -5 Pa, such as Figure 15 As shown;

[0105] The manufacture of SiC heterogeneous thyristors with dual-wavelength light control function is achieved through dotting, scribing and packaging.

[0106] Example 2

[0107] The structure of the SiC heterogeneous crystal thyristor with dual wavelength light control function of the present invention is as follows: - Substrate 1, thickness 300 μm, donor impurity concentration 2.0×10 13 cm -3 ;

[0108] n - One side of the substrate 1 is made with n + Buffer layer 2, thickness is 3.0 μm, and the donor impurity concentration is 5.0×10 16 cm -3 ;

[0109] n + The surface of the buffer layer 2 is made with a convex platform + SiC emitter 3, the platform thickness is 3.0 μm, the platform width is 9.0 μm, and the acceptor impurity concentration is 5.0×10 19 cm -3 ;

[0110] Two adjacent convex-shaped p + SiC emitter regions 3 are embedded with p + NiO emitter 4, p + The NiO emitter region 4 has a thickness of 3.0 μm, a width of 9.0 μm, and an acceptor impurity concentration of 1.0×10 19 cm -3 ;

[0111] n - On the other side of the substrate 1, a p-type short base region 5 is formed upward, with a thickness of 3.0 μm and an acceptor impurity concentration of 5.0×10 16 cm -3 ;

[0112] The surface of the p-type short base region 5 is formed with a convex platform n + SiC emitter 6, convex platform n + The SiC emitter region 6 has a thickness of 3.0 μm, a width of 100 μm, and a donor impurity concentration of 1.0×10 19 cm -3 ;

[0113] Two adjacent bosses n + An i-type Ga2O3 commutation region 7 is fabricated on the surface of the p-type short base region 5 between the SiC emitter regions 6. The i-type Ga2O3 commutation region 7 has a thickness of 3.0 μm, a width of 100 μm, and an impurity concentration of 1.0×10 8 cm -3 ;

[0114] n + A passivation layer 8 is formed on the edge and sidewalls of the SiC emitter region 6. The passivation layer 8 is also formed on the edge and sidewalls of the i-type Ga2O3 commutation region 7. The passivation layer 8 is made of a combination of SiO2, AlN, and Si3N4, with a total thickness of 2 μm.

[0115] A convex platform dielectric layer 9 is formed on the upper surface of the i-type Ga2O3 commutation region 7. The material of the convex platform dielectric layer 9 is a combination of SiO2, AlN, and Si3N4. The overall thickness is 2μm and the width is 10μm.

[0116] Between the passivation layer 8 n + The surface of the SiC emitter region 6 and the surface of the i-type Ga2O3 commutation region 7 between the dielectric layers 9 are made with a cathode ohmic contact metal 10. The material of the cathode ohmic contact metal 10 is a combination of Ti, Ni, Al, Cu, and Au, and the overall thickness is 500nm.

[0117] p + SiC emitter region 3 and p + An anode ohmic contact metal 11 is made on the surface of the NiO emitter region 4. The material of the anode ohmic contact metal 11 is a combination of Ti, Ni, W, Al, and Ta, and the overall thickness is 500nm.

[0118] A cathode PAD metal 12 is formed on the surface of the passivation layer 8 and the cathode ohmic contact metal 10. The material of the cathode PAD metal 12 is a combination of Ti, Al, Cu, and Au, and the overall thickness is 10 μm.

[0119] An anode PAD metal 13 is formed on the surface of the anode ohmic contact metal 11. The material of the anode PAD metal 13 is a combination of Ti, Ag, Ni, and Au, and the overall thickness is 2.0 μm.

[0120] The present invention provides a method for preparing a SiC heterogeneous crystal thyristor with dual-wavelength light control function, which is implemented according to the following steps:

[0121] The n-SiC material was prepared by PVT method - Substrate 1, growth temperature is 2100℃, reaction pressure is 0.5Pa, argon gas flow rate is 100sccm, as shown in Figure 2 Show;

[0122] By CVD method - One side of the substrate 1 is epitaxially prepared with the surface facing upwards + Buffer layer 2, temperature is 1500℃;

[0123] The p-type epitaxial layer is prepared by CVD on the surface of n+ buffer layer 2. + SiC emitter region 3, temperature is 1500℃;

[0124] The p + The SiC emitter region 3 makes p + The SiC emitter region 3 is in the shape of several convex platforms, and the atmosphere is CF4 with a pressure of 1.0 Pa;

[0125] By CVD method, the platform-shaped + SiC emitter region 3 is prepared between p + NiO emission region 4, pressure is 2.0 Pa;

[0126] Flip the wafer;

[0127] By CVD method - The other side of the substrate 1 is epitaxially grown upward to form a p-type short base region 5 at a temperature of 1500° C.

[0128] The n-type short base region 5 is epitaxially grown upwards by CVD. + SiC emitter region 6, temperature is 1500°C;

[0129] Through the photolithography and dry etching process, n + The SiC emitter region 6 is in the shape of a convex platform, and the atmosphere is SF6 with a pressure of 10Pa;

[0130] By CVD method + Between the SiC emitter regions 6, an i-type Ga2O3 commutation region 7 is epitaxially grown on the surface of the p-type short base region 5 at a temperature of 1100°C;

[0131] By combining CVD method with photolithography and etching, + A passivation layer 8 is formed on the upper surface edge and sidewall of the SiC emitter region 6 and the i-type Ga2O3 commutation region 7 at a temperature of 600°C;

[0132] A dielectric layer 9 is formed on the upper surface of the i-type Ga2O3 commutation region 7 by a CVD method combined with photolithography and etching at a temperature of 600°C;

[0133] By photolithography and vacuum evaporation method, n + The cathode ohmic contact metal 10 is made on the surface of the SiC emitter region 6 and the surface of the i-type Ga2O3 commutation region 7 between the dielectric layers 9. The background vacuum pressure is 5×10 -4 Pa;

[0134] By vacuum evaporation and rapid thermal annealing method, the + SiC emitter region 3 and p + The anode ohmic contact metal 11 is made on the surface of the NiO emitter region 4, and the background vacuum pressure is 5×10 -4 Pa, annealing temperature is 1100℃;

[0135] The cathode PAD metal 12 is formed on the surface of the passivation layer 8 and the cathode ohmic contact metal 10 by vacuum evaporation and etching. The background vacuum pressure is 5×10 -4 Pa;

[0136] The anode PAD metal 13 is fabricated on the surface of the anode ohmic contact metal 11 by vacuum evaporation method, and the background vacuum pressure is 5×10 -4 Pa;

[0137] The manufacture of SiC heterogeneous thyristors with dual-wavelength light control function is achieved through dotting, scribing and packaging.

[0138] Example 3

[0139] The structure of the SiC heterogeneous crystal thyristor with dual wavelength light control function of the present invention is as follows: - Substrate 1, thickness 200 μm, donor impurity concentration 1.0×10 14 cm -3 ;

[0140] n - One side of the substrate 1 is made with n + Buffer layer 2, thickness is 2.0 μm, and the donor impurity concentration is 2.5×10 17 cm -3 ;

[0141] n + The surface of the buffer layer 2 is made with a convex platform + SiC emitter region 3, the platform thickness is 2.0 μm, the platform width is 6.0 μm, and the acceptor impurity concentration is 1.0×10 19 cm -3 ;

[0142] Two adjacent convex-shaped p + SiC emitter regions 3 are embedded with p + NiO emitter 4, p + The NiO emitter region 4 has a thickness of 1.0 μm, a width of 4.0 μm, and an acceptor impurity concentration of 1.0×10 18 cm -3 ;

[0143] n - On the other side of the substrate 1, a p-type short base region 5 is formed upward, with a thickness of 2.5 μm and an acceptor impurity concentration of 2.5×10 17 cm -3 ;

[0144] The surface of the p-type short base region 5 is formed with a convex platform n +SiC emitter 6, convex platform n + The thickness of the SiC emitter region 6 is 2.5 μm, the width is 20 μm, and the donor impurity concentration is 5.0×10 18 cm -3 ;

[0145] Two adjacent bosses n + An i-type Ga2O3 commutation region 7 is fabricated on the surface of the p-type short base region 5 between the SiC emitter regions 6. The i-type Ga2O3 commutation region 7 has a thickness of 3.0 μm, a width of 30 μm, and an impurity concentration of 1.0×10 7 cm -3 ;

[0146] n + A passivation layer 8 is formed on the edge and sidewalls of the SiC emitter region 6. The passivation layer 8 is also formed on the edge and sidewalls of the i-type Ga2O3 commutation region 7. The passivation layer 8 is made of a combination of SiO2 and Si3N4, and has a thickness of 1.0 μm.

[0147] A convex platform dielectric layer 9 is formed on the upper surface of the i-type Ga2O3 commutation region 7. The material of the convex platform dielectric layer 9 is a combination of SiO2 and Si3N4, with an overall thickness of 1.0 μm and a width of 10 μm.

[0148] Between the passivation layer 8 n + A cathode ohmic contact metal 10 is fabricated on the surface of the SiC emitter region 6 and the surface of the i-type Ga2O3 commutation region 7 between the dielectric layers 9. The cathode ohmic contact metal 10 is made of a combination of Ti, Ni, Al, and Cu, with an overall thickness of 500 nm.

[0149] p + SiC emitter region 3 and p + An anode ohmic contact metal 11 is made on the surface of the NiO emitter region 4. The material of the anode ohmic contact metal 11 is a combination of Ti, Ni, W, and Ta, and the overall thickness is 300nm.

[0150] A cathode PAD metal 12 is formed on the surface of the passivation layer 8 and the cathode ohmic contact metal 10. The cathode PAD metal 12 is made of a combination of Al and Cu, and has an overall thickness of 6.0 μm.

[0151] An anode PAD metal 13 is formed on the surface of the anode ohmic contact metal 11. The material of the anode PAD metal 13 is a combination of Ti and Au, and the overall thickness is 2.0 μm.

[0152] The present invention provides a method for preparing a SiC heterogeneous crystal thyristor with dual-wavelength light control function, which is implemented according to the following steps:

[0153] The n-SiC material was prepared by PVT method- Substrate 1, growth temperature 2150°C, reaction pressure 1.0 Pa, argon gas flow rate 200 sccm;

[0154] By CVD method - An n+ buffer layer 2 is formed by epitaxial growth on one side of the substrate 1 with the surface facing upwards at a temperature of 1550°C;

[0155] By CVD method + Buffer layer 2 surface upward epitaxial preparation p + SiC emitter region 3, temperature is 1550℃;

[0156] The p + The SiC emitter region 3 makes p + The SiC emitter region 3 is in the shape of several convex platforms, with an atmosphere of CF4 and a pressure of 2.0 Pa;

[0157] By CVD method, the platform-shaped + SiC emitter region 3 is prepared between p + NiO emission region 4, pressure is 1.5 Pa;

[0158] Flip the wafer and deposit it on n - The other side of the substrate 1 is epitaxially grown upward to form a p-type short base region 5 at a temperature of 1550° C.

[0159] The n-type short base region 5 is epitaxially grown upwards by CVD. + SiC emitter region 6, temperature is 1550℃;

[0160] Etch n by photolithography plus dry etching process + The SiC emitter region 6 makes n + The SiC emitter region 6 is in the shape of a convex platform, with an atmosphere of CF4 and a pressure of 5 Pa;

[0161] By CVD method + Between the SiC emitter regions 6, an i-type Ga2O3 commutation region 7 is epitaxially grown on the surface of the p-type short base region 5 at a temperature of 950°C;

[0162] By combining CVD method with photolithography and etching, + A passivation layer 8 is formed on the upper surface edge and sidewall of the SiC emitter region 6 and the i-type Ga2O3 commutation region 7 at room temperature;

[0163] A dielectric layer 9 is formed on the upper surface of the i-type Ga2O3 commutation region 7 by a CVD method combined with photolithography and etching at room temperature;

[0164] By photolithography and vacuum evaporation method, n +The cathode ohmic contact metal 10 is made on the surface of the SiC emitter region 6 and the surface of the i-type Ga2O3 commutation region 7 between the dielectric layers 9. The background vacuum pressure is 1×10 -4 Pa;

[0165] By vacuum evaporation and rapid thermal annealing method, the + SiC emitter region 3 and p + The anode ohmic contact metal 11 is made on the surface of the NiO emitter region 4, and the background vacuum pressure is 1×10 -4 Pa, annealing temperature is 1000℃;

[0166] The cathode PAD metal 12 is formed on the surface of the passivation layer 8 and the cathode ohmic contact metal 10 by vacuum evaporation and etching. The background vacuum pressure is 1×10 -4 Pa;

[0167] The anode PAD metal 13 is formed on the surface of the anode ohmic contact metal 11 by vacuum evaporation, and the background vacuum pressure is 1×10 -4 Pa;

[0168] The manufacture of SiC heterogeneous thyristors with dual-wavelength light control function is achieved through dotting, scribing and packaging.

[0169] In order to illustrate the advantages of the SiC heterogeneous crystalline transistor with dual-wavelength light control function of the present invention, the SiC heterogeneous crystalline transistor with dual-wavelength light control function of the above embodiment 1 was verified using the Sentaurus TCAD computer numerical experiment platform.

[0170] Figure 16 The waveforms for the light-triggered on and off of a SiC heterojunction thyristor with dual-wavelength light control in Example 1 of the present invention are shown. As can be seen from the figure, the SiC heterojunction thyristor with dual-wavelength light control can be switched from the off state to the on state by 365nm ultraviolet light triggering, and can also be switched from the on state to the off state by 254nm ultraviolet light control. In summary, the SiC heterojunction thyristor with dual-wavelength light control in the present invention can be switched on and off by controlling the dual-wavelength light signal, improving the problem of existing SiC LTTs having difficulty in autonomously shutting down.

Claims

1. A SiC heterogeneous crystal thyristor with dual-wavelength light control function, characterized in that: Including - Substrate (1), n - One side of the substrate (1) is formed with n + Buffer layer (2), p + SiC emitter region (3), anode ohmic contact metal (11), anode PAD metal (13), p + The contact surface of the SiC emitter region (3) and the anode ohmic contact metal (11) is composed of a plurality of evenly distributed bosses, and a p-type contact is provided between two adjacent bosses. + NiO emitter region (4), n - A p-type short base region (5) is formed on the surface of the other side of the substrate (1) facing upwards. The p-type short base region (5) is away from the n - Several n layers are uniformly formed on one side of the substrate (1) + SiC emitter region (6) and i-type Ga2O3 commutation region (7), n + SiC emitter regions (6) and i-type Ga2O3 commutation regions (7) are distributed alternately, and the adjacent n + A passivation layer (8) is provided between the SiC emitter region (6) and the i-type Ga2O3 commutation region (7). A plurality of dielectric layers (9) are evenly distributed on the side of the i-type Ga2O3 commutation region (7) away from the p-type short base region (5). The longitudinal section of the passivation layer (8) is T-shaped. The vertical portion of the passivation layer (8) is adjacent to the n-type short base region (5). + The sidewalls of the SiC emitter region (6) and the i-type Ga2O3 commutation region (7), the horizontal portion of the passivation layer (8) covers a portion of the n + A cathode ohmic contact metal (10) is provided between the upper surfaces of the SiC emitter region (6) and the i-type Ga2O3 commutation region (7) and the horizontal portion of the passivation layer (8), and a cathode PAD metal (12) is provided on the upper surface of the cathode ohmic contact metal (10).

2. The SiC heterogeneous crystal thyristor with dual-wavelength light control function according to claim 1, characterized in that: The n - The material of the substrate (1) is 4H-SiC, the thickness is 100 to 300 μm, and the donor impurity concentration is 2.0×10 13 cm -3 ~2.0×10 14 cm -3 ; said n + The buffer layer (2) has a thickness of 0.5 μm to 3.0 μm and a donor impurity concentration of 5.0×10 16 cm -3 ~5.0×10 17 cm -3 .

3. The SiC heterogeneous crystal thyristor with dual-wavelength light control function according to claim 1, characterized in that: The p + The thickness of the convex platform of the SiC emitter region (3) is 1.0 to 3.0 μm, the width of the convex platform is 3.0 to 9.0 μm, and the acceptor impurity concentration is 5.0×10 18 cm -3 ~5.0×10 19 cm -3 ; the p + The NiO emitter region (4) has a thickness of 1.0 to 3.0 μm, a width of 3.0 to 9.0 μm, and an acceptor impurity concentration of 1.0×10 18 cm -3 ~1.0×10 19 cm -3 .

4. The SiC heterogeneous crystal thyristor with dual-wavelength light control function according to claim 1, characterized in that: The thickness of the p-type short base region (5) is 2.0-3.0 μm, and the acceptor impurity concentration is 5.0×10 16 cm -3 ~5.0×10 17 cm -3 ; said n + The SiC emitter region (6) has a thickness of 1.0 to 3.0 μm, a width of 15 to 100 μm, and a donor impurity concentration of 1.0×10 18 cm -3 ~1.0×10 19 cm -3 The i-type Ga2O3 commutation region (7) has a thickness of 1.0 to 3.0 μm, a width of 15 to 100 μm, and an impurity concentration of 1.0×10 6 cm -3 ~1.0×10 8 cm -3 .

5. The SiC heterogeneous crystal transistor with dual-wavelength light control function according to claim 1, characterized in that: The material of the passivation layer (8) is a combination of one or more of SiO2, AlN, and Si3N4, and the overall thickness of the passivation layer (8) is 500nm to 2μm; the material of the dielectric layer (9) is a combination of one or more of SiO2, AlN, and Si3N4, and the overall thickness of the dielectric layer (9) is 500nm to 2μm, and the width is 1.0μm to 10μm; the material of the cathode ohmic contact metal (10) is a combination of one or more of Ti, Ni, Al, Cu, and Au, and the overall thickness of the cathode ohmic contact metal (10) is 200nm to 500nm The material of the anode ohmic contact metal (11) is a combination of one or more of Ti, Ni, W, Al, and Ta, and the overall thickness of the anode ohmic contact metal (11) is 200 nm to 500 nm; the material of the cathode PAD metal (12) is a combination of one or more of Ti, Al, Cu, and Au, and the overall thickness of the cathode PAD metal (12) is 2.0 to 10 μm; the material of the anode PAD metal (13) is a combination of one or more of Ti, Ag, Ni, and Au, and the overall thickness of the anode PAD metal (13) is 1.0 to 2.0 μm.

6. A method for preparing a SiC heterogeneous crystal thyristor with dual-wavelength light control function, characterized in that: Please follow the steps below to implement it: Step 1: Prepare n-type 4H-SiC by physical vapor transport (PVT) - substrate (1); Step 2: Chemical vapor deposition (CVD) - An n+ buffer layer (2) is prepared by epitaxially growing the surface of one side of the substrate (1) upward; Step 3: Chemical vapor deposition (CVD) + The buffer layer (2) is epitaxially prepared upwardly + SiC emitter region (4); Step 4: Etch the p by photolithography plus dry etching process + SiC emitter region (3), making p + The surface of the SiC emission region (3) is in the form of several convex terraces; Step 5: Sputtering or CVD method on p + Preparation of p between the protrusions of SiC emitter region (3) + NiO emitter region (4); Step 6: Flip the wafer and deposit it on n - The other side surface of the substrate 1 is epitaxially grown upward to prepare a p-type short base region (5); Step 7: Prepare n-type epitaxial growth on the surface of the p-type short base region 5 by CVD method. + SiC emitter region (6); Step 8: Etch n by photolithography plus dry etching process + SiC emitter region (6); Step 9: CVD method + Epitaxially preparing an i-type Ga2O3 commutation region (7) between the SiC emitter regions (6) and on the surface of the p-type short base region (5); Step 10: Combine CVD method with photolithography and etching method to form a + A passivation layer (8) is formed on the upper surface edge and side wall of the SiC emitter region (6) and the i-type Ga2O3 commutation region (7); Step 11: fabricating a dielectric layer (9) on the upper surface of the i-type Ga2O3 commutation region (7) by a CVD method combined with photolithography and etching; Step 12: Between the passivation layer (8), n + A cathode ohmic contact metal (10) is fabricated on the surface of the SiC emitter region (6), between the dielectric layers (9), and on the surface of the i-type Ga2O3 commutation region (7); Step 13: vacuum evaporation and rapid thermal annealing + SiC emitter region 3 and p + Anode ohmic contact metal 11 is made on the surface of NiO emitter region 4; Step 14: forming a cathode PAD metal (12) on the surface of the passivation layer (8) and the cathode ohmic contact metal (10) by vacuum evaporation and etching; Step 15: forming an anode PAD metal (13) on the surface of the anode ohmic contact metal (11) by vacuum evaporation; The manufacture of SiC heterogeneous thyristors with dual-wavelength light control function is achieved through dotting, scribing and packaging.

7. The method for preparing a SiC heterogeneous crystal thyristor with dual-wavelength light control function according to claim 6, characterized in that: In the step 1, the growth temperature of the physical vapor transport (PVT) method is 2100° C. to 2200° C., the reaction pressure is 0.5 Pa to 1.5 Pa, and the argon gas flow rate is 100 sccm to 500 sccm.

8. The method for preparing a SiC heterogeneous crystal thyristor with dual-wavelength light control function according to claim 6, characterized in that: The deposition temperature of the chemical vapor deposition CVD method in step 2 is 1500°C to 1600°C; the deposition temperature of the chemical vapor deposition CVD method in step 3 is 1500°C to 1600°C; the pressure range of the sputtering or CVD method in step 5 is 0.8Pa to 2.0Pa; the deposition temperature of the chemical vapor deposition CVD method in step 6 is 1500°C to 1600°C; the deposition temperature of the chemical vapor deposition CVD method in step 7 is 1500°C to 1600°C; the deposition temperature of the chemical vapor deposition CVD method in step 9 is 850°C to 1100°C; the deposition temperature of the chemical vapor deposition CVD method in steps 10 and 11 is room temperature to 600°C.

9. The method for preparing a SiC heterogeneous crystal thyristor with dual-wavelength light control function according to claim 6, characterized in that: The atmosphere of the dry etching process in step 4 is CF4 and SF6, and the pressure range is 1.0Pa~10Pa; the atmosphere of the dry etching process in step 8 is CF4 and SF6, and the pressure range is 1.0Pa~10Pa.

10. The method for preparing a SiC heterogeneous crystal thyristor with dual-wavelength light control function according to claim 6, characterized in that: The background vacuum pressure of the vacuum evaporation method in step 12, step 13, step 14, and step 15 is 5×10 -5 Pa~5×10 -4 Pa; the annealing temperature of the rapid thermal annealing in step 13 is 900°C to 1100°C.

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