VSYNC signal processing device and method for local dimming, and electronic device

Abstract

The present disclosure provides a VSYNC signal processing device and method, and an electronic device for regional dimming, wherein the device includes: a first timer, wherein the VSYNC input signal is captured by a first input channel on the rising edge of the VSYNC input signal and triggers a first interrupt task; and is captured by a second input channel on the falling edge of the VSYNC input signal and triggers a second interrupt task; a single-chip microcomputer, connected to the first timer, which pulls up a first GPIO outputting the VSYNC output signal when processing the first interrupt task, controls the first timer to reset the count, and calculates the duty cycle and frequency of the VSYNC input signal when a preset condition is met; and the single-chip microcomputer pulls down the first GPIO when processing the second interrupt task. Through the present disclosure, the problem of being unable to use hardware to measure and calculate the VSYNC signal frequency and duty cycle, and being unable to cope with the situation where the system VSYNC signal is lost, is solved. The present disclosure uses a hardware timer to measure VSYNC signal parameters and can follow them in real time, with fast response and good reliability.

Description

Technical Field

[0001] The present invention relates to the field of local dimming technology, and in particular to a VSYNC signal processing device and method, and electronic equipment for local dimming. Background Art

[0002] The vertical synchronization (VSYNC) signal, also known as the field sync signal, is provided by the SoC or TCON in local dimming backlight applications. It is used to synchronize the backlight brightness when switching between frames. An unstable VSYNC signal or an unresponsive receiver can cause backlight flicker, affecting the visual experience.

[0003] The existing technology mainly uses the following methods to process the received system VSYNC signal:

[0004] 1. The receiving MCU only enables the GPIO rising and falling edge triggers and outputs the follower signal through another GPIO.

[0005] 2. When the MCU is powered on and initialized, it tests the received VSYNC signal, calculates the duty cycle and frequency, and then sets the timer with fixed parameters to independently output a VSYNC signal to the driver chip.

[0006] The existing technology has the following problems:

[0007] 1. The VSYNC signal frequency and duty cycle cannot be measured and calculated using hardware, and the system cannot cope with the situation where the VSYNC signal is lost.

[0008] 2. As time accumulates, the VSYNC signal independently given to the driver chip will lose synchronization with the system VSYNC signal. When the system VSYNC signal changes, the timely response is poor.

[0009] Currently, no effective solution has been proposed for the problem in related technologies that the VSYNC signal frequency and duty cycle cannot be calculated using hardware measurement, and that the system cannot cope with the situation where the VSYNC signal is lost. Summary of the Invention

[0010] The purpose of the present disclosure is to address the deficiencies in the prior art and to provide a VSYNC signal processing device, method, electronic device, and computer-readable storage medium for local dimming, so as to at least solve the problem in the related art that the VSYNC signal frequency and duty cycle cannot be measured and calculated by hardware, and that the system VSYNC signal cannot be lost.

[0011] According to one aspect of the present disclosure, a VSYNC signal processing apparatus for local dimming is provided, comprising:

[0012] The first timer includes a first input channel and a second input channel, wherein a VSYNC input signal is captured by the first input channel at a rising edge of the VSYNC input signal and triggers a first interrupt task; and the VSYNC input signal is captured by the second input channel at a falling edge of the VSYNC input signal and triggers a second interrupt task;

[0013] A single-chip microcomputer is connected to the first timer. When processing the first interrupt task, the single-chip microcomputer pulls up the first GPIO that outputs the VSYNC output signal, controls the first timer to reset the count, and calculates the duty cycle and frequency of the VSYNC input signal when a preset condition is met; when processing the second interrupt task, the single-chip microcomputer pulls down the first GPIO.

[0014] According to another aspect of the present disclosure, a VSYNC signal processing method for local dimming is provided, comprising:

[0015] Determine whether the VSYNC input signal is detected;

[0016] If the VSYNC input signal is detected, when a first interrupt task triggered by a rising edge of the VSYNC input signal is detected, the first timer is controlled to reset the count, and it is determined whether a preset condition is met. If the preset condition is met, the duty cycle and frequency of the VSYNC input signal are calculated, and the GPIO outputting the VSYNC output signal is pulled high; if the preset condition is not met, the GPIO outputting the VSYNC output signal is directly pulled high;

[0017] When the second interrupt task triggered by the falling edge of the VSYNC input signal is detected, the GPIO outputting the VSYNC output signal is pulled low.

[0018] According to another aspect of the present disclosure, there is provided an electronic device, comprising:

[0019] processor; and

[0020] Memory for storing programs,

[0021] The program includes instructions, which, when executed by the processor, enable the processor to perform the VSYNC signal processing method for local dimming in the present disclosure.

[0022] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable the computer to execute the VSYNC signal processing method for local dimming in the present disclosure.

[0023] One or more technical solutions provided in the embodiments of the present disclosure, by using a first timer, the VSYNC input signal is captured by the rising edge of the first input channel of the first timer and triggers the first interrupt task; is captured by the second input channel at the falling edge and triggers the second interrupt task, and then the first GPIO of the output VSYNC output signal is pulled high when the single-chip microcomputer processes the first interrupt task, the first timer is controlled to reset the count, and the duty cycle and frequency of the VSYNC input signal are calculated when the preset conditions are met; the first GPIO is pulled low when processing the second interrupt task, which can solve the problem in the related art that the VSYNC signal frequency and duty cycle cannot be calculated by hardware measurement, and the situation that the system VSYNC signal is lost can not be dealt with, and the effect of using hardware timers to measure VSYNC signal parameters and follow in real time, with fast response and good reliability can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Further details, features and advantages of the present disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0025] Figure 1 A schematic diagram illustrating a VSYNC signal processing apparatus for local dimming according to an exemplary embodiment of the present disclosure is shown;

[0026] Figure 2 A flowchart of a VSYNC signal processing method for local dimming according to an exemplary embodiment of the present disclosure is shown;

[0027] Figure 3 A flowchart of a VSYNC signal processing method for local dimming according to a preferred embodiment of the present disclosure is shown;

[0028] Figure 4 A structural block diagram of an exemplary electronic device that can be used to implement the embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0029] The following describes embodiments of the present disclosure in more detail with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure.

[0030] It should be understood that the various steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this respect.

[0031] The term "including" and its variations used in this document are open inclusions, that is, "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one other embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the description below. It should be noted that the concepts of "first", "second", etc. mentioned in this disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0032] It should be noted that the modifications of "one" and "multiple" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, they should be understood as "one or more".

[0033] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0034] Aspects of the present disclosure are described below with reference to the accompanying drawings.

[0035] An exemplary embodiment of the present disclosure provides a VSYNC signal processing apparatus for local dimming.

[0036] Figure 1 FIG. 1 shows a schematic diagram of a VSYNC signal processing device for local dimming according to an exemplary embodiment of the present disclosure. Figure 1 As shown, the device may include:

[0037] The first timer (i.e. Figure 1 The timer 1 shown in FIG. 1 includes a first input channel (ie Figure 1 Input channel 1 shown) and the second input channel (i.e. Figure 1 The input channel 2 shown in the figure) is configured such that the VSYNC input signal output by the system on chip (SOC) is captured by the first input channel at the rising edge of the VSYNC input signal through the GPIO In, and a first interrupt task is triggered; the VSYNC input signal is captured by the second input channel at the falling edge of the VSYNC input signal, and a second interrupt task is triggered.

[0038] Single chip microcomputer (ie Figure 1 MCU CORE shown), is connected to the first timer, and the single chip pulls up the first GPIO (ie, the first GPIO of the output VSYNC output signal) when processing the first interrupt task. Figure 1GPIO Out shown), controls the first timer to reset the count, and calculates the duty cycle and frequency of the VSYNC input signal when a preset condition is met; the single chip microcomputer pulls down the first GPIO when processing the second interrupt task.

[0039] The second timer (i.e. Figure 1 The timer 2 shown is connected to the single-chip microcomputer, wherein the first timer triggers an overflow interrupt task when the VSYNC input signal is not detected for more than a preset time, and the single-chip microcomputer processes the overflow interrupt task to control the second timer to pulse-width modulate the VSYNC output signal with the previous duty cycle and frequency.

[0040] like Figure 1 As shown, the first GPIO (ie Figure 1 GPIOOut shown), connected to the driver chip, for outputting the VSYNC output signal; the second GPIO is Figure 1 The GPIO In shown is connected to the system-level chip and is used to receive the VSYNC input signal.

[0041] An exemplary embodiment of the present disclosure provides a VSYNC signal processing method for local dimming. Figure 2 A flow chart of a VSYNC signal processing method for local dimming according to an exemplary embodiment of the present disclosure is shown. Figure 2 As shown, the method includes the following steps:

[0042] Step S201, determining whether a VSYNC input signal is detected;

[0043] Step S202: If the VSYNC input signal is detected, when a first interrupt task triggered by a rising edge of the VSYNC input signal is detected, the first timer is controlled to reset the count and determine whether a preset condition is met. If the preset condition is met, the duty cycle and frequency of the VSYNC input signal are calculated, and the GPIO outputting the VSYNC output signal is pulled high; if the preset condition is not met, the GPIO outputting the VSYNC output signal is directly pulled high.

[0044] Step S203: When a second interrupt task triggered by a falling edge of the VSYNC input signal is detected, the GPIO outputting the VSYNC output signal is pulled low.

[0045] By using the above steps, the hardware timer can be configured without active software intervention, and can both measure VSYNC parameters and track them in real time, with fast response and high reliability. This solves the problem in related technologies where hardware cannot be used to measure and calculate the VSYNC signal frequency and duty cycle, and cannot cope with the loss of the system VSYNC signal.

[0046] In some embodiments, determining whether a preset condition is met includes:

[0047] Determine whether it is the first time that the first interrupt task is triggered by the rising edge of the VSYNC input signal;

[0048] If the first interrupt task triggered by the rising edge of the VSYNC input signal is detected for the first time, determining that the preset condition is met;

[0049] If it is not the first time that the first interrupt task is triggered by the rising edge of the VSYNC input signal, determining whether a difference between a current parameter of the VSYNC input signal and a previously recorded historical parameter of the VSYNC input signal exceeds a target threshold;

[0050] If the difference between the current parameter of the VSYNC input signal and the historical parameter of the VSYNC input signal recorded last time exceeds the target threshold, it is determined that the preset condition is met;

[0051] If the difference between the current parameter of the VSYNC input signal and the historical parameter of the VSYNC input signal recorded last time does not exceed the target threshold, it is determined that the preset condition is not met.

[0052] It should be noted that the system VSYNC input signal is captured by the first timer's two input channels (input channel 1 and input channel 2) on the rising and falling edges of the signal, triggering a capture event interrupt. The first timer is set to count in Restart mode and resets the count on the next rising edge.

[0053] When the MCU handles the first interrupt task for the first input channel (rising edge), it first pulls high the GPIO corresponding to the driver chip's VSYNC output signal, and simultaneously resets the first timer. The registers associated with the first and second input channels retain the captured high and low time durations of the VSYNC input signal, which are used to calculate the frequency and duty cycle of the system's VSYNC input signal.

[0054] The second interrupt task of the second input channel (falling edge) of the first timer is relatively simple. The microcontroller only pulls down the GPIO corresponding to the VSYNC output signal of the driver chip, thus completing the parameter calculation and real-time tracking of the VSYNC signal.

[0055] Considering the performance of the MCU, the duty cycle and frequency of the VSYNC input signal don't need to be calculated every time. Instead, they can be fully measured and recorded once during power-up initialization. Subsequently, recalculation is required only when the difference between the real-time data recorded by the MCU timer and the historical data retained by the MCU exceeds a threshold. Otherwise, the GPIO is simply pulled high or low to track the system's VSYNC input signal. The threshold should be adjusted based on subjective evaluation of backlight flicker as the system SOC gradually changes.

[0056] In some embodiments, after determining whether the VSYNC input signal is detected, the following steps may also be performed:

[0057] When the VSYNC input signal is not detected for more than a preset time, the second timer is controlled to perform pulse width modulation on the VSYNC output signal with a previous duty cycle and frequency.

[0058] It should be noted that the first timer also enables an update (overflow) interrupt. The MCU uses the measured frequency of the system VSYNC input signal to promptly and appropriately adjust the first timer's auto-reload value. Specifically, after the VSYNC input signal frequency is updated, the period is calculated based on the new VSYNC input signal frequency, and then the new auto-reload value is calculated based on the first timer's clock frequency. The time required for the first timer to reach this auto-reload value is slightly longer than the new VSYNC input signal period by 10% to 20% to avoid false timeouts. This allows the first timer overflow interrupt to be triggered even when the system VSYNC input signal has no rising or falling triggers. This allows for a rapid response to system VSYNC input signal timeouts or frame loss, enabling the second timer's PWM output function to output PWM at the previous system VSYNC input signal frequency and duty cycle. When the first timer detects the system VSYNC input signal again, the second timer is disabled, ensuring backlight stability and preventing flicker.

[0059] In some embodiments, after detecting the VSYNC input signal, the method further includes:

[0060] Determine whether the initialization VSYNC signal provided during initialization is valid;

[0061] If the initialization VSYNC signal is valid, then after turning off the initialization VSYNC signal, determining whether the overflow interrupt of the first timer is enabled; if the initialization VSYNC signal is invalid, then directly determining whether the overflow interrupt of the first timer is enabled;

[0062] If the overflow interrupt of the first timer is not enabled, then enabling the overflow interrupt of the first timer and determining whether the first interrupt task triggered by the rising edge of the VSYNC input signal is detected;

[0063] If the overflow interrupt of the first timer is enabled, it is directly determined whether the first interrupt task triggered by the rising edge of the VSYNC input signal is detected.

[0064] The embodiments of the present application are described and illustrated below through preferred embodiments.

[0065] Figure 3 FIG. 1 shows a flow chart of a VSYNC signal processing method for local dimming according to a preferred embodiment of the present disclosure. Figure 3 As shown, the method includes the following steps:

[0066] Step S301, during initialization, the MCU provides an initial VSYNC signal; the MCU here is a single chip microcomputer, and the initial VSYNC signal is a VSYNC input signal;

[0067] Step S302: When the system VSYNC signal is input normally, determine whether the VSYNC signal is captured; if so, execute step S303; if not, execute step S317;

[0068] Step S303, determine whether the VSYNC provided by the MCU is still valid; if so, execute step S304; if not, execute step S305;

[0069] Step S304, turning off the self-provided VSYNC;

[0070] Step S305, determining whether the overflow interrupt of timer 1 (i.e., the first timer in the embodiment of the present disclosure) is enabled; if not, executing step S306; if yes, executing step S307;

[0071] Step S306, enable timer 1 overflow interrupt;

[0072] Step S307, determine whether a rising edge trigger is captured; if not, execute step S308; if yes, execute step S309;

[0073] Step S308: pull down the GPIO of the MCU output VSYNC, and then wait for a trigger event;

[0074] Step S309, reset timer 1;

[0075] Step S310, determine whether it is the first time to trigger the capture event; if so, execute step S311; if not, execute step S313;

[0076] Step S311, calculate the frequency and duty cycle of the system VSYNC and save the backup in the MCU;

[0077] Step S312, reload the count value of timer 1;

[0078] Step S313, determine whether the difference compared with the old data exceeds a threshold; if so, execute step S311; if not, execute step S314;

[0079] Step S314: pull high the GPIO of the MCU output VSYNC signal, and then wait for a trigger event.

[0080] When the system VSYNC is lost, execute step S315 to determine whether timer 1 has counted overflow; if so, execute step S316; enable MCU timer 2 (i.e., the second timer in the embodiment of the present disclosure) to output VSYNC with the same parameters, turn off the timer 1 overflow interrupt, and then execute step S317 to retain the last set VSYNC, and then wait for the trigger event.

[0081] The disclosed embodiments use an MCU hardware timer to measure the VSYNC signal frequency and duty cycle in regional dimming or multi-zone dynamic backlight applications, while simultaneously following the output VSYNC in real time, and automatically providing a VSYNC signal with the same parameters after a timeout to ensure backlight stability, and restoring the following and measurement functions after the system VSYNC is restored.

[0082] It should be noted that the steps shown in the above process or the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0083] The exemplary embodiments of the present disclosure further provide an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor. The memory stores a computer program executable by the at least one processor, the computer program being configured to cause the electronic device to perform a method according to an exemplary embodiment of the present disclosure when executed by the at least one processor.

[0084] Exemplary embodiments of the present disclosure further provide a non-transitory computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor of a computer, is used to cause the computer to perform a method according to an embodiment of the present disclosure.

[0085] Exemplary embodiments of the present disclosure further provide a computer program product, including a computer program, wherein when the computer program is executed by a processor of a computer, it is used to cause the computer to perform the method according to the embodiment of the present disclosure.

[0086] refer to Figure 4 , a block diagram of an electronic device 400 that can serve as a server or client of the present disclosure will now be described, which is an example of a hardware device that can be applied to various aspects of the present disclosure. The electronic device is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0087] like Figure 4 As shown, electronic device 400 includes a computing unit 401, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 402 or a computer program loaded from a storage unit 408 into a random access memory (RAM) 403. Various programs and data required for the operation of device 400 can also be stored in RAM 403. Computing unit 401, ROM 402, and RAM 403 are connected to each other via a bus 404. An input / output (I / O) interface 405 is also connected to bus 404.

[0088] Multiple components within electronic device 400 are connected to I / O interface 405, including an input unit 406, an output unit 407, a storage unit 408, and a communication unit 409. Input unit 406 can be any type of device capable of inputting information into electronic device 400. Input unit 406 can receive input numeric or character information and generate key signal inputs related to user settings and / or function control of the electronic device. Output unit 407 can be any type of device capable of presenting information and may include, but is not limited to, a display, a speaker, a video / audio output terminal, a vibrator, and / or a printer. Storage unit 408 may include, but is not limited to, a magnetic disk or an optical disk. Communication unit 409 allows electronic device 400 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks and may include, but is not limited to, a modem, a network card, an infrared communication device, a wireless communication transceiver and / or a chipset, such as a Bluetooth device, a WiFi device, a WiMax device, a cellular communication device, and / or the like.

[0089] The computing unit 401 can be various general-purpose and / or specialized processing components with processing and computing capabilities. Some examples of the computing unit 401 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 401 performs the various methods and processes described above. For example, in some embodiments, the VSYNC signal processing method for local dimming can be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 408. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 400 via the ROM 402 and / or the communication unit 409. In some embodiments, the computing unit 401 can be configured to perform the VSYNC signal processing method for local dimming by any other appropriate means (e.g., via firmware).

[0090] The program code for implementing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0091] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0092] As used in this disclosure, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, apparatus, and / or device (e.g., a magnetic disk, an optical disk, a memory, a programmable logic device (PLD)) for providing machine instructions and / or data to a programmable processor, including machine-readable media that receive machine instructions as machine-readable signals. The term "machine-readable signal" refers to any signal used to provide machine instructions and / or data to a programmable processor.

[0093] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0094] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0095] Computer systems may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The client and server relationship arises through computer programs running on the respective computers and having a client-server relationship to each other.

Claims

1. A VSYNC signal processing device for local dimming, characterized in that: include: The first timer includes a first input channel and a second input channel, wherein a VSYNC input signal is captured by the first input channel at a rising edge of the VSYNC input signal and triggers a first interrupt task; and the VSYNC input signal is captured by the second input channel at a falling edge of the VSYNC input signal and triggers a second interrupt task; A single-chip microcomputer is connected to the first timer. When processing the first interrupt task, the single-chip microcomputer pulls up the first GPIO outputting the VSYNC output signal, controls the first timer to reset the count, and determines whether it is the first time that the first interrupt task is triggered by the rising edge of the VSYNC input signal; if it is the first time that the first interrupt task is triggered by the rising edge of the VSYNC input signal, it is determined that the preset condition is met; if it is not the first time that the first interrupt task is triggered by the rising edge of the VSYNC input signal, it is determined whether the current parameter of the VSYNC input signal is consistent with the last recorded VSYNC whether the difference between the historical parameters of the input signal exceeds the target threshold; if the difference between the current parameter of the VSYNC input signal and the historical parameter of the VSYNC input signal recorded last time exceeds the target threshold, it is determined that the preset condition is met; if the difference between the current parameter of the VSYNC input signal and the historical parameter of the VSYNC input signal recorded last time does not exceed the target threshold, it is determined that the preset condition is not met; and when the preset condition is met, the duty cycle and frequency of the VSYNC input signal are calculated; the single-chip microcomputer pulls down the first GPIO when processing the second interrupt task; the duty cycle and frequency of VSYNC are calculated based on the high and low level time of the VSYNC input signal captured by the first input channel and the second input channel; A second timer is connected to the single-chip microcomputer, wherein the first timer triggers an overflow interrupt task when the VSYNC input signal is not detected for more than a preset time, and the single-chip microcomputer processes the overflow interrupt task to control the second timer to pulse-width modulate the VSYNC output signal with the last duty cycle and frequency; wherein the preset time is longer than the period of the VSYNC input signal by 10%-20% of the period of the VSYNC input signal, and the period of the VSYNC input signal is calculated based on the frequency of the VSYNC input signal.

2. The VSYNC signal processing device for local dimming according to claim 1, wherein: Also includes: The first GPIO is connected to the driver chip and is used to output the VSYNC output signal; The second GPIO is connected to the system-on-chip and is used to receive the VSYNC input signal.

3. A VSYNC signal processing method for local dimming, characterized in that: include: Determine whether the VSYNC input signal is detected; If the VSYNC input signal is detected, when a first interrupt task triggered by a rising edge of the VSYNC input signal is detected, the first timer is controlled to reset the count and determine whether a preset condition is met. If the preset condition is met, the duty cycle and frequency of the VSYNC input signal are calculated, and the GPIO outputting the VSYNC output signal is pulled high; if the preset condition is not met, the GPIO outputting the VSYNC output signal is directly pulled high; the duty cycle and frequency of VSYNC are calculated based on the high and low level times of the VSYNC input signal captured by the first input channel and the second input channel; When detecting a second interrupt task triggered by a falling edge of the VSYNC input signal, pulling down the GPIO outputting the VSYNC output signal; When the VSYNC input signal is not detected for a preset time, controlling the second timer to pulse-width modulate the VSYNC output signal with a previous duty cycle and frequency; wherein the preset time is longer than a period of the VSYNC input signal by 10%-20% of the period of the VSYNC input signal, and the period of the VSYNC input signal is calculated based on the frequency of the VSYNC input signal; The determination of whether the preset condition is met includes: Determine whether it is the first time that the first interrupt task is triggered by the rising edge of the VSYNC input signal; If the first interrupt task triggered by the rising edge of the VSYNC input signal is detected for the first time, determining that the preset condition is met; If it is not the first time that the first interrupt task is triggered by the rising edge of the VSYNC input signal, determining whether a difference between a current parameter of the VSYNC input signal and a previously recorded historical parameter of the VSYNC input signal exceeds a target threshold; If the difference between the current parameter of the VSYNC input signal and the historical parameter of the VSYNC input signal recorded last time exceeds the target threshold, it is determined that the preset condition is met; If the difference between the current parameter of the VSYNC input signal and the historical parameter of the VSYNC input signal recorded last time does not exceed the target threshold, it is determined that the preset condition is not met.

4. The VSYNC signal processing method for local dimming according to claim 3, wherein: After detecting the VSYNC input signal, the method further includes: Determine whether the overflow interrupt of the first timer is enabled; If the overflow interrupt of the first timer is not enabled, then enabling the overflow interrupt of the first timer and determining whether the first interrupt task triggered by the rising edge of the VSYNC input signal is detected; If the overflow interrupt of the first timer is enabled, it is directly determined whether the first interrupt task triggered by the rising edge of the VSYNC input signal is detected.

5. The VSYNC signal processing method for local dimming according to claim 4, wherein: After detecting the VSYNC input signal, the method further includes: Determine whether the initialization VSYNC signal provided during initialization is valid: If the initialization VSYNC signal is valid, then turning off the initialization VSYNC signal and then executing the step of determining whether the overflow interrupt of the first timer is enabled; If the initialization VSYNC signal is invalid, the step of determining whether the overflow interrupt of the first timer is enabled is directly performed.

6. An electronic device, characterized in that: include: processor; as well as Memory for storing programs, The program includes instructions, which, when executed by the processor, enable the processor to perform the VSYNC signal processing method for local dimming according to any one of claims 3 to 5.

7. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to enable the computer to execute the VSYNC signal processing method for local dimming according to any one of claims 3 to 5.

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