Timing control circuit and timing control method

Abstract

A timing control circuit includes a receiving circuit and a line memory coupled to the receiving circuit. The line memory is configured to output a first data signal during a first frame and output a second data signal during a second frame. The end of the first frame coincides with the beginning of the second frame. One of the first data signal and the second data signal corresponds to a long horizontal scan pause mode, and the other of the first data signal and the second data signal corresponds to a long vertical scan pause mode.

Description

Technical Field

[0001] This application relates to a timing control circuit and a timing control method thereof, and more particularly to a timing control circuit and a timing control method thereof that can improve display quality and reliability. Background Technology

[0002] In a touch and display driver integrated circuit (TDDI), display operations and touch operations are performed in a time-sharing manner to avoid noise interference affecting touch sensitivity or producing erroneous display results. There is still room for improvement in the operation of the touch and display driver integrated circuit to enhance display quality and reliability. Summary of the Invention

[0003] Therefore, this application mainly provides a timing control circuit and a timing control method thereon to improve display quality and reliability.

[0004] This application discloses a timing control circuit, including a receiving circuit and a line memory coupled to the receiving circuit, wherein the line memory is used to output a first data signal during a first frame and to output a second data signal during a second frame, wherein the end time of the first frame coincides with the start time of the second frame, wherein one of the first data signal and the second data signal corresponds to a long horizontal scan pause mode, and the other of the first data signal and the second data signal corresponds to a long vertical scan pause mode.

[0005] This application also discloses a timing control method, including outputting a first data signal during a first frame; and outputting a second data signal during a second frame, wherein the end time of the first frame coincides with the start time of the second frame, wherein one of the first data signal and the second data signal corresponds to a long horizontal scan pause mode, and the other of the first data signal and the second data signal corresponds to a long vertical scan pause mode. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of a touch display device according to an embodiment of this application.

[0007] Figure 2 This is a timing diagram of an embodiment of this application.

[0008] Figure 3 and Figure 4 They are respectively Figure 2 A magnified view of a portion of the image.

[0009] Figures 5 to 7 These are timing diagrams for embodiments of this application.

[0010] The reference numerals in the attached figures are explained as follows:

[0011] 10 Touch display devices

[0012] 100 video packet streams

[0013] 110 drive circuit

[0014] 111 Timing Control Circuit

[0015] 111a Receiver Circuit

[0016] 111b Line Memory

[0017] 111c timing generation circuit

[0018] 111d oscillation circuit

[0019] 112 Source Driver

[0020] 113 Gate Driver

[0021] 114 Touch circuit

[0022] 120 Touch Display Panel

[0023] 122 Touch Electrode

[0024] Touch signals 122S, 122S1a~122S10b, 122S1c, 122S2c

[0025] BLLP low power gap

[0026] DL2~DL4 Delay

[0027] Frames F1-F4, F12-F14, F22, F23

[0028] During frames FP1~FP3, FP12, and FP13

[0029] FP2DP, FP2DPr displays the operation period

[0030] FP2TP touch operation

[0031] FP3DP1~FP3DP10, FP2DP1~FP2DPn show the operation sub-periods.

[0032] FP3TP1~FP3TP10 Touch operation sub-period

[0033] HBP horizontal trailing edge

[0034] HFP Horizontal Front

[0035] HS horizontal synchronization begins

[0036] Hsync1 External Horizontal Synchronization Signal

[0037] Hsync2 internal horizontal synchronization signal

[0038] LPM Low Power

[0039] RGB horizontal sync pulse line period

[0040] Horizontal period tL1~tL3,tL2',tL3',tL12~tL14

[0041] tVBP2,tVBP3,tVBP2',tVBP3',tVBP13' Vertical trailing edge time

[0042] tVFP2,tVFP3,tVFP2',tVFP3',tVFP12' Vertical leading edge time

[0043] VS Vertical synchronization ended

[0044] Vsync1 External Vertical Synchronization Signal Detailed Implementation

[0045] Figure 1 This is a schematic diagram of a touch display device 10 according to an embodiment of this application. The touch display device 10 includes a driving circuit 110 and a touch display panel 120. The driving circuit 110 can receive a video packet stream 100 from a front-end circuit (not shown) (e.g., a processor) via a transmission interface. The video packet stream 100 may correspond to different horizontal periods (also known as 1H or line time) of different frames, and the driving circuit 110 can switch between a long horizontal scan pause mode (long H mode) and a long vertical scan pause mode (long V mode) to ensure display quality.

[0046] In detail, the driving circuit 110 may include a timing control circuit 111, a source driver 112, a gate driver 113, and a touch circuit 114. The timing control circuit 111 may receive video packet stream 100. The timing control circuit 111 may provide a vertical start signal or a gate frequency signal to the gate driver 113 according to the video packet stream 100, such that the gate driver 113 can drive at least one gate line (not shown) of the touch display panel 120. The timing control circuit 111 may provide a vertical synchronization signal, a horizontal start signal, or a data signal to the source driver 112 according to the video packet stream 100, such that the source driver 112 can drive at least one data line (not shown) of the touch display panel 120. The timing control circuit 111 may control the touch circuit 114, such that the touch circuit 114 can provide touch signals to drive at least one touch electrode 122 of the touch display panel 120.

[0047] The timing control circuit 111 may include a receiving circuit 111a, a line memory 111b, a timing generation circuit 111c, and an oscillation circuit 111d. Please refer to these components together. Figures 1 to 4 , Figure 2 This is a timing diagram of an embodiment of the present application. Figure 3 and Figure 4 They are respectively Figure 2 A magnified view of a portion of the image.

[0048] The receiving circuit 111a can be used to receive the video packet stream 100. In one embodiment, the receiving circuit 111a can decode the video packet stream 100 to generate... Figure 2 The external vertical synchronization signal Vsync1, external horizontal synchronization signal Hsync1, or raw data signal are shown. The external vertical synchronization signal Vsync1 is used to indicate the start or end of a frame. For example... Figure 2 As shown, the external horizontal synchronization signal Hsync1 can have multiple pulses (or lines) in a frame (e.g., one of frames F1 to F4). The period of one pulse is one horizontal period (e.g., horizontal periods tL1, tL2, tL3). The horizontal period (e.g., horizontal period tL2) of each pulse in a frame (e.g., frame F2) is the same, but the horizontal periods (e.g., horizontal periods tL2, tL3) of different frames (e.g., frames F2, F3) can be different.

[0049] The oscillation circuit 111d can be used to provide an internal frequency signal to the timing generation circuit 111c or the touch circuit 114.

[0050] The timing generation circuit 111c can be used to receive the external horizontal synchronization signal Hsync1 from the receiving circuit 111a, and convert the external horizontal synchronization signal Hsync1 into an internal horizontal synchronization signal Hsync2 according to the internal frequency signal from the oscillation circuit 111d. Furthermore, the timing generation circuit 111c can be used to detect the duration of the horizontal period (e.g., horizontal period tL1~tL3) of the external horizontal synchronization signal Hsync1 to determine whether to switch to a long horizontal scan pause mode or a long vertical scan pause mode.

[0051] In one embodiment, the line memory 111b can be used to receive an external vertical synchronization signal Vsync1, an external horizontal synchronization signal Hsync1, or a raw data signal from the receiving circuit 111a, and can write pixel data (e.g., raw data signal) into the line memory 111b according to the external horizontal synchronization signal Hsync1. The line memory 111b can be used to receive an internal horizontal synchronization signal Hsync2 from the timing generation circuit 111c, and can provide pixel data (e.g., a first data signal output by FP2 during frame period or a second data signal output by FP3 during frame period) to the source driver 112 according to the internal horizontal synchronization signal Hsync2. The first data signal and the second data signal can correspond to different scan pause modes. For example, the first data signal can correspond to a long vertical scan pause mode, and the second data signal can correspond to a long horizontal scan pause mode.

[0052] In short, the timing generation circuit 111c can be used to determine whether the duration of the external horizontal synchronization signal Hsync1 is the same in the horizontal period (e.g., horizontal period tL1 to tL3) of two consecutive frames. Based on the difference in duration between the horizontal periods tL2 and tL3, the first data signal and the second data signal correspond to different long horizontal scan pause modes and long vertical scan pause modes, respectively. Based on the absence of a difference in duration between the horizontal periods tL1 and tL2, the data signal output by FP1 during the frame period and the second data signal output by FP2 during the frame period correspond to the same long horizontal scan pause mode and long vertical scan pause mode.

[0053] For example, receiving circuit 111a can receive a first external signal from video packet stream 100 in frame F2, extract the external horizontal synchronization signal Hsync1 during the horizontal period tL2 of frame F2 and the original data signal of frame F2 from the first external signal, and write the original data signal into line memory 111b according to the external horizontal synchronization signal Hsync1. Accordingly, line memory 111b can provide a first data signal to source driver 112 during frame period FP2 according to internal horizontal synchronization signal Hsync2. The frame period FP2 corresponds to frame F2 and has the same time length as frame F2. Furthermore, based on the shorter horizontal period tL2, the first data signal can correspond to a long vertical scan pause mode. Based on the equality of horizontal period tL1 and horizontal period tL2, the data signal output by FP1 during frame period and the first data signal can both correspond to a long vertical scan pause mode.

[0054] like Figure 2 As shown, in the long vertical scan pause mode, the frame period FP2 is divided into a display operation period FP2DP and a touch operation period FP2TP. The display operation period FP2DP is used to output pixel data to the touch display panel 120, and a continuous display operation period FP2DP is used for all display operations within one frame. The touch operation period FP2TP is used to transmit the touch signal 122S, and the scanning of the touch electrode 122 is performed continuously. Figure 3 The touch signal 122S shown is transmitted via FP2TP during continuous touch operations. The long vertical scan pause mode allows touch operation to occur after all pixel data for all gate lines has been output, meaning that touch operation only occurs after a complete frame of display operation is finished. Since the display operation is continuous, horizontal lines seen in the long horizontal scan pause mode are avoided, and reliability is improved.

[0055] Similarly, receiving circuit 111a can receive a second external signal from video packet stream 100 in frame F3, extract the external horizontal synchronization signal Hsync1 during the horizontal period tL3 of frame F3 and the original data signal of frame F3 from the second external signal, and write the original data signal into line memory 111b according to the external horizontal synchronization signal Hsync1. Accordingly, line memory 111b can provide a second data signal to source driver 112 during frame period FP3 according to internal horizontal synchronization signal Hsync2. The frame period FP3 corresponds to frame F3 and has the same time length as frame F3. Furthermore, since the horizontal period tL3 is longer (compared to the horizontal period tL2), the second data signal can correspond to a long horizontal scan pause mode.

[0056] In long horizontal scan pause mode, the frame period FP3 is divided into multiple time units (e.g., 10 time units). Each time unit has a display operation sub-period and a touch operation sub-period. The display operation sub-periods FP3DP1 to FP3DP10 are used to output pixel data to the touch display panel 120. The touch operation sub-periods FP3TP1 to FP3TP10 are used to transmit touch signals. For example, Figure 4 The touch signals 122S1a to 122S10b shown can be transmitted during intermittent touch operation sub-periods FP3TP1 to FP3TP10, respectively. Since the duration of a touch operation sub-period cannot be too long, only a portion of the touch electrodes 122 (e.g., one row / column or several rows / columns of touch electrodes 122) are driven during a single touch operation sub-period. A touch operation sub-period can be inserted between two adjacent display operation sub-periods. That is, in the long horizontal scan pause mode, the display operation sub-periods FP3DP1 to FP3DP10 and the touch operation sub-periods FP3TP1 to FP3TP10 are interleaved. In other words, in the long horizontal scan pause mode, the display operation can be paused during a long horizontal scan pause period (i.e., one touch operation sub-period) after driving a fixed number of gate lines (or outputting pixel data corresponding to these gate lines) to allow for touch operation.

[0057] During a touch operation sub-period (e.g., touch operation sub-period FP3TP1), the pixel data written to the line memory 111b is read out from the line memory 111b by the corresponding internal horizontal synchronization signal Hsync2 during the next display operation sub-period (e.g., display operation sub-period FP3DP2). In one embodiment, the data line is not necessarily equal to 0 volts during touch operation sub-periods FP3TP1 to FP3TP10; the data line may have a waveform with the same voltage difference / phase as the touch signal to reduce the load on the touch signal (i.e., load-free drive, LFD).

[0058] In long horizontal scan pause mode, the long horizontal scan pause typically occurs on the same gate line, making the drive time of this gate line much longer than that of other gate lines. Therefore, the degradation rate of circuit elements (such as thin-film transistors) located on this gate line is faster than that of circuit elements on other gate lines, resulting in poor display efficiency for this gate line. For example, prolonged conduction of thin-film transistors on certain gate lines causes severe aging of these gate lines, potentially leading to irreversible horizontal lines (also known as horizontal lines, long H lines, or horizontal gate line stripes) on the touch display panel 120. Switching between long horizontal scan pause mode and long vertical scan pause mode can prevent the formation of irreversible horizontal lines on the touch display panel 120.

[0059] High frame rate and low frame rate

[0060] In one embodiment, a long vertical scan pause mode can be used at high frame rates (HFR), and a long horizontal scan pause mode can be used at low frame rates (LFR). For example, the frame period FP2 can be 8.33 milliseconds (ms), and the frame rate (refresh rate, frame rate, or display frame rate) is the reciprocal of the frame period. Therefore, the frame rate corresponding to the frame period FP2 can be, for example, 120 Hertz (Hz). The frame period FP3 can be, for example, 16.67 milliseconds, and the frame rate can be, for example, 60 Hz. Since the frame period FP2 of the first data signal is shorter than the frame period FP3 of the second data signal (that is, frame periods FP2 and FP3 correspond to high frame rates and low frame rates, respectively), the first data signal corresponds to the long vertical scan pause mode, and the second data signal corresponds to the long horizontal scan pause mode. Using the long vertical scan pause mode at high frame rates can avoid the generation of unrecoverable horizontal lines on the touch display panel 120 when the horizontal period tL2 is short.

[0061] In one embodiment, the frame period FP2 of the first data signal is less than the frame period FP3 of the second data signal. The first data signal corresponds to a long vertical scan pause mode, and the second data signal corresponds to a long horizontal scan pause mode and an extended horizontal scan pause mode (extend H mode). The number of pulses (i.e., line count) of the frame period FP3 corresponding to the extended horizontal scan pause mode remains unchanged (e.g., equal to the number of pulses of the frame period FP2). On the other hand, the horizontal period tL3 corresponding to the extended horizontal scan pause mode is longer (e.g., greater than the horizontal period tL2), and the frame period FP3 corresponding to the extended horizontal scan pause mode is also longer (e.g., greater than the frame period FP2), so that the frame period FP3 corresponds to a low frame rate (e.g., lower than the frame rate corresponding to the frame period FP2). In the extended horizontal scan pause mode, the vertical blank period of the display operation does not need to be less than half of the frame period FP3. The vertical blank period of a frame may include the vertical front Porch (VFP), the vertical back Porch (VBP) time, or the vertical synchronization time corresponding to the external vertical synchronization signal Vsync1. Because the vertical leading edge time tVFP3' of FP3 during the frame period is not too long when using the extended horizontal scan pause mode, screen flickering can be avoided. Furthermore, the horizontal period tL3 corresponding to the extended horizontal scan pause mode is relatively long, making it easier for the voltage to reach the predetermined level.

[0062] In another embodiment, the second data signal may also correspond to the extended Vprochmode. In the extended Vprochmode, due to the longer vertical blanking period of a frame, the non-driving time of each gate line is longer, and the circuit elements (e.g., thin-film transistors) on the gate lines are not turned on for a long time, causing the potential of the liquid crystal capacitor to drop and affecting the expected grayscale value. In the next frame, the circuit elements on the gate lines turn on again and the liquid crystal capacitor is charged to adjust to the expected grayscale value, which may cause the touch display panel 120 to flicker.

[0063] Touch report rate

[0064] In one embodiment, frame duration FP2 and frame duration FP3 are not equal, but the touch report rate corresponding to frame duration FP2 can be equal to the touch report rate (or touch frame rate) corresponding to frame duration FP3. For example, frame duration FP2 and frame duration FP3 can be 8.33 milliseconds and 16.67 milliseconds, respectively, so that the frame rates are 120Hz and 60Hz, respectively, but the touch report rate can be 120Hz for both.

[0065] Specifically, in long vertical scan pause mode, the touch reporting rate can be equal to the frame rate. Therefore, during a frame period (e.g., frame period FP2), all display operations of a frame are performed, and a touch operation can scan the touch display panel 120 once. For example, FP2TP uses the touch signal 122S to drive the touch electrode 122 only during the touch operation period.

[0066] In long horizontal scan pause mode, the touch reporting rate may not be equal to the frame rate; it may be an integer multiple or a fractional multiple of the frame rate. Therefore, during a frame period (e.g., frame period FP3), all display operations for one frame can be performed, and touch operations can scan the entire touch display panel 120 an integer or non-integer number of times. For example, the touch display panel 120 may include 10 rows (or 10 columns) of touch electrodes 122. Touch operation sub-periods FP3TP1 to FP3TP5 can be used to perform the first scan of the 1st to 10th rows (columns) of touch electrodes 122, and touch operation sub-periods FP3TP6 to FP3TP10 can be used to perform the second scan of the 1st to 10th rows (columns) of touch electrodes 122. For example, during a touch operation sub-period, FP3TP1 uses touch signal 122S1a to drive the touch electrodes 122 in the first row (column), and during a touch operation sub-period, FP3TP6 uses touch signal 122S1b to drive the touch electrodes 122 in the first row (column). That is, a touch operation can scan the entire touch display panel 120 twice. Accordingly, the long horizontal scan pause mode can achieve a touch reporting rate different from the frame rate.

[0067] In short, by switching between long horizontal scan pause mode and long vertical scan pause mode, even if the frame period FP2 and frame period FP3 are not equal, and the frame rate corresponding to frame period FP2 is not equal to the frame rate corresponding to frame period FP3, the touch reporting rate corresponding to frame period FP2 can be equal to the touch reporting rate corresponding to frame period FP3.

[0068] In one embodiment, when switching from a high frame rate (e.g., 120Hz) to a low frame rate (e.g., 40Hz), the touch reporting rate can remain at 120Hz, but this application is not limited thereto. In another embodiment, when switching from a high frame rate (e.g., 120Hz) to a low frame rate (e.g., 40Hz), the touch reporting rate can be changed according to different design considerations (e.g., switching from 120Hz to 60Hz).

[0069] Delay

[0070] In one embodiment, pixel data may not be written to the line memory 111b during the long vertical scan pause mode. In another embodiment, the line memory 111b can be used to switch between the long horizontal scan pause mode and the long vertical scan pause mode. That is, in the long horizontal scan pause mode, pixel data can be written to the line memory 111b to extract time for touch operation. Correspondingly, in the long vertical scan pause mode, pixel data is also written to the line memory 111b.

[0071] Specifically, please refer to Figure 1 and Figure 4 In long horizontal scan pause mode, the frequency of the internal horizontal synchronization signal Hsync2 can be higher than the frequency of the external horizontal synchronization signal Hsync1. The receiving circuit 111a can write pixel data (e.g., raw data signal) to the line memory 111b according to the external horizontal synchronization signal Hsync1. Furthermore, the pixel data can be read from the line memory 111b at a faster data rate during frame intervals by FP3 according to the internal horizontal synchronization signal Hsync2. In this way, the display operation time can be compressed, and the time available for touch operation can be squeezed out.

[0072] like Figure 4 As shown, the horizontal period tL3' corresponding to the display operation sub-period FP3DP1 is less than the horizontal period tL3 of the external horizontal synchronization signal Hsync1, thus the touch operation sub-period FP3TP1 used for touch operation can be extracted. The horizontal period tL3 of the external horizontal synchronization signal Hsync1 can correspond to the time for writing pixel data corresponding to a gate line to the line memory 111b. The horizontal period tL3' can be the periodic time for applying voltage to a row of pixels in the touch display panel 120 (i.e., the time length between the start time of applying voltage to a row of pixels and the start time of applying voltage to another row of pixels), which is the periodic time for driving a gate line (i.e., the time length between the start time of driving one gate line and the start time of driving another gate line). The horizontal period tL3' can also correspond to the time for reading pixel data corresponding to a gate line from the line memory 111b.

[0073] For example, in long horizontal scan pause mode, the receiving circuit 111a can write the pixel data corresponding to the 20 gate lines received into the line memory 111b according to the external horizontal synchronization signal Hsync1 within one time unit. The internal horizontal synchronization signal Hsync2 can be used to control the pixel data corresponding to the 20 gate lines to be read from the line memory 111b at a faster data rate and transferred to the touch display panel 120, so as to perform the display operation of the pixel data corresponding to the 20 gate lines within one display operation sub-period (e.g., display operation sub-period FP3DP1). That is, the number of pixel data received in one time unit is equal to the number of pixel data output in the display operation sub-period of one time unit.

[0074] For example, in long horizontal scan pause mode, a specific number of pixel data (e.g., pixel data corresponding to the gate lines of columns 1 to 20) can be output to the touch display panel 120 in a display operation sub-period (e.g., display operation sub-period FP3DP1) corresponding to the internal horizontal synchronization signal Hsync2. After that, in the touch operation sub-period (e.g., touch operation sub-period FP3TP1), some other pixel data (e.g., pixel data corresponding to the gate lines of columns 21 to 27) are still continuously written (temporarily stored) into the line memory 111b in the touch operation sub-period FP3TP1 corresponding to the external horizontal synchronization signal Hsync1. Furthermore, the pixel data newly written to the line memory 111b (the pixel data corresponding to the gate lines of the 21st to 27th columns) will be read from the line memory 111b in the next display operation sub-period (e.g., display operation sub-period FP3DP2) corresponding to the internal horizontal synchronization signal Hsync2, and other pixel data (e.g., the pixel data corresponding to the gate lines of the 28th to 40th columns) will be written to the line memory 111b in the display operation sub-period FP3DP2 corresponding to the external horizontal synchronization signal Hsync1 and output to the touch display panel 120 corresponding to the internal horizontal synchronization signal Hsync2.

[0075] In long horizontal scan pause mode, because some pixel data (e.g., pixel data corresponding to the gate lines of columns 1 to 7) must be written (temporarily stored) in line memory 111b before the display operation period (e.g., display operation period FP3DP1), therefore, as Figure 2As shown, there may be a delay DL3 between the external horizontal synchronization signal Hsync1 (frame F3) and the internal horizontal synchronization signal Hsync2 (frame period FP3). The delay DL3 can be greater than or equal to the write time of the pixel data that needs to be written to the line memory 111b first, to avoid needing to read pixel data that has not yet been written to the line memory 111b during the display operation sub-period (e.g., display operation sub-period FP3DP1). For example, during the touch operation sub-period (e.g., touch operation sub-period FP3TP1), corresponding to 50 lines (meaning writing the pixel data corresponding to 50 gate lines to the line memory 111b), the line memory 111b can store pixel data corresponding to 100 rows of gate lines. Therefore, the number of lines corresponding to the delay DL3 can be greater than or equal to 50 but less than 100.

[0076] In one embodiment, in the long vertical scan pause mode, such as Figure 2 As shown, a delay DL2 may exist between the external horizontal synchronization signal Hsync1 (frame F2) and the internal horizontal synchronization signal Hsync2 (frame period FP2). In one embodiment, in order to dynamically switch between a long horizontal scan pause mode and a long vertical scan pause mode, in the long vertical scan pause mode, as... Figure 2 As shown, there may be a delay DL4 between the external horizontal synchronization signal Hsync1 (frame F4) and the internal horizontal synchronization signal Hsync2 (frame period FP4).

[0077] In one embodiment, the delays DL2, DL3, and DL4 between the external horizontal synchronization signal Hsync1 and the internal horizontal synchronization signal Hsync2 can correspond to the same number of lines (or pulses). For example, delays DL2, DL3, and DL4 can each correspond to 50 lines. In one embodiment, delay DL2 is proportional to the horizontal period tL2, delay DL3 is proportional to the horizontal period tL3, and the ratio between delays DL2 and DL3 is equal to the ratio between the horizontal period tL2 and the horizontal period tL3. In one embodiment, since the horizontal period tL2 is shorter than the horizontal period tL3, the duration of delay DL3 can be longer than the duration of delay DL2. In another embodiment, the number of lines corresponding to delays DL2 and DL4 can be greater than the number of lines corresponding to delay DL3.

[0078] Detect touch events or touch locations

[0079] In long vertical scan pause mode, such as Figure 3As shown, during the vertical leading edge time tVFP2' corresponding to the touch operation period FP2TP, the timing generation circuit 111c can control the touch circuit 114 to drive (all) touch electrodes 122 of the touch display panel 120 (time-division) in order to sense / detect touch events and / or touch positions occurring on the touch display panel 120.

[0080] In another embodiment, in the long vertical scan pause mode, the display operation time can be compressed to further extract the time used for touch operation. Please refer to... Figure 5 , Figure 5 This is a timing diagram illustrating an embodiment of this application. Figure 5 As shown, touch operations can be performed during touch operation sub-periods FP2TP1 and FP2TP2, where touch operation sub-period FP2TP2 corresponds to the vertical leading edge time tVFP2', and is equivalent to Figure 3 The FP2TP is shown during the touch operation.

[0081] Specifically, in the long vertical scan pause mode, the frequency of the internal horizontal synchronization signal Hsync2 can be higher than the frequency of the external horizontal synchronization signal Hsync1. The receiving circuit 111a can write pixel data (e.g., raw data signal) into the line memory 111b according to the external horizontal synchronization signal Hsync1. Furthermore, the pixel data can be read from the line memory 111b at a faster data rate during frame intervals by FP2 according to the internal horizontal synchronization signal Hsync2.

[0082] For example, in long vertical scan pause mode, the duration of one display operation sub-period (e.g., display operation sub-period FP2DP1) is equivalent to 32 horizontal periods tL2' of the internal synchronization signal Hsync2 (corresponding to 32 pulses / line count) or 31 horizontal periods tL2 of the external horizontal synchronization signal Hsync1 (corresponding to 31 pulses / line count). During one display operation sub-period (e.g., display operation sub-period FP2DP1), the receiving circuit 111a can write the pixel data corresponding to the 31 gate lines received into the line memory 111b according to the external horizontal synchronization signal Hsync1. Furthermore, the pixel data corresponding to the 32 gate lines can be read from the line memory 111b at a faster data rate during frame period FP2 according to the internal horizontal synchronization signal Hsync2.

[0083] In the long vertical scan pause mode, if the 32 horizontal cycles tL2' of the internal synchronization signal Hsync2 (corresponding to one display operation sub-period) are equivalent to the 31 horizontal cycles tL2 of the external horizontal synchronization signal Hsync1, and the display operation period FP2DPr can be divided into n (e.g., 45) display operation sub-periods FP2DP1~FP2DPn, then... Figure 3Compared to the display operation period FP2DP shown, the display operation period FP2DPr has n (e.g. 45) horizontal cycles tL2 of the external horizontal synchronization signal Hsync1, which can be used as the touch operation sub-period FP2TP1.

[0084] In other words, in the long vertical scan pause mode, such as Figure 5 As shown, touch operations can be performed during touch operation sub-period FP2TP1 and touch operation sub-period FP2TP2 corresponding to the vertical leading edge time tVFP2'. During touch operation sub-periods FP2TP1 and FP2TP2, timing generation circuit 111c can control touch circuit 114 to drive (all) touch electrodes 122 of touch display panel 120 (time-division) to sense / detect touch events and / or touch positions occurring on touch display panel 120. For example, it is possible to utilize Figure 5 The touch signal 122S1c drives the touch electrode 122 in the first row (column), utilizing Figure 5 The touch signal 122S2c drives the touch electrode 122 in the second row (column). When the touch operation is performed using the touch operation period FP2TP1, the vertical leading edge time tVFP2' (or the number of lines of the vertical leading edge) can be shortened, the bit rate can be reduced, the required bandwidth can be reduced, and thus power consumption can be saved.

[0085] In long vertical scan pause mode, if the 32 horizontal cycles tL2' of the internal synchronization signal Hsync2 (corresponding to one display operation sub-period) are equivalent to the 31 horizontal cycles tL2 of the external horizontal synchronization signal Hsync1, then the line memory 111b may need to temporarily store pixel data corresponding to one gate line (or pixel data corresponding to one line number) for one display operation sub-period (e.g., display operation sub-period FP2DP1). If the display operation period FP2DPr can be divided into 45 display operation sub-periods FP2DP1 to FP2DPn, then the line memory 111b may need to temporarily store pixel data corresponding to 45 gate lines. If the line memory 111b can store pixel data corresponding to 100 rows of gate lines, then the number of lines corresponding to delay DL2 can be greater than or equal to 45 but less than 100.

[0086] In another embodiment, in the long vertical scan pause mode, only when... Figure 5 Touch operation is performed during the touch operation sub-period FP2TP1, but not during the touch operation sub-period FP2TP2 corresponding to the vertical leading edge time tVFP2'. During touch operation sub-period FP2TP1, timing generation circuit 111c can control touch circuit 114 to (simultaneously) drive (partially or mutually short-circuited) touch electrodes 122 in order to sense / detect touch events.

[0087] In one embodiment, Figure 3 During the touch operation, FP2TP corresponds to the vertical leading edge time tVFP2' and Figure 5 The touch operation sub-period FP2TP2 corresponds to the vertical leading edge time tVFP2', but this application is not limited to this, the touch operation period or touch operation sub-period can also correspond to the vertical trailing edge time.

[0088] synchronous

[0089] In one embodiment, in order to synchronize the timing of the internal horizontal synchronization signal Hsync2 with the timing of the external horizontal synchronization signal Hsync1 and the external vertical synchronization signal Vsync1, the timing generation circuit 111c can perform a synchronization operation at regular intervals.

[0090] For example, such as Figure 4 As shown, in the long horizontal scan pause mode, the external horizontal synchronization signal Hsync1 and the internal horizontal synchronization signal Hsync2 can be synchronized at the start time point of each time unit (indicated by the white arrow). For example, the external horizontal synchronization signal Hsync1 can perform synchronization once every 20 horizontal cycles tL3.

[0091] For example, such as Figure 5 As shown, in the long vertical scan pause mode, the external horizontal synchronization signal Hsync1 and the internal horizontal synchronization signal Hsync2 can be synchronized at the start time of each display operation sub-period (e.g., display operation sub-period FP2DP1) (indicated by the white arrow). For example, the external horizontal synchronization signal Hsync1 can perform synchronization once every 31 horizontal cycles tL2.

[0092] In one embodiment, the vertical leading edge time tVFP2, tVFP3 or the vertical trailing edge time tVBP2, tVBP3 of frames F2 and F3 of the external horizontal synchronization signal Hsync1 can be equal to the vertical leading edge time tVFP2', tVFP3' or the vertical trailing edge time tVBP2', tVBP3' of frame period FP2, respectively.

[0093] In one embodiment, the delay DL2, vertical leading edge time tVFP2, or vertical trailing edge time tVBP2 corresponding to frame F2 may be different from or equal to the delay DL3, vertical leading edge time tVFP3, or vertical trailing edge time tVBP3 corresponding to frame F3. Since the touch operation can be performed at the vertical leading edge time tVFP2, increasing the vertical leading edge time tVFP2 can increase the duration of the touch operation. In one embodiment, the vertical leading edge time tVFP2 of frame F2 may be greater than the vertical leading edge time tVFP3 of frame F3.

[0094] In one embodiment, during a display operation sub-period (e.g. Figure 4 The display operation sub-periods shown are FP3DP1~FP3DP10 or Figure 5 The display operation sub-periods (FP2DP1~FP2DPn) shown can be used to output pixel data corresponding to the same number of gate lines, so the time length of each display operation sub-period can be equal. Similarly, the touch operation sub-periods (e.g. Figure 4 The touch operation sub-periods (FP3TP1~FP3TP10) shown can be used to drive the same number of touch electrodes 122, so the duration of each touch operation sub-period can be equal. Touch operation sub-periods (e.g. Figure 4 The number of touch operation sub-periods (FP3TP1 to FP3TP10) shown (e.g., 10) may be related to the number of rows (or columns) of touch electrodes 122.

[0095] same frame rate

[0096] In one embodiment, different of a long horizontal scan pause mode and a long vertical scan pause mode can be used at the same frame rate. Please refer to... Figure 1 and Figure 6 , Figure 6 This is a timing diagram of an embodiment of this application.

[0097] In one embodiment, the timing generation circuit 111c can be used to determine whether the external horizontal synchronization signal Hsync1 is in two consecutive frames (e.g., Figure 6 The horizontal period of frames F12-F14 shown (e.g.) Figure 6 Are the time lengths of the horizontal periods tL12 to tL14 shown the same? Based on the fact that the horizontal period tL13 is longer than the horizontal period tL12, the data signal output by FP12 during the frame period can correspond to the long vertical scan pause mode, and the data signal output by FP13 during the frame period can correspond to the long horizontal scan pause mode.

[0098] In one embodiment, frame duration FP12 and frame duration FP13 are equal, but the touch reporting rate corresponding to frame duration FP2 may not be equal to the touch reporting rate corresponding to frame duration FP3. For example, frame duration FP12 and frame duration FP13 may both be 11.11 milliseconds, resulting in a frame rate of 90Hz, but the touch reporting rates may be 90Hz and 180Hz, respectively.

[0099] In another embodiment, the microcontroller unit (MCU) (not shown) of the drive circuit 110 can use an algorithm to interpolate points so that the touch reporting rate in the long vertical scan pause mode can be different from the frame rate. For example, the frame period FP12 can be, for example, 11.11 milliseconds, resulting in a frame rate of 90Hz, but the touch reporting rate can be, for example, 180Hz. In this way, when switching from the long vertical scan pause mode to the long horizontal scan pause mode, the frame rate can remain at 90Hz, and the touch reporting rate can remain at 180Hz.

[0100] Dynamic switching between long vertical scan pause mode and long horizontal scan pause mode

[0101] like Figure 2 or Figure 6 As shown, dynamic switching is possible between long vertical scan pause mode and long horizontal scan pause mode. That is, during the switch from long vertical scan pause mode to long horizontal scan pause mode, it is not necessary to first enter sleep mode (or pause or power off the integrated circuit, IC) from long vertical scan pause mode, and then end sleep mode (or power on or power off the integrated circuit) to switch to long horizontal scan pause mode. Therefore, during the switch from long vertical scan pause mode to long horizontal scan pause mode, the touch display panel 120 will not dim but will continue to display the image. In other words, a frame using long vertical scan pause mode (e.g., frame period FP12) and a frame using long horizontal scan pause mode (e.g., frame period FP13) are two consecutive frames, and the end time of the frame using long vertical scan pause mode (e.g., frame period FP12) is connected to the start time of the frame using long horizontal scan pause mode (e.g., frame period FP13). For example, the vertical leading edge time tVFP12' of a frame using a long vertical scan pause mode (e.g., during frame FP12) is connected to the vertical trailing edge time tVBP13' of a frame using a long horizontal scan pause mode (e.g., during frame FP13).

[0102] In short, in one embodiment, the timing generation circuit 111c can be used to determine whether the time length of the external horizontal synchronization signal Hsync1 in two consecutive frames (e.g., horizontal periods tL12, tL13) is the same, in order to determine whether to switch to the long vertical scan pause mode or the long horizontal scan pause mode.

[0103] In another embodiment, the timing generation circuit 111c can determine whether to switch to a long vertical scan pause mode or a long horizontal scan pause mode based on the received external horizontal synchronization signal Hsync1 and by detecting the duration of the horizontal period (e.g., horizontal period tL12). For example, based on the duration of the horizontal period tL12, the data signal output by FP12 during the frame period can correspond to the long vertical scan pause mode. Based on the duration of the horizontal period tL13, the data signal output by FP13 during the frame period can correspond to the long horizontal scan pause mode.

[0104] In another embodiment, the timing generation circuit 111c can determine whether to switch to a long vertical scan pause mode or a long horizontal scan pause mode based on the received command. For example, based on the command received by the timing generation circuit 111c, the data signal output by FP12 during the frame period can correspond to the long vertical scan pause mode, and the data signal output by FP13 during the frame period can correspond to the long horizontal scan pause mode.

[0105] Figure 7 This is a timing diagram of one embodiment of the present application. In another embodiment, the timing generation circuit 111c can determine whether to switch to a long vertical scan pause mode or a long horizontal scan pause mode based on the received external synchronization signal Hsync1 by detecting the duration tBLLP (Blanking or Low Power interval) of the horizontal period (e.g., horizontal periods tL22, tL23), the horizontal active line (HACT) period (RGB), the horizontal back porch (HBP) or the horizontal front porch (HFP) duration tBLLP, tHACT, tHBP, tHFP. Frames F22 and F23 may respectively include a vertical sync end packet (VS), a horizontal sync start packet (HS), a low power mode (LPM), a low power blanking period (BLLP), a horizontal active line (HACT) period (RGB), and a horizontal back porch (HBP) or a horizontal front porch (HFP).

[0106] In one embodiment, the durations of the horizontal periods tL22, tL23, low-power blank period BLLP, horizontal synchronization pulse line period RGB, and horizontal trailing edge HBP or horizontal leading edge HFP are actually determined by the preceding circuitry (not shown in the diagram). Figure 1The timing is determined by the video packet stream 100 transmitted from the front-end circuit. In other words, the front-end circuit determines whether the frame rate changes. The timing generation circuit 111c passively switches internally based on the video packet stream 100 from the front-end circuit (timing switching corresponding to long vertical scan pause mode or long horizontal scan pause mode).

[0107] In one embodiment, the touch display panel 120 may include a display panel for display operations and a touch screen for touch operations. The touch screen may be embedded within the display panel.

[0108] In one embodiment, the driving circuit 110 may include touch and display driver integrated circuitry and / or other driving circuitry. The transmission interface may include a Mobile Industry Processor Interface (MIPI) and / or other transmission interfaces.

[0109] For ease of explanation, the drawings in this application are merely illustrative to facilitate understanding, and their detailed proportions can be adjusted according to design requirements. The term "comprising" as used in this application is an open-ended term and should be interpreted as "including but not limited to." The terms "first," "second," etc., used in this application are only used to distinguish different elements and do not impose any restrictions on their order or coexistence. The phrase "when..." as used in this application can mean "if," "under certain conditions," "immediately when...", "immediately after...", or "after..." and after a (tolerable / negligible) period of time." Embodiments of this application can be combined in various ways without conflict.

[0110] In summary, the driving circuit of this application can automatically switch between a long horizontal scan pause mode and a long vertical scan pause mode based on the period corresponding to the received video packet stream, such as whether the horizontal period lengths of two consecutive frames are the same, thereby ensuring display quality. This application can use a long vertical scan pause mode at high frame rates and a long horizontal scan pause mode at low frame rates to save power. Using a long vertical scan pause mode at high frame rates can avoid the generation of irreversible horizontal lines on the touch display panel when the horizontal period is short. Using a long horizontal scan pause mode and an extended horizontal scan pause mode at low frame rates, the vertical blank period is not too long, thus avoiding screen flickering and other display abnormalities. Because the horizontal period is longer when using a long horizontal scan pause mode and an extended horizontal scan pause mode at low frame rates, the voltage is more likely to reach the predetermined level. Furthermore, in this application, the touch reporting rate corresponding to the high frame rate can be equal to the touch reporting rate corresponding to the low frame rate.

[0111] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A timing control circuit, characterized in that, include: A receiving circuit; as well as A line memory, coupled to the receiving circuit, wherein the line memory is used to: A horizontal synchronization signal is received, wherein the horizontal synchronization signal includes a plurality of first pulses and a plurality of second pulses, each of the plurality of first pulses having a first period and each of the plurality of second pulses having a second period; Output a first data signal during the first frame; and A second data signal is output during the second frame. The end time of the first frame coincides with the start time of the second frame. Wherein, one of the first data signal and the second data signal corresponds to a long horizontal scan pause mode, and the other of the first data signal and the second data signal corresponds to a long vertical scan pause mode. Wherein, based on the time length difference between the first cycle and the second cycle, the first data signal and the second data signal respectively correspond to different ones in the long horizontal scan pause mode and the long vertical scan pause mode.

2. The timing control circuit as described in claim 1, characterized in that, The receiving circuit is used to: Receive a first external signal, wherein the first external signal corresponds to the first period; and Receive a second external signal, wherein the second external signal corresponds to the second period, the first period and the second period are not equal, and both the first period and the second period are horizontal periods, horizontal synchronization pulse line periods, low power blank periods, horizontal trailing edges or horizontal leading edges.

3. The timing control circuit as described in claim 1, characterized in that, The receiving circuit is used to: Receive a second external signal, wherein the second external signal corresponds to the second period. Wherein, based on the second period, the second data signal corresponds to the long vertical scan pause mode or the long horizontal scan pause mode.

4. The timing control circuit as described in claim 1, characterized in that, Since the first frame period of the first data signal is longer than the second frame period of the second data signal, the first data signal corresponds to the long horizontal scan pause mode. Since the first frame period of the first data signal is shorter than the second frame period of the second data signal, the first data signal corresponds to the long vertical scan pause mode.

5. The timing control circuit as described in claim 1, characterized in that, The first frame period of the first data signal is not equal to the second frame period of the second data signal, and a first touch reporting rate corresponding to the first frame period is equal to a second touch reporting rate corresponding to the second frame period.

6. The timing control circuit as described in claim 1, characterized in that, The first data signal and the second data signal correspond to the long horizontal scan pause mode and the extended horizontal scan pause mode, respectively.

7. The timing control circuit as described in claim 1, characterized in that, The receiving circuit is used to: Receive a first external signal, wherein the first external signal corresponds to the first period, and the first data signal and the first external signal have a first delay, the first delay being proportional to the first period; and A second external signal is received, wherein the second external signal corresponds to the second period, and there is a second delay between the first data signal and the second external signal, the second delay being proportional to the second period, and the first delay being unequal to the second delay.

8. The timing control circuit as described in claim 7, characterized in that, The ratio between the first delay and the second delay is equal to the ratio between the first period and the second period.

9. The timing control circuit as described in claim 1, characterized in that, The first frame period of the first data signal is equal to the second frame period of the second data signal, and the first touch reporting rate corresponding to the first data signal is not equal to the second touch reporting rate corresponding to the second data signal.

10. The timing control circuit as described in claim 1, characterized in that, The first vertical leading edge time corresponding to the first data signal is not equal to the second vertical leading edge time corresponding to the first data signal.

11. A timing control method, characterized in that, include: A horizontal synchronization signal is received, wherein the horizontal synchronization signal includes a plurality of first pulses and a plurality of second pulses, each of the plurality of first pulses having a first period and each of the plurality of second pulses having a second period; Output a first data signal during the first frame; and A second data signal is output during the second frame. The end time of the first frame coincides with the start time of the second frame. Wherein, one of the first data signal and the second data signal corresponds to a long horizontal scan pause mode, and the other of the first data signal and the second data signal corresponds to a long vertical scan pause mode. Wherein, based on the time length difference between the first cycle and the second cycle, the first data signal and the second data signal respectively correspond to different ones in the long horizontal scan pause mode and the long vertical scan pause mode.

12. The timing control method as described in claim 11, characterized in that, Also includes: Receive a first external signal, wherein the first external signal corresponds to the first period; and Receive a second external signal, wherein the second external signal corresponds to the second period, the first period and the second period are not equal, and both the first period and the second period are horizontal periods, horizontal synchronization pulse line periods, low power blank periods, horizontal trailing edges or horizontal leading edges.

13. The timing control method as described in claim 11, characterized in that, Also includes: Receive a second external signal, wherein the second external signal corresponds to the second period. Wherein, based on the second period, the second data signal corresponds to the long vertical scan pause mode or the long horizontal scan pause mode.

14. The timing control method as described in claim 11, characterized in that, Since the first frame period of the first data signal is longer than the second frame period of the second data signal, the first data signal corresponds to the long horizontal scan pause mode. Since the first frame period of the first data signal is shorter than the second frame period of the second data signal, the first data signal corresponds to the long vertical scan pause mode.

15. The timing control method as described in claim 11, characterized in that, The first frame period of the first data signal is not equal to the second frame period of the second data signal, and a first touch reporting rate corresponding to the first frame period is equal to a second touch reporting rate corresponding to the second frame period.

16. The timing control method as described in claim 11, characterized in that, The first data signal and the second data signal correspond to the long horizontal scan pause mode and the extended horizontal scan pause mode, respectively.

17. The timing control method as described in claim 11, characterized in that, Also includes: Receive a first external signal, wherein the first external signal corresponds to the first period, and the first data signal and the first external signal have a first delay, the first delay being proportional to the first period; and A second external signal is received, wherein the second external signal corresponds to the second period, and there is a second delay between the first data signal and the second external signal, the second delay being proportional to the second period, and the first delay being unequal to the second delay.

18. The timing control method as described in claim 17, characterized in that, The ratio between the first delay and the second delay is equal to the ratio between the first period and the second period.

19. The timing control method as described in claim 11, characterized in that, The first frame period of the first data signal is equal to the second frame period of the second data signal, and the first touch reporting rate corresponding to the first data signal is not equal to the second touch reporting rate corresponding to the second data signal.

20. The timing control method as described in claim 11, characterized in that, The first vertical leading edge time corresponding to the first data signal is not equal to the second vertical leading edge time corresponding to the first data signal.

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