Graphic information processing methods, systems and computer-readable storage media

Abstract

This invention discloses a graphic information processing method, system, and computer-readable storage medium, comprising: preprocessing an acquired integrated circuit layout to obtain a graphic library; calculating an index for each polygon in the graphic library based on a preset evaluation formula to obtain an evaluation index value corresponding to each polygon, wherein the evaluation index value is used to characterize the occurrence probability of a unit pattern of a preset polygon, and the unit pattern is used to characterize a repeating pattern including the minimum size of the preset polygon; sorting the unit patterns of the polygons according to the evaluation index values ​​to obtain an instance set; performing pattern expansion on the elements in the instance set based on a preset simulated annealing algorithm to obtain repeating graphic information; and updating the integrated circuit layout according to the repeating graphic information to obtain a target layout. In this embodiment of the invention, by performing pattern expansion and index calculation on the polygons, the efficiency of repeating pattern extraction can be improved and computing resources can be saved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of circuit electronics, and particularly relates to a graphic information processing method and system and a computer readable storage medium. BACKGROUND

[0002] With the continuous reduction of the process size of super large scale integrated circuits, the feature size of chip manufacturing is also continuously reduced. Due to the influence of diffraction effect and chemical reaction effect of photoresist under light source irradiation, there is a deviation between the lithography pattern and the original layout pattern at the design time. In order to solve this problem, the optical correction technology is gradually derived. The graphic information processing technology compensates for the transfer distortion of the pattern in the photoetching process by pre-correcting the design layout. The generation of this technology has largely solved the above-mentioned transfer distortion problem and is widely used in the field of photoetching. However, for super large scale integrated circuits, with the increase of design complexity, the complexity of the layout is also increasing. Since the optical correction adopts a complex calculation model, the number of mask layout of each layer can reach hundreds of billions, and each pattern needs to be corrected, which is a huge workload. Moreover, due to the hierarchical design, there are many repeated pattern modes in most layouts. Although there are some methods for extracting repeated pattern modes based on the original hierarchy of the layout, the original unit hierarchy of the layout often overlaps together, and the effect of this kind of layout processing method largely depends on the design mode of the layout, thereby leading to low extraction efficiency of repeated pattern modes and large consumption of computing resources. SUMMARY

[0003] The present application aims to at least solve one of the technical problems existing in the prior art, and provides a graphic information processing method, system and computer readable storage medium, which can improve the extraction efficiency of repeated pattern modes and save computing resources.

[0004] In a first aspect, the present application provides a graphic information processing method, comprising:

[0005] preprocessing the obtained integrated circuit layout to obtain a graphic library, wherein the graphic library is used to store a polygon data set of the integrated circuit layout;

[0006] calculating an evaluation index value corresponding to each polygon in the graphic library based on a preset evaluation formula, wherein the evaluation index value is used to represent the occurrence probability of a preset unit mode of the polygon, and the unit mode is used to represent a repeated pattern including the minimum size of the preset polygon;

[0007] sorting the unit mode of the polygon according to the evaluation index value to obtain an instance set;

[0008] based on the preset simulated annealing algorithm, the elements in the instance set are pattern expanded to obtain repeated graphic information;

[0009] the integrated circuit layout is updated according to the repeated graphic information to obtain a target layout.

[0010] The graphic information processing method provided by the embodiment of the present application has at least the following beneficial effects: first, the integrated circuit layout obtained is preprocessed to obtain a graphic library for storing a polygon data set, then, based on a preset evaluation formula, an evaluation index value corresponding to each polygon in the graphic library is calculated to obtain the occurrence probability of the preset unit pattern of the polygon, then, the elements in the instance set are pattern expanded according to the evaluation index value to obtain the instance set, which facilitates subsequent accurate finding of the repeated graphic information, comprehensive searching of the repeated graphic information is realized, then, based on the preset simulated annealing algorithm, the elements in the instance set are pattern expanded to obtain the repeated graphic information, the accuracy of searching for the repeated graphic information is improved, finally, the integrated circuit layout is updated according to the repeated graphic information to obtain a target layout, automatic extraction of the repeated pattern of the integrated circuit layout is realized, the calculation amount of optical proximity correction and other operations is reduced, and the calculation resources are saved.

[0011] According to some embodiments of the present application, the preprocessing of the integrated circuit layout obtained to obtain a graphic library comprises:

[0012] graphic extraction is performed on each layer of the integrated circuit layout to obtain a polygon data set of the integrated circuit layout, wherein the polygon data set comprises vertex list information of a polygon;

[0013] all polygons in the polygon data set are encoded according to the vertex list information to obtain polygon class information, wherein the polygon class information is used to represent position information and encoding information of the polygon in the layer;

[0014] the graphic library is generated according to the polygon class information and the polygon data set.

[0015] According to some embodiments of the present application, the index calculation of each polygon in the graphic library based on the preset evaluation formula to obtain an evaluation index value corresponding to each polygon comprises:

[0016] the preset polygon in the graphic library is expanded to obtain a unit pattern corresponding to the polygon;

[0017] the unit pattern is calculated to obtain a pattern area and a repetition number of the unit pattern;

[0018] An index of the pattern area and the repetition number is calculated based on a preset evaluation formula to obtain an evaluation index value corresponding to each polygon.

[0019] According to some embodiments of the present application, the unit patterns of the polygons are sorted according to the evaluation index values to obtain an instance set, including:

[0020] A pattern library for storing the unit patterns of the polygons is constructed.

[0021] The unit patterns of the polygons are sorted in descending order according to the evaluation index values to obtain a descending sequence, and the descending sequence is stored in the pattern library to obtain the instance set.

[0022] According to some embodiments of the present application, the pattern library includes frame information; and the elements in the instance set are extended in pattern based on a preset simulated annealing algorithm to obtain repetition pattern information, including:

[0023] A first element in the instance set is extracted, and frame information corresponding to the unit pattern of the first element is extracted from the pattern library;

[0024] The frame information is extended in pattern according to a preset extension step and direction information to obtain a plurality of extension results;

[0025] The stability of each extension result is detected to obtain a unit extension pattern corresponding to the extension result;

[0026] An index of the unit extension pattern is calculated according to the evaluation formula to obtain an extension index value;

[0027] The extension index value is compared with the evaluation index value based on a preset simulated annealing algorithm to obtain a comparison result;

[0028] In a case where the comparison result is that the extension index value is less than the evaluation index value, a backtracking calculation is performed on the unit extension pattern according to a backtracking algorithm in the simulated annealing algorithm to obtain a backtracking unit pattern, and an area limitation is performed on the backtracking unit pattern according to an acceptance criterion formula in the simulated annealing algorithm to obtain the repetition pattern information;

[0029] In a case where the comparison result is that the extension index value is greater than the evaluation index value, and the unit extension pattern satisfies a preset area condition, the unit extension pattern is taken as a first element, and the elements in the instance set are continuously extended in pattern until all the elements in the instance set are traversed to obtain the repetition pattern information.

[0030] According to some embodiments of the present application, the expansion result comprises an expansion frame boundary; the stability detection on each expansion result to obtain a unit expansion mode corresponding to the expansion result comprises:

[0031] cutting detection on the expansion frame boundary and the polygons in the instance set to obtain a detection result;

[0032] when the detection result is determined as the expansion frame boundary is not cut by the polygons, the unit expansion mode is determined according to the expansion frame boundary;

[0033] when the detection result is determined as the expansion frame boundary is cut by the polygons, the mode expansion on the expansion frame boundary is continued until the expansion frame boundary after the mode expansion is not cut by the polygons.

[0034] According to some embodiments of the present application, the backtracking calculation on the unit expansion mode according to the backtracking algorithm in the simulated annealing algorithm to obtain a backtracking unit mode, and the area limitation on the backtracking unit mode according to the acceptance criterion formula in the simulated annealing algorithm to obtain the repetitive graphic information comprises:

[0035] determination of the expansion times according to the backtracking algorithm;

[0036] for each expansion within the expansion times, index calculation on the unit expansion mode based on the evaluation formula to obtain a backtracking index value;

[0037] generation of a backtracking index set according to the expansion times and the backtracking index value;

[0038] when each element in the backtracking index set is less than the expansion index value, backtracking operation is performed on the unit expansion mode until the expansion index value of the unit expansion mode is greater than the evaluation index value to obtain the backtracking unit mode;

[0039] when a target element in the backtracking index set is greater than the expansion index value, the backtracking unit mode is determined according to the backtracking index value of the target element;

[0040] probability calculation on the backtracking unit mode according to the acceptance criterion formula to obtain a mode probability value;

[0041] when the mode probability value is greater than a preset target probability value, the backtracking unit mode is taken as a first element, and the mode expansion on the elements in the instance set is continued to obtain the repetitive graphic information.

[0042] According to some embodiments of the present application, after the integrated circuit layout is updated according to the repetitive pattern information to obtain a target layout, the method further comprises:

[0043] According to the evaluation formula, index values of all unit patterns in the target layout are calculated to obtain target index values.

[0044] In a second aspect, the present application provides a pattern information processing system, comprising:

[0045] A layout processing module is configured to pre-process the obtained integrated circuit layout to obtain a pattern library, wherein the pattern library is configured to store a polygon data set of the integrated circuit layout.

[0046] An index calculation module is configured to calculate index values of each polygon in the pattern library based on a preset evaluation formula, wherein the evaluation index value is configured to represent the occurrence probability of a unit pattern of the polygon, and the unit pattern is configured to represent a repetitive pattern including the minimum size of the polygon.

[0047] A pattern sorting module is configured to sort the unit patterns of the polygons according to the evaluation index values to obtain an instance set.

[0048] A pattern expansion module is configured to expand the elements in the instance set based on a preset simulated annealing algorithm to obtain repetitive pattern information.

[0049] A layout updating module is configured to update the integrated circuit layout according to the repetitive pattern information to obtain a target layout.

[0050] In a third aspect, the present application provides a computer readable storage medium, wherein the computer readable storage medium stores computer executable instructions, and the computer executable instructions are configured to make a computer execute the pattern information processing method of the first aspect.

[0051] Other features and advantages of the present application will be further described in the following description, and part of them will become apparent from the description, or will be understood by those skilled in the art. The purposes and other advantages of the present application can be achieved and obtained by the structures specifically pointed out in the description and the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0052] The accompanying drawings are used to provide a further understanding of the technical solutions of the present application, and constitute a part of the specification, and are used to explain the technical solutions of the present application together with the embodiments of the present application, and do not constitute a limitation to the technical solutions of the present application.

[0053] Figure 1is a flow chart of a graphic information processing method provided by an embodiment of the present application;

[0054] Figure 2 is Figure 1 is a specific method flow chart of step S101 in

[0055] Figure 3 is Figure 1 is a specific method flow chart of step S102 in

[0056] Figure 4 is Figure 1 is a specific method flow chart of step S103 in

[0057] Figure 5 is Figure 1 is a specific method flow chart of step S104 in

[0058] Figure 6 is Figure 5 is a specific method flow chart of step S504 in

[0059] Figure 7 is Figure 5 is a specific method flow chart of step S506 in

[0060] Figure 8 is a flow chart of a graphic information processing method provided by another embodiment of the present application;

[0061] Figure 9 is a structural schematic diagram of a graphic information processing system provided by an embodiment of the present application;

[0062] Figure 10 is a schematic diagram of a layout to be processed provided by a specific example of the present application;

[0063] Figure 11 is a schematic diagram of a unit pattern provided by a specific example of the present application;

[0064] Figure 12 is a schematic diagram of pattern extension provided by a specific example of the present application;

[0065] Figure 13 is a schematic diagram of pattern extension provided by another specific example of the present application;

[0066] Figure 14 is a schematic diagram of reaching a stable state provided by a specific example of the present application;

[0067] Figure 15 is a hardware structural schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0068] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0069] It should be noted that although the logical order is shown in the flowchart, in some cases, the steps shown or described can be performed in an order different from that in the flowchart. The terms "first", "second", etc. in the specification and claims and the above-described drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence.

[0070] The present application provides a kind of graphic information processing method, system and computer readable storage medium, first, the integrated circuit layout obtained is preprocessed, obtain the graphic library for storing polygon data set, then based on the index calculation of each polygon in graphic library according to preset evaluation formula, obtain the evaluation index value corresponding to each polygon, so as to obtain the occurrence probability of the unit mode of the preset polygon, then, according to evaluation index value, the elements in instance set are expanded in mode, obtain instance set, it is convenient for subsequent accurate finding of repeated graphic information, realize the comprehensive search of repeated graphic information, again based on the mode expansion of the elements in instance set according to preset simulated annealing algorithm, obtain repeated graphic information, improve the accuracy of finding repeated graphic information, finally, according to repeated graphic information, integrated circuit layout is updated, obtain target layout, realize the automatic extraction of the repeated mode of inheritance circuit layout, reduce the calculation amount of optical proximity correction and other operations, save computing resources.

[0071] The embodiments of the present application will be further described below with reference to the accompanying drawings.

[0072] Reference Figure 1 , Figure 1 It is the flowchart of the graphic information processing method provided by an embodiment of the present application, and the graphic information processing method includes but is not limited to steps S101 to S105.

[0073] Step S101: the integrated circuit layout obtained is preprocessed to obtain a graphic library;

[0074] It should be noted that the graphic library is used to store the polygon data set of integrated circuit layout.

[0075] In some embodiments, the obtained inheritance circuit layout is preprocessed to obtain a graphic library, wherein the graphic library stores the polygon data set obtained by scanning and analyzing the integrated circuit layout, so as to facilitate subsequent classification and matching of polygon mode.

[0076] Step S102: performing index calculation on each polygon in the graphic library based on a preset evaluation formula to obtain an evaluation index value corresponding to each polygon;

[0077] It should be noted that the evaluation index value is used to represent the occurrence probability of the unit pattern of the polygon, and the unit pattern is used to represent a repeating pattern including a minimum size of the preset polygon.

[0078] In some embodiments, the index calculation is performed on each polygon in the graphic library based on a preset evaluation formula to obtain an evaluation index value corresponding to each polygon, thereby improving the accuracy of the calculation of the repeating pattern in the integrated circuit layout and improving the accuracy of the calculation, facilitating the subsequent determination of the repeating pattern.

[0079] Step S103: sorting the unit pattern of the polygon according to the evaluation index value to obtain an instance set;

[0080] In some embodiments, the unit pattern of the polygon is sorted in descending order according to the evaluation index value, and the frame of the polygon is inserted into the pattern library as a spatial index tree element to obtain an instance set, thereby facilitating the calling of the elements in the instance set and improving the efficiency of the calculation of the repeating pattern.

[0081] Step S104: performing pattern expansion on the elements in the instance set based on a preset simulated annealing algorithm to obtain repeating pattern information;

[0082] In some embodiments, the elements in the instance set are expanded based on a preset simulated annealing algorithm to obtain repeating pattern information, thereby seeking the possibility of jumping out of the local optimal solution with the smallest possible calculation cost and approaching the global optimal solution.

[0083] It should be noted that the simulated annealing algorithm in the present embodiment is compared with the traditional simulated annealing algorithm, and a backtracking mechanism is provided to accurately determine the pattern and avoid misjudgment.

[0084] Step S105: updating the integrated circuit layout according to the repeating pattern information to obtain a target layout.

[0085] In some embodiments, after obtaining the repeating pattern information, the repeating pattern information is removed from the integrated circuit layout to obtain a final target layout, thereby removing the repeating pattern and reducing the calculation scale of the full-chip optical proximity correction.

[0086] Referring to Figure 2 , Figure 2 is Figure 1 the specific method flowchart of step S101 in

[0087] Step S201: performing graphic extraction on each layer of the integrated circuit layout to obtain a polygon data set of the integrated circuit layout;

[0088] It should be noted that the polygon data set includes vertex list information of the polygon.

[0089] In some embodiments, it is necessary to first perform graphic extraction on the fill polygon data of each layer of the circuit layout to obtain the fill polygon of each layer, and then generate the polygon data set according to the plurality of fill polygons, so as to facilitate subsequent generation of the graphic library.

[0090] It should be noted that the database file format of the integrated circuit layout data storage is commonly used in two formats of GDSII (Geometrical Data base for Information Interchange, information exchange geometry database) and OASIS (Open Artwork System Interchange Standard, open artwork system interchange standard). The file is stored in binary, contains the geometric shape of the plane in the integrated circuit layout, text or label, and other related information and can be composed of a hierarchical structure. The GDSII data can be used to reconstruct the layout information and can be used as a photomask. In the process of performing graphic extraction on the integrated circuit layout in the embodiment, GDSII needs to be parsed to extract various information of the layout from the binary file, including the layout layer, the module unit hierarchy, the graphic element, and the like, so as to convert each layer of the integrated circuit layout into a data set composed of different polygon vertex arrangements. Among them, the fill polygon data of each layer is mainly extracted here, and the fill polygon is saved in the clockwise or counterclockwise order in the polygon data set. The vertex coordinate values of each corner point are generated according to the vertex coordinate values, and the vertex list information is not limited in the embodiment.

[0091] Step S202: encoding all polygons in the polygon data set according to the vertex list information to obtain polygon class information;

[0092] It should be noted that the polygon class information is used to represent the position information and the encoding information of the polygon in the layer.

[0093] In some embodiments, all polygons in the polygon data set are scanned according to the vertex list information, and the scanned polygons are encoded to obtain the polygon class information, so as to facilitate subsequent searching and analysis of the polygon and save the calculation time.

[0094] It should be noted that the position information in the polygon class information includes but is not limited to the polygon frame, polygon number, polygon symmetry number, polygon symmetry type, vertex list, access record and the like, and the encoding information includes but is not limited to the vertex ordering, center movement distance, polygon symmetry type judgment and the like.

[0095] Step S203: generating a pattern library according to the polygon class information and the polygon data set.

[0096] In some embodiments, the pattern library is generated according to the polygon and the polygon data set, thereby facilitating subsequent classification and matching of patterns.

[0097] Referring to Figure 3 , Figure 3 is Figure 1 a specific method flowchart of step S102, and step S102 includes but is not limited to steps S301 to S303.

[0098] Step S301: performing extension processing on a preset polygon in the pattern library to obtain a unit pattern corresponding to the polygon;

[0099] In some embodiments, the extension processing is performed on the preset polygon in the pattern library to obtain a unit pattern corresponding thereto, thereby improving the accuracy of repeated pattern recognition.

[0100] It should be noted that the pattern refers to a boundary box containing a plurality of complete polygons. The repeated pattern refers to a pattern repeated more than twice in the layout.

[0101] It should be noted that, unlike the general definition, the pattern in the present embodiment requires to contain complete polygons in the integrated circuit layout, that is, the frame line cannot cut the polygons it contains. The unit pattern refers to a repeated pattern with the smallest size containing the preset polygon p in the layout.

[0102] It should be noted that in step S301, the extension processing is performed from the preset polygon in the pattern library until all polygons in the pattern library are traversed, thereby obtaining a unit pattern corresponding to each polygon.

[0103] Step S302: calculating the unit pattern to obtain a pattern area and a repetition number of the unit pattern;

[0104] In some embodiments, the unit pattern is calculated to obtain a pattern area S and a repetition number C of the unit pattern in the integrated circuit layout, thereby facilitating subsequent calculation of the corresponding evaluation index value.

[0105] Step S303: Calculate the pattern area and repetition count based on the preset evaluation formula to obtain the evaluation index value corresponding to each polygon.

[0106] In some embodiments, the pattern area S and the number of repetitions C are calculated based on a preset evaluation formula to obtain the evaluation index value corresponding to each polygon, thereby improving the accuracy of the calculation of repeated graphics in the layout and reducing the computational load of operations such as optical proximity correction.

[0107] It should be noted that the specific formula for calculating the pattern area and repetition count based on the evaluation formula is shown in the following formula (1):

[0108] θ=S(C-1) (1)

[0109] Reference Figure 4 , Figure 4 yes Figure 1 The flowchart of the specific method of step S103 is as follows: step S103 includes, but is not limited to, steps S401 to S402.

[0110] Step S401: Construct a pattern library for storing unit patterns of polygons;

[0111] Step S402: Sort the unit patterns of the polygon in descending order according to the evaluation index values ​​to obtain a descending sequence, and store the descending sequence in the pattern library to obtain an instance set.

[0112] In some embodiments, steps S401 to S402 involve constructing a pattern library for storing unit models of polygons, sorting the polygon unit patterns in descending order according to evaluation index values, recording the results of the descending sort to obtain a descending sequence, storing the descending sequence in the pattern library to obtain an instance set, which facilitates subsequent expansion of the elements in the instance set and avoids the situation of disordered expansion order.

[0113] It should be noted that since polygons are located in different areas of the layout, their shapes and sizes vary greatly. Therefore, storing their spatial indexes is crucial. In this embodiment, their borders are inserted as elements of a spatial index tree (also known as an rtree) to facilitate rapid spatial indexing. Furthermore, for a given polygon instance, its borders can be quickly obtained through the spatial index tree. Therefore, in this embodiment, polygons are inserted as objects of each rtree element.

[0114] Reference Figure 5 , Figure 5 yes Figure 1 The flowchart of the specific method of step S104 is as follows: step S104 includes, but is not limited to, steps S501 to S507.

[0115] It should be noted that the mode library includes the frame information.

[0116] Step S501: Extract the first element in the instance set, and extract the frame information corresponding to the unit mode of the first element in the mode library;

[0117] In some embodiments, the first element in the instance set is extracted, and the frame information corresponding to the unit mode of the first element in the mode library is extracted, so as to facilitate subsequent expansion of the frame information.

[0118] It should be noted that the frame information includes frame attributes such as frame position and frame shape, and includes frame intersection judgment, position relationship judgment and other frame methods, and the present embodiment does not make specific limitations.

[0119] Step S502: Mode expansion is performed on the frame information according to a preset expansion step and direction information, to obtain a plurality of expansion results;

[0120] In some embodiments, the mode expansion is performed on the frame information according to a preset expansion step and direction information, to obtain a plurality of expansion results, wherein the expansion step can be controlled through an external parameter interface, and the user can balance the running speed and the mode accuracy through the selection of the parameter.

[0121] It should be noted that the mode expansion is performed in the same direction in each direction, so the direction information can be selected by the user as needed.

[0122] Step S503: Stability detection is performed on each expansion result, to obtain a unit expansion mode corresponding to the expansion result;

[0123] In some embodiments, stability detection is performed on each expansion result, to obtain a unit expansion mode corresponding to the expansion result, so as to avoid the case that the bounding box cuts the polygon.

[0124] It should be noted that in the process of stability detection on the expansion result, the frame of the mode needs to be expanded to a square. The specific method is to take the maximum value of the frame width and height in the frame information of the mode, and expand the frame to a square frame according to the maximum value. Then, the mode frame is enlarged by the center scaling method, and is made stable. The specific implementation will be described in the subsequent steps.

[0125] Step S504: Index calculation is performed on the unit expansion mode according to an evaluation formula, to obtain an expansion index value;

[0126] In some embodiments, the unit expansion pattern after the mode expansion is subjected to index calculation according to the evaluation formula to obtain an expansion index value, so as to facilitate subsequent determination of the expansion stop condition.

[0127] It is worth noting that in each expansion process, new patterns can be generated. After the generation of the new patterns is determined, the patterns are stored in a newly established pattern library, and all the patterns are arranged in descending order according to their evaluation index values. The new patterns can cause the evaluation index values of the patterns to increase or decrease. Therefore, only the first element is taken out as the starting point of the next expansion.

[0128] Step S505: Comparing the expansion index value with the evaluation index value based on the preset simulated annealing algorithm to obtain a comparison result;

[0129] In some embodiments, the expansion index value is compared with the evaluation index value based on the preset simulated annealing algorithm to obtain a comparison result, so as to seek the possibility of jumping out of the local optimal solution with the smallest possible calculation cost, and thereby approach the global optimal solution as much as possible.

[0130] It should be noted that with the expansion of the pattern, the evaluation index value θ determined by the algorithm does not monotonically change, but can have a non-monotonic change trend. The reason for this phenomenon is that during the mode expansion, the area of the pattern will inevitably increase, but on the other hand, the number of repetitions of the pattern cannot increase, but can remain unchanged or decrease. As a result, the two multiplier factors that affect the evaluation index value θ of a certain pattern will inevitably show opposite trends, thereby making the change of the evaluation index not necessarily monotonous, and thus possibly causing the inclusion of a local optimal solution. The purpose of introducing the simulated annealing algorithm here is to seek the possibility of jumping out of the local optimal solution with the smallest possible calculation cost, and thereby approach the global optimal solution as much as possible.

[0131] Step S506: In a case where it is determined that the comparison result is that the expansion index value is less than the evaluation index value, performing backtracking calculation on the unit expansion pattern according to the backtracking algorithm in the simulated annealing algorithm to obtain a backtracking unit pattern, and performing area limitation on the backtracking unit pattern according to the acceptance criterion formula in the simulated annealing algorithm to obtain the repetitive graphic information;

[0132] In some embodiments, in a case where it is determined that the comparison result is that the expansion index value is less than the evaluation index value, it indicates that the evaluation index of the pattern after the expansion is deteriorated. Therefore, the unit expansion pattern is subjected to backtracking calculation according to the backtracking algorithm in the simulated annealing algorithm to obtain a backtracking unit pattern, and the backtracking unit pattern is subjected to area limitation according to the acceptance criterion formula in the simulated annealing algorithm to obtain the repetitive graphic information, so as to avoid misjudgment and improve the accuracy of the calculation.

[0133] It should be noted that the backtracking algorithm in this embodiment is Metropolis criterion. In the process of calculating the simulated annealing algorithm, the previous evaluation index and the current evaluation index of the mode are input, and the difference between the two is investigated. If the difference between the former and the latter is negative, the evaluation index becomes better, at this time the algorithm accepts this good result, and judges whether the algorithm meets the area requirement of the mode at this time, if it meets, the repeated mode instance is taken out from the layout; if it does not meet the area requirement, continue to expand outward from the current repeated mode as the starting point, thereby entering the next cycle. If the difference between the former and the latter is positive, it means that the evaluation index becomes worse after the current expansion, but this does not mean that there is no chance for the evaluation index to become better as the expansion proceeds. Therefore, the Metropolis criterion is adopted to accept the current evaluation index.

[0134] Step S507: In the case where it is determined that the comparison result is that the expansion index value is greater than the evaluation index value, and the unit expansion mode meets the preset area condition, the unit expansion mode is taken as the first element, and the mode expansion is continued on the elements in the instance set until all the elements in the instance set are traversed, to obtain the repeated graphic information.

[0135] In some embodiments, in the case where it is determined that the comparison result is that the expansion index value is greater than the evaluation index value, and the unit expansion mode meets the preset area condition, it is indicated that the expanded unit expansion mode is a repeated graphic, the unit expansion mode needs to be taken out from the integrated circuit layout, and the unit expansion mode is taken as the first element, and the mode expansion is continued on the elements in the instance set until all the elements in the instance set are traversed, to obtain the final repeated graphic information.

[0136] It should be noted that the preset area condition is set by the user according to the user's needs, which can be the area size of the unit expansion mode, the area position of the expansion mode, etc., and the embodiment is not limited specifically.

[0137] Reference Figure 6 , Figure 6 is Figure 5 the specific method flowchart of step S503 in the method, and step S503 includes but is not limited to steps S601-S603.

[0138] It should be noted that the expansion result includes the expansion frame boundary.

[0139] Step S601: cutting detection is performed on the expansion frame boundary and the polygons in the instance set, to obtain a detection result;

[0140] In some embodiments, cutting detection is performed on the expansion frame boundary and the polygons in the instance set, to obtain a detection result, so as to avoid the case that the frame boundary cuts the polygons.

[0141] Step S602: When the detection result is that the extended frame boundary is not cut by the polygon, determine the unit expansion mode according to the extended frame boundary.

[0142] In some embodiments, when the detection result is that the extended frame boundary is not cut by the polygon, the unit expansion mode is determined according to the extended frame boundary, so as to avoid the situation of mode overlap.

[0143] Step S603: When the detection result is that the extended frame boundary is cut by the polygon, continue to expand the mode of the extended frame boundary until the extended frame boundary after mode expansion is not cut by the polygon.

[0144] In some embodiments, when the detection result is that the extended frame boundary is cut by the polygon, it is necessary to continue to expand the mode of the extended frame boundary until the extended frame boundary after mode expansion is not cut by the polygon, wherein the expansion process of the frame boundary mainly includes searching for elements in the required expansion rectangular frame and detecting whether there is a situation of cutting the polygon, and the main process is that the frames intersecting or overlapping with the current mode frame are obtained through the index of rtree, and whether the polygons stored in the frames are cut by the current mode frame is judged, if there is cutting, the polygons are included in the preset expansion list, and the process is continuously performed until the current mode is stable.

[0145] It should be noted that during the mode expansion process, the phenomenon of overlapping extended frames may occur, and this situation is not allowed in the process of layout extraction. For example, four mode libraries are constructed, and expansion is performed in four directions. At this time, it is found that the four mode libraries overlap, and then four new mode libraries are newly constructed, which correspond to the directions of the four mode libraries, and the modes in the mode libraries are analyzed. If there is a situation that the polygon instance is being accessed, it is not inserted into the new mode library. If all polygon instances of a certain mode are not in the state of being accessed, the mode is inserted into the new mode library, and after insertion, the polygon instances contained in the mode are set to be in the state of being accessed. When a mode library has been processed, all polygon instances in all modes in the mode library are marked as not being accessed, so that subsequent expansion in different directions can be carried out without being affected. Such processing will not cause the modes obtained by expansion to overlap with each other in the layout.

[0146] Referring to Figure 7 , Figure 7 is Figure 5 the specific method flowchart of step S506, and step S506 includes but is not limited to steps S701-S707.

[0147] It should be noted that the simulated annealing algorithm in the embodiment is different from the general simulated annealing algorithm. The expansion process of the mode in the general simulated annealing algorithm is irreversible, and the general simulated annealing algorithm is a neighborhood search algorithm, which contains search in different directions, and the mode expansion is a one-way search. Therefore, the embodiment needs to set a backtracking mechanism for the algorithm, so that if the evaluation index continues to decrease, it can be considered with a high probability that it is not a direction worthy of expansion. The backtracking mechanism can return the algorithm to the position where the evaluation index does not decrease as the final basis for judging each expansion. The simulated annealing algorithm in the embodiment will be further described below.

[0148] Step S701: determining the number of expansions allowed for mode expansion according to the backtracking algorithm;

[0149] In some embodiments, the number of expansions allowed for mode expansion is first set according to the backtracking algorithm in the simulated annealing algorithm, to avoid misjudgment of the mode and improve the accuracy of the mode judgment.

[0150] Step S702: for each expansion within the number of expansions, performing index calculation on the unit expansion mode based on the evaluation formula to obtain a backtracking index value;

[0151] In some embodiments, for each expansion within the number of expansions, index calculation is needed to be performed on the unit expansion mode based on the evaluation formula, so as to obtain the backtracking index value of each expansion, which is convenient for subsequent judgment of repeated patterns.

[0152] Step S703: generating a backtracking index set according to the number of expansions and the backtracking index value;

[0153] In some embodiments, the backtracking index set is generated according to the number of expansions and the backtracking index value, which is convenient for judgment of the index value and improves the accuracy of repeated pattern recognition.

[0154] Step S704: when each element in the backtracking index set is less than the expansion index value, performing a backtracking operation on the unit expansion mode until the expansion index value of the unit expansion mode is greater than the evaluation index value, to obtain a backtracking unit mode;

[0155] In some embodiments, when all elements in the backtracking index set are less than the expansion index value, a backtracking operation needs to be performed on the unit expansion mode until the expansion index value of a certain unit expansion mode is greater than the evaluation index value. Then, the unit expansion mode greater than the evaluation index value is taken as the backtracking unit mode.

[0156] Step S705: when a target element in the backtracking index set is greater than the expansion index value, determining a backtracking unit mode according to the backtracking index value of the target element;

[0157] In some embodiments, when the target element in the backtracking index set is greater than the expansion index value, the backtracking unit pattern can be directly determined according to the backtracking index value of the target element.

[0158] Step S706: According to the acceptance criterion formula, the probability of the backtracking unit pattern is calculated to obtain a pattern probability value.

[0159] In some embodiments, the probability of the backtracking unit pattern is calculated according to the acceptance criterion formula to obtain a pattern probability value, wherein the calculation process of the acceptance criterion formula is shown in the following formula (2):

[0160] P = exp (-△θ / (kT)) (2)

[0161] Wherein, △θ = θ0-θ, θ0 is the previous unit pattern of the backtracking unit pattern, θ is the current backtracking unit pattern, if △θ < 0, the expanded pattern is accepted as the new state, k is the generalized Boltzmann constant, T is the generalized temperature, wherein T is a variable that is constantly reduced during the algorithm running process, the reduction here can be linear reduction, or a non-linear reduction method can be used according to the algorithm running time requirement, the embodiment does not make specific limitation.

[0162] Step S707: When the pattern probability value is greater than the preset target probability value, the backtracking unit pattern is taken as the first element, and the elements in the instance set are continuously expanded to obtain the repetitive graphic information.

[0163] In some embodiments, when the pattern probability value is greater than the preset target probability value, it indicates that the algorithm accepts the backtracking unit pattern, and the backtracking unit pattern can be continuously expanded as the starting point, the backtracking unit pattern is taken as the first element, and the elements in the instance set are continuously expanded to obtain the repetitive graphic information.

[0164] In some embodiments, when the pattern probability value is less than or equal to the preset target probability value, it indicates that the evaluation index continuously decreases within the expansion times, and the algorithm considers that this expansion is not desirable or cannot be continuously performed, and then rejects this expansion, and the previous pattern needs to be read out as the final state of this continuous expansion.

[0165] Reference Figure 8 , Figure 8 is a flowchart of a graphic information processing method provided by another embodiment of the application, and the graphic information processing method includes but is not limited to step S801.

[0166] Step S801: According to the evaluation formula, the index of all unit patterns in the target layout is calculated to obtain a target index value.

[0167] In some embodiments, after the integrated circuit layout is updated according to the repetitive pattern information to obtain a target layout, an index value of all polygons in the target layout is calculated according to an evaluation formula, so that the amount of calculation resources that can be saved in the calculation of lithography simulation can be determined according to the size of the target index value.

[0168] It should be noted that the target index value can be calculated according to the following formula (3):

[0169] θ=∑ i θ i =∑ i S i (C i -1) (3)

[0170] It can be understood that S i is the area of different unit patterns, and C i is the number of repetitions of each unit pattern in the integrated circuit layout.

[0171] It should be noted that the target index value is the sum of the θ values of all patterns extracted from the layout, and the result obtained is the amount of calculation that can be omitted after one round of processing. This process can continue on the simplified layout until it can no longer be processed or the required calculation has been reached.

[0172] In some embodiments, the present embodiment also includes symmetry judgment of polygons or patterns, which can save storage space when encoding the polygons and patterns, and has an advantage in judging the same pattern, for example, the pattern can still be recognized by the program after rotation and mirroring operation, and not only the pattern that is exactly the same as the current pattern can be stored in the pattern library. Similarly, the recognition of the symmetric pattern of the polygon can process the polygon obtained by rotating and mirroring the polygon.

[0173] With reference to Figure 9 , the embodiment of the present application also provides a pattern information processing system, which can implement the pattern information processing method described above, and the system comprises:

[0174] The layout processing module 901 is configured to pre-process the obtained integrated circuit layout to obtain a pattern library, wherein the pattern library is configured to store a polygon data set of the integrated circuit layout.

[0175] The index calculation module 902 is configured to calculate an index of each polygon in the pattern library based on a preset evaluation formula to obtain an evaluation index value corresponding to each polygon, wherein the evaluation index value is configured to represent the occurrence probability of a unit pattern of the polygon, and the unit pattern is configured to represent a repetitive pattern including the smallest size of the polygon.

[0176] The mode sorting module 903 is configured to sort the unit modes of the polygons according to the evaluation index values, to obtain an instance set.

[0177] The mode expanding module 904 is configured to perform mode expansion on elements in the instance set based on a preset simulated annealing algorithm, to obtain repetitive graphic information.

[0178] The layout updating module 905 is configured to update the integrated circuit layout according to the repetitive graphic information, to obtain a target layout.

[0179] The specific implementation of the graphic information processing system is basically the same as that of the above-mentioned graphic information processing method, and will not be repeated here.

[0180] In order to more clearly illustrate the graphic information processing method provided by the embodiment of the present application, the following will be described with specific examples.

[0181] Example 1

[0182] Referring to Figure 10 , Figure 10 a schematic diagram of a to-be-processed layout provided by an example of the present application;

[0183] The following steps are used to find the maximum repetitive information in the to-be-processed layout in Figure 10 :

[0184] Step 101, the graphic distribution information is preprocessed and initialized as an input file, and the frame of each graphic and the information of the polygon contained therein are stored in the rtree;

[0185] Step 102, all polygons in the layout are scanned in sequence, and the polygon type thereof is stored. The corresponding number and transformation mode code are assigned thereto;

[0186] Referring to Figure 11 , Figure 11 a schematic diagram of a unit mode provided by an example of the present application;

[0187] Step 103, the unit mode of each polygon is found, and is stored in a newly created mode library. The unit modes are sorted according to the evaluation index values, to obtain an instance set;

[0188] Referring to Figures 12-13 , Figure 12 a schematic diagram of mode expansion provided by an example of the present application;

[0189] Figure 13 a schematic diagram of mode expansion provided by another example of the present application;

[0190] Step 104, expanding each unit pattern, first expanding the frame of each unit pattern to a square as shown in Figure 12 After that, on the basis of the square, the same step width in each direction (up, down, left, right) is performed. The square frame is expanded outward by a part to obtain a frame line as shown in Figure 13 .

[0191] Referring to Figure 14 , Figure 14 a schematic diagram of reaching a steady state provided by an example of the present application;

[0192] Step 105, continuing to expand each pattern, the expansion here is to make each pattern reach a steady state to obtain a unit expansion pattern, wherein the frame of the unit expansion pattern is as shown in Figure 14 .

[0193] Step 106, storing the newly obtained pattern in a newly created pattern library, and calculating a new θ value.

[0194] Step 107, if the θ value rises, continue to repeat the above steps 104 and 105. If the θ value falls, determine whether the area of the obtained pattern meets the requirements. If it meets the requirements, output the corresponding pattern. If it does not meet the requirements, continue to the next step.

[0195] Step 108, performing the processing of steps 103-106 on the next type of unit pattern.

[0196] In some embodiments, the graphic information processing method in the present embodiment is not restricted by the layout design pattern, and can be applied to hierarchical layout or flat layout. The graphic information processing method in the present embodiment can effectively compress the integrated circuit layout with large layout size and high repetitive graphic distribution, such as memory and image sensor circuit layout, can automatically extract the repetitive pattern of the integrated circuit layout, and can effectively reduce the calculation amount of optical proximity correction and physical verification operations.

[0197] The present application also provides an electronic device, which comprises a memory, a processor, a program stored in the memory and executable on the processor, and a data bus for realizing the connection and communication between the processor and the memory, and the program is executed by the processor to realize the above graphic information processing method. The electronic device can be any smart terminal including a tablet computer, a vehicle-mounted computer, etc.

[0198] Please refer to Figure 15 , Figure 15 a hardware structure of an electronic device of another embodiment is shown, which comprises:

[0199] The processor 1001 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits, and is configured to execute related programs to implement the technical solutions provided by the embodiments of the present application.

[0200] The memory 1002 can be implemented by a ROM (Read Only Memory), a static storage device, a dynamic storage device, or a RAM (Random Access Memory), and the like. The memory 1002 can store an operating system and other application programs. When the technical solutions provided by the embodiments of the present application are implemented by software or firmware, the related program codes are stored in the memory 1002 and are called and executed by the processor 1001 to implement the module management method of the online guest system according to the embodiments of the present application.

[0201] The input / output interface 1003 is configured to implement information input and output.

[0202] The communication interface 1004 is configured to implement the communication interaction between the device and other devices. The communication can be implemented by a wired manner (for example, a USB, a network cable, and the like) or a wireless manner (for example, a mobile network, WIFI, Bluetooth, and the like).

[0203] The bus 1005 is configured to transmit information between various components (for example, the processor 1001, the memory 1002, the input / output interface 1003, and the communication interface 1004) of the device.

[0204] The processor 1001, the memory 1002, the input / output interface 1003, and the communication interface 1004 are connected to each other through the bus 1005 to realize the communication connection between the devices.

[0205] In addition, an embodiment of the present application further provides a computer readable storage medium, which stores computer executable instructions. The computer executable instructions are executed by a processor or a controller, for example, a processor in the above-mentioned system embodiment, so that the above-mentioned processor executes the above-mentioned graphic information processing method.

[0206] The embodiments described in the embodiments of the present application are used to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. It can be known by those skilled in the art that, with the evolution of technology and the appearance of new application scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0207] Those skilled in the art can understand that the technical solutions shown in the above embodiments are not limited to the embodiments of the present application, and more or fewer steps can be included, or some steps can be combined, or different steps can be included. Figures 1-8 The technical solutions shown in the above embodiments do not constitute a limitation on the embodiments of the present application, and more or fewer steps can be included, or some steps can be combined, or different steps can be included.

[0208] The system embodiments described above are only illustrative, and units described as separate components can or can not be physically separated, that is, they can be located in one place, or they can be distributed on multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiments.

[0209] Those skilled in the art can understand that all or some steps in the above disclosed method, functional modules / units in the system, and the device can be implemented as software, firmware, hardware, and appropriate combinations thereof.

[0210] The terms "first", "second", "third", "fourth" and the like (if any) in the specification of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0211] It should be understood that in the present application, "at least one" means one or more, and "multiple" means two or more. "And / or" is used to describe the association between the associated objects, which means that there can be three relationships, for example, "A and / or B" can represent three cases: only A, only B, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b or c can mean a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0212] In several embodiments provided in the present application, it should be understood that the disclosed system and method can be implemented in other manners. For example, the system embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There can be another division manner for the actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between different units, can be indirect couplings or communication connections through some interfaces, and electrical, mechanical or other forms.

[0213] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they can be located in one place, or can be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0214] In addition, the functional units in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0215] If the integrated unit is realized in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part of the prior art that contributes to the technical solutions or all or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes multiple instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program storage media.

[0216] The preferred embodiments of the embodiments of the present application are described above with reference to the accompanying drawings, but this does not limit the scope of the rights of the embodiments of the present application. Any modifications, equivalent replacements and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall be within the scope of the rights of the embodiments of the present application.

Claims

1. A method of processing graphical information, characterized by, The method includes: The obtained integrated circuit layout is preprocessed to obtain a graphics library, wherein the graphics library is used to store the polygon data set of the integrated circuit layout; Based on a preset evaluation formula, an index is calculated for each polygon in the graphics library to obtain an evaluation index value corresponding to each polygon. The evaluation index value is used to characterize the probability of occurrence of a unit pattern of a preset polygon. The unit pattern is used to characterize a repeating pattern including the minimum size of the preset polygon. The evaluation formula is used to characterize the product calculated based on the pattern area corresponding to the unit pattern obtained after polygon expansion processing and the number of repetitions, and the product is used as the evaluation index value corresponding to the polygon. The unit patterns of the polygons are sorted according to the evaluation index values ​​to obtain an instance set; Based on a preset simulated annealing algorithm, the elements in the instance set are pattern expanded to obtain repeating graphic information; The integrated circuit layout is updated based on the repeating graphic information to obtain the target layout; The pattern library used to store the unit patterns of the polygons includes border information; The preset simulated annealing algorithm is used to perform pattern expansion on the elements in the instance set to obtain repeating graphic information, including: Extract the first element from the instance set, and extract the border information corresponding to the unit pattern of the first element from the pattern library; The border information is pattern expanded according to the preset expansion step size and direction information to obtain multiple expansion results; For each of the expansion results, a stability test is performed to obtain the unit expansion pattern corresponding to the expansion result; the unit expansion pattern is the pattern that the unit pattern reaches stability after expansion. The unit expansion mode is calculated according to the evaluation formula to obtain the expansion index value; The extended index value is compared with the evaluation index value based on the preset simulated annealing algorithm to obtain the comparison result; If the comparison result indicates that the expansion index value is less than the evaluation index value, the unit expansion pattern is backtracked according to the backtracking algorithm in the simulated annealing algorithm to obtain the backtracked unit pattern. Then, the area of ​​the backtracked unit pattern is limited according to the acceptance criterion formula in the simulated annealing algorithm to obtain the repeating graphic information. The backtracking algorithm is the Metropolis criterion, and the backtracked unit pattern is a unit expansion pattern that is greater than the evaluation index value. If the comparison result indicates that the expanded index value is greater than the evaluation index value, and the unit expansion pattern meets the preset area condition, the unit expansion pattern is used as the first element, and the pattern expansion is continued to be performed on the elements in the instance set until all elements in the instance set are traversed to obtain the repeated graphic information.

2. The graphic information processing method according to claim 1, characterized by, The preprocessing of the acquired integrated circuit layout to obtain a graphics library includes: Graphical extraction is performed on each layer of the integrated circuit layout to obtain a polygon data set of the integrated circuit layout, wherein the polygon data set includes vertex list information of the polygons; Encode all polygons in the polygon data set according to the vertex list information to obtain polygon class information, wherein the polygon class information is used to represent position information and encoding information of the polygons in the layer; Generate the graphic library according to the polygon class information and the polygon data set.

3. The graphic information processing method according to claim 1, characterized by, Calculate an evaluation index value corresponding to each polygon in the graphic library based on a preset evaluation formula, including: Perform extension processing on a preset polygon in the graphic library to obtain a unit pattern corresponding to the polygon; Calculate the unit pattern to obtain a pattern area and a repetition number of the unit pattern; Calculate an evaluation index value corresponding to each polygon based on a preset evaluation formula.

4. The graphic information processing method according to claim 1, characterized by, Sort the unit patterns of the polygons according to the evaluation index values to obtain an instance set, including: Construct a pattern library for storing the unit patterns of the polygons; Sort the unit patterns of the polygons in descending order according to the evaluation index values to obtain a descending sequence, and store the descending sequence in the pattern library to obtain the instance set.

5. The graphic information processing method according to claim 1, characterized by, The extension result includes an extension frame boundary; the stability detection on each extension result to obtain a unit extension pattern corresponding to the extension result, including: Perform cutting detection on the extension frame boundary and the polygons in the instance set to obtain a detection result; When it is determined that the detection result is that the extension frame boundary is not cut by the polygons, determine the unit extension pattern according to the extension frame boundary; When it is determined that the detection result is that the extension frame boundary is cut by the polygons, continue to perform pattern extension on the extension frame boundary until the extension frame boundary after the pattern extension is not cut by the polygons.

6. The graphic information processing method according to claim 1, characterized by, Perform backtracking calculation on the unit extension pattern according to a backtracking algorithm in the simulated annealing algorithm to obtain a backtracking unit pattern, and perform area limitation on the backtracking unit pattern according to an acceptance criterion formula in the simulated annealing algorithm to obtain the repetitive graphic information, including: Determine an extension number according to the backtracking algorithm; For each extension within the extension number, calculate an evaluation index value of the unit extension pattern based on the evaluation formula; Generate a backtracking index set according to the extension number and the evaluation index value; When each element in the backtracking index set is less than the extension index value, perform backtracking operation on the unit extension pattern until the extension index value of the unit extension pattern is greater than the evaluation index value to obtain the backtracking unit pattern; When a target element in the backtracking index set is greater than the extension index value, determine the backtracking unit pattern according to the backtracking index value of the target element; Perform probability calculation on the backtracking unit pattern according to the acceptance criterion formula to obtain a pattern probability value; When the mode probability value is greater than a preset target probability value, the backtracking unit mode is taken as a first element, and mode expansion is continuously performed on elements in the instance set to obtain the repetitive pattern information.

7. The graphic information processing method according to claim 1, characterized by, After the integrated circuit layout is updated according to the repetitive pattern information to obtain a target layout, the method further includes: performing index calculation on all unit modes in the target layout according to the evaluation formula to obtain a target index value.

8. A graphic information processing system characterized by comprising: The method includes: a layout processing module configured to pre-process an obtained integrated circuit layout to obtain a pattern library, wherein the pattern library is configured to store a polygon data set of the integrated circuit layout; an index calculation module configured to perform index calculation on each polygon in the pattern library based on a preset evaluation formula to obtain an evaluation index value corresponding to each polygon, wherein the evaluation index value is configured to represent an occurrence probability of a preset unit mode of the polygon, the unit mode is configured to represent a repetitive pattern including a minimum size of the polygon, and the evaluation formula is configured to represent a product obtained by multiplying a pattern area corresponding to a unit mode obtained after expansion processing of the polygon and a repetition number, and the product is taken as the evaluation index value corresponding to the polygon; a mode sorting module configured to sort unit modes of the polygon according to the evaluation index value to obtain an instance set; a mode expansion module configured to perform mode expansion on elements in the instance set based on a preset simulated annealing algorithm to obtain repetitive pattern information; a layout updating module configured to update the integrated circuit layout according to the repetitive pattern information to obtain a target layout; wherein a mode library configured to store the unit mode of the polygon includes frame information; the mode expansion on the elements in the instance set based on the preset simulated annealing algorithm to obtain the repetitive pattern information includes: extracting a first element in the instance set and extracting frame information corresponding to a unit mode of the first element in the mode library; performing mode expansion on the frame information according to a preset expansion step and direction information to obtain a plurality of expansion results; performing stability detection on each expansion result to obtain a unit expansion mode corresponding to the expansion result; the unit expansion mode is a mode that is stable after expansion of the unit mode; performing index calculation on the unit expansion mode according to the evaluation formula to obtain an expansion index value; comparing the expansion index value with the evaluation index value based on the preset simulated annealing algorithm to obtain a comparison result; in a case where it is determined that the comparison result is that the expansion index value is less than the evaluation index value, performing backtracking calculation on the unit expansion mode according to a backtracking algorithm in the simulated annealing algorithm to obtain a backtracking unit mode, and performing area limitation on the backtracking unit mode according to an acceptance criterion formula in the simulated annealing algorithm to obtain the repetitive pattern information; the backtracking algorithm is a Metropolis criterion, and the backtracking unit mode is a unit expansion mode greater than the evaluation index value. In a case where it is determined that the comparison result is that the expansion indicator value is greater than the evaluation indicator value, and the unit expansion mode satisfies a preset area condition, the unit expansion mode is taken as a first element, and mode expansion is continuously performed on elements in the instance set until all elements in the instance set are traversed, to obtain the repetitive pattern information.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer executable instructions for causing a computer to execute the pattern information processing method according to any one of claims 1 to 7.

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