Quantum computing task mapping method and quantum computer operating system
By forming and updating the topology in the idle qubits of a quantum chip, the problems of low resource utilization and long task waiting time of quantum chips are solved, and efficient execution of quantum computing tasks is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ORIGIN QUANTUM COMPUTING TECH (HEFEI) CO LTD
- Filing Date
- 2021-08-31
- Publication Date
- 2026-05-12
AI Technical Summary
Existing technologies suffer from problems such as low utilization of quantum bit resources in quantum chips, long waiting times for quantum computing tasks, and low program efficiency.
By forming a first topological structure in the idle qubits of the target quantum chip, it is determined whether the quantum computing task to be executed can be performed in the structure. If not, the structure is updated based on the idle qubits that are directly connected to the first topological structure until the task can be executed.
This improves the resource utilization of quantum chips and the execution timeliness of quantum computing tasks, reduces matching waiting time, and achieves high-quality matching between quantum bit topology and tasks.
Smart Images
Figure CN115730663B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of quantum computing technology, and in particular to a quantum computing task mapping method and a quantum computer operating system. Background Technology
[0002] Quantum computers use qubits as their basic unit and leverage properties such as quantum superposition and quantum entanglement to achieve revolutionary computing methods. They offer the potential to surpass all classical computing techniques in terms of information carrying capacity and ultra-powerful parallel computing capabilities. Quantum computing is expected to outperform classical computing in problems such as machine learning, chemical simulation, and solving linear equations.
[0003] In existing technologies, a single-program mapping method is used when mapping quantum tasks, mapping each quantum program to a quantum chip one by one. This mapping method tends to select the highest quality chips and qubits. Generally, all qubits on the quantum chip are first divided into several executable quantum circuit blocks (i.e., qubit topologies) using a multi-layer partitioning method. Then, available executable quantum circuit blocks are selected based on the number of qubits in the quantum computing task to be run for mapping. However, with the increasing demand for quantum computing in quantum computer operating systems, the number of quantum computing tasks to be processed will continue to increase, and the number of qubits required for each quantum computing task varies significantly. Using executable quantum circuit blocks for mapping quantum computing tasks will result in problems such as unreasonable partitioning of executable quantum circuit blocks, long processing time for finding executable quantum circuit blocks that match the task, low utilization of quantum chip qubit resources, long waiting time for quantum computing tasks, and low program efficiency. Summary of the Invention
[0004] The purpose of this invention is to provide a quantum computing task mapping method and a quantum computer operating system to solve the problems of low qubit resource utilization, long waiting time for quantum computing tasks, and low program runtime efficiency in existing technologies.
[0005] To address the aforementioned technical problems, this invention proposes a quantum computing task mapping method, comprising:
[0006] In the idle qubits of the target quantum chip, a first qubit whose qubit parameters meet the requirements is obtained to form a first topology, wherein the qubit parameters characterize the state of the qubit, and the idle qubit is the qubit in the target quantum chip that is in an idle state;
[0007] Determine whether the quantum computing task to be executed can be performed in the first topology;
[0008] If so, the quantum computing task to be executed is mapped into the first topology;
[0009] If not, the first topology is updated based on the free qubits that are directly connected to the first topology, and the process returns to the step of determining whether the quantum computing task to be performed can be executed in the first topology.
[0010] Optionally, updating the first topology based on idle qubits directly connected to the first topology includes:
[0011] Idle qubits that are directly connected to the first topology are obtained as qubits to be partitioned, wherein each of the qubits to be partitioned and the first topology constitute an integral structure.
[0012] Based on the compactness of the overall structure, one of the qubits to be partitioned is selected from all the qubits to be partitioned and assigned to the first topology to update the first topology.
[0013] Optionally, updating the first topology based on idle qubits directly connected to the first topology includes:
[0014] Idle qubits that are directly connected to the first topology are obtained as qubits to be partitioned, wherein each of the qubits to be partitioned and the first topology constitute an integral structure.
[0015] Based on the fidelity parameters of the qubits in the overall structure, one of the qubits to be partitioned is selected from all the qubits to be partitioned and partitioned into the first topology to update the first topology. The fidelity parameters include one or a combination of three factors: read fidelity, fidelity of performing a single-qubit quantum logic gate operation on any qubit, fidelity of performing a two-qubit quantum logic gate operation between any two qubits that are directly connected.
[0016] Optionally, updating the first topology based on idle qubits directly connected to the first topology includes:
[0017] Idle qubits that are directly connected to the first topology are obtained as qubits to be partitioned, wherein each of the qubits to be partitioned and the first topology constitute an integral structure.
[0018] Based on the number of feed lines in the overall structure, one of the qubits to be partitioned is selected from all the qubits to be partitioned and partitioned into the first topology to update the first topology. The feed lines are coupled to connect several qubits in the quantum chip and transmit quantum state information.
[0019] Optionally, updating the first topology based on idle qubits directly connected to the first topology includes:
[0020] Idle qubits that are directly connected to the first topology are obtained as qubits to be partitioned, wherein each of the qubits to be partitioned and the first topology constitute an integral structure.
[0021] Based on the compactness of the overall structure and the fidelity parameters and number of feed lines of the qubits in the overall structure, one qubit to be partitioned is selected from all the qubits to be partitioned and partitioned into the first topology to update the first topology. The fidelity parameters include one or a combination of readout fidelity, fidelity of performing a single-qubit quantum logic gate operation on any qubit, fidelity of performing a two-qubit quantum logic gate operation between any two qubits with a direct connection relationship, and the feed lines couple and connect several qubits in the quantum chip and transmit quantum state information.
[0022] Optionally, the step of dividing several qubits to be divided into the first topology according to the compactness of the overall structure and the fidelity parameters and number of feed lines of the qubits in the overall structure to update the first topology includes:
[0023] The weighting coefficients for the density, fidelity parameters, and number of feeders are determined based on the quantum computing task to be performed and the target quantum chip.
[0024] Based on the determined weighting coefficients, several qubits to be divided are assigned to the first topology according to the compactness of the overall structure, the fidelity parameters of the qubits in the overall structure, and the number of feed lines, so as to update the first topology.
[0025] Optionally, the quantum computing task mapping method further includes:
[0026] Obtain the coherence time of all free qubits that are directly connected to the first topology;
[0027] Quantum bits with a coherence time less than a first threshold are set as unusable qubits, wherein the first topology does not include the unusable qubits.
[0028] Based on the same inventive concept, this invention also proposes a quantum computing task mapping device, comprising:
[0029] The first module is configured to acquire a first qubit with qubit parameters that meet the requirements from the idle qubits of the target quantum chip to form a first topology, wherein the qubit parameters characterize the state of the qubit, and the idle qubit is a qubit in the target quantum chip that is in an idle state.
[0030] The second module is configured to determine whether the quantum computing task to be performed can be executed in the first topology.
[0031] The third module is configured to map the quantum computing task to be executed into the first topology when the determination result is yes;
[0032] The fourth module is configured to update the first topology based on the free qubits that are directly connected to the first topology when the determination result is negative, and return to the step of determining whether the quantum computing task to be performed can be executed in the first topology.
[0033] Based on the same inventive concept, the present invention also proposes a readable storage medium storing a computer program thereon, which, when executed by a processor, can implement the quantum computing task mapping method described in any of the above technical features.
[0034] Based on the same inventive concept, the present invention also proposes an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the quantum computing task mapping method described in any of the above technical features.
[0035] Based on the same inventive concept, the present invention also proposes a quantum computer operating system, including the quantum computing task mapping method described in any of the above-described features.
[0036] Compared with the prior art, the present invention has the following beneficial effects:
[0037] The quantum computing task mapping method proposed in this invention performs high-quality, real-time, dynamic partitioning of idle qubits in a quantum chip according to the actual needs of the quantum computing tasks to be executed. The obtained qubit topology can match the quantum computing tasks to be executed, with no matching waiting time and a high matching degree. This greatly improves the resource utilization of the quantum chip and also effectively improves the execution timeliness of quantum computing tasks in the program waiting queue. Using the mapping method of this application, the optimal partitioning region of each quantum computing task in the program waiting queue can be quickly found on the idle qubits of the quantum chips in the quantum chip cluster that meet the requirements for execution mapping.
[0038] This invention also proposes a quantum computing task mapping device, a readable storage medium, an electronic device, and a quantum computer operating system, which belong to the same inventive concept as the quantum computing task mapping method and therefore have the same beneficial effects, and will not be described in detail here. Attached Figure Description
[0039] Figure 1 This is a flowchart illustrating a quantum computing task mapping method proposed in an embodiment of the present invention;
[0040] Figure 2 This is a schematic diagram of a 2*3 quantum chip according to an embodiment of the present invention. Detailed Implementation
[0041] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0042] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0043] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0044] Please refer to Figure 1This invention proposes a quantum computing task mapping method, comprising:
[0045] S1: In the idle qubits of the target quantum chip, a first qubit whose qubit parameters meet the requirements is obtained to form a first topology, wherein the qubit parameters characterize the state of the qubit, and the idle qubit is the qubit in the target quantum chip that is in an idle state;
[0046] S2: Determine whether the quantum computing task to be executed can be performed in the first topology;
[0047] S3: If so, then map the quantum computing task to be executed into the first topology;
[0048] S4: If not, update the first topology based on the free qubits that are directly connected to the first topology, and return to the step of determining whether the quantum computing task to be performed can be executed in the first topology.
[0049] Unlike existing technologies, the quantum computing task mapping method proposed in this invention performs high-quality, real-time, dynamic partitioning of idle qubits in a quantum chip according to the actual needs of the quantum computing tasks to be executed. The resulting qubit topology can match the quantum computing tasks to be executed, with no matching waiting time and a high matching degree. This greatly improves the resource utilization of the quantum chip and also effectively improves the execution timeliness of quantum computing tasks in the program waiting queue. Using the mapping method of this application, each quantum computing task in the program waiting queue can quickly find its optimal partitioning region on the idle qubits of a quantum chip in the system's quantum chip cluster that meets the requirements for execution mapping.
[0050] Specifically, in step S4, updating the first topology based on the free qubits directly connected to the first topology includes:
[0051] Step 1: Obtain the free qubits that are directly connected to the first topology as qubits to be divided, wherein each of the qubits to be divided and the first topology constitute an integral structure;
[0052] Step 2: Based on the compactness of the overall structure, select one of the qubits to be divided from all the qubits to be divided and assign it to the first topology to update the first topology.
[0053] Those skilled in the art should understand that the density refers to the degree of connection between qubits in the overall structure. This density can be obtained using a community detection algorithm, which is a type of clustering algorithm used to discover community structures within a network. These divided community structures form a subgraph, including vertices and edges. Vertices within the same community are tightly connected, while connections between communities are relatively sparse. Density is chosen as a metric to evaluate the quality of a community structure partitioning, and its calculation formula is:
[0054]
[0055] Where Q is the density of a community structure C, m is the total number of edges in the community structure C, and I c Let D be the number of all internal edges in the community structure C. c Let C be the sum of the degrees of all vertices in the community structure C.
[0056] Quantum computing tasks create entanglement using two-qubit quantum logic gates, and these gates can only be executed between two physically coupled qubits on a quantum chip. Therefore, the qubits on the quantum chip required to execute a single quantum computing task should be tightly allocated, and crosstalk and other interference should be avoided between different quantum computing tasks. The qubit topology is equivalent to a community structure of idle physical qubits on the quantum chip. Therefore, the tightness of the overall structure can be obtained using the community detection algorithm, where each qubit in the grid structure of the quantum chip is equivalent to a vertex of the community structure, and the link between two qubits is equivalent to an edge of the community structure.
[0057] It should be noted that in the specific implementation process, when allocating qubits to the first topological structure each time, the qubit to be allocated corresponding to the overall structure with the highest density after combination can be allocated to the first topological structure. Alternatively, a threshold can be set for the density, and one qubit can be randomly selected from those that meet the threshold requirement to be allocated to the first topological structure. There are many other methods available, which will not be elaborated here. In practical applications, the appropriate method can be chosen according to actual needs. Those skilled in the art will understand that using the density of the overall structure as a factor to obtain the first topological structure can ensure that the density of the obtained first topological structure meets the requirements.
[0058] Besides obtaining the first topological structure through the density of the overall structure, step S4, which updates the first topological structure based on the free qubits directly connected to the first topological structure, can also be performed in the following ways:
[0059] Step 1: Obtain the free qubits that are directly connected to the first topology as qubits to be divided, wherein each of the qubits to be divided and the first topology constitute an integral structure;
[0060] Step 2: Based on the fidelity parameters of the qubits in the overall structure, select one qubit from all the qubits to be partitioned and assign it to the first topology to update the first topology. The fidelity parameters include one or a combination of readout fidelity, fidelity of performing a single-qubit quantum logic gate operation on any qubit, fidelity of performing a two-qubit quantum logic gate operation between any two directly connected qubits. Readout fidelity refers to the accuracy of reading quantum state information from the qubit. The fidelity of a single-qubit quantum logic gate operation is obtained by the error rate of performing the operation on the qubit; the sum of fidelity and error rate is 1. The fidelity of a two-qubit quantum logic gate operation is obtained similarly to that of a single-qubit operation. Those skilled in the art will understand that extensive testing is required before the quantum chip is put into use. The fidelity parameters are obtained during the testing phase of the quantum chip and are directly used as known parameters in the specific implementation.
[0061] It should be noted that in the specific implementation process, when allocating qubits to the first topology each time, the qubit to be allocated can be the one corresponding to the overall structure with the highest fidelity parameter after combination. Alternatively, a threshold can be set for the fidelity parameter, and one qubit can be randomly selected from those that meet the threshold to be allocated to the first topology. Many other methods are also available, which will not be elaborated here. In practical applications, the appropriate method can be chosen based on actual needs. Those skilled in the art will understand that using the fidelity parameter of the qubits in the overall structure as a factor to obtain the first topology ensures that the fidelity parameter of the obtained first topology meets the requirements.
[0062] To obtain the quantum state information of qubits, this is typically done via feeders, with each feeder coupling multiple qubits. When a measurement is being performed on one qubit coupled to the same feeder, other qubits cannot be measured. If two quantum computing tasks share the same feeder and they have different depths, their measurements must be synchronized or not overlap in time. To avoid partial overlap in the measurement processes of two quantum computing tasks, the start of the shorter-depth quantum computing task is generally delayed to ensure synchronized measurements. However, in practical applications, the inventors found that this approach effectively prolongs the total time consumed by the shorter quantum computing task, resulting in the qubits used to perform the shorter-depth quantum computing task being idle for a period of time. Based on these findings, the inventors considered using the number of feeders used in the overall structure as a factor in obtaining the first topology. The specific solution is as follows:
[0063] The step of updating the first topology based on idle qubits that are directly connected to the first topology includes:
[0064] Step 1: Obtain the free qubits that are directly connected to the first topology as qubits to be divided, wherein each of the qubits to be divided and the first topology constitute an integral structure;
[0065] Step 2: Based on the number of feed lines in the overall structure, select one of the qubits to be divided from all the qubits to be divided and assign it to the first topology to update the first topology. The feed lines are coupled to connect several qubits in the quantum chip and transmit quantum state information.
[0066] It should be noted that in the specific implementation process, when allocating qubits to the first topology each time, the qubit to be allocated can be the one corresponding to the overall structure with the fewest combined feed lines. Alternatively, a threshold can be set for the number of feed lines, and one qubit can be randomly selected from those that meet the threshold to be allocated to the first topology. Many other methods are also available, which will not be elaborated here. In practical applications, the appropriate method can be chosen based on actual needs. Those skilled in the art will understand that using the number of feed lines of the qubits in the overall structure as a factor to obtain the first topology ensures that the number of feed lines in the obtained first topology meets the requirements.
[0067] Furthermore, in addition to considering the density, fidelity parameter, and number of feeders individually, these factors can be combined to evaluate whether the qubits are suitable for inclusion in the first topology. Therefore, in step S4, updating the first topology based on the free qubits directly connected to the first topology can also be performed in the following manner:
[0068] Step 1: Obtain the free qubits that are directly connected to the first topology as qubits to be divided, wherein each of the qubits to be divided and the first topology constitute an integral structure;
[0069] Step 2: Based on the compactness of the overall structure and the fidelity parameters and number of feed lines of the qubits in the overall structure, select one qubit to be partitioned from all the qubits to be partitioned and partition it into the first topology to update the first topology. The fidelity parameters include one or a combination of readout fidelity, fidelity of performing a single-qubit quantum logic gate operation on any qubit, fidelity of performing a two-qubit quantum logic gate operation between any two qubits with a direct connection relationship, and the feed lines couple and connect several qubits in the quantum chip and transmit quantum state information.
[0070] The step of dividing the qubits to be divided into the first topology according to the compactness of the overall structure and the fidelity parameters and number of feed lines of the qubits in the overall structure to update the first topology may specifically include:
[0071] Step 1: Determine the weighting coefficients for the density, fidelity parameters, and number of feed lines based on the quantum computing task to be performed and the target quantum chip;
[0072] Step 2: Based on the determined weighting coefficients, according to the compactness of the overall structure and the fidelity parameters of the qubits in the overall structure and the number of feed lines, divide several qubits to be divided into the first topology to update the first topology.
[0073] Those skilled in the art will understand that the compactness of the overall structure and the weighting coefficients of the fidelity parameters of the qubits and the number of feed lines in the overall structure can be adjusted according to actual needs, and are not limited herein. To facilitate understanding of the technical solution of this application, a scheme using a reward function to characterize the above factors in the overall structure is provided below. Specifically, the value of the reward function is determined jointly by the compactness of the overall structure and the fidelity parameters of the qubits and the number of feed lines in the overall structure. The reward function is:
[0074]
[0075] Where F is the value of the reward function, Q m Q represents the compactness of the overall structure after adding another qubit. o E represents the compactness of the overall structure before adding another qubit, E represents the average fidelity of performing a two-bit quantum logic gate operation between any two directly connected qubits in the overall structure after adding another qubit, V represents the average read fidelity of all qubits in the overall structure after adding another qubit, ω and β are pre-configured weighting coefficients, and L represents the total number of feeders in the overall structure after adding another qubit.
[0076] Furthermore, each quantum computing task needs to be completed within the coherence time of the qubit; otherwise, significant errors in the execution results will occur. Therefore, before configuring quantum chip resources for a specific quantum computing task, it is necessary to identify unavailable qubits for that task and exclude them from the first topological structure to be partitioned. Specifically, the quantum computing task mapping method further includes:
[0077] Step 1: Obtain the coherence time of all free qubits that are directly connected to the first topology;
[0078] Step 2: Set the qubits with coherence time less than the first threshold as unusable qubits, wherein the first topology does not include the unusable qubits.
[0079] To facilitate a better understanding of the technical solution of this application by those skilled in the art, the above solution is explained in detail below with reference to a specific example:
[0080] Taking a quantum computing task requiring 4 qubits as an example, it is necessary to find the optimal execution region on a quantum chip for this task. Assuming that there are a total of 6 free qubits available in the existing quantum chip, the structure of the quantum chip can be referenced... Figure 2 The quantum chip is a 2x3 two-dimensional structure. The quantum chip contains quantum bits Q0, Q1, Q2, Q3, Q4, and Q5, and it is assumed that the coherence time of all quantum bits meets the requirements of quantum computing tasks.
[0081] In the initial stage, suitable qubits need to be found among the six qubits. Assuming qubit Q0 meets the requirements, it is set as the overall structure. Since this is insufficient for the quantum computing task, qubits directly connected to the current overall structure (which only includes qubit Q0) need to be merged into the overall structure, i.e., qubits Q1 and Q3 are merged into the overall structure. The reward function values of the overall structures of qubits Q0 and Q1 and Q0 and Q3 are then compared. If the reward function value of the overall structure of qubits Q0 and Q1 is greater than that of the overall structure of qubits Q0 and Q3, the overall structure is updated to include qubits Q0 and Q1, and the first topology is also updated. Since the number of qubits in the first topology is still insufficient for the quantum computing task, other qubits need to be merged. At this point, the qubits to be divided in the overall structure include qubits Q2, Q3, and Q4. These three qubits are merged with the current overall structure to obtain a new overall structure, and the reward function values are compared. Assuming the overall structure of the combination of qubits Q0, Q1, and Q2 has the largest reward function value, qubit Q2 is assigned to the first topology, and the overall structure is updated. At this point, the overall structure and the first topology include qubits Q0, Q1, and Q2. Similarly, the number of qubits in the first topology is still insufficient for the quantum computing task, so other qubits need to be merged. The qubits to be assigned in the current overall structure include qubits Q3, Q4, and Q5. These three qubits are merged with the current overall structure to obtain a new overall structure, and the reward function values are compared. Assuming the overall structure of the combination of qubits Q0, Q1, Q2, and Q3 has the largest reward function value, qubit Q3 is assigned to the first topology, and the overall structure is updated. At this point, the number of qubits in the first topology meets the requirements of the quantum computing task. Therefore, the current first topology is used as the desired structure, and the quantum computing task can be mapped to the current first topology.
[0082] Based on the same inventive concept, this embodiment also proposes a quantum computing task mapping device, comprising:
[0083] The first module is configured to acquire a first qubit with qubit parameters that meet the requirements from the idle qubits of the target quantum chip to form a first topology, wherein the qubit parameters characterize the state of the qubit, and the idle qubit is a qubit in the target quantum chip that is in an idle state.
[0084] The second module is configured to determine whether the quantum computing task to be performed can be executed in the first topology.
[0085] The third module is configured to map the quantum computing task to be executed into the first topology when the determination result is yes;
[0086] The fourth module is configured to update the first topology based on the free qubits that are directly connected to the first topology when the determination result is negative, and return to the step of determining whether the quantum computing task to be performed can be executed in the first topology.
[0087] It is understood that the first module, the second module, the third module, and the fourth module can be implemented in a single device, or any one of these modules can be divided into multiple sub-modules. Alternatively, at least some of the functions of one or more of the first module, the second module, the third module, and the fourth module can be combined with at least some of the functions of other modules and implemented in a single functional module. According to embodiments of the present invention, at least one of the first module, the second module, the third module, and the fourth module can be at least partially implemented as a hardware circuit, such as a Field Programmable Gate Array (FPGA), a Programmable Logic Array (PLA), a System-on-Chip, a System-on-Substrate, a System-on-Package, an Application-Specific Integrated Circuit (ASIC), or can be implemented in hardware or firmware in any other reasonable manner of integrating or packaging the circuit, or in a suitable combination of software, hardware, and firmware implementations. Alternatively, at least one of the first module, the second module, the third module, and the fourth module can be at least partially implemented as a computer program module, which, when run by a computer, can execute the functions of the corresponding module.
[0088] Based on the same inventive concept, this embodiment also proposes a readable storage medium storing a computer program thereon, which, when executed by a processor, can implement the quantum computing task mapping method described in any of the above features.
[0089] The readable storage medium can be a tangible device capable of holding and storing instructions for use by an instruction execution device, such as, but not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof. The computer programs described herein can be downloaded from the readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network can include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. Each computing / processing device's network adapter card or network interface receives the computer program from the network and forwards it for storage in a readable storage medium within the respective computing / processing device. The computer program used to perform the operations of this invention can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, etc., and conventional procedural programming languages such as "C" or similar languages. The computer program can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuits, such as programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), are personalized by utilizing state information from a computer program. These electronic circuits can execute computer-readable program instructions, thereby realizing various aspects of the present invention.
[0090] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, systems, and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by a computer program. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer programs can also be stored in a readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the readable storage medium storing the computer program comprises an article of manufacture including instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams.
[0091] A computer program may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the computer program executing on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.
[0092] Based on the same inventive concept, this embodiment also proposes an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the quantum computing task mapping method described in any of the above features.
[0093] Based on the same inventive concept, this embodiment also proposes a quantum computer operating system, including the quantum computing task mapping method described in any of the above-described features.
[0094] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," or "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0095] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.
Claims
1. A quantum computing task mapping method, characterized in that, include: In the idle qubits of the target quantum chip, a first qubit whose qubit parameters meet the requirements is obtained to form a first topology, wherein the qubit parameters characterize the state of the qubit, and the idle qubit is the qubit in the target quantum chip that is in an idle state; Determine whether the quantum computing task to be executed can be performed in the first topology; If so, the quantum computing task to be executed is mapped into the first topology; If not, the first topology is updated based on the free qubits that are directly connected to the first topology, and the process returns to the step of determining whether the quantum computing task to be performed can be performed in the first topology. The step of updating the first topology based on idle qubits that are directly connected to the first topology includes: Idle qubits that are directly connected to the first topology are obtained as qubits to be partitioned, wherein each of the qubits to be partitioned and the first topology constitute an integral structure. Based on the number of feed lines in the overall structure, one of the qubits to be partitioned is selected from all the qubits to be partitioned and partitioned into the first topology to update the first topology. The feed lines are coupled to connect several qubits in the quantum chip and transmit quantum state information.
2. The quantum computing task mapping method as described in claim 1, characterized in that, The step of updating the first topology based on idle qubits that are directly connected to the first topology includes: Idle qubits that are directly connected to the first topology are obtained as qubits to be partitioned, wherein each of the qubits to be partitioned and the first topology constitute an integral structure. Based on the compactness of the overall structure, one of the qubits to be partitioned is selected from all the qubits to be partitioned and assigned to the first topology to update the first topology.
3. The quantum computing task mapping method as described in claim 1, characterized in that, The step of updating the first topology based on idle qubits that are directly connected to the first topology includes: Idle qubits that are directly connected to the first topology are obtained as qubits to be partitioned, wherein each of the qubits to be partitioned and the first topology constitute an integral structure. Based on the fidelity parameters of the qubits in the overall structure, one of the qubits to be partitioned is selected from all the qubits to be partitioned and partitioned into the first topology to update the first topology. The fidelity parameters include one or a combination of three factors: read fidelity, fidelity of performing a single-qubit quantum logic gate operation on any qubit, fidelity of performing a two-qubit quantum logic gate operation between any two qubits that are directly connected.
4. The quantum computing task mapping method as described in claim 1, characterized in that, The step of updating the first topology based on idle qubits that are directly connected to the first topology includes: Idle qubits that are directly connected to the first topology are obtained as qubits to be partitioned, wherein each of the qubits to be partitioned and the first topology constitute an integral structure. Based on the compactness of the overall structure and the fidelity parameters and number of feed lines of the qubits in the overall structure, one qubit to be partitioned is selected from all the qubits to be partitioned and partitioned into the first topology to update the first topology. The fidelity parameters include one or a combination of readout fidelity, fidelity of performing a single-qubit quantum logic gate operation on any qubit, fidelity of performing a two-qubit quantum logic gate operation between any two qubits with a direct connection relationship, and the feed lines couple and connect several qubits in the quantum chip and transmit quantum state information.
5. The quantum computing task mapping method as described in claim 4, characterized in that, The step of dividing several qubits to be divided into the first topology according to the compactness of the overall structure and the fidelity parameters and number of feed lines of the qubits in the overall structure to update the first topology includes: The weighting coefficients for the density, fidelity parameters, and number of feeders are determined based on the quantum computing task to be performed and the target quantum chip. Based on the determined weighting coefficients, several qubits to be divided are assigned to the first topology according to the compactness of the overall structure, the fidelity parameters of the qubits in the overall structure, and the number of feed lines, so as to update the first topology.
6. The quantum computing task mapping method as described in claim 1, characterized in that, The quantum computing task mapping method also includes: Obtain the coherence time of all free qubits that are directly connected to the first topology; Quantum bits with a coherence time less than a first threshold are set as unusable qubits, wherein the first topology does not include the unusable qubits.
7. A quantum computing task mapping device, characterized in that, include: The first module is configured to acquire a first qubit with qubit parameters that meet the requirements from the idle qubits of the target quantum chip to form a first topology, wherein the qubit parameters characterize the state of the qubit, and the idle qubit is a qubit in the target quantum chip that is in an idle state. The second module is configured to determine whether the quantum computing task to be performed can be executed in the first topology. The third module is configured to map the quantum computing task to be executed into the first topology when the determination result is yes; The fourth module is configured to update the first topology based on the free qubits that are directly connected to the first topology when the judgment result is negative, and return to the step of judging whether the quantum computing task to be performed can be executed in the first topology. The step of updating the first topology based on idle qubits that are directly connected to the first topology includes: Idle qubits that are directly connected to the first topology are obtained as qubits to be partitioned, wherein each of the qubits to be partitioned and the first topology constitute an integral structure. Based on the number of feed lines in the overall structure, one of the qubits to be partitioned is selected from all the qubits to be partitioned and partitioned into the first topology to update the first topology. The feed lines are coupled to connect several qubits in the quantum chip and transmit quantum state information.
8. A readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it can implement the quantum computing task mapping method according to any one of claims 1 to 6.
9. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to perform the quantum computing task mapping method according to any one of claims 1 to 6.
10. A quantum computer operating system, characterized in that, Including the quantum computing task mapping method as described in any one of claims 1-6.