Display Driver and Display Module

Abstract

Display driver and display module, the display driver includes: a driver circuit, which drives the electro-optical panel; an output terminal, which outputs the output signal from the driver circuit; an output line, which connects the output of the driver circuit to the output terminal; and a check circuit, which detects abnormalities in the output signal by monitoring the voltage of the output signal output by the driver circuit to the output line. The check circuit determines whether the voltage of the output signal is abnormal by comparing a reference voltage that changes according to a given period with the voltage of the output signal.

Description

Technical Field

[0001] The present invention relates to a display driver, a display module, and the like. Background Art

[0002] Patent Document 1 discloses a common driver for a display panel. The common driver includes: a voltage output circuit that outputs different inspection voltages to an inspection voltage output line during a first period and a second period, outputting a first voltage to a first segment electrode and a second voltage to a second segment electrode during the first and second periods; a signal output circuit that outputs a first signal voltage to a signal voltage output line during the first period and a second signal voltage to the signal voltage output line during the second period; and an inspection circuit that detects the presence of an abnormality based on the voltages of the inspection voltage output line and the signal voltage output line. This common driver can detect abnormalities in the voltages applied to the electrodes of the display panel.

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2021-56344

[0004] In the common driver of the display panel shown in Patent Document 1, the reference voltage value set to determine whether the output voltage of the output signal of the common driver is normal is fixed. Therefore, the abnormal state may not be properly determined based on the output voltage value in the abnormal state. Summary of the Invention

[0005] One embodiment of the present invention relates to a display driver, comprising: a driver circuit that drives an electro-optical panel; an output terminal that outputs an output signal from the driver circuit; an output line that connects the output of the driver circuit to the output terminal; and a check circuit that detects abnormalities in the output signal by monitoring the voltage of the output signal output by the driver circuit to the output line. The check circuit determines whether the voltage of the output signal is abnormal by comparing a reference voltage whose voltage changes according to a given period with the voltage of the output signal.

[0006] Another aspect of the present invention relates to a display module including the display driver described above and the electro-optical panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is an example of the structure of the display driver in this embodiment.

[0008] Figure 2 This is an explanatory diagram of the wiring state of the display driver and the segment electrodes of the electro-optical panel.

[0009] Figure 3This is an explanatory diagram of the wiring state of the display driver and the common electrode of the electro-optical panel.

[0010] Figure 4 This is a detailed configuration example of the display driver according to this embodiment.

[0011] Figure 5 This is a configuration example of the electrostatic protection circuit of this embodiment.

[0012] Figure 6 This is a configuration example of the electrostatic protection circuit of this embodiment.

[0013] Figure 7 This is a configuration example of the electrostatic protection circuit of this embodiment.

[0014] Figure 8 This is a configuration example of the reference voltage generating circuit of this embodiment.

[0015] Figure 9 This is a configuration example of a selector in the reference voltage generating circuit of this embodiment.

[0016] Figure 10 This is an example of a criterion for determining an abnormal state of the voltage of an output signal in a segment inspection circuit.

[0017] Figure 11 This is the equivalent circuit diagram when the panel signal line and the power supply voltage are short-circuited.

[0018] Figure 12 These are examples of waveforms of various signals when the panel signal line is short-circuited to the power supply voltage.

[0019] Figure 13 These are waveform examples of various signals when a panel signal line is short-circuited to the power supply voltage and the abnormal voltage state is not appropriately determined.

[0020] Figure 14 These are waveform examples of various signals when an abnormal voltage state is appropriately determined when a panel signal line is short-circuited to a power supply voltage.

[0021] Figure 15 This is the equivalent circuit diagram when the panel signal line is short-circuited to the ground.

[0022] Figure 16 These are examples of waveforms of various signals when the panel signal line is short-circuited to ground.

[0023] Figure 17 These are waveform examples of various signals when a panel signal line is short-circuited to ground and an abnormal voltage state is not appropriately determined.

[0024] Figure 18These are waveform examples of various signals when an abnormal voltage state is appropriately determined when a panel signal line is short-circuited to ground.

[0025] Figure 19 This is a first signal waveform example of the reference voltage in this embodiment when the panel signal line and the power supply voltage are short-circuited.

[0026] Figure 20 This is a first signal waveform example of the reference voltage in this embodiment when the panel signal line is short-circuited to the ground.

[0027] Figure 21 This is a second signal waveform example of the reference voltage in this embodiment when the panel signal line and the power supply voltage are short-circuited.

[0028] Figure 22 This is a second signal waveform example of the reference voltage in this embodiment when the panel signal line is short-circuited to the ground.

[0029] Figure 23 This is an example of command setting of the first reference voltage.

[0030] Figure 24 This is an example of command setting of the second reference voltage.

[0031] Figure 25 This is a structural example of the display module of this embodiment.

[0032] Label Description

[0033] 20: Display driver; 30: Segment driver circuit; 31: Driver circuit; 32: Level shifter; 34: Output driver; 40: Segment check circuit; 41: Check circuit; 50: Row latch; 60: Data storage unit; 70: Common driver circuit; 80: Common check circuit; 82: Polarity inversion circuit; 90: Electrostatic protection circuit; 100: Control circuit; 102: Oscillation circuit; 110: Interface circuit; 112: Instruction setting register; 12 0: Processing device; 132: Internal circuit; 140: Reference voltage generation circuit; 142: Selector; 144: Selector; 150: Comparator circuit; 152: Level shifter; 160: Determination circuit; 200: Electro-optical panel; 300: Display module; CQ: Determination result; EC: Common electrode; ECD1: Common electrode; ECD2: Common electrode; ECS1-ECS7: Common electrodes; ES: Segment electrode; ESD1: Segment electrode; EESD 2: Segment electrode; ESS1~ESS7: Segment electrode; LO: Output line; LP: Latch pulse; LPN: Panel signal line; LSD1~LSD4: Segment signal line; LSS1~LSS7: Segment signal line; LCD1~LSD6: Common signal line; POL: Polarity signal; RESD: Protection resistor; RH0~RH7: Resistors; RLO~RL7: Resistors; RON: Segment drive data; SGDT: Judgment result; SGMO: Segment monitor output signal; SGO: Output signal; SGOP: Output signal; SLAT: Segment signal; SVREFH: Signal; SVREFL: Signal; SW: Switch; T: Frame period ; T1: first frame period; T2: second frame period; T3: third frame period; T4: fourth frame period; T5: fifth frame period; T6: sixth frame period; T7: seventh frame period; T8: eighth frame period; TCD1: common terminal; TCD2: common terminal; Tdiv: frame division period; TO: output terminal; TSD1~TSD4: segment terminals; TSS1~TSS7: segment terminals; VDD: power supply voltage; VDV1: divided voltage; VDV2: divided voltage; VGND: ground voltage; VH: first voltage; VL: second voltage; VREF: reference voltage; VREFH: first reference voltage; VREFL: second reference voltage DETAILED DESCRIPTION

[0034] The present embodiment will be described below. The present embodiment described below does not unduly limit the contents of the claims. All of the structures described in this embodiment are not necessarily essential components.

[0035] 1. Display driver

[0036] Figure 1The following is a structural example of the display driver 20 of this embodiment. The display driver 20 includes a segment driver circuit 30, a common driver circuit 70, a segment check circuit 40, a common check circuit 80, a row latch 50, a data storage unit 60, an oscillation circuit 102, a control circuit 100, and an interface circuit 110. The processing device 120 is provided outside the display driver 20. The processing device 120 can communicate with the display driver 20, for example, regarding information for causing the electro-optical panel 200 to display. The electro-optical panel 200 performs the following operations based on the signal from the display driver 20. Figure 2 、 Figure 3 Display of numbers etc. displayed by segments as described in .

[0037] The interface circuit 110 performs communication between the display driver 20 and the processing device 120. Specifically, the interface circuit 110 receives the segment drive data SGD from the processing device 120. The segment drive data SGD is used to control the display driver 20 to be described later. Figure 2 、 Figure 3 The segment drive data SGD is data used to control the display of the electro-optical panel 200 described above. For example, in the case of static driving, the segment drive data SGD is data for turning the display of the electro-optical panel 200 on or off. Alternatively, in the case of PWM driving in static driving, the segment drive data SGD is data for setting the display grayscale of the electro-optical panel 200.

[0038] The processing device 120 is a host device for the display driver 20. The processing device 120 is, for example, a processor or a display controller. The processor is, for example, a CPU or a microcomputer. The interface circuit 110 can use a serial interface such as I2C (Inter Integrated Circuit) or SPI (Serial Peripheral Interface). Alternatively, a parallel interface can be used. The interface circuit 110 can include input / output buffer circuits and a control circuit to implement these communication methods.

[0039] The control circuit 100 is a logic circuit that operates according to a clock signal input from the oscillation circuit 102. The control circuit 100 is responsible for all the control required to drive the electro-optical panel 200. Specifically, the control circuit 100 controls the segment driver circuit 30 and the common driver circuit 70, which will be described later. Figure 4 Monitoring of the display state of the electro-optical panel 200 described in the above, etc.

[0040] The data storage unit 60 mainly stores information input from the control circuit 100. The data storage unit 60 is, for example, a RAM. Alternatively, the data storage unit 60 may be a register.

[0041] The row latch 50 latches the segment drive data for one frame read from the data storage unit 60. The row latch 50 is formed of, for example, a flip-flop circuit.

[0042] The segment driver circuit 30 drives the photovoltaic panel 200. The segment driver circuit 30 performs the following steps. Figure 2 Specifically, the segment driver circuit 30 supplies voltage to the segment electrodes ES by outputting segment drive signals corresponding to polarities from the segment terminals.

[0043] The common driver circuit 70 drives the electro-optical panel 200 together with the segment driver circuit 30. The common driver circuit 70 drives the electro-optical panel 200. Figure 3 Specifically, the common driver circuit 70 supplies a voltage to the common electrode EC by outputting a common drive signal corresponding to the polarity from the common terminal. The common drive signal is a low-level signal when the polarity is positive and a high-level signal when the polarity is negative.

[0044] The segment inspection circuit 40 checks whether the display of the electro-optical panel 200 is normal. Specifically, it checks whether the voltage of the output signal of the segment driver circuit 30 is the desired voltage. The segment inspection circuit 40 outputs the inspection result to the control circuit 100. If the inspection result indicates a driving abnormality, the control circuit 100 notifies the processing device 120 of the driving abnormality via the interface circuit 110.

[0045] Similar to the segment inspection circuit 40, the common inspection circuit 80 also inspects whether the display of the electro-optical panel 200 is normal. However, unlike the segment inspection circuit 40, the common inspection circuit 80 inspects whether the voltage of the output signal of the common driver circuit 70 is the expected voltage. The common inspection circuit 80 outputs the inspection result to the control circuit 100. If the inspection result indicates a driving abnormality, the control circuit 100 notifies the processing device 120 of the driving abnormality via the interface circuit 110.

[0046] Figure 2 and Figure 3 1 is a diagram showing the wiring state of the electro-optical panel 200 and the display driver 20 . Figure 2 FIG. 4 shows an example of connection between the display driver 20 and the segment electrodes ES. Figure 3 1 and 2 show an example of connection between the display driver 20 and the common electrode EC. The electro-optical panel 200 includes a glass substrate provided with the segment electrodes ES, a glass substrate provided with the common electrode EC, and liquid crystal provided therebetween.

[0047] like Figure 2 As shown, the electro-optical panel 200 includes segment electrodes ESD1, ESD2, ESS1 to ESS7 and segment signal lines LSD1 to LSD4, LSS1 to LSS7. In this embodiment, these segment electrodes and segment signal lines are collectively referred to as segment electrodes ES and segment signal lines LS. The display driver 20 includes segment terminals TSD1 to TSD4, TSS1 to TSS7 and common terminals TCD1 and TCD2. Figure 3 As shown, the electro-optical panel 200 includes common electrodes ECD1, ECD2, ECS1 to ECS7, and common signal lines LCD1 to LSD6. In this embodiment, these common electrodes and common signal lines are appropriately collectively referred to as common electrodes EC and common signal lines LC. The segmented electrode ES and the segmented signal line LS are transparent conductive films arranged on a glass substrate. The transparent conductive film is, for example, ITO (Indium Tin Oxide). In the transparent conductive film, the portion opposite to the common electrode EC sandwiched between the liquid crystal is the segmented electrode ES, and the portion supplying the segmented drive signal to the segmented electrode ES is the segmented signal line LS. For example, the segmented electrode ESD1 and the segmented signal lines LSD1 and LSD2 are formed by an integrated transparent conductive film. Among them, Figure 3 The portion opposite to the common electrode ECD1 is the segment electrode ESD1. In the following description, the segment signal lines LS and the common signal line LC are appropriately referred to as panel signal lines LPN, and the segment terminals TSD1 to TSD4, TSS1 to TSS7 and the common terminals TCD1 and TCD2 are appropriately referred to as output terminals TO.

[0048] The display driver 20 is mounted on the glass substrate of the electro-optical panel 200. Specifically, the display driver 20 is an integrated circuit device, and the pads formed on its semiconductor substrate correspond to the segment terminals TSD1 to TSD4 and TSS1 to TSS7. Furthermore, the semiconductor substrate is mounted on the electro-optical panel 200 in such a manner that the surface provided with the pads faces the glass substrate of the electro-optical panel 200. At this time, the segment terminal TSD1 is connected to the segment signal line LSD1, for example, via a metal bump or the like. The segment terminals TSD2 to TSD4 are similarly connected to the segment signal lines LSD2 to LSD4, and the segment terminals TSS1 to TSS7 are similarly connected to the segment signal lines LSS1 to LSS7. In addition, in Figure 2 In the figure, the surface of the semiconductor substrate where no segment terminals are provided can be seen, but segment terminals hidden in the semiconductor substrate are also shown.

[0049] The display driver 20 supplies voltage to the segment electrode ESD1 via the segment signal line LSD1 by outputting a segment drive signal from the segment terminal TSD1. The segment electrode ESD1 has a predetermined icon shape, and the display driver 20 supplies voltage to the segment electrode ESD1, and the icon is controlled to be displayed or not. Then, the segment drive signal is fed back from the segment electrode ESD1 to the segment terminal TSD2 via the segment signal line LSD2. This fed-back segment drive signal is called a segment monitoring signal. The display driver 20 detects an abnormality in the voltage supplied to the segment electrode ESD1 based on the segment monitoring signal input to the segment terminal TSD2. This abnormality refers to, for example, the failure to apply the voltage of the segment drive signal that should have been applied to the segment electrode ES. Examples of such abnormalities include abnormalities caused by an abnormality in the segment signal line, poor connection of the segment terminal, and an abnormality in the segment drive signal.

[0050] Similarly, the display driver 20 supplies a voltage to the segment electrode ESD2 by outputting a segment drive signal from the segment terminal TSD3 . The display driver 20 then detects an abnormality in the voltage supplied to the segment electrode ESD2 based on a segment monitoring signal input to the segment terminal TSD4 .

[0051] The display driver 20 outputs segment drive signals from the segment terminals TSS1 to TSS7 , thereby supplying voltages to the segment electrodes ESS1 to ESS7 via the segment signal lines LSS1 to LSS7 .

[0052] 2. Detailed structure example

[0053] Figure 4 A detailed configuration example of the display driver 20 according to this embodiment is shown. Figure 4 The display driver 20 is in addition to Figure 1 In addition to the structure of the display driver 20 shown, it also includes a polarity inversion circuit 82, an electrostatic protection circuit 90, and an output terminal TO. In addition, the driver circuit 31 includes a level shifter 32 and an output driver 34, and the inspection circuit 41 includes a reference voltage generation circuit 140, a comparison circuit 150, a level shifter 152, a determination circuit 160, and a switch SW. Figure 4 The driver circuits 31 in FIG. 3 correspond to the segment driver circuits 30 and the common driver circuit 70 , respectively, and the inspection circuits 41 correspond to the segment inspection circuits 40 and the common inspection circuit 80 , respectively.

[0054] The polarity inversion circuit 82 performs polarity inversion processing on the segment drive data SGD based on the polarity signal POL from the control circuit 100. That is, the polarity inversion circuit 82 outputs the segment drive data SGD having the same logic level as the segment drive data SGD in a positive polarity frame, and outputs the segment drive data SGD with the logic level inverted in a negative polarity frame.

[0055] The level shifter 32 of the driver circuit 31 shifts the level of the segment signal SLAT. Specifically, the level shifter 32 outputs a signal with the same waveform as the input segment signal SLAT but with a different voltage. The level shifter 32 can be composed of an inverter, a MOS transistor, a resistor, and the like.

[0056] The output driver 34 outputs an output signal SGO to the electrostatic protection circuit 90 based on the signal output from the level shifter 32. The output driver 34 can be configured by, for example, an inverter including a P-type transistor and an N-type transistor.

[0057] The output terminal TO is an external connection terminal of the display driver 20. When the display driver 20 supplies voltage to the segment electrodes ES and the common electrodes EC of the electro-optical panel 200, the voltage is supplied from the output terminal TO. Figure 2 、 Figure 3 As explained in the Figure 4 The output terminal TO corresponds to .

[0058] The output line LO is an electrical wiring that electrically connects the driver circuit 31 to the output terminal TO. The output signal SGO output from the driver circuit 31 is input to the electrostatic protection circuit 90 via the output line LO. Furthermore, the output signal SGO is input from the output terminal TO to the electro-optical panel 200 via the panel signal line LPN. The output signal output from the output terminal TO to the electro-optical panel 200 is distinguished from the output signal SGO within the display driver 20 and is referred to as the output signal SGOP. This supplies voltage to the segment electrodes ES of the electro-optical panel 200.

[0059] Reference voltage generation circuit 140 generates a reference voltage VREF that serves as a reference when inspection circuit 41 determines whether the voltage of output signal SGO is a predetermined voltage. The generated reference voltage VREF is then output to comparison circuit 150. Reference voltage generation circuit 140 can be implemented, for example, by a bandgap reference circuit, a circuit utilizing a gate work function difference, or a circuit utilizing a threshold voltage difference caused by varying a channel impurity concentration.

[0060] As described above, the display driver 20 of this embodiment includes a driver circuit that drives the electro-optical panel 200; an output terminal TO that outputs an output signal SGO from the driver circuit; an output line LO that connects the output of the driver circuit to the output terminal TO; and a detection circuit 41 that detects abnormalities in the output signal by monitoring the voltage of the output signal SGO outputted by the driver circuit to the output line LO. Furthermore, the detection circuit 41 determines whether the voltage of the output signal is abnormal by comparing a reference voltage VREF, which varies with a predetermined period, with the voltage of the output signal. For example, with a certain setting of the reference voltage VREF, it may be impossible to accurately determine whether the voltage of the output signal SGO is the expected voltage. However, according to this embodiment, the reference voltage VREF can be varied with a predetermined period, enabling reliable detection of abnormalities in the output signal SGO based on various abnormal conditions. Furthermore, in the display driver 20 of this embodiment, the predetermined period is the frame period T. Alternatively, the detection circuit 41 can compare the reference voltage VREF, which varies with the frame period T, with the voltage of the output signal SGO. In this way, an abnormal state of the voltage of the output signal SGO of the driver circuit 31 can be detected during the frame period T. Furthermore, the predetermined period can be the frame division period Tdiv obtained by dividing the frame period T, and the inspection circuit can compare the voltage of the output signal SGO with the reference voltage VREF, whose voltage varies according to the frame division period Tdiv. Thus, when the predetermined period of the reference voltage VREF is set to the frame division period Tdiv, the period of the signal waveform of the reference voltage VREF becomes shorter than when the predetermined period is set to the frame period T, enabling prompt detection of an abnormal state of the voltage of the output signal SGO.

[0061] Figure 4 The electrostatic protection circuit 90 is an ESD (Electro-Statics Discharge) protection circuit. It is provided between the driver circuit 31 and the output terminal TO. When a surge voltage, such as static electricity, is applied to the output terminal TO, the electrostatic protection circuit 90 is configured to discharge the charge generated by static electricity to the ground or power supply, thereby protecting the circuits and components within the display driver 20. For example, the electrostatic protection circuit 90 is comprised of an electrostatic protection element serving as an ESD protection element. Examples of the electrostatic protection element include a diode for electrostatic protection and a resistor for electrostatic protection.

[0062] exist Figures 5 to 7A specific structural example of the electrostatic protection circuit 90 is shown in FIG. The basic structure of the electrostatic protection circuit 90 is as follows: an output signal SGOP including noise caused by a surge voltage is inputted from the outside to the internal circuit 132 via the protection resistor RESD. In addition, two PN diodes are provided in a manner connected to either or both of the wiring between the output terminal TO and the protection resistor RESD, and the wiring between the protection resistor RESD and the internal circuit 132, so that the charge generated by the overvoltage is discharged to the power supply or the ground. Figure 5 In the structure, the wiring connecting the output terminal TO and the protection resistor RESD is connected to the power supply and the ground respectively via the PN diode. Figure 6 In the structure, the wiring connecting the protection resistor RESD and the internal circuit 132 is connected to the power supply and the ground respectively via the PN diode. Figure 7 In the structure of , the PN diode is connected to the wiring connecting the output terminal TO and the protection resistor RESD, and the wiring connecting the protection resistor RESD and the internal circuit 132, respectively.

[0063] Thus, the display driver 20 of this embodiment may also include an electrostatic protection circuit 90 provided between the output line LO and the output terminal TO. In this manner, when a surge voltage, such as static electricity, is applied to the output terminal TO, the charge caused by the static electricity is discharged to the ground or power supply, thereby protecting the internal circuits and components of the display driver 20 from adverse conditions caused by the overvoltage. Furthermore, the electrostatic protection circuit 90 of the display driver 20 of this embodiment may also include a protection resistor RESD provided between the output line LO and the output terminal TO. In this manner, even when a larger surge voltage is applied to the output terminal TO, the internal circuits and components of the display driver 20 can be appropriately protected from adverse conditions caused by the overvoltage.

[0064] Figure 4 A switch SW is provided between the output line LO connecting the driver circuit 31 and the electrostatic protection circuit 90 and the comparison circuit 150 of the inspection circuit 41. The switch SW is controlled to be on and off based on a signal from the control circuit 100. Specifically, when the switch is on, the voltage of the output signal SGO of the output line LO is input to the comparison circuit 150, and the comparison circuit 150 can monitor the voltage of the output signal SGO. The switch SW can be implemented using a MOS transistor or the like.

[0065] Next, the above-mentioned reference voltage generating circuit 140 will be described in detail. Figure 8The following illustrates a detailed configuration example of the reference voltage generation circuit 140. The reference voltage generation circuit 140 includes a selector 142, a selector 144, and resistors RH0 to RH7 and RL0 to RL7. The reference voltage VREF includes a first reference voltage VREFH and a second reference voltage VREFL. When the inspection circuit 41 inspects the voltage of the output signal SGO for abnormalities, the first reference voltage VREFH is used as the reference voltage for inspecting the High state of the signal waveform, while the second reference voltage VREFL is used as the reference voltage for inspecting the Low state. The control circuit 100 instructs the reference voltage generation circuit 140 to select one of multiple voltages as the reference voltage VREF. Based on this instruction, the reference voltage generation circuit 140 generates the first reference voltage VREFH and the second reference voltage VREFL. Specifically, the control circuit 100 transmits a signal SVREFH to the selector 142 for setting the first reference voltage VREFH. The selector 142 generates the first reference voltage VREFH based on the signal SVREFH. Furthermore, the control circuit 100 transmits a signal SVREFL for setting the second reference voltage VREFL to the selector 144. The selector 144 generates the second reference voltage VREFL based on the signal SVREFL. Resistors RH0 to RH7 are connected in series between the ground voltage VGND and the power supply voltage VDD. Furthermore, voltages VRH0 to VRH7 and VRL0 to VRL7 are generated within the reference voltage generation circuit 140 in response to voltage drops across the resistors RH0 to RH7. Voltages VRH0 to VRH7 are input to the selector 142, and voltages VRL0 to VRL7 are input to the selector 144.

[0066] Figure 9 The internal structure of selectors 142 and 144 of reference voltage generation circuit 140 is shown. Selectors 142 and 144 are composed of inverters and multiple switches SW. Input voltage signal IN0 corresponds to voltage VRH0 or voltage VRL0. The same applies to input voltage signals IN1 to IN7. Selectors 142 and 144 select one of input voltage signals IN1 to IN7 in response to an instruction from control circuit 100 and can output the voltage instructed by control circuit 100. In this way, selectors 142 and 144 generate a first reference voltage VREFH and a second reference voltage VREFL, which are then output from reference voltage generation circuit 140.

[0067] Figure 4 The comparison circuit 150 checks the voltage of the output signal SGO of the driver circuit 31. Specifically, the comparison circuit 150 performs this check by comparing the voltage of the output signal SGO with the first reference voltage VREFH and the second reference voltage VREFL. The comparison circuit 150 can be formed of a comparator, for example. Figure 10An example of a determination criterion for an abnormal state of the output signal voltage is shown. This determination is performed by comparing the voltage of the output signal SGO with the first voltage VH, the second voltage VL, the first reference voltage VREFH, and the second reference voltage VREFL. Here, the first voltage VH is a high-potential voltage, such as the power supply voltage. Furthermore, the second voltage VL is a low-potential voltage, such as the ground voltage VGND. Furthermore, the relationship VH>VREFH>VREFL>VL exists. The comparison circuit 150 determines that the output signal SGO is in a high state if the voltage is between the first reference voltage VREFH and the first voltage VH. It determines that the output signal SGO is in a low state if the voltage is between the second voltage VL and the second reference voltage VREFL. Furthermore, it determines that the output voltage is in a low state if the voltage is between the first reference voltage VREFH and the second reference voltage VREFL. Furthermore, it determines that the output voltage is in an error state if the voltage is between the first reference voltage VREFH and the second reference voltage VREFL. The comparison circuit 150 outputs this determination result CQ to the level shifter 152.

[0068] The level shifter 152 performs a level shift on the output signal of the comparison circuit 150. Specifically, the level shifter 152 outputs a signal having the same waveform as the determination result CQ from the comparison circuit 150, but with a different voltage value. For example, the level shifter 152 performs a level shift from a high power supply voltage level to a low power supply voltage level. Like the level shifter 32, the level shifter 152 can be composed of an inverter, a MOS transistor, a resistor, and the like.

[0069] The determination circuit 160 determines whether the output signal SGO output from the driver circuit 31 is normally supplied to the segment electrodes ES of the electro-optical panel 200 based on the segment monitor output signal SGMO output from the level shifter 152 , and sends a determination result SGDT to the control circuit 100 .

[0070] As described above, in the display driver 20 of this embodiment, the inspection circuit 41 may also include a reference voltage generation circuit 140 that generates a plurality of voltages and outputs a reference voltage VREF selected from the plurality of voltage levels at a predetermined cycle; and a comparison circuit 150 that compares the reference voltage VREF with the voltage of the output signal SGO. Thus, by comparing the reference voltage VREF selected from a plurality of voltage levels at a predetermined cycle with the voltage of the output signal SGO in the comparison circuit 150, abnormalities in the voltage of the output signal SGO of the driver circuit 31 can be reliably detected.

[0071] Furthermore, the control circuit 100 of the display driver 20 of this embodiment may instruct the reference voltage generation circuit 140 which of a plurality of voltages to select as the reference voltage VREF. In this manner, when the voltage variation of the output signal SGO of the driver circuit 31 is within a fixed range, the setting level of the reference voltage VREF can be preset in the control circuit 100.

[0072] Figure 11 This is an equivalent circuit diagram of the display driver 20 when the panel signal line LPN is short-circuited with the power supply voltage VDD, which is a wiring between the output terminal TO and the segment electrode ES of the electro-optical panel 200. Figure 11 In this case, the N-type transistor constituting the output driver 34 is turned on, and the voltage of the output signal SGO is set to the ground voltage VGND. The output driver 34 can be composed of a P-type transistor and an N-type transistor connected in series between VDD and GND. Furthermore, the switch SW is turned on. In this case, since the panel signal line LPN is shorted to the power supply voltage VDD, the output signal SGOP supplied to the electro-optical panel 200 is at the power supply voltage VDD. Consequently, the voltage at the wiring node between the on-resistor RON and the protection resistor RESD is between the ground voltage VGND and the power supply voltage VDD, reaching a voltage VDV1 = (VDD - VGND) × RON / (RON + RESD) divided by the on-resistance RON of the N-type transistor of the output driver 34 and the protection resistor RESD. In other words, during the period when the N-type transistor of the output driver 34 is turned on and the output signal SGO is originally at the ground voltage VGND, the short circuit causes the output signal SGO to increase to the divided voltage VDV1 = (VDD - VGND) × RON / (RON + RESD).

[0073] Figure 12 1 is a signal waveform diagram showing the waveforms of various signals when the panel signal line LPN is short-circuited to the power supply voltage VDD. The segment drive data SGD is a rectangular wave synchronized with the fixed frequency clock signal controlled by the oscillation circuit 102. The latch pulse LP is a pulse signal for latching the segment drive data SGD at the center of the high level period or the low level period. The segment signal SLAT is a signal that latches the segment drive data SGD by the latch pulse LP. Here, Figure 12 As shown, T1 is set as the first frame period, T2 is set as the second frame period, T3 is set as the third frame period... Figures 13 to 22 The frame period is a period of a display frame of the electro-optical panel 200, and the latch pulse LP is a pulse signal that becomes a high level in accordance with the frame period. Figure 12The figure shows a situation where the short circuit between panel signal line LPN and power supply voltage VDD begins during the fifth frame period T5. After the short circuit occurs during the fifth frame period T5, the voltage of panel signal line LPN reaches power supply voltage VDD due to the short circuit. Therefore, as described above, the voltage of output signal SGO of output line LO reaches the divided voltage VDV1 = (VDD - VGND) × RON / (RON + RESD) during the fifth frame period T5 and the seventh frame period T7, periods when it would normally be at ground voltage.

[0074] Figure 13 It shows Figure 12 Signal waveform diagram of various signal waveforms in the comparison circuit 150 and the determination circuit 160 in the case of . Figure 13 The signal waveform diagram described in the upper section is a signal waveform diagram that overlaps the output signal SGO, the first reference voltage VREFH, and the second reference voltage VREFL input to the comparison circuit 150. Here, the output signal SGO is represented by a solid line, the first reference voltage VREFH is represented by a dotted line, and the second reference voltage VREFL is represented by a dashed line. As described above, during the fifth frame period T5 and the seventh frame period T7 of the output signal SGO output divided voltage VDV1 = (VDD-VGND)×RON / (RON+RESD), the output signal SGO does not drop to the ground voltage VGND, so the determination circuit 160 must have determined that the voltage of the output signal SGO is abnormal. However, in Figure 13 In the example, the second reference voltage VREFL indicated by the dot-dash line is set to a voltage greater than the divided voltage VDV1, so that the voltage of the output signal SGO in the fifth and seventh frame periods T5 and T7 is erroneously determined to be normal. Figure 14 is with Figure 13 An example of a case where the voltage levels of the first reference voltage VREFH and the second reference voltage VREFL are different from each other. Figure 13 Compared with the case of , the first reference voltage VREFH becomes a voltage close to the first voltage VH, for example, the power supply voltage VDD, and the second reference voltage VREFL becomes a value close to the second voltage VL, for example, the ground voltage VGND. Figure 13 In the fifth frame period T5 and the seventh frame period T7, which are erroneously determined in the case of the output signal SGO, the voltage of the output signal SGO becomes a voltage higher than the second reference voltage VREFL indicated by the dotted line, and therefore the output signal SGO is correctly determined to be in an abnormal state.

[0075] Figure 15 1 is an equivalent circuit diagram of the display driver 20 when the panel signal line LPN is short-circuited to the ground voltage VGND, that is, the wiring between the output terminal TO and the segment electrode ES of the electro-optical panel 200. Figure 15 In this case, the P-type transistor constituting output driver 34 is turned on, and the voltage of output signal SGO is set to power supply voltage VDD. Furthermore, switch SW is turned on. In this case, panel signal line LPN is shorted to ground voltage VGND, so output signal SGOP supplied to electro-optical panel 200 is at ground voltage VGND. Consequently, the voltage of output signal SGO at the wiring node between on-resistance RON and protection resistor RESD is between ground voltage VGND and power supply voltage VDD. This voltage is divided by the on-resistance RON of the P-type transistor of output driver 34 and the protection resistor RESD of electrostatic protection circuit 90, namely, VDV2 = (VDD - VGND) × RESD / (RON + RESD). In other words, during the period when the P-type transistor of output driver 34 is turned on and output signal SGO is originally at power supply voltage VDD, this short circuit causes output signal SGO to decrease to the divided voltage VDV2 = (VDD - VGND) × RESD / (RON + RESD).

[0076] Figure 16 The signal waveform diagram shows the waveforms of various signals when the panel signal line LPN is short-circuited with the ground voltage VGND. The segment drive data SGD, the latch pulse LP and the segment signal SLAT are shown in FIG. Figure 12 As described in . Figure 16 FIG. 4 shows a case where the short circuit occurs in the middle of the fourth frame period T4. Figure 16 Due to this short circuit, the voltage of the panel signal line LPN becomes the ground voltage VGND from the middle of the fourth frame period T4. Therefore, as described above, the output signal SGO becomes the divided voltage VDV2 = (VDD-VGND) × RESD / (RON + RESD) obtained by dividing the on-resistance RON of the output driver 34 and the protection resistance RESD of the electrostatic protection circuit 90 during the periods during which it should have been at the power supply voltage VDD, namely, the fourth frame period T4, the sixth frame period T6, and the eighth frame period T8.

[0077] Figure 17 It shows Figure 16 Signal waveform diagram of various signal waveforms in the comparison circuit 150 and the determination circuit 160 in the case of . Figure 17 The signal waveform diagram in the upper section of FIG. 1 overlaps and displays the signal waveforms of the output signal SGO, the first reference voltage VREFH, and the second reference voltage VREFL input to the comparison circuit 150. Figure 13 、 Figure 14 Likewise, in Figure 17 、 Figure 18In FIG, the output signal SGO is represented by a solid line, the first reference voltage VREFH is represented by a dotted line, and the second reference voltage VREFL is represented by a dashed line. As described above, during the fourth frame period T4 and the seventh frame period T7 when the output signal SGO does not normally output the power supply voltage VDD, the determination circuit 160 should determine that the voltage of the output signal SGO is abnormal. However, Figure 17 In the example shown in FIG, the first reference voltage VREFH indicated by the dotted line is set to a voltage level lower than the aforementioned divided voltage VDV2 = (VDD-VGND) × RESD / (RON+RESD), so that the output signal SGO is erroneously determined to be normal during the fourth frame period T4, the sixth frame period T6, and the eighth frame period T8. On the other hand, Figure 18 is with Figure 17 The example of changing the setting of the voltage levels of the first reference voltage VREFH and the second reference voltage VREFL compared to the case of Figure 18 The first reference voltage VREFH in Figure 17 Compared with the case where the voltage is set to a higher value, Figure 18 The second reference voltage VREFL is Figure 17 In this case, the voltage is set to a lower value than that in Figure 17 During the fourth frame period T4, the sixth frame period T6 and the eighth frame period T8, the output signal SGO is mistakenly judged to be normal. Figure 18 In the example, the voltage of output signal SGO becomes lower than the first reference voltage VREFH indicated by the dotted line, and thus is correctly determined to be abnormal. By changing the setting voltages of first reference voltage VREFH and second reference voltage VREFL in this manner, even if the output signal SGO changes from its original signal waveform due to the short circuit, inspection circuit 41 can accurately determine that the output signal SGO is abnormal. Specifically, by setting first reference voltage VREFH to a higher voltage relative to first voltage VH and second reference voltage VREFL to a lower voltage relative to second voltage VL, an abnormality can be reliably detected even if the output signal SGO deviates from its original rectangular signal waveform.

[0078] Figure 19 is Figure 12 Figures 1 and 2 show various signal waveforms when the voltage levels of the first reference voltage VREFH and the second reference voltage VREFL vary over time, i.e., when the panel signal line LPN is short-circuited to the power supply voltage VDD. Specifically, the first reference voltage VREFH varies in voltage according to the frame period T, changing to three levels. Similarly, the second reference voltage VREFL also varies in voltage according to the frame period T, changing to three levels.

[0079] exist Figure 19 In the figure, the second reference voltage VREFL represented by the dotted line changes to a voltage lower than the second reference voltage VREFL in the first frame period T1 when it changes from the first frame period T1 to the second frame period T2. Thereafter, when it changes from the second frame period T2 to the third frame period T3, it changes to a voltage higher than the second reference voltage VREFL in the first frame period T1. Moreover, after the fourth frame period T4, the second reference voltage VREFL also continues to change according to the frame period T. Here, during the fifth frame period T5 where a short circuit occurs between the panel signal line LPN and the power supply voltage VDD, the second reference voltage VREFL is set to a voltage lower than the divided voltage VDV1 = (VDD-VGND) × RON / (RON+RESD) which becomes the voltage of the output signal SGO, so that the abnormal state of the voltage of the output signal SGO can be properly detected. That is, during Figure 17 、 Figure 18 In the embodiment of the present invention, it is explained that when the first reference voltage VREFH and the second reference voltage VREFL are set to constant, if the voltage level of the second reference voltage VREFL is inappropriate, there is a problem that an abnormal state of the output signal SGO caused by a short circuit of the panel signal line LPN cannot be properly detected. However, by Figure 19 This abnormal state can be detected by changing the reference voltage VREF in accordance with the frame period T. In the following description, the first reference voltage VREFH and the second reference voltage VREFL are collectively referred to as the reference voltage VREF as appropriate.

[0080] Figure 20 It is shown in Figure 16 In the case of short circuit between the panel signal line LPN and the ground voltage VGND, the reference voltage VREF is Figure 19Similarly, the signal waveforms for the case where the frame period T changes. As described above, due to this short circuit, the voltage of the output signal SGO in the High state becomes lower than the power supply voltage VDD starting midway through the fourth frame period T4. Here, the first reference voltage VREFH, shown by the dotted line, is set to a voltage lower than the divided voltage VDV2 = (VDD - VGND) × RESD / (RON + RESD), which is the voltage of the output signal SGO, during the fourth frame period T4. This results in the output signal SGO being determined to be in the High state, and thus, the abnormal state of the output signal SGO voltage cannot be detected. Furthermore, during the sixth frame period T6, the first reference voltage VREFH is also set to a voltage lower than that during the fourth frame period T4, and therefore, the abnormal state of the output signal SGO voltage cannot be detected. However, during the eighth frame period T8, the first reference voltage VREFH is set to a voltage higher than the divided voltage VDV2, which is the voltage of the output signal SGO, making it possible to detect the abnormal state of the output signal SGO voltage. For example, in the case where the abnormal state of the output signal SGO is not properly determined when a constant voltage reference voltage VREF is set, consider the case where the resistance values of the on-resistance RON of the aforementioned output driver 34 and the protection resistor RESD of the electrostatic protection circuit 90 change, resulting in changes in the divided voltages VDV1 and VDV2 as the voltage of the aforementioned output signal SGO. Here, the resistance values of the on-resistance RON and the protection resistor RESD change according to the deviation of the manufacturing process, temperature, etc. In addition, the on-resistance RON changes according to the gate voltage. Therefore, it is not easy to set the reference voltage VREF by predicting in advance the divided voltages VDV1 and VDV2 in the output signal SGO when the short circuit occurs. However, as described above, if the reference voltage VREF changes according to the frame period T, the abnormal state of the output signal SGO can be reliably detected even when the divided voltages VDV1 and VDV2 as the voltage of the output signal SGO change. According to Figure 19 、 Figure 20 The method described in the above description can change the reference voltage in synchronization with the frame period T, so that the control of the reference voltage change becomes easy. For example, the control circuit only needs to instruct the reference voltage VREF to change in synchronization with the latch pulse LP, so the control of the reference voltage becomes easy. Figure 19 、 Figure 20In the example described above, the reference voltage VREF is varied to three different voltage levels. However, the number of levels of the reference voltage VREF is not limited to this. Specifically, if the number of levels of the reference voltage VREF is set to M, the voltage level of the reference voltage VREF returns to its original level after a period of T × M. Increasing the number of levels of the voltage level, M, allows detection of voltage anomalies even for small changes in the voltage of the output signal SGO.

[0081] Figure 21 、 Figure 22 is with Figure 19 、 Figure 20 The signal waveform of the reference voltage VREF is shown as an example of a different signal waveform. Specifically, Figure 19 、 Figure 20 In the frame period T, the voltage level of the reference voltage VREF changes, but Figure 21 、 Figure 22 The difference is that the frame division period Tdiv obtained by dividing the frame period T into three parts changes. In this way, when the given period is set as the frame period T, it returns to the original voltage level of the reference voltage VREF after the period of T×M has passed. In contrast, since the reference voltage VREF returns to the original voltage level of the reference voltage VREF after the frame period has passed, it is possible to quickly detect an abnormal state of the voltage of the output signal SGO. In addition, Figure 21 、 Figure 22 The fact that the voltage level of the reference voltage VREF is not limited to three levels is different from Figure 19 、 Figure 20 The same situation.

[0082] Here, one method for setting the reference voltage VREF is to set it from the aforementioned external processing device 120. The following describes a method for setting the reference voltage VREF from the external processing device 120. When setting the reference voltage VREF using this method, the display driver 20 includes, for example, a command setting register 112. The command setting register 112 stores setting information for commands input to the processing device 120. The command setting register 112 can be implemented, for example, by a flip-flop circuit or a memory such as RAM. The information input to the processing device 120 is input to the interface circuit 110, and the interface circuit 110 writes the command setting information to the command setting register 112. Based on this information, the control circuit 100 outputs information such as the voltage set as the reference voltage VREF to the reference voltage generation circuit 140.

[0083] Figure 23 、 Figure 24This command and the value of the reference voltage VREF corresponding to the command are exemplified. Figure 23 The first instruction is an instruction for setting the voltage level of the first reference voltage VREFH. Figure 23 In the case of , by setting any value from 0 to 5 by the first instruction, the first reference voltage VREFH can be set to any voltage from 0.70V, 0.75V, 0.80V, 0.85V, 0.90V, and 0.95V according to the set value. Figure 24 The second instruction is an instruction for setting the voltage level of the second reference voltage VREFL. Figure 24 In this case, a value of 0 to 5 can be set by the second command, and the second reference voltage VREFL can be set to any one of 0.05V, 0.10V, 0.15V, 0.20V, 0.25V, and 0.30V according to the set value.

[0084] Specifically, the display driver 20 may include a command setting register 112 in which commands are set by the external processing device 120, and the control circuit 100 may instruct the reference voltage generation circuit 140 to select which of the multiple voltages to use as the reference voltage VREF based on the command setting in the command setting register 112. This can easily accommodate situations where, for example, the divided voltages VDV1 and VDV2 that form the voltage of the output signal SGO vary due to various factors such as process variations, requiring separate settings for the reference voltage VREF to be compared.

[0085] In addition, Figure 23 、 Figure 24 In the example, the processing device 120 may also set the instruction in the instruction setting register according to a given cycle. Figures 19 to 22 The invention explains that by changing the reference voltage VREF in accordance with a given cycle, a short circuit between the output terminal TO and the segment electrode ES of the electro-optical panel 200 can be reliably detected. However, the setting of the reference voltage VREF can also be changed by an external processing device 120. That is, in the display driver 20 of this embodiment, the control circuit 100 can also instruct the reference voltage generation circuit 140 to select which voltage among a plurality of voltages as the reference voltage VREF according to the instruction setting set by the processing device 120 in the instruction setting register 112 in accordance with a given cycle. In this way, when a short circuit occurs, Figure 11 、 Figure 15 In the case of short circuit described above, the control circuit 100 can instruct the reference voltage generation circuit 140 to select which voltage among a plurality of voltages as the reference voltage VREF for determining whether the voltage of the output signal SGO is in an abnormal state in a given cycle.

[0086] While the above description assumes a static drive scheme, the display driver 20 of this embodiment is not limited to this and can also be applied to a duty-cycle drive scheme. In the duty-cycle drive scheme, time-divided segment drive signals are input to the segment electrodes ESS1 to ESS7 during a frame period. Specifically, voltages synchronized with latch pulses are supplied to each of the segment electrodes ESS1 to ESS7, controlling the display of digits and predetermined symbols.

[0087] 3. Display module

[0088] Figure 25 The display module 300 of this embodiment is a structural example. The display module 300 includes a display driver 20 and an electro-optical panel 200. The display driver 20 is connected to the display module 300. Figure 1 、 Figure 4 The structure of the display driver 20 is the same as that of the display driver 20 described in FIG. Figure 2 、 Figure 3 The display module 300 can be applied to wristwatches, wearable devices, biological information measuring devices, portable information terminals such as smartphones and mobile phones, cordless phones, shavers, electric toothbrushes, handheld terminals, and automobiles.

[0089] According to this embodiment, since the display module 300 can be applied to a variety of electronic devices, and even if a display malfunction occurs on the electro-optical panel 200, the reference voltage can be changed according to a given period, the abnormal state can be reliably detected based on the voltage of the output signal SGO of the driver circuit.

[0090] As described above, the display driver of this embodiment includes: a driver circuit, which drives the electro-optical panel; an output terminal, which outputs an output signal from the driver circuit; an output line, which connects the output of the driver circuit to the output terminal; and a check circuit, which detects an abnormality in the output signal by monitoring the voltage of the output signal output by the driver circuit to the output line. The check circuit determines whether the voltage of the output signal is abnormal by comparing a reference voltage, the voltage of which changes according to a given period, with the voltage of the output signal.

[0091] According to this embodiment, since the reference voltage generating circuit can change the reference voltage at a predetermined cycle, an abnormal state can be appropriately detected even when the voltage change of the output signal of the driver circuit is not constant.

[0092] Furthermore, in the present embodiment, the given period may be a frame period, and the inspection circuit may compare a reference voltage whose voltage changes according to the frame period with the voltage of the output signal.

[0093] In this way, the reference voltage only needs to be changed in synchronization with the frame period, and thus the control of the reference voltage change becomes easy.

[0094] In the present embodiment, the predetermined period may be a frame division period obtained by dividing the frame period, and the inspection circuit may compare a reference voltage whose voltage varies according to the frame division period with the voltage of the output signal.

[0095] In this manner, compared to a case where a predetermined period is set as a frame period, the period of the signal waveform of the reference voltage becomes shorter, and an abnormal state of the voltage of the output signal of the driver circuit can be detected quickly.

[0096] Furthermore, in this embodiment, the display driver may include an electrostatic protection circuit provided between the output line and the output terminal.

[0097] Thus, when a surge voltage such as static electricity is applied to the output terminal, the charge generated by the static electricity is discharged to the ground or the power supply, thereby protecting the circuits and elements provided in the display driver from malfunctions caused by the overvoltage.

[0098] Furthermore, in this embodiment, the electrostatic protection circuit of the display driver may include a protection resistor provided between the output line and the output terminal.

[0099] In this way, even when a large surge voltage is applied to the output terminal, the circuits and elements provided inside the display driver can be appropriately protected from malfunctions caused by the overvoltage.

[0100] In this embodiment, the inspection circuit may include: a reference voltage generating circuit that generates a plurality of voltages and outputs a reference voltage selected from the plurality of voltages at a given cycle; and a comparison circuit that compares the reference voltage with the voltage of the output signal.

[0101] In this way, a reference voltage capable of appropriately determining the voltage of the output signal of the driver circuit can be generated, and an abnormal state of the voltage of the output signal can be reliably detected within a fixed period.

[0102] Furthermore, in the present embodiment, the display driver may include a control circuit that instructs the reference voltage generation circuit to select which voltage among a plurality of voltages as the reference voltage.

[0103] In this way, when the voltage variation of the output signal of the driver circuit is within a fixed range, the voltage level of the reference voltage can be set in advance in the control circuit.

[0104] In this embodiment, the display driver may include a command setting register in which a command is set by an external processing device, and the control circuit may instruct the reference voltage generation circuit to select which of the multiple voltages as the reference voltage based on the command setting in the command setting register.

[0105] In this way, regarding the abnormal state of the voltage of the output signal of the driver circuit, an appropriate reference voltage corresponding to factors such as process variations can be set from outside the electro-optical panel 200 , and the abnormal state can be determined based on this.

[0106] Furthermore, in this embodiment, the control circuit of the display driver may instruct the reference voltage generation circuit which voltage among the plurality of voltages to select as the reference voltage based on a command setting set in a command setting register by the processing device at a predetermined cycle.

[0107] In this manner, it is possible to determine an abnormal state of the voltage of the output signal of the driver circuit based on an appropriate reference voltage at a predetermined cycle.

[0108] In addition, the display module of this embodiment includes a display driver and an electro-optical panel, and the display driver includes: a driver circuit, which drives the electro-optical panel; an output terminal, which outputs an output signal from the driver circuit; an output line, which connects the output of the driver circuit to the output terminal; and an inspection circuit, which detects abnormalities in the output signal by monitoring the voltage of the output signal output by the driver circuit to the output line. The inspection circuit determines whether the voltage of the output signal is abnormal by comparing a reference voltage whose voltage changes according to a given period with the voltage of the output signal.

[0109] According to this embodiment, the display module can be applied to various electronic devices, and even if a display malfunction occurs on the electro-optical panel, the reference voltage can be changed according to a given period, so that an abnormal state can be reliably detected based on the voltage of the output signal of the driver circuit.

[0110] In addition, although the present embodiment is described in detail as described above, it should be easily understood by those skilled in the art that various modifications can be made that do not substantially deviate from the novelties and effects of the present invention. Therefore, all such modifications are included in the scope of the present invention. For example, in the specification or the drawings, a term recorded together with a different term in a broader sense or with the same meaning can be replaced with a different term at any position in the specification or the drawings at least once. In addition, all combinations of the present embodiment and the modifications are also included in the scope of the present invention. In addition, the structure, operation, etc. of the display driver and the display module are not limited to the contents described in the present embodiment, and various modifications can be implemented.

Claims

1. A display driver, characterized in that: The display driver includes: a driver circuit for driving the electro-optical panel; an output terminal that outputs an output signal from the driver circuit; an output line connecting an output of the driver circuit to the output terminal; and a check circuit that detects an abnormality in the output signal by monitoring a voltage of the output signal outputted by the driver circuit to the output line, The inspection circuit compares the first reference voltage and the second reference voltage with the voltage of the output signal according to a given period to determine whether the voltage of the output signal is abnormal. The value of the first reference voltage is higher than the value of the second reference voltage, The inspection circuit comprises: a reference voltage generating circuit that generates a plurality of voltages and outputs the first reference voltage and the second reference voltage selected from the plurality of voltages in accordance with the given cycle; and A comparison circuit compares whether the voltage of the output signal is between the first reference voltage and the second reference voltage, and determines that the voltage of the output signal is abnormal when the voltage of the output signal is between the first reference voltage and the second reference voltage, and determines that the voltage of the output signal is normal when the voltage of the output signal deviates from the range between the first reference voltage and the second reference voltage. The comparison circuit supplies abnormality information including the comparison result to a control circuit that controls the display driver.

2. The display driver according to claim 1, wherein: The given period is a frame period, The inspection circuit compares the first reference voltage and the second reference voltage, whose voltages vary according to the frame period, with the voltage of the output signal.

3. The display driver according to claim 1, wherein: The given period is a frame division period obtained by dividing the frame period. The inspection circuit compares the first reference voltage and the second reference voltage, whose voltages vary according to the frame division period, with the voltage of the output signal.

4. The display driver according to any one of claims 1 to 3, wherein: The display driver includes an electrostatic protection circuit provided between the output line and the output terminal.

5. The display driver according to claim 4, wherein: The electrostatic protection circuit includes a protection resistor provided between the output line and the output terminal.

6. The display driver according to claim 1, wherein: The control circuit instructs the reference voltage generation circuit to select which voltage among the plurality of voltages as one of the first reference voltage and the second reference voltage.

7. The display driver according to claim 6, wherein: The display driver includes an instruction setting register for setting instructions by an external processing device. The control circuit instructs the reference voltage generation circuit to select which voltage among the plurality of voltages as one of the first reference voltage and the second reference voltage based on the command setting of the command setting register.

8. The display driver according to claim 7, wherein: The control circuit instructs the reference voltage generation circuit to select which of the plurality of voltages as one of the first reference voltage and the second reference voltage based on the command setting set in the command setting register by the processing device in the predetermined cycle.

9. A display module, characterized in that: The display module includes: The display driver according to any one of claims 1 to 8; and The electro-optical panel.

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