Pixel driving circuit, display device and driving method of pixel driving circuit

Abstract

An embodiment of the present invention provides a pixel driving circuit that solves the problem of low retention capability of an ultrasonic detection array. The pixel driving circuit includes: a pixel driving module, including a second transistor and a third transistor, the drain of the second transistor being connected to the source of the third transistor, the gate of the second transistor receiving a third data signal voltage, the gate of the third transistor receiving a second data signal voltage, and the drain of the third transistor receiving a first data signal voltage; and a current diversion module, configured to provide a flow path for leakage current of the third transistor, the current diversion module being connected to the drain of the second transistor and the source of the third transistor, and receiving a sixth data signal voltage signal to control the closing or conduction of the current diversion module.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel driving circuit, a display device, and a driving method of the pixel driving circuit. Background Art

[0002] Medical ultrasound imaging typically uses linear array probes and single-frequency scanning, which often limits detection depth and resolution. To address this issue, large-area two-dimensional (2D) array detection technology is often used. This technology significantly increases the amount of detection information through 2D imaging, thereby improving detection depth and resolution. However, existing large-area 2D array technology suffers from low ultrasound detection array retention, resulting in image line unevenness and line signal distortion. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a pixel driving circuit, a display device, and a driving method of the pixel driving circuit, which solve the problem of low retention capability of an ultrasonic detection array.

[0004] To make the objectives, technical means, and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings. Obviously, the embodiments described are only a portion of the embodiments of this application, rather than all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0005] In a first aspect, an embodiment of the present invention provides a pixel driving circuit comprising: a pixel driving module, comprising a second transistor and a third transistor, wherein the drain of the second transistor is connected to the source of the third transistor, the gate of the second transistor receives a third data signal voltage, the gate of the third transistor receives a second data signal voltage, and the drain of the third transistor receives a first data signal voltage;

[0006] The diversion and drainage module is configured to provide a flow path for the leakage current of the third transistor. The diversion and drainage module is connected to the drain of the second transistor and the source of the third transistor. The diversion and drainage module receives a sixth data signal voltage signal to control the closing or conduction of the diversion and drainage module.

[0007] In one embodiment, the diversion and drainage module includes a fifth transistor, the source of which receives a sixth data signal voltage; the source of the fifth transistor is connected to the gate of the fifth transistor; and the drain of the fifth transistor is connected to the drain of the second transistor and the source of the third transistor.

[0008] In one embodiment, the resistance between the source and drain of the fifth transistor in the off state is equal to or approximately equal to the resistance between the source and drain of the third transistor in the off state, and the resistance between the source and drain of the second transistor in the off state is greater than the resistance between the source and drain of the fifth transistor in the off state.

[0009] In one embodiment, the pixel driving module further includes a first transistor and a fourth transistor, the gate of the first transistor is connected to the source of the second transistor, the source of the first transistor is connected to the drain of the fourth transistor, the drain of the first transistor receives a fourth data signal voltage, and the gate of the fourth transistor receives a fifth data signal voltage.

[0010] In one embodiment, a storage module is further included, one end of which is connected to the source of the second transistor and the gate of the first transistor.

[0011] In one embodiment, the other end of the storage module is grounded; or the other end of the storage module is connected to the drain of the first transistor; or the other end of the storage module is connected to the gate of the fourth transistor.

[0012] In one embodiment, the storage module includes a capacitor.

[0013] In one embodiment, the storage module includes a sixth transistor, the gate of the sixth transistor is connected to the source of the second transistor and the gate of the first transistor, the source and drain of the sixth transistor are connected to the gate of the fourth transistor, or the source and drain of the sixth transistor are connected to the drain of the first transistor; or the source and drain of the sixth transistor are connected to the gate of the first transistor, the gate of the sixth transistor is connected to the gate of the fourth transistor, or the gate of the sixth transistor is connected to the drain of the first transistor.

[0014] In a second aspect, an embodiment of the present invention provides a display device including: the pixel driving circuit described above.

[0015] In one embodiment, the invention further comprises a controller configured to perform the following steps:

[0016] transmitting a first scan control signal having a first voltage amplitude to the drain of the third transistor, transmitting a second scan control signal having a first voltage amplitude to the gate of the third transistor, so as to turn on the third transistor; transmitting a third scan control signal having a first voltage amplitude to the gate of the second transistor, so as to turn on the second transistor; transmitting a fourth scan control signal having a second voltage amplitude to the drain of the first transistor, transmitting a fifth scan control signal having a second voltage amplitude to the gate of the fourth transistor, so as to turn on the first transistor and turn off the fourth transistor; transmitting a sixth scan control signal having a second voltage amplitude to the gate, source, and gate of the fifth transistor, so as to turn off the fifth transistor;

[0017] transmitting a second scan control signal having a second voltage amplitude to the gate of the third transistor to turn off the third transistor; and then transmitting a third scan control signal having a second voltage amplitude to the gate of the second transistor to turn off the second transistor;

[0018] A fourth scan control signal having a first voltage amplitude is transmitted to the drain of the first transistor to turn on the first transistor; and a fifth scan control signal having the first voltage amplitude is transmitted to the gate of the fourth transistor to turn on the fourth transistor.

[0019] In a third aspect, an embodiment of the present invention provides an imaging device, comprising the display device described above.

[0020] In a fourth aspect, an embodiment of the present invention provides a driving method of a pixel driving circuit, including:

[0021] In the first stage, a first scan control signal with a first voltage amplitude is applied to the drain of the third transistor, and a second scan control signal with a first voltage amplitude is applied to the gate of the third transistor to turn on the third transistor; a third scan control signal with a first voltage amplitude is applied to the gate of the second transistor to turn on the second transistor; a fourth scan control signal with a second voltage amplitude is applied to the drain of the first transistor, and a fifth scan control signal with a second voltage amplitude is applied to the gate of the fourth transistor to turn on the first transistor and the fourth transistor; a sixth scan control signal with a second voltage amplitude is applied to the gate, source, and gate of the fifth transistor to turn off the fifth transistor;

[0022] In the second stage, a second scanning control signal having a second voltage amplitude is applied to the gate of the third transistor to turn off the third transistor; and then a third scanning control signal having a second voltage amplitude is applied to the gate of the second transistor to turn off the second transistor.

[0023] In the fourth stage, a second scanning control signal with a second voltage amplitude is continuously applied to the gate of the third transistor to turn off the third transistor; a fourth scanning control signal with a second voltage amplitude is continuously applied to the drain of the first transistor, and a fifth scanning control signal with a second voltage amplitude is applied to the gate of the fourth transistor to turn on the first transistor and turn off the fourth transistor; a sixth scanning control signal with a second voltage amplitude is continuously applied to the gate and source of the fifth transistor to turn off the fifth transistor; and a third scanning control signal with a second voltage amplitude is continuously applied to the gate of the second transistor to turn off the second transistor.

[0024] In the fourth stage, a fourth scanning control signal with a first voltage amplitude is applied to the drain of the first transistor to turn off the first transistor; then a fifth scanning control signal with a first voltage amplitude is applied to the gate of the fourth transistor to turn on the fourth transistor and turn on the first transistor.

[0025] An embodiment of the present invention provides a pixel driving circuit, a display device, and a driving method for a pixel driving circuit. By adding a current diversion and drainage module between the drain of the second transistor and the source of the third transistor, a more convenient flow path is provided for the leakage current of the third transistor, thereby reducing the impact of the leakage current of the third transistor on the first transistor, greatly improving the ability to maintain the gate potential of the first transistor, and thus maintaining the stability of the output current, improving the uniformity and accuracy of the collected signal, and reducing the impact of the limited detection range, further improving the dynamic range of ultrasonic detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Shown is a schematic diagram of an ultrasonic two-dimensional detection array pixel circuit in the prior art.

[0027] Figure 2a Shown is a prior art I out Schematic diagram of how changes affect a single frame image.

[0028] Figure 2b The figure shows a ΔI in the prior art. out Schematic diagram of the impact of changes on acoustic signals.

[0029] Figure 3 FIG2 is a schematic diagram of a pixel driving circuit provided in an embodiment of the present application.

[0030] Figure 4 The present invention provides an embodiment of an I out Comparison of retention capability simulation results.

[0031] Figure 5The figure shows a ΔI provided by an embodiment of the present application. out Comparison of retention capability simulation results.

[0032] Figure 6 Shown is a circuit connection diagram of a storage module provided in one embodiment of the present application.

[0033] Figure 7 Shown is a circuit connection diagram of a storage module provided in another embodiment of the present application.

[0034] Figure 8 Shown is a circuit connection diagram of a storage module provided in another embodiment of the present application.

[0035] Figure 9 Shown is a circuit connection diagram of a storage module provided in another embodiment of the present application.

[0036] Figure 10 Shown is a circuit connection diagram of a storage module provided in another embodiment of the present application.

[0037] Figure 11 Shown is a circuit connection diagram of a storage module provided in another embodiment of the present application.

[0038] Figure 12 Shown is a circuit connection diagram of a storage module provided in another embodiment of the present application.

[0039] Figure 13 Shown is a timing control diagram of a pixel driving circuit provided by another embodiment of the present application. DETAILED DESCRIPTION

[0040] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0041] In existing technologies, to achieve high-precision imaging, the array must have a size of 1000×1000 to 2000×2000 elements, with the target resolution capable of resolving objects with an accuracy of 0.5mm. The acquisition process involves simultaneous global acquisition, while the reading process is row-by-row. Due to the large number of rows and columns in the array, the difference in reading time between the first and last rows of a frame can be 1 second or more, placing very high demands on the signal retention capability during the post-acquisition signal retention process. During such a long period of holding, the original ultrasonic detection array pixel structure can produce a signal difference of up to 157% between the first and last rows (holding time 2s, 7uA for the first row, 18uA for the last row), which results in a row-by-row transition in the signal of a single-frame image, severe distortion, and reduced signal accuracy. At the same time, in order to ensure that the output of the entire image is within the measurement range (e.g., 1 to 30uA), the output change generated by the acoustic signal must not exceed 12uA, otherwise the last row will exceed the measurement range, greatly limiting the dynamic range of ultrasonic detection. Moreover, after subtracting the acoustic signal image from the silent signal image, the amount of pure acoustic signal obtained will also increase over time (holding time 2s, receiving the same signal, ΔIout = 1.49uA for the first row, ΔIout = 2.61uA for the last row), resulting in a row-by-row transition in the acoustic signal, with a distortion of 75%, which seriously interferes with the restoration of acoustic information. Therefore, there is an urgent need to improve the holding capability of the ultrasonic detection array.

[0042] The original 4T or 4T1C pixel structure is as follows Figure 1 As shown, during the holding process, M3 and M2 are both closed. Due to the jump voltage of the potential switching, the potential V4>VB≈VA, the VDS potential difference of M3 causes Ioff leakage current in M3. The Ioff leakage current can only be stored in the PVDF capacitor and through C1 of M2 (or M1 parasitic capacitance CGS, CGD), and has no other release path. It has a greater impact on the VA potential. The simulation results show that after 2s, I out Will increase from 7uA to 18uA (increase 11uA), receiving the same signal, ΔI out Increased from 1.49uA to 2.61uA (increased by 1.12uA), where I out Large changes indicate that a frame of image has obvious non-uniformity problems, such as Figure 2a As shown, this problem will make I out Due to the range limitation, in order to ensure that the entire image does not exceed the range, the ultrasonic detection dynamic range can only be reduced; ΔI out Large changes mean that the pure signal difference obtained by the sound signal and the silence signal has a gradient problem, such as Figure 2b shown.

[0043] To address the above-mentioned issues, the present invention provides a pixel driving circuit, a display device, and a driving method for the pixel driving circuit. By adding a current diversion module between the drain of the second transistor and the source of the third transistor, a more efficient flow path is provided for the leakage current of the third transistor, thereby reducing the impact of the leakage current of the third transistor on the first transistor, greatly improving the ability to maintain the gate potential of the first transistor, thereby maintaining the stability of the output current, improving the uniformity and accuracy of the collected signal, and reducing the impact of the limited detection range, further improving the dynamic range of ultrasonic detection. Specific implementation methods are described in the following embodiments.

[0044] An embodiment of the present invention provides a pixel driving circuit, such as Figure 3 As shown, the pixel driving circuit includes a pixel driving module and a current diversion module. The pixel driving module includes a second transistor M2 and a third transistor M3, wherein the drain of the second transistor M2 is connected to the source of the third transistor M3, the gate of the second transistor M3 receives the third data signal voltage V3, the gate of the third transistor M3 receives the second data signal voltage V2, and the drain of the third transistor M3 receives the first data signal voltage V1; the current diversion module is configured to provide a flow path for the leakage current of the third transistor M3, the current diversion module is connected to the drain of the second transistor M2 and the source of the third transistor M3, and receives a sixth data signal voltage signal to control the closing or conduction of the current diversion module.

[0045] The pixel driving circuit provided by the present invention provides a flow path for the leakage current of the third transistor by adding a diversion and diversion module at the connection point of the drain of the second transistor and the source of the third transistor (the position of node 2). When the diversion and diversion module does not exist, the leakage current of the third transistor can only flow through the second transistor and be stored in the capacitor. After the diversion and diversion module is added, the presence of the diversion and diversion module provides the third transistor with a path for the leakage current to pass more easily, thereby reducing the current flowing through the second transistor, realizing the diversion and diversion of the leakage current of the third transistor by the diversion and diversion module during the maintenance process, reducing the influence of the leakage current of the third transistor on node 1, greatly improving the VA holding ability during the maintenance process, that is, the holding ability of the gate potential of the first transistor, and thus maintaining the output current I of the read end. out It can improve the stability of the ultrasonic detection, enhance the uniformity and accuracy of the collected signal, reduce the impact of limited detection range, and further enhance the dynamic range of ultrasonic detection.

[0046] In one embodiment of the present invention, the current diversion module includes a fifth transistor M5, wherein the source of the fifth transistor M5 receives the sixth data signal voltage V6; the source of the fifth transistor M5 is connected to the gate of the fifth transistor M5; and the drain of the fifth transistor M5 is connected to the drain of the second transistor M2 and the source of the third transistor M3. The resistance of the fifth transistor M5 is equal to the resistance of the third transistor M3, and the resistance of the second transistor M2 is greater than the resistance of the fifth transistor M5.

[0047] In one embodiment of the present invention, the resistance between the source and drain of the fifth transistor in the off state is equal to or approximately equal to the resistance between the source and drain of the third transistor in the off state, and the resistance between the source and drain of the second transistor in the off state is greater than the resistance between the source and drain of the fifth transistor in the off state. Approximately equal means that there is a certain allowable error range between the resistance between the source and drain of the fifth transistor in the off state and the resistance between the source and drain of the third transistor in the off state. The allowable error range can be set as required and is not limited in this embodiment.

[0048] In this embodiment, after adding a fifth transistor at the node 2, the pixel circuit diagram is as shown in FIG. Figure 3 As shown, during the holding process, the potential gradient V4>VB>V6, when the fifth transistor does not exist, the leakage current path of the third transistor can only flow through the second transistor, and the presence of the fifth transistor provides the third transistor with a leakage current path that is easier to pass through, and the resistance M2>>M3≈M5. In this embodiment, the current flowing through the second transistor can be reduced by the resistance difference between the third transistor, the fifth transistor and the second transistor, so that the current is more easily released through the fifth transistor, and the leakage current of the third transistor is guided by the fifth transistor during the holding process, thereby reducing the impact of the leakage current of the third transistor on the node 1. For example, the data comparison Figure 4 and Figure 5 As shown, the simulation verification is maintained for 2s. out Will increase from 10uA to 12uA (only 2uA increase), receiving the same signal, ΔI out It changes from 1.79uA to 1.73uA (an increase of only 0.06uA). It can be seen from the figure that the presence of the fifth transistor improves the ability to maintain VA during the holding process, that is, the ability to maintain the gate potential of M1, thereby stabilizing the output current, improving the uniformity and accuracy of the collected signal, and reducing the impact of limited detection range. It greatly improves the problems of uneven line and line signal distortion of the screen, reduces the range limit, and further improves the dynamic range of ultrasonic detection.

[0049] In one embodiment of the present invention, Figure 3As shown, the pixel driving module further includes a first transistor M1 and a fourth transistor M4, the gate of the first transistor M1 is connected to the source of the second transistor M2, the source of the first transistor M1 is connected to the drain of the fourth transistor M4, the drain of the first transistor M1 receives a fourth data signal voltage V4, and the gate of the fourth transistor M4 receives a fifth data signal voltage V5.

[0050] In one embodiment of the present invention, the first transistor is configured to convert voltage into current; the second transistor is configured to perform data transmission and data retention; the third transistor is configured to reset and initialize; and the fourth transistor is configured to perform data reading.

[0051] In one embodiment of the present invention, the material of the transistor here can be LTPS (Low Temperature Poly-Silicon, low temperature polycrystalline silicon, polycrystalline silicon is also referred to as p-Si), optionally, the transistor can be NMOS (N-Metal-Oxide-Semiconductor, N-type metal-oxide-semiconductor) or PMOS (positive-channel-Metal-Oxide-Semiconductor, P-type metal-oxide-semiconductor); the material of the transistor can also be a-Si (amorphous silicon) or oxide; the material of the ultrasound receiving array can be PVDF (poly (vinylidene fluoride) resin), and the type of the ultrasound receiving array can be CMUT (Capacitive Micromachined Ultrasonic Transducers, electronic micro-ultrasound probe technology).

[0052] In one embodiment of the present invention, Figure 6 As shown, the pixel driving circuit includes a storage module, one end of which is connected to the source of the second transistor and the gate of the first transistor. The other end of the storage module is grounded; or, the other end of the storage module is connected to the drain of the first transistor; or, the other end of the storage module is connected to the gate of the fourth transistor.

[0053] In one embodiment of the present invention, the storage module includes a capacitor. One end of the capacitor is connected to the source of the second transistor and the gate of the first transistor, and the other end of the capacitor is grounded; or, the other end of the capacitor is connected to the drain of the first transistor; or, the other end of the capacitor is connected to the gate of the fourth transistor. Further, a capacitor C1 can be added to the position of the pixel structure node 1, with one end of C1 connected to node 1 and the other end connected to the ground signal (such as Figure 6 As shown), you can also connect to the V4 terminal (as shown Figure 7 as shown) or V5 end (as shown) Figure 8 shown).

[0054] In one embodiment of the present invention, the storage module includes a sixth transistor, the gate of the sixth transistor is connected to the source of the second transistor and the gate of the first transistor, and the source and drain of the sixth transistor are connected to the gate of the fourth transistor; or, the source and drain of the sixth transistor are connected to the drain of the first transistor. The sixth transistor is used as the storage module, the gate of the sixth transistor is connected to node 1, and the source and drain are connected to V4 or V5. Figure 9 and Figure 10 or the gate side of the fifth transistor is connected to V5 or V4, the source and drain side is connected to node 1, as shown Figure 11 and Figure 12 shown.

[0055] In one embodiment of the present invention, the CGS (gate-source capacitance) parasitic capacitance and the CGD (gate-drain capacitance) parasitic capacitance of the first transistor can be used as the storage capacitor. The gate-source capacitance is the parasitic capacitance between the gate and drain of the first transistor; the gate-drain capacitance is the parasitic capacitance between the gate and source of the first transistor.

[0056] In an embodiment, a display device is provided, which includes a pixel driving circuit and a controller. The controller is configured to perform the following steps:

[0057] transmitting a first scan control signal having a first voltage amplitude to the drain of the third transistor, transmitting a second scan control signal having a first voltage amplitude to the gate of the third transistor, so as to turn on the third transistor; transmitting a third scan control signal having a first voltage amplitude to the gate of the second transistor, so as to turn on the second transistor; transmitting a fourth scan control signal having a second voltage amplitude to the drain of the first transistor, transmitting a fifth scan control signal having a second voltage amplitude to the gate of the fourth transistor, so as to turn on the first transistor and turn off the fourth transistor; transmitting a sixth scan control signal having a second voltage amplitude to the gate and source of the fifth transistor, so as to turn off the fifth transistor;

[0058] transmitting a second scan control signal having a second voltage amplitude to the gate of the third transistor to turn off the third transistor; and then transmitting a third scan control signal having a second voltage amplitude to the gate of the second transistor to turn off the second transistor;

[0059] A fourth scan control signal having a first voltage amplitude is transmitted to the drain of the first transistor to turn on the first transistor; and a fifth scan control signal having the first voltage amplitude is transmitted to the gate of the fourth transistor to turn on the fourth transistor.

[0060] This embodiment provides an imaging device, which includes the display device described above. The display device can be used in the field of medical ultrasound imaging.

[0061] This embodiment provides a driving method for a pixel driving circuit, including:

[0062] In the first stage, a first scan control signal with a first voltage amplitude is applied to the drain of the third transistor, and a second scan control signal with a first voltage amplitude is applied to the gate of the third transistor to turn on the third transistor; a third scan control signal with a first voltage amplitude is applied to the gate of the second transistor to turn on the second transistor; a fourth scan control signal with a second voltage amplitude is applied to the drain of the first transistor, and a fifth scan control signal with a second voltage amplitude is applied to the gate of the fourth transistor to turn on the first transistor and the fourth transistor; a sixth scan control signal with a second voltage amplitude is applied to the gate, source, and gate of the fifth transistor to turn off the fifth transistor;

[0063] In the second stage, a second scanning control signal having a second voltage amplitude is applied to the gate of the third transistor to turn off the third transistor; and then a third scanning control signal having a second voltage amplitude is applied to the gate of the second transistor to turn off the second transistor.

[0064] In the third stage, a second scanning control signal with a second voltage amplitude is continuously applied to the gate of the third transistor to turn off the third transistor; a fourth scanning control signal with a second voltage amplitude is continuously applied to the drain of the first transistor, and a fifth scanning control signal with a second voltage amplitude is applied to the gate of the fourth transistor to turn on the first transistor and turn off the fourth transistor; a sixth scanning control signal with a second voltage amplitude is continuously applied to the gate and source of the fifth transistor to turn off the fifth transistor; and a third scanning control signal with a second voltage amplitude is continuously applied to the gate of the second transistor to turn off the second transistor.

[0065] In the fourth stage, a fourth scanning control signal with a first voltage amplitude is applied to the drain of the first transistor to turn off the first transistor; then a fifth scanning control signal with a first voltage amplitude is applied to the gate of the fourth transistor to turn on the fourth transistor and turn on the first transistor.

[0066] Optionally, the first voltage amplitude is a high level, and the second voltage amplitude is a low level.

[0067] In one embodiment of the present invention, in order to better understand the above pixel driving circuit and the driving method of the driving circuit, the working process of the above pixel circuit is described in detail below in combination with more specific embodiments.

[0068] Take NMOS transistor as an example to illustrate, combined with Figure 13 As shown, Figure 6 The working process of the pixel driving circuit is as follows:

[0069] (1) The first stage is the emission stage. The ultrasonic sound source emits ultrasonic waves. A constant voltage high level is applied to the V1 terminal and a high level is applied to the V2 terminal to turn on the third transistor M3. A high level is applied to the V3 terminal to turn on the second transistor M2. This resets the VA terminal and the VB terminal and writes the potential of the V1 terminal. A low level is applied to the V4 terminal and a low level is applied to the V5 terminal to turn off the fourth transistor M4. A constant voltage low level is applied to the V6 terminal to turn off the fifth transistor M5. At this time, the first transistor is in the on state.

[0070] (2) The second stage is the acquisition stage. When the array receives the ultrasonic echo signal, a low potential is applied to the V2 terminal, and then a low potential is applied to the V3 terminal, turning off the third transistor M3 first and then the second transistor M2. The closing nodes of M3 and M2 can be selected at the echo peak and trough moments or at the echo trough and peak moments, so that the echo peak value can be collected; a low level is applied to the V4, V5, and V6 terminals, turning off the fourth transistor M4 and the fifth transistor M5.

[0071] (3) The third stage is the holding stage. A low potential is applied to the V2, V3, V4, V5, and V6 terminals to turn off the second transistor M2, the third transistor M3, the fourth transistor M4, and the fifth transistor M5. During the acquisition process, when V2 and V3 switch to low levels, the cgs, cgd, and other pixel parasitic capacitances of M3 and M2 cause voltage jumps at the VA and VB nodes. During the holding period, VA≈VB<V1, and the potential VB>V6. Therefore, the leakage current of M3 can be released through M5. By adjusting the V6 potential and the W / L of M5, the leakage current of M5 can be kept as low as possible, and at the same time, the resistance M2>>M3=M5 can be ensured. This can greatly reduce the path of current passing through M2 and improve the stability of the VA potential. At this time, the first transistor is in the open state.

[0072] (4) The fourth stage is the read stage. A high level is first applied to the V4 terminal, causing the first transistor M1 to operate in the saturation region. A high level is then applied to the V5 terminal, causing the fourth transistor M4 to turn on row by row. The source of M4 outputs the read current Iout. Optionally, a constant high voltage can also be applied to the V4 terminal during the fourth stage.

[0073] Those skilled in the art will appreciate that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention. Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0074] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. On the other hand, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0075] The basic principles of the present application have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, and effects mentioned in this application are merely illustrative and not restrictive, and it should not be assumed that these advantages, strengths, and effects are required of each embodiment of this application. In addition, the specific details disclosed above are merely illustrative and facilitating understanding, and are not restrictive. The above details do not limit this application to necessarily being implemented using the above specific details.

[0076] The block diagrams of devices, apparatuses, equipment, and systems referred to in this application are intended only as illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems may be connected, arranged, or configured in any manner.

[0077] It should also be noted that in the apparatus, device, and method of the present application, each component or each step can be decomposed and / or recombined, and such decomposition and / or recombination should be regarded as equivalent solutions of the present application.

[0078] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present application. Therefore, the present application is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0079] In the description of the application, the meaning of "multiple" is at least two, for example two, three, etc., unless otherwise clearly and specifically limited. In the embodiments of the present application, all directional indications (such as up, down, left, right, front, back, top, bottom ...) are only used to explain the relative position relationship, motion situation, etc. between each component under a certain specific posture (as shown in the drawings). If this specific posture changes, this directional indication also changes accordingly. In addition, the terms "comprise" and "have" and any deformation thereof are intended to cover non-exclusive inclusion. For example, the process, method, system, product or equipment comprising a series of steps or units is not limited to the steps or units listed, but optionally also includes the steps or units not listed, or optionally also includes other steps or units inherent to these processes, methods, products or equipment.

[0080] In addition, references to "embodiments" herein mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of such phrases in various places in the specification does not necessarily refer to the same embodiment, nor does it necessarily refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0081] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art who can easily think of changes or replacements within the technical scope disclosed by the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims. The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A pixel driving circuit, characterized in that: include: a pixel driving module, comprising a second transistor and a third transistor, wherein the drain of the second transistor is connected to the source of the third transistor, the gate of the second transistor receives a third data signal voltage, the gate of the third transistor receives a second data signal voltage, and the drain of the third transistor receives the first data signal voltage; a current diversion and grooming module configured to provide a flow path for the leakage current of the third transistor, the current diversion and grooming module being connected to the drain of the second transistor and the source of the third transistor, and receiving a sixth data signal voltage signal to control the closing or conducting of the current diversion and grooming module; The current diversion module includes a fifth transistor, a source of the fifth transistor receiving a sixth data signal voltage; the source of the fifth transistor is connected to the gate of the fifth transistor; and the drain of the fifth transistor is connected to the drain of the second transistor and the source of the third transistor. The resistance between the source and drain of the fifth transistor in the off state is equal to or approximately equal to the resistance between the source and drain of the third transistor in the off state, and the resistance between the source and drain of the second transistor in the off state is greater than the resistance between the source and drain of the fifth transistor in the off state.

2. The pixel driving circuit according to claim 1, wherein: The pixel driving module further includes a first transistor and a fourth transistor, the gate of the first transistor is connected to the source of the second transistor, the source of the first transistor is connected to the drain of the fourth transistor, the drain of the first transistor receives a fourth data signal voltage, and the gate of the fourth transistor receives a fifth data signal voltage.

3. The pixel driving circuit according to claim 2, wherein: It also includes a storage module, one end of which is connected to the source of the second transistor and the gate of the first transistor.

4. The pixel driving circuit according to claim 3, wherein: The other end of the storage module is grounded; or, the other end of the storage module is connected to the drain of the first transistor; or, the other end of the storage module is connected to the gate of the fourth transistor.

5. The pixel driving circuit according to claim 3, wherein: The storage module includes a capacitor.

6. A display device, characterized in that: include: The pixel driving circuit according to any one of claims 1 to 5.

7. The display device according to claim 6, wherein: Also includes: Controller, configured as: transmitting a first scan control signal having a first voltage amplitude to the drain of the third transistor, transmitting a second scan control signal having a first voltage amplitude to the gate of the third transistor, so as to turn on the third transistor; transmitting a third scan control signal having a first voltage amplitude to the gate of the second transistor, so as to turn on the second transistor; transmitting a fourth scan control signal having a second voltage amplitude to the drain of the first transistor, transmitting a fifth scan control signal having a second voltage amplitude to the gate of the fourth transistor, so as to turn on the first transistor and turn off the fourth transistor; transmitting a sixth scan control signal having a second voltage amplitude to the gate and source of the fifth transistor, so as to turn off the fifth transistor; transmitting a second scan control signal having a second voltage amplitude to the gate of the third transistor to turn off the third transistor; and then transmitting a third scan control signal having a second voltage amplitude to the gate of the second transistor to turn off the second transistor; A fourth scan control signal having a first voltage amplitude is transmitted to the drain of the first transistor to turn on the first transistor; and a fifth scan control signal having a first voltage amplitude is transmitted to the gate of the fourth transistor to turn on the fourth transistor.

8. An imaging device, characterized in that: The display device comprises the display device according to claim 6 or 7.

9. A driving method of the pixel driving circuit according to any one of claims 1 to 5, comprising: In the first stage, a first scanning control signal having a first voltage amplitude is applied to the drain of the third transistor, and a second scanning control signal having a first voltage amplitude is applied to the gate of the third transistor to turn on the third transistor; Applying a third scan control signal having a first voltage amplitude to the gate of the second transistor to turn on the second transistor; Applying a fourth scan control signal having a second voltage amplitude to the drain of the first transistor, and applying a fifth scan control signal having a second voltage amplitude to the gate of the fourth transistor, so as to turn on the first transistor and turn off the fourth transistor; Applying a sixth scan control signal having a second voltage amplitude to the gate, the source, and the gate of the fifth transistor to turn off the fifth transistor; In the second stage, a second scanning control signal having a second voltage amplitude is applied to the gate of the third transistor to turn off the third transistor; and then a third scanning control signal having a second voltage amplitude is applied to the gate of the second transistor to turn off the second transistor. In the third stage, a second scanning control signal with a second voltage amplitude is continuously applied to the gate of the third transistor to turn off the third transistor; a fourth scanning control signal with a second voltage amplitude is continuously applied to the drain of the first transistor, and a fifth scanning control signal with a second voltage amplitude is applied to the gate of the fourth transistor to turn on the first transistor and turn off the fourth transistor; continuously applying a sixth scanning control signal having a second voltage amplitude to the gate, source, and gate of the fifth transistor to turn off the fifth transistor; continuously applying a third scanning control signal having a second voltage amplitude to the gate of the second transistor to turn off the second transistor; In the fourth stage, a fourth scanning control signal with a first voltage amplitude is applied to the drain of the first transistor to turn off the first transistor; then a fifth scanning control signal with a first voltage amplitude is applied to the gate of the fourth transistor to turn on the fourth transistor and turn on the first transistor.

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