Storage cell for simulating content addressable memory and apparatus thereof

Abstract

The present disclosure provides a storage cell for an analog content addressable memory and an analog content addressable memory device. The storage cell for the analog content addressable memory includes an N-type transistor, a P-type transistor, and a current control circuit. A gate of the N-type transistor is configured to receive a first input signal. A gate of the P-type transistor is configured to receive a second input signal. The current control circuit is coupled to at least one of the N-type transistor and the P-type transistor and configured to generate at least one conduction current. When an input voltage of the first input signal and an input voltage of the second input signal are within a matching range, the N-type transistor and the P-type transistor are both turned on, and the corresponding conduction current is substantially a fixed current value. The matching range is related to a threshold voltage of the N-type transistor, a threshold voltage of the P-type transistor, and the fixed current value.

Description

TECHNICAL FIELD

[0001] The present application relates to a storage cell for an analog content-addressable memory and an analog content-addressable memory device, and in particular, to a storage cell for an analog content-addressable memory and an analog content-addressable memory device. BACKGROUND

[0002] With the development of memory technology, a content-addressable memory (CAM) is proposed. CAM is a special memory applied to in-memory search, and can compare input search words with all columns of storage words in the array using a highly parallel manner. CAM provides very powerful functions in many applications of pattern matching and search.

[0003] Compared with a conventional ternary CAM, analog CAM significantly increases data density and reduces energy loss of in-memory processing circuit operation and area of the processing circuit. Analog CAM needs to have good stability of the storage cell and higher array density. With the development of big data, when searching and comparing data in a huge database, a high-density analog CAM is needed. How to avoid misjudgment of data comparison when judging whether the search range matches the storage range is one of the directions that the industry strives for.

[0004] DISCLOSURE

[0005] The present application relates to a storage cell for an analog content-addressable memory and an analog content-addressable memory device, which uses a current control circuit to fix the current level corresponding to different input signals in the matching range, and reduces the misjudgment during data comparison.

[0006] According to a first aspect of the present application, a storage cell for an analog content-addressable memory (analog CAM) is provided. The storage cell includes an N-type transistor, a P-type transistor, and a current control circuit. The N-type transistor has a first gate. The first gate of the N-type transistor is configured to receive a first input signal. The P-type transistor has a second gate. The second gate of the P-type transistor is configured to receive a second input signal. The current control circuit is coupled to at least one of the N-type transistor and the P-type transistor and is configured to generate a conduction current. When an input voltage of the first input signal and an input voltage of the second input signal are within a match range, the N-type transistor and the P-type transistor are both turned on, and the corresponding conduction current is substantially a fixed current value. The match range is related to a threshold voltage of the N-type transistor, a threshold voltage of the P-type transistor, and the fixed current value.

[0007] According to another aspect of the present application, an analog content-addressable memory device is provided. The analog content-addressable memory device includes a word line driving circuit, a plurality of storage cells, a plurality of match signal lines, a plurality of source lines, a source line driving circuit, and a sense amplifier circuit. The word line driving circuit is configured to provide a plurality of first input signals and a plurality of second input signals. Each storage cell includes an N-type transistor, a P-type transistor, and a current control circuit. The N-type transistor has a first gate. The first gate of the N-type transistor is configured to receive a corresponding first input signal. The P-type transistor has a second gate. The second gate of the P-type transistor is configured to receive a corresponding second input signal. The current control circuit is coupled to at least one of the N-type transistor and the P-type transistor and is configured to generate a conduction current. Each match signal line is coupled to a corresponding storage cell. Each source line is coupled to a corresponding current control circuit. The source line driving circuit is coupled to the source lines. The sense amplifier circuit is coupled to the match signal lines. For a particular storage cell among the storage cells, when an input voltage of the first input signal corresponding to the particular storage cell and an input voltage of the second input signal corresponding to the particular storage cell are both within a match range of the particular storage cell, the N-type transistor and the P-type transistor of the particular storage cell are both turned on, and the conduction current of the particular storage cell is substantially a fixed current value. The match range of the particular storage cell is related to a threshold voltage of the N-type transistor of the particular storage cell, a threshold voltage of the P-type transistor of the particular storage cell, and the fixed current value.

[0008] According to yet another aspect of the present application, an analog content-addressable memory device is provided. The analog content-addressable memory device includes a first word line driving circuit, a second word line driving circuit, a first N-channel NAND string group, a first P-channel NAND string group, a plurality of first sense amplifiers, a plurality of second sense amplifiers, and a plurality of first AND gates. The first word line driving circuit is configured to provide a plurality of first input signals. The second word line driving circuit is configured to provide a plurality of second input signals. The first N-channel NAND string group includes a plurality of first N-channel NAND strings. Each of the first N-channel NAND strings is configured to receive the first input signals. Each of the first N-channel NAND strings is further configured to generate a first current. The first P-channel NAND string group includes a plurality of first P-channel NAND strings. Each of the first P-channel NAND strings is configured to receive the second input signals. Each of the first P-channel NAND strings is further configured to generate a second current. The first sense amplifiers are respectively coupled to the first N-channel NAND strings of the first N-channel NAND string group. The second sense amplifiers are respectively coupled to the first P-channel NAND strings of the first P-channel NAND string group. The first sense amplifiers and the second sense amplifiers each have a threshold current value. Each of the first AND gates is coupled to a corresponding first sense amplifier and a corresponding second sense amplifier. One of the first AND gates is a selected first AND gate. The selected first AND gate outputs a first logic value when the first current and the second current corresponding to the selected first AND gate are each greater than or equal to the threshold current value.

[0009] For a better understanding of the above-described and other aspects and advantages of the present application, reference is made to the following detailed description taken in conjunction with the accompanying drawings, in which: BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 An operation schematic diagram of an analog content-addressable memory (analog CAM);

[0011] Figure 2 An analog CAM memory cell;

[0012] Figure 3 A matching range of an analog CAM memory cell;

[0013] Figure 4 A circuit diagram of a memory cell of an analog content-addressable memory according to an embodiment;

[0014] Figure 5A A matching range of a memory cell without a current control circuit;

[0015] Figure 5B A connection diagram of a memory cellFigure 5A The relationship between the output voltage of the matching signal line of the memory cell and the discharge time is shown in the figure.

[0016] Figure 6A The matching range for memory cells with current control circuitry;

[0017] Figure 6B To connect to Figure 6A The relationship between the output voltage of the matching signal line of the memory cell and the discharge time is shown in the figure.

[0018] Figure 7 To be Figure 4 The storage unit shown is an example of an analog content-addressable memory device 300;

[0019] Figure 8 A circuit diagram of a storage cell of an analog content-addressable memory according to another embodiment;

[0020] Figure 9 A schematic diagram of the matching range of a memory cell with current control circuitry;

[0021] Figure 10 For application Figure 8 The circuit diagram of the analog content addressable memory device of the storage unit.

[0022] Figure 11 This is a simulated content-addressable memory device according to another embodiment.

[0023] Explanation of reference numerals in the attached figures

[0024] 100, 200, 400: Analog Content Addressable Memory

[0025] 202, 304: Storage Unit

[0026] 204, 312, ML: Matching signal lines

[0027] 206, 306, 402: N-type transistors

[0028] 208, 308, 404: P-type transistors

[0029] 210, 310, 406: Current control circuit

[0030] 210A, 310A: Control transistors

[0031] 300, 500, 600: Analog Content Addressable Memory Devices

[0032] 302: Word line driver circuit

[0033] 314, SL: Source line

[0034] 316: source line driver circuit

[0035] 318: sense amplifier circuit

[0036] 406A: first sense amplifier

[0037] 406B: second sense amplifier

[0038] 408: AND logic gate

[0039] 502: first word line driver circuit

[0040] 504: second word line driver circuit

[0041] 506: first N-channel NAND string set

[0042] 508: first P-channel NAND string set

[0043] 510(1), 510(2), 510(n): first sense amplifier circuit

[0044] 512(1), 512(2), 512(n): second sense amplifier circuit

[0045] 514(1), 514(2), 514(n): first AND logic gate

[0046] 516(1), 516(2), 516(n): first N-channel NAND string

[0047] 518(1), 518(2), 518(n): first P-channel NAND string

[0048] 520, 620: decoder

[0049] 602: third word line driver circuit

[0050] 604: fourth word line driver circuit

[0051] 606: second N-channel NAND string set

[0052] 608: second P-channel NAND string set

[0053] 610(1), 610(2), 610(n): third sense amplifier circuit

[0054] 612(1), 612(2), 612(n): fourth sense amplifier circuit

[0055] 614(1), 614(2), 614(n): second AND logic gate

[0056] 616(1), 616(2), 616(n): second N-channel NAND string

[0057] 618(1), 618(2), 618(n): second P-channel NAND string

[0058] 622(1), 622(2), 622(n): third AND logic gate

[0059] CL1: analog CAM memory cell

[0060] R(1), R(2), R(3), R(4): row

[0061] Rn: no match result

[0062] Ry: match result

[0063] MSn: first floating gate device

[0064] MSp: second floating gate device

[0065] Ip, I pass : on current

[0066] MR, MR0, MR1, MRa, MRb, MRc: match range

[0067] CN, CP: curve

[0068] LB: lower limit

[0069] UB: upper limit

[0070] G1, G2, G3: gate

[0071] D1, D2, D3: drain

[0072] S1, S2, S3: source

[0073] C(1), C(2),..., C(n), C(i): control voltage

[0074] I1(1), I1(2), I1(n): first current

[0075] I2(1), I2(2), I2(n): second current

[0076] I3(1), I3(2), I3(n): third current

[0077] I4(1), I4(2), I4(n): fourth current

[0078] SL1(1), SL1(2), SL1(m): first input signal

[0079] SL2(1), SL2(2), SL2(m): second input signal

[0080] SL3(1), SL3(2), SL3(m): third input signal

[0081] SL4(1), SL4(2), SL4(m): fourth input signal

[0082] BL1(1), BL1(2), BL1(3), BL1(n): first bit line signal

[0083] BL2(1), BL2(2), BL2(3), BL2(n): second bit line signal

[0084] BL3(1), BL3(2), BL3(3), BL3(n): third bit line signal

[0085] BL4(1), BL4(2), BL4(3), BL4(n): fourth bit line signal DETAILED DESCRIPTION

[0086] Reference is made to Figure 1 which is a schematic diagram of the operation of an analog content-addressable memory (analog CAM) 100. The analog CAM 100 includes a plurality of analog CAM storage cells CL1. The analog CAM storage cells CL1 are arranged in a plurality of columns R(1), R(2), R(3), R(4) to store a plurality of analog contents. For example, the contents stored in column R(1) are "0.00~1.00, 0.48~0.76, 0.00~0.15". "0.00~1.00" means that any value can be matched. The contents stored in column R(2) are "0.62~1.00, 0.25~0.63, 0.25~1.00". The contents stored in column R(3) are "0.26~0.61, 0.12~0.40, 0.00~1.00". The contents stored in column R(4) are "0.00~0.43, 0.00~0.28, 0.58~1.00". A plurality of input signals S1 are input to the analog CAM 100. The contents of the first input signal S1 is "0.81", the contents of the second input signal S1 is "0.62", and the contents of the third input signal S1 is "0.12".

[0087] The input signals S1 are compared with the contents stored in column R(1). The "0.00-1.00, 0.48-0.76, 0.00-0.15" stored in column R(1) are matched. Since "0.81", "0.62" and "0.12" fall into "0.00-1.00", "0.48-0.76" and "0.00-0.15" respectively, a match success result Ry is outputted.

[0088] The input signals S1 are compared with the contents stored in column R(2). A match failure result Rn is outputted. The input signals S1 are compared with the contents stored in column R(3). A match failure result Rn is outputted. The input signals S1 are compared with the contents stored in column R(4). A match failure result Rn is outputted. That is, the analog content addressable memory 100 can store analog contents, and any analog contents matched with the input signals S1 can be searched out.

[0089] Please refer to Figure 2 which is an analog CAM memory cell CL1. The analog CAM memory cell CL1 includes a first floating gate device MSn and a second floating gate device MSp. The first floating gate device MSn has an N-type channel, and the second floating gate device MSp has a P-type channel. The second floating gate device MSp is connected to the first floating gate device MSn in series. The first floating gate device MSn is an N-type metal oxide semiconductor (NMOS), and the second floating gate device MSp is a P-type metal oxide semiconductor (PMOS). The drain of the first floating gate device MSn is connected to a match signal line ML, and the source of the first floating gate device MSn is connected to the source of the second floating gate device MSp. The drain of the second floating gate device MSp is connected to a source line SL. The input signals S1 are inputted to the gates of the first floating gate device MSn and the second floating gate device MSp.

[0090] Please refer to Figure 3 which is the match range MR of the analog CAM memory cell CL1. The curve CN is the characteristic curve of the first floating gate device MSn, and the curve CP is the characteristic curve of the second floating gate device MSp. The steep slope of the curve CN and the curve CP is greater than 0.01 mV / dec. For example, Figure 3 the steep curve of the curve CN and the curve CP of the analog CAM memory cell CL1 is 0.015 mV / dec. The first floating gate device MSn and the second floating gate device MSp are super steep slope devices.

[0091] In the analog CAM memory cell CL1, the threshold voltage of the first floating gate device MSn is lower than the threshold voltage of the second floating gate device MSp, thereby forming a matching range MR between the threshold voltages of the first floating gate device MSn and the second floating gate device MSp. In the analog CAM memory cell CL1, the lower limit LB of the matching range MR is the threshold voltage of the first floating gate device MSn, and the upper limit UB of the matching range MR is the threshold voltage of the second floating gate device MSp.

[0092] like Figure 2 and Figure 3 As shown, when the input signal S1 falls within the matching range MR, the first floating gate device MSn is turned on and the second floating gate device MSp is also turned on, thus forming a conduction current Ip. When the input signal S1 is not within the matching range MR, the first floating gate device MSn or the second floating gate device MSp is not turned on, so no conduction current Ip is formed.

[0093] Please refer to Figure 4 This is a circuit diagram of a storage cell 202 of an analog content addressable memory 200 according to an embodiment of the present disclosure. The analog content addressable memory 200 includes, for example, storage cell 202 and matching signal line 204. Storage cell 202 includes an N-type transistor 206, a P-type transistor 208, and a current control circuit 210. The N-type transistor 206 has a gate G1 for receiving an input signal B(i). The P-type transistor 208 has a gate G2 for receiving an input signal A(i). The current control circuit 210 is coupled to at least one of the N-type transistor 206 and the P-type transistor 208, for example, coupled to the P-type transistor 208, and the current control circuit 210 is used to generate at least one on-state current, for example, an on-state current I. pass Specifically, when the input voltage of input signal B(i) and the input voltage of input signal A(i) are within the matching range, both N-type transistor 206 and P-type transistor 208 are turned on, and the corresponding on-current I... pass Essentially, it is a fixed current value. The matching range is related to the threshold voltage 206 of the N-type transistor, the threshold voltage of the P-type transistor 208, and this fixed current value.

[0094] Thus, by using the current control circuit 210, the magnitude of the current flowing through the N-type transistor 206 and the P-type transistor 208 when they are turned on is fixed to the magnitude of the current flowing through the current control circuit 210. Therefore, even if the input voltage of the input signal A(i) or B(i) may have multiple different levels, the magnitude of the current flowing through the N-type transistor 206 and the P-type transistor 208 when they are turned on remains substantially the same. Thus, even if the input voltage of the input signal A(i) or B(i) may have multiple different levels, the discharge time on the matching signal line 204 connected to the storage cell 202 remains the same, resulting in a stable discharge time for the matching signal line 204 and reducing the occurrence of misjudgments.

[0095] like Figure 4 As shown, the current control circuit 210 includes, for example, a control transistor 210A, which is a metal-oxide-semiconductor field-effect transistor (MOSFET) or a floating gate (FG) transistor. The drain D1 of the N-type transistor 206 is electrically connected to the matching signal line 204. The source S1 of the N-type transistor 206 is electrically connected to the source S2 of the P-type transistor 208. The drain D2 of the P-type transistor 208 is electrically connected to one end of the control transistor 210A (e.g., the drain D3 of the control transistor 210A). The control transistor 210A has a gate G3, which receives a control voltage C(i), which is essentially a fixed voltage value.

[0096] The other end of the control transistor 210A (e.g., the source S3 of the control transistor 210A) is electrically connected to a source line SL, for example. In an embodiment, the N-type transistor 206 and the P-type transistor 208 are 2D (two-dimensional) flash memory structures or 3D (three-dimensional) flash memory structures. In an embodiment, the N-type transistor 206 and the P-type transistor 208 can be programmed using F-N tunneling (Fowler-Nordheim tunneling), CHE (Channel Hot Electron), or poly to poly. In programming, the input voltage of the input signal A(i) and the input voltage of the input signal B(i) can be different. In data search and comparison, the input voltage of the input signal A(i) and the input voltage of the input signal B(i) are the same. In an embodiment, the N-type transistor 206 and the P-type transistor 208 can be erased using F-N tunneling, BTBHH (Band-To-Band Hot Hole), or poly to poly.

[0097] In an embodiment, the analog content addressable memory 200 is a flash memory. The flash memory is a charge storage memory, a charge trapping memory, a split gate memory, or a FeFET (Ferroelectric field-effect transistor) memory, for example. In another embodiment, the analog content addressable memory 200 is a super steep slope flash memory. The super steep slope flash memory is a TRAM (Thyristor Random Access Memory), a GCT (Gate Control Thyristor), a TFET (Tunnel Field-Effect Transistor), or a NCFET (Negative Capacitance Field-Effect Transistor).

[0098] Please refer to Figure 5A and Figure 5B , Figure 5A is the matching range MR0 of the memory cell 202 without the current control circuit 210, Figure 5Bto be connected to Figure 5A The output voltage of the match signal line 204 connected to the storage unit 202 and the discharge time are shown in the graph. The curve CN is the characteristic curve of the N-type transistor 206, and the curve CP is the characteristic curve of the P-type transistor 208. The threshold voltage Vthn of the N-type transistor 206 (for example, about -2.8 V) and the threshold voltage Vthp of the P-type transistor 208 (for example, about -0.4 V) define a matching range MR0. When the N-type transistor 206 and the P-type transistor 208 operate in the subthreshold region, the slopes of the curves CN and CP in the matching range MR0 are not steep enough, which is a possible situation. As shown in Figure 5A and Figure 5B When the storage unit 202 does not have the current control circuit 210, when the input voltages of the input signals A(i) and B(i) are VI, the on current of the N-type transistor 206 is I1, so that the on current of the P-type transistor 208 is also I1. At this time, the on N-type transistor 206 and the on P-type transistor 208 will make the output voltage on the match signal line 204 drop from the original voltage Vms according to the curve V(I1), and drop to the reference voltage Vref for judging whether the match at the time point t2. Similarly, when the input voltages of the input signals A(i) and B(i) are V2, the on current of the N-type transistor 206 is I2, so that the output voltage on the match signal line 204 drops from the original voltage Vms according to the curve V(I2), and drops to the reference voltage Vref for judging whether the match at the time point t1. When the input voltages of the input signals A(i) and B(i) are V3, the on current of the N-type transistor 206 is I3, so that the output voltage on the match signal line 204 drops from the original voltage Vms according to the curve V(I3), and drops to the reference voltage Vref for judging whether the match at the time point t3. Since different input voltages of the input signals A(i) and B(i) will correspond to different on current sizes, the time for the output voltage on the match signal line 204 to drop from the original voltage Vms to the reference voltage Vref is different. That is, for a plurality of input signals A(i) or B(i) with different voltage levels, since the current level when the match signal line 204 discharges is not fixed, the discharge time on the match signal line 204 connected to the storage unit 202 is different, so that the match signal line 204 has different discharge times. Thus, when the data search and comparison in the memory are performed to judge whether the data range stored in the storage unit and the input data match, the length of time required for the judging action becomes not fixed, and the probability of misjudgment increases.

[0099] Please refer to Figure 6A and Figure 6B , Figure 6AFor the matching range MR1 of the memory cell 202 with current control circuit 210, Figure 6B To connect to Figure 6A The relationship between the output voltage of the matching signal line 204 of the storage cell 202 and the discharge time is shown in the figure. Figure 6A The curve CN is the same as the curve CP. Figure 5A The curves CN and CP are given. The matching range MR1 of the memory cell 202 with current control circuit 210 is related to the threshold voltage of N-type transistor 206, the threshold voltage of P-type transistor 208, and a fixed current value. The matching range MR1 is, for example, determined by the on-state current I of N-type transistor 206 and P-type transistor 208. pass When both are on, the minimum gate voltage V4 of the corresponding N-type transistor 206 (greater than the threshold voltage Vthn of the N-type transistor 206) and the maximum gate voltage V5 of the corresponding P-type transistor 208 (less than the threshold voltage Vthp of the P-type transistor 208) are defined. Figure 6A and Figure 6B As shown, when the input voltages of input signals A(i) and B(i) are V1, the conduction currents of N-type transistor 206 and P-type transistor 208 are I. pass At this time, the conducting N-type transistor 206 and P-type transistor 208 will cause the output voltage on the matching signal line 204 to decrease from the original voltage Vms according to curve V, and at time point t4, it will decrease to the reference voltage Vref used to determine whether matching is achieved. Similarly, when the input voltages of input signals A(i) and B(i) are V2 and V3, respectively, the conduction current of N-type transistor 206 remains I. pass This causes the output voltage on the matching signal line 204 to decrease from the original voltage Vms according to curve V), and at time point t4, it decreases to the reference voltage Vref used to determine whether a match has occurred. Since the input voltages of different input signals A(i) and B(i) will correspond to the same conduction current I... pass This ensures that the discharge time for the output voltage on the matching signal line 204 to drop from the original voltage Vms to the reference voltage Vref is almost the same. In other words, when the storage cell 202 has a current control circuit 210, because the magnitude of the current during discharge on the matching signal line 204 is fixed, the discharge time corresponding to the input voltage of different input signals connected to the matching signal line 204 of the storage cell 202 is substantially the same, thus ensuring a stable discharge time for the matching signal line 204. This fixes the time required for data searching and comparison within the memory to determine whether the data stored in the storage cell matches the input data, thereby reducing the probability of misjudgment.

[0100] Please refer to Figure 7 , he is a general Figure 4The storage cells shown are applied to an example of an analog content addressable memory device 300. The analog content addressable memory device 300 includes a word line driving circuit 302, a plurality of storage cells 304 (i.e. Figure 4 the storage cells 202), a plurality of match signal lines 312, a plurality of source lines 314, a source line driving circuit 316, and a sense amplifier circuit 318. The word line driving circuit 302 is configured to provide a plurality of input signals B(l), B(2),..., B(n) and a plurality of input signals A(l), A(2),..., A(n). Each storage cell 304 of the analog content addressable memory device 300 includes an N-type transistor 306, a P-type transistor 308, and a current control circuit 310. The N-type transistor 306 of each storage cell 304 has a gate G1, which is configured to receive a corresponding input signal B(i), i being a positive integer from 1 to n. The P-type transistor 308 of each storage cell 304 has a gate G2, which is configured to receive a corresponding input signal A(i). The current control circuit 310 is coupled to the P-type transistor 308 and is configured to generate a conduction current I pass . Each match signal line 312 is coupled to a corresponding storage cell 304, and each source line 314 is coupled to a corresponding current control circuit 310. The source line driving circuit 316 is coupled to the plurality of source lines 314, and the sense amplifier circuit 318 is coupled to the plurality of match signal lines 312. For a particular storage cell 304(j,i) (j being an integer between 1 and m) among the storage cells, when the input voltage of the input signal B(i) corresponding to the particular storage cell 304(j,i) and the input voltage of the input signal A(i) corresponding to the particular storage cell 304(j,i) are both within a matching range of the particular storage cell 304(j,i), the N-type transistor 306 and the P-type transistor 308 of the particular storage cell 304(j,i) are both turned on, and the conduction current I pass of the particular storage cell 304(j,i) is substantially a fixed current value. The matching range of the particular storage cell 304(j,i) is related to the threshold voltage of the N-type transistor 306 of the particular storage cell 304(j,i), the threshold voltage of the P-type transistor 308 of the particular storage cell 304(j,i), and the fixed current value.

[0101] When programming or erasing the plurality of storage cells 304 (e.g., the storage cells 304(l,l) to 304(m,n)), the input signal A(i) can be different from the input signal B(i). When comparing the input signals A(l) to A(n) with the contents stored in the first column to the mth column of the storage cells 304, the input signal A(i) is the same as the input signal B(i).

[0102] For example, when input signals A(1) to A(n) are compared with the contents of storage cells 304(1,1) to 304(m,n) stored in columns 1 to m, assuming that input signals A(1) to A(n) are respectively within the matching range of storage cells 304(1,1) to 304(1,n) in column 1, it means that the contents of input signals A(1) to A(n) match the contents of storage cells 304(1,1) to 304(1,n) in column 1. That is, the analog values ​​corresponding to input signals A(1) to A(n) are respectively within the range of analog values ​​corresponding to the matching range of storage cells 304(1,1) to 304(1,n) in column 1. At this time, all storage cells 304(1,1) to 304(1,n) in the first column will be turned on and current will flow through them, so as to pull down the voltage of the matching signal line 312(1) and enable the sensing amplifier circuit 318 to detect the matching success result.

[0103] If any of the input signals A(1) to A(n) is not within the matching range of the storage cells 304(1,1) to 304(1,n) in the first column, it means that the content of the input signals A(1) to A(n) does not match the content of the storage cells 304(1,1) to 304(1,n) in the first column. That is, the analog values ​​corresponding to the input signals A(1) to A(n) are not completely within the range of analog values ​​corresponding to the matching range of the storage cells 304(1,1) to 304(1,n) in the first column. At this time, at least one of the storage cells 304(1,1) to 304(1,n) in the first column will not be turned on, so that the voltage of the matching signal line 312(1) will not be pulled down to less than the reference voltage Vref. Thus, the sensing amplifier circuit 318 will detect the unsuccessful matching result. In other words, the analog content addressable memory 300 can store analog content, and any analog content that matches input signals A(1) to input signals A(n) (e.g., analog content stored in a certain column of storage cell 304) can be searched out.

[0104] By using Figure 4 The storage unit shown allows the analog content addressable memory device 300 to perform data search and comparison within the memory to determine whether the data stored in the storage unit matches the input data. The conducting storage unit can use a fixed current to reduce the voltage of the matching signal line 312, making the voltage drop time of the matching signal line 312 controllable to reduce the probability of misjudgment.

[0105] Referring to Figure 8 is a circuit diagram of a storage unit 400 of an analog content addressable memory according to another embodiment of the present disclosure. The storage unit 400 includes an N-type transistor 402 having a gate G1 for receiving an input signal B(i), a P-type transistor 404 having a gate G2 for receiving an input signal A(i), a current control circuit 406 having a first sense amplifier 406A and a second sense amplifier 406B, and an AND logic gate 408 coupled to the first sense amplifier 406A and the second sense amplifier 406B, each having a threshold current value. The N-type transistor 402 is electrically connected to the first sense amplifier 406A, and the P-type transistor 404 is electrically connected to the second sense amplifier 406B. When the input voltage of the input signal B(i) and the input voltage of the input signal A(i) are within a matching range, at least one on current I1 of the N-type transistor 402 and another on current I2 of the P-type transistor 404 are greater than or equal to the threshold current value, and the AND logic gate 408 outputs a first logic value.

[0106] Referring to Figure 8 and Figure 9 wherein Figure 9 is a matching range diagram of the storage unit 400 having the current control circuit 406. The matching range is related to a threshold voltage Vthn of the N-type transistor 402, a threshold voltage Vthp of the P-type transistor 404, and the threshold current values of the first sense amplifier 406A and the second sense amplifier 406B. As shown in Figure 9 , when the threshold current values of the first sense amplifier 406A and the second sense amplifier 406B are threshold current value Ith1, the matching range MRa is determined by a gate voltage V1’ at which the on current of the N-type transistor 402 is the threshold current value Ith1 and a gate voltage V6’ at which the on current of the P-type transistor 404 is the threshold current value Ith1. When the threshold current values of the first sense amplifier 406A and the second sense amplifier 406B are threshold current value Ith2, the matching range MRa is determined by a gate voltage V2’ at which the on current of the N-type transistor 402 is the threshold current value Ith2 and a gate voltage V5’ at which the on current of the P-type transistor 404 is the threshold current value Ith1. When the threshold current values of the first sense amplifier 406A and the second sense amplifier 406B are threshold current value Ith3, the matching range MRa is determined by a gate voltage V3’ at which the on current of the N-type transistor 402 is the threshold current value Ith3 and a gate voltage V4’ at which the on current of the P-type transistor 404 is the threshold current value Ith1.

[0107] The threshold current value Ith1 of the first sensing amplifier 406A and the second sensing amplifier 406B is taken as an example for illustration. Please refer to Figure 8 and Figure 9 When the input voltage of the input signal A(i) and the input voltage of the input signal B(i) are within the matching range MRa, the N-type transistor 402 generates a first current I1, and the P-type transistor 404 generates a second current I2. When both the first current I1 and the second current I2 are greater than or equal to the threshold current value of the first sensing amplifier 406A and the second sensing amplifier 406B, the first sensing amplifier 406A and the second sensing amplifier 406B output a first logic value, for example, logic value 1. When the inputs of both the inputs of the AND logic gate 408 are the first logic value, the AND logic gate 408 outputs the first logic value (for example, logic value 1) to indicate that the input voltage of the input signal A(i) and the input voltage of the input signal B(i) are both within the matching range MRa.

[0108] Therefore, according to the embodiment of the present application, the first sensing amplifier 406A and the second sensing amplifier 406B of the storage unit 400 can respectively determine whether the N-type transistor 402 and the P-type transistor 404 are turned on by using the same threshold current value of the first sensing amplifier 406A and the second sensing amplifier 406B when the input signal A(i) and the input signal B(i) are within the matching range, so that the probability of misjudgment can be reduced. Figure 8

[0109] Please refer to Figure 10 which is applied Figure 8 ​Figure 5 is a circuit diagram of an analog content addressable memory device 500 having a plurality of storage units. The analog content addressable memory device 500 includes a first word line drive circuit 502, a second word line drive circuit 504, a first N-channel NAND string set 506, a first P-channel NAND string set 508, a plurality of first sense amplifiers 510(1), 510(2),..., 510(n), a plurality of second sense amplifiers 512(1), 512(2),..., 512(n), and a plurality of first AND logic gates 514(1), 514(2),..., 514(n). The first word line drive circuit 502 is configured to provide a plurality of first input signals SL1(1), SL1(2),..., SL1(m), and the second word line drive circuit 504 is configured to provide a plurality of second input signals SL2(1), SL2(2),..., SL2(m). The first N-channel NAND string set 506 includes a plurality of first N-channel NAND strings 516(1), 516(2),..., 516(n), each of which is configured to receive a first input signal SL1(1), SL1(2),..., SL1(m) and to generate a first current, e.g., the first N-channel NAND strings 516(1), 516(2),..., 516(n) generate first currents I1(1), I1(2),..., I1(n), respectively. The first P-channel NAND string set 508 includes a plurality of first P-channel NAND strings 518(1), 518(2),..., 518(n), each of which is configured to receive a second input signal SL2(1), SL2(2),..., SL2(m). Each of the first P-channel NAND strings 518 is also configured to generate a second current, e.g., the first P-channel NAND strings 518(1), 518(2),..., 518(n) generate second currents I2(1), I2(2),..., I2(n), respectively. The plurality of first sense amplifiers 510(1), 510(2),..., 510(n) are coupled to the first N-channel NAND strings 516(1), 516(2),..., 516(n) of the first N-channel NAND string set 506, respectively. The second sense amplifiers 512(1), 512(2),..., 512(n) are coupled to the first P-channel NAND strings 518(1), 518(2),..., 518(n) of the first P-channel NAND string set 508, respectively. Each of the first sense amplifiers 510(1), 510(2),..., 510(n) and the second sense amplifiers 512(1), 512(2),..., 512(n) has a threshold current value. Each of the first AND logic gates 514(1), 514(2),..., 514(n) is coupled to a corresponding first sense amplifier 510 and a corresponding second sense amplifier 512.wherein one of the first AND logic gates 514(1), 514(2),..., 514(n) is a selected first AND logic gate 514(i) (i is a positive integer from 1 to n). When the first current I1(i) and the second current I2(i) of the selected first AND logic gate 514(i) are both greater than or equal to the threshold current value, the selected first AND logic gate 514(i) outputs a first logic value to the decoder 520. At this time, the decoder 520 will determine that the data provided by the first word line drive circuit 502 matches the data stored in the first N-channel NAND string 516(i) and the data provided by the second word line drive circuit 504 matches the data stored in the first P-channel NAND string 518(i).

[0110] Therefore, according to the above-mentioned embodiment, the first sensing amplifier circuit 510(i) and the second sensing amplifier circuit 512(i) of the analog content addressable memory device 500 can output the first logic value when the first current I1(i) and the second current I2(i) are greater than or equal to the same current level, i.e., the threshold current value of the first sensing amplifier circuit 510(i) and the second sensing amplifier circuit 512(i). In this way, the time required for detecting whether the match occurs can be the same when the search and comparison of the analog data stored in the memory are performed, so that the misjudgment can be avoided. Figure 9

[0111] Further, as mentioned above, the first sensing amplifier circuit 510(i) and the second sensing amplifier circuit 512(i) of the analog content addressable memory device 500 can output the first logic value when the first current I1(i) and the second current I2(i) are greater than or equal to the same current level, i.e., the threshold current value of the first sensing amplifier circuit 510(i) and the second sensing amplifier circuit 512(i). In this way, the time required for detecting whether the match occurs can be the same when the search and comparison of the analog data stored in the memory are performed, so that the misjudgment can be avoided. Figure 10 ​As shown, one end of the first N-channel NAND string 516(i) of the first N-channel NAND string group 506 is configured to receive a first bit line signal BL1(i), and the other end of the first N-channel NAND string 516(i) of the first N-channel NAND string group 506 is coupled to a corresponding first sense amplifier circuit 510(i). One end of the first P-channel NAND string 518(i) of the first P-channel NAND string group 508 is configured to receive a second bit line signal BL2(i), and the other end of the first P-channel NAND string 518(i) of the first P-channel NAND string group 508 is coupled to a second sense amplifier circuit 512(i). The first N-channel NAND string 516(i) of the first N-channel NAND string group 506 includes a plurality of first N-type transistors, and the first P-channel NAND string 518(i) of the first P-channel NAND string group 508 includes a plurality of first P-type transistors. The gates of the first N-type transistors of the first N-channel NAND string 516(i) are configured to receive first input signals SL1(1), SL1(2), …, SL1(m). The gates of the first P-type transistors of the first P-channel NAND string 518(i) are configured to receive second input signals SL2(1), SL2(2), …, SL2(m).

[0112] Assume that one of the plurality of first N-channel NAND strings (e.g., first N-channel NAND string 516(i), i being a positive integer from 1 to n) stores data within a range that matches the input signal. When the first input signal SL1(1), SL1(2),..., SL1(m) provided by the first word line driver circuit 502 matches the storage range of the m number of memory cells in the first N-channel NAND string 516(i), i.e., the voltage levels of the first input signal SL1(1), SL1(2),..., SL1(m) are within the matching range of the m number of memory cells in the first N-channel NAND string 516(i), respectively, the first N-channel NAND string 516(i) outputs a first current I1(i). Similarly, when the second input signal SL2(1), SL2(2),..., SL2(m) provided by the second word line driver circuit 504 matches the storage range of the m number of memory cells in the first P-channel NAND string 518(i), i.e., the voltage levels of the second input signal SL2(1), SL2(2),..., SL2(m) are within the matching range of the m number of memory cells in the first P-channel NAND string 518(i), respectively, the first P-channel NAND string 518(i) outputs a second current I2(i). At this time, when the first current I1(i) and the second current I2(i) are both greater than or equal to a threshold current value, the first AND logic gate 514(i) outputs a first logic value, indicating that the data provided by the first word line driver circuit 502 matches the data stored in the first N-channel NAND string 516(i), and the data provided by the second word line driver circuit 504 matches the data stored in the first P-channel NAND string 518(i).

[0113] In one embodiment, the first N-channel NAND string group 506 and the first P-channel NAND string group 508 are 2D flash memory structures or 3D flash memory structures. In one embodiment, the first N-channel NAND string group 506 and the first P-channel NAND string group 508 can be programmed using F-N tunneling, channel hot electron injection technology, or polysilicon-to-polysilicon. In one embodiment, the first N-channel NAND string group 506 and the first P-channel NAND string group 508 can be erased using F-N tunneling, band-to-band hot hole injection, or polysilicon-to-polysilicon.

[0114] In one embodiment, the analog content addressable memory device 500 is a flash memory, which is a charge storage memory, a charge trapping memory, a split-gate memory, or a ferroelectric field effect transistor memory. In another embodiment, the analog content addressable memory device 500 is a super steep flash memory, which is a thyristor random access memory, a gate-controlled thyristor, a tunneling field effect transistor, or a negative capacitance field effect transistor.

[0115] Reference is made to Figure 11 which is an analog content addressable memory device 600 according to another embodiment. The analog content addressable memory device 600 includes Figure 10The analog content addressable memory device 500, the third word line driver circuit 602, the fourth word line driver circuit 604, the second N-channel NAND string group 606, the second P-channel NAND string group 608, the plurality of third sense amplifiers 610(1), 610(2),..., 610(n), the plurality of fourth sense amplifiers 612(1), 612(2),..., 612(n), the plurality of second AND logic gates 614(1), 614(2),..., 614(n), and the plurality of third AND logic gates 622(1), 622(2),..., 622(n) are also included. The third word line driver circuit 602 is configured to provide a plurality of third input signals SL3(1), SL3(2),..., SL3(m), and the fourth word line driver circuit 604 is configured to provide a plurality of fourth input signals SL4(1), SL4(2),..., SL4(m). The second N-channel NAND string group 606 includes a plurality of second N-channel NAND strings 616(1), 616(2),..., 616(n), each of which is configured to receive a third input signal SL3(1), SL3(2),..., SL3(m). Each of the second N-channel NAND strings is also configured to generate a third current, such as the second N-channel NAND strings 616(1), 616(2),..., 616(n) generating third currents I3(1), I3(2),..., I3(n), respectively. The second P-channel NAND string group 608 includes a plurality of second P-channel NAND strings 618(1), 618(2),..., 618(n). Each of the second P-channel NAND strings is configured to receive a fourth input signal SL4(1), SL4(2),..., SL4(m), and each of the second P-channel NAND strings is also configured to generate a fourth current, such as the second P-channel NAND strings 618(1), 618(2),..., 618(n) generating fourth currents I4(1), I4(2),..., I4(n), respectively. The third sense amplifiers 610(1), 610(2),..., 610(n) are coupled to the plurality of second N-channel NAND strings 616(1), 616(2),..., 616(n) of the second N-channel NAND string group 606, and the fourth sense amplifiers 612(1), 612(2),..., 612(n) are coupled to the plurality of second P-channel NAND strings 618(1), 618(2),..., 618(n) of the second P-channel NAND string group 608. Each of the third sense amplifiers 610(1), 610(2),..., 610(n) and each of the fourth sense amplifiers 612(1), 612(2),..., 612(n) has a threshold current value. Each of the second AND logic gates 614(1), 614(2),..., 614(n) is coupled to a corresponding third sense amplifier and a corresponding fourth sense amplifier.Each of the third AND logic gates 622(1), 622(2), …, 622(n) is coupled to a corresponding first AND logic gate and a corresponding second AND logic gate. One of the second AND logic gates 614(1), 614(2), …, 614(n) is a selected second AND logic gate 614(i), i being a positive integer from 1 to n. The selected second AND logic gate 614(i) outputs a first logic value when the current of the third current I3(i) and the fourth current I4(i) corresponding to the selected second AND logic gate 614(i) are both greater than or equal to a threshold current value. One of the third AND logic gates 622(1), 622(2), …, 622(n) is a selected third AND logic gate 622(i). The selected third AND logic gate 622(i) outputs a first logic value when the first AND logic gate 514(i) and the second AND logic gate 614(i) corresponding to the selected third AND logic gate 622(i) both output the first logic value.

[0116] As Figure 11As shown, one end of each second N-channel NAND string 616(1), 616(2), …, 616(n) of the second N-channel NAND string group 606 is configured to receive a third bit line signal, for example, the second N-channel NAND strings 616(1), 616(2), …, 616(n) receive third bit line signals BL3(1), BL3(2), …, BL3(n), respectively. The other end of each second N-channel NAND string 616(1), 616(2), …, 616(n) of the second N-channel NAND string group 606 is coupled to a corresponding third sense amplifier circuit, for example, each second N-channel NAND string 616(1), 616(2), …, 616(n) is coupled to a third sense amplifier circuit 610(1), 610(2), …, 610(n), respectively. One end of each second P-channel NAND string 618(1), 618(2), …, 618(n) of the second P-channel NAND string group 608 is configured to receive a fourth bit line signal, for example, the second P-channel NAND strings 618(1), 618(2), …, 618(n) receive fourth bit line signals BL4(1), BL4(2), …, BL4(n). The other end of each second P-channel NAND string 618(1), 618(2), …, 618(n) of the second P-channel NAND string group 608 is coupled to a corresponding fourth sense amplifier circuit, for example, the other end of the second P-channel NAND strings 618(1), 618(2), …, 618(n) is coupled to a fourth sense amplifier circuit 612(1), 612(2), …, 612(n). Each second N-channel NAND string of the second N-channel NAND string group 606 includes a plurality of second N-type transistors. Each second P-channel NAND string of the second P-channel NAND string group 608 includes a plurality of second P-type transistors. A gate of each second N-type transistor of each second N-channel NAND string is configured to receive a corresponding third input signal. A gate of each second P-type transistor of each second P-channel NAND string is configured to receive a corresponding fourth input signal. Thus, in accordance with the present application, the second N-channel NAND string group 606 and the second P-channel NAND string group 608 are configured to perform a NAND operation on the third input signals and the fourth input signals, respectively, and to output a result of the NAND operation on the third input signals and the fourth input signals, respectively. Figure 11In the embodiment, the first sensing amplifier circuit 510(1), 510(2), …, 510(n), the second sensing amplifier circuit 512(1), 512(2), …, 512(n), the third sensing amplifier circuit 610(1), 610(2), …, 610(n), and the fourth sensing amplifier circuit 612(1), 612(2), …, 612(n) of the analog content addressable memory device 600 correspond to the first input signal SL1(1), SL1(2), …, SL1(m), the second input signal SL2(1), SL2(2), …, SL2(m), the third input signal SL3(1), SL3(2), …, SL3(m), and the fourth input signal SL4(1), SL4(2), …, SL4(m), respectively. When the third input signal SL3(1), SL3(2), …, SL3(m) provided by the third word line driving circuit 602 matches the storage range of the m storage units in the second N-channel NAND string 616(i), i.e., the voltage level of the third input signal SL3(1), SL3(2), …, SL3(m) is within the matching range of the m storage units in the second N-channel NAND string 616(i), respectively, the second N-channel NAND string 616(i) outputs a third current I3(i). Similarly, when the fourth input signal SL4(1), SL4(2), …, SL4(m) provided by the fourth word line driving circuit 604 matches the storage range of the m storage units in the second P-channel NAND string 618(i), i.e., the voltage level of the fourth input signal SL4(1), SL4(2), …, SL4(m) is within the matching range of the m storage units in the second P-channel NAND string 618(i), respectively, the second P-channel NAND string 618(i) outputs a fourth current I4(i). At this time, when the third current I3(i) and the fourth current I4(i) are both greater than or equal to a threshold current value, the second AND logic gate 614(i) outputs a first logic value, indicating that the data provided by the third word line driving circuit 602 matches the data stored in the second N-channel NAND string 616(i), and the data provided by the fourth word line driving circuit 604 matches the data stored in the second P-channel NAND string 618(i).

[0117] When the first AND logic gate 514(i) outputs a first logic value and the second AND logic gate 614(i) outputs a first logic value, the third AND logic gate 622(i) will output a first logic value. As shown in FIG. 11, when i = 2, the third AND logic gate 622(2) will output a first logic value (e.g., logic value "1") to the decoder 620. At this time, the decoder 620 will determine that the data provided by the first word line driver circuit 502 matches the data stored in the first N-channel NAND string 516(i), the data provided by the second word line driver circuit 504 matches the data stored in the first P-channel NAND string 518(i), the data provided by the third word line driver circuit 602 matches the data stored in the second N-channel NAND string 616(i), and the data provided by the fourth word line driver circuit 604 matches the data stored in the second P-channel NAND string 618(i). Thus, by simulating the content addressable memory device 600, the amount of data searched (i.e., the amount of input signals) can be increased, for example, the data provided by the third word line driver circuit 602 and the data provided by the fourth word line driver circuit 604 can be added to perform data searching and comparison, so as to improve the performance of the analog content addressable memory. Furthermore, the analog content addressable memory device 600 can also reduce the size of the N-channel NAND string and the P-channel NAND string, so as to reduce the RC delay, so as to accelerate the response speed of the analog content addressable memory device.

[0118] According to the above-mentioned embodiments, the storage unit of the analog content addressable memory and the analog content addressable memory device provided by the present disclosure utilize the current control circuit to fix the current levels of different input signals within the matching range, so as to stabilize the discharge time of the matching signal line, so as to reduce the probability of misjudgment during data searching and comparison, and can accelerate the processing speed of the analog content addressable memory device.

[0119] In summary, although the present disclosure has been disclosed as above with embodiments, it is not intended to limit the present disclosure. Those skilled in the art, without departing from the spirit and scope of the present disclosure, can make various modifications and decorations. Therefore, the protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A storage cell for simulating content-addressable memory, the storage cell comprising: An N-type transistor has a first gate, the first gate of the N-type transistor being used to receive a first input signal; A P-type transistor having a second gate, the second gate of the P-type transistor being used to receive a second input signal; as well as A current control circuit, coupled to at least one of the N-type transistor and the P-type transistor, is used to generate at least one on-current. The N-type transistor, the P-type transistor, and the current control circuit are connected in series. The N-type transistor is coupled to a matching signal line, and the current control circuit is coupled to a source line. When the input voltage of the first input signal and the input voltage of the second input signal are within a matching range, both the N-type transistor and the P-type transistor are turned on, and the corresponding on-current is essentially a fixed current value. The matching range is related to the threshold voltage of the N-type transistor, the threshold voltage of the P-type transistor, and the fixed current value.

2. The memory cell according to claim 1, wherein the current control circuit has a control transistor, the control transistor being a metal-oxide-semiconductor field-effect transistor or a floating gate transistor, a first terminal of the N-type transistor being electrically connected to a first terminal of the P-type transistor, a second terminal of the P-type transistor being electrically connected to a terminal of the control transistor, the control transistor having a third gate, the third gate of the control transistor being used to receive a control voltage, the control voltage being substantially a fixed voltage value.

3. The memory cell according to claim 2, wherein a second terminal of the N-type transistor is electrically connected to the matching signal line, the second terminal of the N-type transistor is the drain, and the first terminal of the N-type transistor is the source.

4. The memory cell according to claim 1, wherein the memory cell further includes an AND gate, the current control circuit has a first sensing amplifier and a second sensing amplifier, the AND gate is coupled to the first sensing amplifier and the second sensing amplifier, the first sensing amplifier and the second sensing amplifier each have a threshold current value, the N-type transistor is electrically connected to the first sensing amplifier, and the P-type transistor is electrically connected to the second sensing amplifier. in, When one current of the at least one conducting current corresponding to the N-type transistor and another current of the at least one conducting current corresponding to the P-type transistor are both greater than or equal to the threshold current value, the AND logic gate outputs a first logic value.

5. The storage unit according to claim 1, wherein the analog content addressable memory is a flash memory, which is a charge storage memory, a charge trapping memory, a discrete gate memory, or a ferroelectric field-effect transistor memory.

6. The storage unit according to claim 1, wherein the analog content addressable memory is an ultra-steep flash memory, which is a thyristor random access memory, a gate-controlled thyristor, a tunneling field-effect transistor, or a negative capacitance field-effect transistor.

7. The memory cell according to claim 1, wherein the N-type transistor and the P-type transistor constitute a 2D flash memory structure or a 3D flash memory structure.

8. An analog content-addressable memory device, comprising: A single-line driver circuit is used to provide multiple first input signals and multiple second input signals; Multiple storage units, each storage unit comprising: An N-type transistor has a first gate, the first gate of the N-type transistor being used to receive the corresponding first input signal; A P-type transistor having a second gate, the second gate of the P-type transistor being used to receive a corresponding second input signal; and A current control circuit, coupled to at least one of the N-type transistor and the P-type transistor, is used to generate a conduction current; Multiple matching signal lines, each of which is coupled to the corresponding memory cell; Multiple source lines, each of which is coupled to the corresponding current control circuit; A source line drive circuit is coupled to these source lines; and A sense amplifier circuit is coupled to these matching signal lines; The N-type transistor, the P-type transistor, and the current control circuit are connected in series. The N-type transistor is coupled to a matching signal line, and the current control circuit is coupled to a source line. For a specific memory cell, when the input voltage of the first input signal corresponding to the specific memory cell and the input voltage of the second input signal corresponding to the specific memory cell are both within a matching range of the specific memory cell, both the N-type transistor and the P-type transistor of the specific memory cell are turned on. The conduction current of the specific memory cell is essentially a fixed current value. The matching range of the specific memory cell is related to the threshold voltage of the N-type transistor of the specific memory cell, the threshold voltage of the P-type transistor of the specific memory cell, and the fixed current value.

9. The analog content addressable memory device of claim 8, wherein the current control circuit of each memory cell has a control transistor, the control transistor being a metal-oxide-semiconductor field-effect transistor or a floating gate transistor, a first terminal of the N-type transistor being electrically connected to a first terminal of the P-type transistor, a second terminal of the P-type transistor being electrically connected to a terminal of the control transistor, the control transistor having a third gate for receiving a control voltage, the control voltage being substantially a fixed voltage value.

10. The analog content addressable memory device of claim 9, wherein a second terminal of the N-type transistor of each memory cell is electrically connected to the corresponding matching signal line, the second terminal of the N-type transistor being the drain and the first terminal of the N-type transistor being the source.

11. The analog content addressable memory device according to claim 8, wherein the analog content addressable memory device is a flash memory, which is a charge storage memory, a charge trapping memory, a discrete gate memory, or a ferroelectric field-effect transistor memory.

12. The analog content addressable memory device according to claim 8, wherein the analog content addressable memory device is an ultra-steep flash memory, the ultra-steep flash memory being a thyristor random access memory, a gate-controlled thyristor, a tunneling field-effect transistor, or a negative capacitance field-effect transistor.

13. The analog content addressable memory device according to claim 8, wherein the N-type transistor and the P-type transistor constitute a 2D flash memory structure.

14. An analog content-addressable memory device, comprising: A first word line driving circuit and a second word line driving circuit, the first word line driving circuit being used to provide a plurality of first input signals, and the second word line driving circuit being used to provide a plurality of second input signals; A first N-channel NAND serial array group includes multiple first N-channel NAND serial arrays, each first N-channel NAND serial array being used to receive these first input signals, and each first N-channel NAND serial array being used to generate a first current; A first P-channel NAND serial array group includes multiple first P-channel NAND serial arrays, each first P-channel NAND serial array is used to receive these second input signals, and each first P-channel NAND serial array is also used to generate a second current; Multiple first sensing amplifier circuits and multiple second sensing amplifier circuits are respectively coupled to the first N-channel NAND serial lines of the first N-channel NAND serial line group, and the second sensing amplifier circuits are respectively coupled to the first P-channel NAND serial lines of the first P-channel NAND serial line group. Each of the first sensing amplifier circuits and the second sensing amplifier circuits has a threshold current value. as well as Multiple first AND logic gates, each of which is coupled to the corresponding first sensing amplifier circuit and the corresponding second sensing amplifier circuit; One of these first AND logic gates is a selected first AND logic gate. When the currents of the first current and the second current corresponding to the selected first AND logic gate are both greater than or equal to the threshold current value, the selected first AND logic gate outputs a first logic value.

15. The analog content addressable memory device of claim 14, wherein one end of each of the first N-channel NAND serial segments of the first N-channel NAND serial group is used to receive a first bit line signal, the other end of each of the first N-channel NAND serial segments of the first N-channel NAND serial group is coupled to the corresponding first sense amplifier circuit, one end of each of the first P-channel NAND serial segments of the first P-channel NAND serial group is used to receive a second bit line signal, and each of the first P-channel NAND serial segments of the first P-channel NAND serial group... The other end of the ND string is coupled to the corresponding second sensing amplifier circuit. Each of the first N-channel NAND string groups includes a plurality of first N-type transistors, and each of the first P-channel NAND string groups includes a plurality of first P-type transistors. The gate of each of the first N-type transistors in each of the first N-channel NAND string groups is used to receive the corresponding first input signal, and the gate of each of the first P-type transistors in each of the first P-channel NAND string groups is used to receive the corresponding second input signal.

16. The analog content addressable memory device of claim 14, wherein the analog content addressable memory device further comprises: A third word line driving circuit and a fourth word line driving circuit, wherein the third word line driving circuit is used to provide a plurality of third input signals and the fourth word line driving circuit is used to provide a plurality of fourth input signals; A second N-channel NAND serial array group includes multiple second N-channel NAND serial arrays, each second N-channel NAND serial array is used to receive these third input signals, and each second N-channel NAND serial array is also used to generate a third current; A second P-channel NAND serial group includes multiple second P-channel NAND serial groups, each second P-channel NAND serial group is used to receive these fourth input signals, and each second P-channel NAND serial group is also used to generate a fourth current; Multiple third sensing amplifier circuits and multiple fourth sensing amplifier circuits are coupled to the second N-channel NAND serial groups of the second N-channel NAND serial group, and the fourth sensing amplifier circuits are coupled to the second P-channel NAND serial groups of the second P-channel NAND serial group. Each of the third sensing amplifier circuits and the fourth sensing amplifier circuits has a threshold current value. as well as Multiple second AND logic gates, each of which is coupled to the corresponding third sensing amplifier circuit and the corresponding fourth sensing amplifier circuit; Multiple third AND logic gates, each of which is coupled to the corresponding first AND logic gate and the corresponding second AND logic gate; Among these, one of these second AND logic gates is a selected second AND logic gate. When the currents of the third current and the fourth current corresponding to the selected second AND logic gate are both greater than or equal to the threshold current value, the selected second AND logic gate outputs the first logic value; and One of these third AND logic gates is a selected third AND logic gate. When the first AND logic gate and the second AND logic gate corresponding to the selected third AND logic gate both output the first logic value, the selected third AND logic gate outputs the first logic value.

17. The analog content addressable memory device of claim 16, wherein one end of each of the second N-channel NAND serial segments of the second N-channel NAND serial group is used to receive a third bit line signal, the other end of each of the second N-channel NAND serial segments of the second N-channel NAND serial group is coupled to the corresponding third sense amplifier circuit, one end of each of the second P-channel NAND serial segments of the second P-channel NAND serial group is used to receive a fourth bit line signal, and each of the second P-channel NAND serial segments of the second P-channel NAND serial group... The other end of the ND string is coupled to the corresponding fourth sensing amplifier circuit. Each of the second N-channel NAND string groups includes a plurality of second N-type transistors, and each of the second P-channel NAND string groups includes a plurality of second P-type transistors. The gate of each of the second N-type transistors in each of the second N-channel NAND string groups is used to receive the corresponding third input signal, and the gate of each of the second P-type transistors in each of the second P-channel NAND string groups is used to receive the corresponding fourth input signal.

18. The analog content addressable memory device of claim 14, wherein the analog content addressable memory device is a flash memory, which is a charge storage memory, a charge trapping memory, a discrete gate memory, or a ferroelectric field-effect transistor memory.

19. The analog content addressable memory device of claim 14, wherein the first N-channel NAND serial group and the first P-channel NAND serial group are a 2D flash memory structure or a 3D flash memory structure.

20. The analog content addressable memory device of claim 14, wherein the analog content addressable memory device is an ultra-steep flash memory, which is a thyristor random access memory, a gate-controlled thyristor, a tunneling field-effect transistor, or a negative capacitance field-effect transistor.

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