Serial interface with shadow register, and associated systems, devices and methods

Abstract

Serial interfaces having shadow registers, and associated systems, devices, and methods are described herein. In one embodiment, a serial interface is an IEEE 1500 interface for an interface die of a high bandwidth memory (HBM) device, for example. The IEEE 1500 interface includes (a) a master package data register (WDR) configured to store first information received in a first package serial input (WSI) signal, (b) a shadow WDR configured to store second information received in a second WSI signal, and (c) a multiplexer. The multiplexer is configured to (i) receive the first information from the master WDR, (ii) receive the second information from the shadow WDR, and (iii) output the first information or the second information based at least in part on a control signal input to the multiplexer.

Description

Technical Field

[0001] This disclosure relates to serial interfaces having one or more shadow registers, and associated systems, apparatus, and methods. For example, several embodiments of this disclosure are directed to serial test interfaces for high-bandwidth memory (HBM) devices, which include at least one shadow register in addition to a main register for storing information (e.g., serial commands, address bits, and / or datasets). Background Technology

[0002] A semiconductor device (e.g., a processor, a memory device, a memory system, or a combination thereof) may include one or more semiconductor circuits configured to store and / or process information. For example, a semiconductor device may include a memory device, such as a volatile memory device, a non-volatile memory device, or a combination thereof. Memory devices such as dynamic random access memory (DRAM) and / or high-bandwidth memory (HBM) can utilize electrical energy to store and access data.

[0003] With technological advancements in other fields and the increasing applications of semiconductor devices, the market is constantly seeking faster, more efficient, and smaller devices. To meet market demands, semiconductor devices are continuously being improved. Generally, improvements can include increasing circuit density, increasing operating speed or otherwise reducing operating latency, increasing reliability, improving data retention, reducing power consumption, or reducing manufacturing costs, as well as other metrics. Summary of the Invention

[0004] According to one aspect of this application, an IEEE 1500 interface is provided. The IEEE 1500 interface includes: a master encapsulated data register (WDR) configured to store first information received in a first encapsulated serial input (WSI) signal; a shadow WDR configured to store second information received in a second WSI signal; and a multiplexer configured to (a) receive the first information from the master WDR, (b) receive the second information from the shadow WDR, and (c) output either the first information or the second information based at least in part on a control signal input to the multiplexer.

[0005] According to another aspect of this application, a method is provided. The method includes: loading first information into a first register of a serial interface, wherein the first register has a first output communicating with a first input of a multiplexer of the serial interface; loading second information into a second register of the serial interface, wherein the second register is a copy of the first register and wherein the second register has a second output communicating with a second input of the multiplexer; outputting the first information to a mode latch via the output of the multiplexer when a control signal input to the multiplexer is in a first state; and outputting the second information to the mode latch via the output of the multiplexer when the control signal is in a second state different from the first state.

[0006] According to another aspect of this application, a high-bandwidth memory (HBM) device is provided. The HBM device includes a memory device comprising one or more core dies, a mode latch, and an interface die having a serial interface, wherein the serial interface includes: a master register configured to store first information received in a first input signal; a shadow register configured to store second information received in a second input signal; and a multiplexer configured to (a) receive the first information from the master register, (b) receive the second information from the shadow register, and (c) output either the first information or the second information to the mode latch, at least in part, based on control signals input to the multiplexer. Attached Figure Description

[0007] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for illustration and understanding only.

[0008] Figure 1A-1E This is a partial schematic block diagram of an instance memory system configured according to various embodiments of the present invention.

[0009] Figure 2 This is a partial schematic block diagram of a memory device configured according to various embodiments of the technology.

[0010] Figure 3 This is a partial schematic block diagram of a serial test interface configured according to various embodiments of the present invention.

[0011] Figure 4 This is an operation according to various embodiments of the technology of the present invention. Figure 3 The flowchart shows a portion of the methods in the serial test interface.

[0012] Figure 5This is a schematic diagram of a system including a memory device according to an embodiment of the present invention. Detailed Implementation

[0013] As discussed in more detail below, the techniques disclosed herein relate to serial interfaces having one or more shadow registers, and associated systems, apparatus, and methods. For example, several embodiments of this disclosure pertain to a serial test interface for an HBM device that includes at least one shadow register in addition to a main register for storing information (e.g., serial commands, address bits, and / or datasets). However, those skilled in the art will understand that the techniques may have additional embodiments, and that the techniques may be described without further reference. Figure 1A-5 The following are some details of the described embodiments in practice.

[0014] In the embodiments described below, the serial interface is primarily described in the context of an HBM device incorporating a serial test interface (e.g., an IEEE 1500 or P1500 interface) with a WDR (Wrapped Data Register) for loading information (e.g., test mode address bits and / or test mode data) into the mode latch of the HBM device's DRAM memory (e.g., in response to vendor-specific instructions or commands). However, the serial interface of the present invention may include interfaces other than test or P1500 interfaces. Alternatively, the serial interface of the present invention may be incorporated into other types of devices, including HBM or other memory devices incorporating SRAM, NAND, phase-change memory, ferroelectric and / or non-NAND-based (e.g., NOR-based), partially NAND-based, or volatile memory media. Furthermore, the test interface of the present invention may include registers other than the WDR, which may be loaded with information and / or operate according to any of the various methods described herein. Additionally, the serial test interface of the present invention may respond to instructions or command operations other than vendor-specific commands.

[0015] A. Overview

[0016] Many memory devices include internal test modes for testing, diagnosing, and / or debugging the memory device. These internal test modes are available to the host device of the memory system (e.g., a controller or processor) and / or another device external to the memory device (e.g., test circuitry, probes, upstream controllers, or processors). For example, in an HBM memory system, the memory device may be packaged together with the host device (e.g., a controller or processor) in a system-in-package (SiP) configuration on a support structure (e.g., a package substrate). Continuing this example, the host device may instruct the memory device to (a) transition to one or more internal test modes, and / or (b) perform one or more test operations while the memory device is in said one or more test modes. In this example, the host device and / or memory device may use various test interfaces, such as the IEEE 1500 interface (also referred to herein as the P1500 interface) or another test interface contained on the interface die of the memory device, to (a) receive signals from the host device, (b) switch the HBM device to test mode, (c) facilitate the execution of test operations corresponding to the test mode, and / or (d) transmit (e.g., the resulting) signals to the host device.

[0017] Alternatively, another device external to the memory device and different from the host device (e.g., test circuitry, probes, upstream controllers, or processors) may instruct the memory device to (a) switch to various test modes within the memory device, and / or (b) perform various test operations while in various test modes. Some of these test modes may be reserved, limited to authorized users, and / or vendor-specific. In many memory devices, external devices are limited to accessing various test modes only via the memory device's P1500 interface.

[0018] The P1500 interface is a serial interface on the die that typically houses the HBM device. The P1500 interface typically includes P1500 circuitry for translating commands and / or data received from and / or transmitted to external devices. The P1500 circuitry includes multiple registers for (a) transitioning the HBM device to test mode and (b) facilitating the execution of various test operations. These registers typically include a Wrap Instruction Register (WIR), which enables wrap operations, establishes test mode or functional operation for the HBM device, and / or generates control signals for selecting and operating other data registers. The registers typically also include (a) a Wrap Bypass Register (WBY) that provides bypass paths for the WSI and WSO signals used for scanning inputs and scanning outputs of wrapped data and instructions, (b) a Wrap Boundary Register (WBR) that applies test data stimuli and captures pattern responses, and (c) a Wrap Data Register (WDR) that is often used as a (e.g., user-specific) shift register to store and output information (e.g., test mode address bits and / or test mode data) corresponding to various (e.g., vendor-specific) instructions received at the WIR.

[0019] When a vendor-specific instruction is provided to the WIR of the P1500 interface, the corresponding information can be loaded into the WDR. Specifically, a single bit of the corresponding information can be loaded into the WDR every 20 ns according to the minimum clock rate specification (referred to as tCKTP). Therefore, for 15 bits of information, it takes approximately 300 ns to load all the corresponding information into the WDR. This information is then output to one or more mode latches to, for example, transition the HBM device to the corresponding test mode and / or perform the corresponding test operation. Then, another 300 ns is needed to load new information into the WDR. This new information may correspond to transitioning the HBM device to another test or operating mode, or it may correspond to transitioning the HBM device out of a test or operating mode (also referred to as "clearing" the mode corresponding to the previous information output to the mode latch). In other words, using the P1500 interface, it takes approximately 300 ns to load information into the WDR and change the information loaded into the mode latch of the HBM device.

[0020] Certain vendor-specific test, diagnostic, and / or debugging activities for HBM devices require test mode sequences that are faster than those currently available from the WDR according to the 20ns minimum clock rate specification. For example, as discussed above, the WDR's current capability includes loading 15 bits of information approximately every 300ns. However, test operations involving timing the TSV capacitor test structure for HBM devices and / or dual-state switching of signals for the peripheral die-break circuitry system of HBM devices require test mode changes within approximately 30ns, which is roughly ten times faster than the WDR's current capability.

[0021] To address these issues, the present invention addresses a P1500 interface comprising a P1500 circuit with multiple WDRs. More specifically, in some embodiments of the present invention, the P1500 circuit includes a master WDR and one or more duplicate or shadow WDRs. Each WDR may be loaded with (e.g., different) information and may be configured to provide the corresponding information to a multiplexer of the P1500 circuit. The P1500 circuit may further include a counter for controlling the output of the multiplexer. In some embodiments, the value stored by the counter may be updated approximately every 20 ns, meaning the output of the multiplexer may be updated approximately every 20 ns. Subsequently, once a WDR has been loaded, a mode latch coupled to the output of the multiplexer may receive new information from the WDR approximately every 20 ns. Thus, the present invention provides a P1500 test interface that facilitates various test, diagnostic, and / or debugging activities of HBMs requiring fast test pattern sequences.

[0022] B. The selection of a memory with a serial interface having a copy register, and associated systems, devices, and methods. Specific Implementation Examples

[0023] Figure 1A-1E This is a partial schematic top view of devices 100a-100e (e.g., memory systems) configured according to various embodiments of the present invention. In some embodiments, devices 100a-100d are SiP devices, each SiP device including a processor 110 (e.g., a central processing unit (CPU), graphics processing unit (GPU), etc.) and one or more memory devices 102 (e.g., HBM) mounted on a support structure 103 (e.g., a package substrate, an internal component, etc.). Figure 1A A first SiP device 100a is shown, comprising a memory device 102a and a processor 110a mounted on a structure 103a. Figure 1B A second SiP device 100b is shown, comprising two memory devices 102b1 and 102b2 mounted on structure 103b and a processor 110b. Figure 1C A third SiP device 100c is shown, comprising four memory devices 102c1-102c4 mounted on structure 103c and a processor 110c. Figure 1D A fourth SiP device 100d is shown, comprising six memory devices 102d1-102d6 mounted on structure 103d and a processor 110d. Device 100 configured according to other embodiments of the invention may include more than one processor 110 and / or... Figure 1A-1D The image shows different (e.g., larger or smaller) numbers of memory devices 102.

[0024] Using SiP device 100a as an illustrative example of the device 100 of the present invention, Figure 1E Show along Figure 1A The diagram shows a partial schematic cross-sectional side view of the SiP device 100a taken from line 1E-1E. As shown, the SiP device 100a includes a memory device 102a and a processor 110a, which are packaged together on a package substrate 114 and / or an insert 112. The package substrate 114 and / or the insert 112 may be... Figure 1A The supporting structure 103a. The processor 110 can act as the host device of the SiP device 100a.

[0025] In some embodiments, memory device 102a may be an HBM device comprising an interface (or logic) die 104 and one or more memory core dies 106 stacked on the interface die 104. Memory device 102a may include one or more through-silicon vias (TSVs) 108, which may be used to couple the interface die 104 and the core dies 106.

[0026] Insert 112 provides electrical connectivity between processor 110a, memory device 102a, and / or package substrate 114. For example, processor 110a and / or memory device 102a may be coupled to insert 112 via several internal connectors (e.g., microbumps 111). Insert 112 may include channels 105 (e.g., interface or connection loops) that electrically couple processor 110a and memory device 102a via corresponding microbumps 111. Although Figure 1E The diagram shows only three channels 105, but other embodiments of the device 100 of the present invention may include more than three channels 105. Figure 1E The diagram shows more or fewer channels 105. Insert 112 may be coupled to package substrate 114 using one or more additional connections (e.g., intermediate bump 113, such as C4 bump).

[0027] The package substrate 114 provides an external interface for the SiP device 100a. For example, the package substrate 114 may include external bumps 115, some of which may be coupled (using, for example, through-silicon vias (TSVs)) to the processor 110a, memory device 102a, or both. The package substrate 114 may further include a direct access (DA) connector 116 (e.g., bumps, TSVs, etc.) that electrically couples a device external to the SiP device 100a to the interface die 104 of the memory device 102a via the package substrate 114 and the insert 112. For example, the DA connector 116 may include one or more of the external bumps 115, one or more TSVs extending through the package substrate 114, one or more of the intermediate bumps 113, one or more TSVs extending through the insert 112, and / or one or more of the microbumps 111.

[0028] In some embodiments, the DA connectors 116 (e.g., one or more of the external bumps 115) may be woven into a probe pad (e.g., a set of test connectors). An external device, such as a tester, may be coupled to the probe pad for direct communication with the memory device 102a. In other words, the external device may use the DA connectors 116 to send signals to and / or receive signals from the memory device 102a without the signals being transmitted to or via the processor 110a. The tester may be used to preload one or more test patterns into a lookup table of the interface die 104. The tester may then provide one or more test instructions along the DA connectors 116. Subsequently, the interface die 104 may perform one or more tests on the core die 106, at least in part, based on the test instructions and the preloaded test patterns, and may generate result information. After the tests are performed, the tester may read the result information via the DA connectors 116.

[0029] The test patterns and instructions may correspond to one or more tests performed on the memory device 102a after it has been packaged into the SiP device 100a. The tests may involve loading data into one or more memory cells of the memory device 102a as a write operation, retrieving stored information from memory cells of the memory device 102a as a read operation, and / or comparing the written data with the read data. Tests may be performed using a built-in self-test (BIST) circuit or another circuit of the memory device 102a. Tests may be performed using long test patterns with random characteristics, which may require more storage space than is feasible in a BIST or other circuitry. These tests can be performed by sending the test patterns and instructions directly via the DA connector 116.

[0030] Figure 2 The memory device 202 is configured according to embodiments of the technology (e.g., Figure 1E This is a partial schematic block diagram of a memory device 102a or a portion thereof. The memory device 202 may include an interface die 204 and one or more core dies 206. For clarity, Figure 2 Only a single core die 206 is shown in this embodiment. However, it should be understood that in other embodiments, multiple core dies 206 may be coupled to the interface die 204. Furthermore, to emphasize the operation of the test procedure, Figure 2 This only shows some components of the interface die 204 involved in the testing process. However, it should be understood that the interface die 204 may contain, in addition to... Figure 2Other components besides those shown, and these other components may be involved in various operations of the memory device 202. For example, the components are shown as coupled via multiplexers to indicate that signals can be routed along different signaling paths. For clarity, the signals controlling these multiplexers and the logic circuitry of the interface die 204 controlling this routing are shown in [the diagram / illustration]. Figure 2 Not shown in the image.

[0031] As shown, the memory device 202 includes one or more circuits for accessing the core die 206 and / or the memory: three different interface terminals for a native microbump (μBump) 205, a DAμBump 216, and a test interface μBump 220. In some embodiments, the native μBump 205 may be included in Figure 1E In the μBump 111. The native μBump 205 can be accessed via one or more channels (e.g., Figure 1E One or more of the channels 105 are coupled to the host device (e.g., Figure 1E The processor 110a). The test interface μBump 220 may be part of a specific interface protocol, such as the IEEE 1500 interface (also referred to as the P1500 interface). Generally, the test interface μBump 220 may be referred to as P1500μBump 220 and / or referred to by terms such as P1500 operating mode, P1500 circuit, etc. However, it should be understood that other test interface protocols may be used in other embodiments of the present invention.

[0032] In some embodiments, the memory device 202 may include three different operating modes corresponding to different interface terminals for accessing the core die 206. More specifically, the memory device 202 may include a native operating mode, a DA operating mode, and a P1500 operating mode. Each operating mode may contain one or more sub-operating modes, each primarily using a corresponding interface terminal from the interface terminals to transmit information to and from the memory device 202. For example, the native operating mode of the memory device 202 may include an HBM standby mode and / or a native mode, each primarily using a native μBump 205 to communicate with the core die 206. As another example, the DA operating mode may include a DA 1500 mode, a DA direct mode, and / or a DA hybrid mode, each primarily using a DA μBump 216 to communicate with the core die 206. As another example, the P1500 operating mode may include a P1500 standby mode and / or a BIST mode, each primarily using a P1500 μBump 220. However, it should be understood that the memory device 202 may have more or fewer operating modes and / or sub-operating modes than discussed above.

[0033] Referring to the native operating mode of the memory device 202, the memory device 202 may (a) receive a reset signal (e.g., via native μBump 205) to transition the memory device 202 to HBM standby mode, and / or (b) receive (e.g., via native μBump 205) a command to transition the memory device 202 to native mode. Native mode may represent the normal operating mode of the memory device 202, in which memory operations are performed based on signals sent to a host device or another device external to the memory device 202 and received from the host device or said other device. For example, in native mode, interface die 204 may send and receive information via native μBump 205. In these embodiments, the host device may use native μBump 205 to initiate one or more modes or operations of the memory device 202, such as the refresh mode of the memory device. Alternatively or additionally, the host device may access information in one or more core dies 206 by sending and receiving information to and from the memory device 202 using native μBump 205.

[0034] During instance access operations, signals from another device external to the host device or memory device 202 can be received at the local μBump 205. These signals may instruct the memory device 202 to perform an access operation, such as a read or write operation, on one or more memory cells in the core die 206. More specifically, the signals may include a data packet AWORD containing (a) command information instructing the memory device 202 to perform a read or write operation, and (b) address information specifying the memory cells of the core die 206 to be read from or written to as part of a read or write operation, respectively. For example, each of the core dies 206 may include a memory array, each containing memory cells arranged in a memory region (e.g., a memory bank) and / or at the intersection of rows (word lines) and columns (bit lines). The address information contained in the AWORD data packet may specify row addresses, column addresses, bank addresses, core die 206, etc., to identify the memory location for the read or write operation. In some embodiments, the command information of the data packet AWORD may include a clock signal for timing the operation and / or command identifier.

[0035] In response to address information during a read command, one or more core dies 206 can read data from the identified memory cells and provide the data as part of a data packet DWORD to the native μBump 205. In response to address information during a write operation, a data packet DWORD can also be received at the native μBump 205 in addition to the data packet AWORD. Continuing this example, the data packet DWORD may contain information to be written to one or more memory cells in core die 206 specified in the address information contained in the data packet AWORD. Subsequently, the data packets AWORD and DWORD are provided to core die 206, and core die 206 can continue to write the information contained in the data packet DWORD to the memory cells specified by the address information in the data packet AWORD.

[0036] In some embodiments, interface die 204 may include serializer circuitry 233. Serializer circuitry 233 may be electrically located along a path extending between core die 206 and native μBump 205. Serializer circuitry 233 may be configured to facilitate the transfer of information between core die 206 and native μBump 205. For example, memory device 202 may include a smaller number of native μBumps 205 than the number of connections extending between interface die 204 and core die 206. Continuing this example, serializer circuitry 233 may receive information in parallel along a first number of data lines (e.g., from one or more of the core dies 206). Then, serializer circuitry 233 may transmit information serially (e.g., to native μBump 205) along a second number of data lines, fewer than the first number of data lines.

[0037] In addition to the native operating mode of the memory device 202, it may be necessary to place the memory device 202 in, for example, a test mode to determine one or more characteristics of the memory device 202. Therefore, Figure 2The memory device 202 may include one or more test modes, some of which may utilize the P1500μBump 220, and some of which may utilize the DAμBump 216. Referring to the P1500μBump 220, the P1500μBump 220 may be used to send signals to or receive signals from the host device or the other device outside the memory device 202. More specifically, the P1500μBump 220 may be used by the memory device 202 when operating in the P1500 operating mode. For example, the memory device 202 may receive a test mode reset signal (e.g., via the P1500μBump 220) to transition the memory device 202 to the P1500 standby mode. The P1500 standby mode is similar to the HBM standby mode of the native operating mode described above, except that the memory device 202 waits to receive one or more commands via the P1500μBump 220 (instead of via the native μBump 205 and / or via the DAμBump 216).

[0038] Alternatively, the memory device 202 may receive (e.g., via P1500μBump 220) commands to switch the memory device 202 to BIST mode for testing the memory device 202, for example, using a test interface (e.g., P1500 interface). Figure 2 As shown, the test interface includes a P1500μBump 220, a test interface circuit 224, a BIST sequencer circuit 228, a lookup table circuit 230, an input buffer circuit 234, an output buffer circuit 235, and an error capture memory (ECM) circuit 232. For clarity, the following discussion of the BIST mode of the memory device 202 and the test interface involves writing data types to one or more memory cells of the core die 206, reading data types from the one or more memory cells, and comparing the written data types with the read data types. However, it should be understood that this is only one example of a test that can be performed on the memory device 202 using the test interface. Therefore, the test interface may include, for example, other than Figure 2 Other circuit components and / or electrical connections besides those shown are used to perform one or more other tests on the memory device 202.

[0039] The P1500μBump 220 of the test interface is electrically coupled to the BIST sequencer circuit 228 via test interface circuit 224 (e.g., hereinafter referred to as "P1500 circuit 224"). P1500 circuit 224 can interpret signals sent to and received from P1500μBump 220 using the P1500 signaling protocol. For example, P1500 circuit 224 can translate signals received at P1500μBump 220 into signals usable by other circuitry of memory device 202. As another example, P1500 circuit 224 can translate various signals received from other circuitry of memory device 202 into signals usable by the host device or another device external to memory device 202. (The following text is related to...) Figure 3 In more detail, the P1500 circuit 224 may include various registers that facilitate switching the memory device 202 to the desired test mode and / or performing various test operations.

[0040] During BIST mode, memory device 202 can use P1500μBump 220 to send and receive signals to operate BIST sequencer circuitry 228. For example, a host device or another device external to memory device 202 can issue instructions to P1500μBump 220 of memory device 202, commanding memory device 202 to perform tests on one or more of the core die 206. Subsequently, P1500 circuitry 224 can translate the instructions and forward them to BIST sequencer circuitry 228, and BIST sequencer circuitry 228 can generate test sequences (e.g., strings of logic bits) to write, for example, to memory cells of core die 206.

[0041] BIST sequencer circuit 228 may include several registers for storing the addresses of memory cells to be tested and / or other test information (e.g., test sequences). Because storage space in BIST sequencer circuit 228 may be limited, all or a subset of the test sequences and / or memory cell addresses may be generated by BIST sequencer circuit 228 based at least in part on instructions received from P1500 circuit 224. For example, BIST sequencer circuit 228 may perform a test on a memory cell address identified in the instructions received from P1500 circuit 224, then increment the memory cell address value by one, and subsequently perform a test on the memory cell corresponding to the newly generated memory cell address value. In embodiments where memory device 202 includes lookup table circuit 230 (e.g., data topology (DTOPO) circuitry), BIST sequencer circuit 228 may load the test sequence into lookup table circuit 230 to save space in BIST sequencer circuit 228. Each entry in the lookup table circuit 230 can be associated with a pointer value (e.g., an index value), and the BIST sequencer circuit 228 can generate a sequence of pointer values ​​in a manner similar to how the BIST sequence 228 generates memory cell address values.

[0042] When tests on one or more of the core die 206 are included in the process of writing test sequence data to memory cells of the core die 206 while the memory device 202 is operating in BIST mode, the BIST sequencer circuit 228 may provide the address information of the memory cells (e.g., row address, column address, group address, identifier of the core die 206, etc.) and the test sequence (e.g., data or values ​​to be written to the memory cells) to the input buffer circuit 234. Alternatively, the BIST sequencer circuit 228 may (a) provide the address information to the input buffer circuit 234 and (b) provide the index information to the lookup table circuit 230. The lookup table circuit 230 may then provide the test sequence to the input buffer circuit 234 based at least in part on the index information received from the BIST sequencer circuit 228.

[0043] Input buffer circuit 234 may include a register configured to store test sequence values ​​and address information received from BIST sequencer circuit 228. In some embodiments, input buffer circuit 234 may operate as a first-in-first-out (FIFO) circuit. Thus, input buffer circuit 234 may be referred to herein as write-FIFO (WFIFO) circuit 234. After receiving the test sequence and address information, input buffer circuit 234 may output the test sequence value and address information, and memory device 202 may write the test sequence to the memory cell corresponding to the address information.

[0044] When tests on one or more of the core die 206 are included in the reading of test sequence data from memory cells of the core die 206 while the memory device 202 is operating in BIST mode, the BIST sequencer circuit 228 can provide address information (e.g., row, column, group, core die 206 identifier, etc.) of the memory cells from which the test sequence previously stored on the core die 206 is to be read. The test sequence value can then be read from the memory cell corresponding to the address information to the output buffer circuit 235. The output buffer circuit 235 may be substantially similar to the input buffer circuit 234, except that the output buffer circuit 235 is configured to (a) receive information from the core die 206 (instead of being configured to output information to the core die 206) and (b) provide information to other circuitry of the interface die 204 (e.g., ECM circuit 232, P1500 circuit 224, etc.). In some embodiments, the output buffer circuit 235 may operate as a FIFO circuit. Thus, the output buffer circuit 235 can be referred to herein as the read FIFO (RFIFO) circuit 235.

[0045] ECM circuit 232 can be used to generate result information based on a test sequence output from output buffer circuit 235. More specifically, ECM circuit 232 can be configured to receive address information and / or a test sequence provided to or output from input buffer circuit 234 during a write operation of the test. ECM circuit 232 can be further configured to store the address information and the test sequence in one or more registers of ECM circuit 232. When a read operation is subsequently performed, ECM circuit 232 can compare the read test sequence output from output buffer circuit 235 during an earlier write operation with (b) the test sequence written to a memory cell. ECM circuit 232 can further generate result information based on the comparison. The result information may include identification of the memory cell that failed to store test sequence data, identification of the test operation corresponding to the test sequence, and / or other information that can be used to diagnose and / or debug memory device 202. ECM circuit 232 may then provide all or a subset of the result information to P1500 circuit 224, which may then output the result information to another device outside the host device or memory device 202 via P1500μBump 220.

[0046] In some scenarios, it may be necessary to bypass the individual components of the SiP package (e.g., Figure 1EThe processor 110a) is configured to send signals directly to and receive signals directly from the memory device 202. In these scenarios, the DA μBump 216 of the memory device 202 can be used. More specifically, all or a subset of the DA μBump 216 can be organized into a probe pad, and a device (e.g., test circuitry, probe, etc.) can be coupled to the probe pad. Subsequently, external devices can use the DA μBump 216 of the probe pad to send signals directly to or receive signals directly from the memory device 202 while the memory device 202 is operating in DA operation mode (e.g., these signals are not transmitted to and / or to other components via SiP packaging).

[0047] In some embodiments, the memory device 202 can be switched (e.g., from HBM standby mode, from BIST mode, and / or from another operating mode or sub-operating mode of the memory device 202) to one of the sub-operating modes of the DA operating mode by activating a DA enable signal. For example, one of the DA μBump 216 can be used as the DA enable pin. Continuing this example, when the DA enable signal is asserted and received at the DA enable pin, the memory device 202 can switch to a sub-operating mode of the DA operating mode (e.g., DA 1500 mode). Alternatively or additionally, the memory device 202 can switch to the DA operating mode when it receives a different signal (e.g., a signal received at one or more of the P1500μBump 220 that indicates the memory device is switching to the DA operating mode).

[0048] When memory device 202 transitions to DA 1500 mode (DA operation mode), DAμBump 216 can be used to send and receive signals using the P1500 interface protocol. For example, signals sent to or received from memory device 202 in DA 1500 mode can conform to the interface standard of P1500μBump 220 discussed above, except that the signals can be sent and received via DA μBump 216 instead of P1500μBump 220. Therefore, in DA1500 mode, memory device 202 can use various test circuits of the P1500 interface, such as P1500 circuit 224, lookup table circuit 230, and / or ECM circuit 232 discussed above. More specifically, devices external to memory device 202 can send information to and / or receive information from P1500 circuit 224 of the P1500 interface via DA μBump 216. Based on the above discussion of P1500 circuit 224, P1500 circuit 224 can be used to (a) translate signals received at DA μBump 216 into signals usable by other circuits of memory device 202, and / or (b) translate various signals received from other circuits of memory device 202 into signals usable by devices external to memory device 202 (e.g., test circuits, probes, etc.).

[0049] When memory device 202 is in DA 1500 mode, test sequences can be loaded into lookup table circuitry 230 via DAμBump 216. In some embodiments, each test sequence may represent a string of one or more logical bits that can be provided (serially or in parallel) to the core die 206. For example, a test sequence may contain a number of bits that match the number of bits of data typically contained in a data packet DWORD. As a particular example, when memory device 202 is operating in DA 1500 mode, a device external to memory device 202 may provide a bit string to DA μBump 216, which may be routed to P1500 circuitry 224, and P1500 circuitry 224 may translate the bit string and / or directly input the bit string into lookup table circuitry 230 via BIST sequencer circuitry 228 and / or via DA converter circuitry 226 (described in more detail below).

[0050] In some embodiments, memory device 202 may transition (e.g., from DA 1500 mode and / or another mode) to one or more other sub-operation modes of DA operation mode. For example, memory device 202 may transition to DA direct mode. In DA direct mode, memory device 202 may operate in a manner substantially similar to how memory device 202 operates in native mode as described above, except that information is provided to or transmitted from memory device 202 via DA μBump 216 (instead of native μBump 205). For example, in DA direct mode, DA μBump 216 may receive and / or transmit data packets AWORD and / or DWORD in a manner similar to how memory device 202 operates in native mode.

[0051] In some embodiments, memory device 202 may include fewer DAμBumps 216 than native μBump 205. In these embodiments, memory device 202 may use deserializer circuitry 222 to simulate write operations of memory device 202 in native mode. For example, deserializer circuitry 222 may (a) serially receive data packets AWORD and / or DWORD from DA μBump 216, and (b) split the data into a plurality of parallel channels for sending the data to core die 206. The number of parallel channels may be the same as or similar to the number of parallel channels used when memory device 202 operates in native mode. The information contained in data packet DWORD may then be written to memory cells of the core die corresponding to the address information contained in data packet AWORD.

[0052] In these and other embodiments, memory device 202 may transition (e.g., from DA 1500 mode or another mode) to a DA hybrid mode. In some embodiments, the DA hybrid mode can be used to perform tests on one or more memory cells of core die 206 using data packets similar to the AWORD and DWORD packets used when memory device 202 is in native mode and / or DA direct mode. More specifically, when memory device 202 is in DA hybrid mode, memory device 202 may receive commands via DA μBump 216 instructing memory device 202 to perform test operations. The commands may contain data packets similar to those received at DA μBump 216 when memory device 202 is in DA direct mode, such as AWORD and / or DWORD packets. However, when memory device 202 is in DA hybrid mode, the DWORD data packet received at DA μBump 216 may contain pointer information (e.g., as a supplement or replacement for test sequence data). Pointer information can be transmitted to lookup table circuitry 230 (e.g., via DA converter circuitry 226 and / or BIST sequencer circuitry 228), and lookup table circuitry 230 can be used to retrieve a pre-loaded test pattern corresponding to the pointer information. Memory device 202 can then execute a test program based on the pre-loaded test pattern retrieved from lookup table circuitry 230. In some embodiments, memory device 202 may additionally or alternatively utilize various other circuits of interface die 204 when operating in DA mixed mode. For example, when memory device 202 is in DA mixed mode, the test program for memory device 202 may utilize P1500 circuitry 224 and / or ECM circuitry 232.

[0053] Figure 3 The P1500 circuit 324 is configured according to various embodiments of the present invention (e.g., Figure 2 A partial schematic block diagram of a portion of the P1500 circuit 324. As shown, said portion of the P1500 circuit 324 includes a main WDR 351, at least one shadow WDR 352 (individually identified as...) Figure 3The system includes WDRs 352a to 352n, a counter 353, and a multiplexer 354. The master WDR 351 may be a shift register for storing information (e.g., test mode address bits and / or test mode data) received at the WIR (not shown) corresponding to the P1500 circuit 324. For example, the master WDR 351 may receive a WSI signal as input. The WSI signal may contain information to be loaded into the master WDR 351. The master WDR 351 may be further configured to (a) output the loaded information to the input of the multiplexer 354, and / or (b) output a WSO signal to other components (not shown) of the P1500 circuit 224, such as the output pins of the P1500 circuit 224. In some embodiments, the master WDR 351 is a 15-bit register formed by 15 corresponding flip-flops. In other embodiments, the main WDR 351 may have different sizes and / or may be formed by other circuit components that complement or replace the trigger.

[0054] Referring now to shadow WDR 352, one or more of shadow WDRs 352 may be replicas of the main WDR 351. For example, shadow WDR 352 may be a shift register having the same size (e.g., 15 flip-flops) and / or circuitry (e.g., composed of flip-flops) as the main WDR 351. In these and other embodiments, one or more of shadow WDRs 352 may have a different size (e.g., a different number of flip-flops) or a different circuitry than the main WDR 351. Similar to the main WDR 351, shadow WDR 352 may receive a WSI signal containing information to be loaded into shadow WDR 352 (e.g., test mode address bits and / or test mode data). Shadow WDR 352 may then be configured to output the loaded information to the input of multiplexer 354.

[0055] In some embodiments, such as Figure 3 As shown, the P1500 circuit 324 may include multiple shadow WDRs 352. For example, the P1500 circuit 324 may include two or three (or more) shadow WDRs 352. In other embodiments, the P1500 circuit 324 may include a single shadow WDR 352.

[0056] In some embodiments, instructions received at the WIR of the P1500 circuit 324 are used to determine whether the information contained in the WSI signal is loaded into the main WDR 351 or into the shadow WDR 352. In these and other embodiments, each of the shadow WDRs 352 can receive an enable signal (identified as...). Figure 3Enable signals (from Enable_A to Enable_N) can be used to control whether the information contained in the WSI signal is loaded into the corresponding shadow WDR 352. In some embodiments, the enable signal is a vendor-specific signal. In embodiments where the P1500 circuit 324 includes multiple shadow WDRs 352, different enable signals (e.g., different vendor-specific commands) can be used to select which shadow WDRs 352 to load the information contained in the WSI signal into. In other embodiments, the same enable signal can be provided to multiple shadow WDRs 352. In these and other embodiments, the enable signal can be used to select multiple shadow WDRs 352 simultaneously, such that the information contained in the WSI signal is loaded into each of the selected shadow WDRs 352 (e.g., simultaneously).

[0057] like Figure 3 As shown, information loaded into each of the main WDR 351 and shadow WDR 352 is output on a parallel data bus to multiplexer 354. Multiplexer 354 is controlled by counter 353. More precisely, the output of multiplexer 354 is controlled by counter 353. Counter 353 receives (a) an Update signal as a clock signal and (b) an Enable_Counter signal. The Update signal may be an IEEE 1500 package serial port update (UPDATEWR) signal and an IEEE 1500 package serial port clock (WRCK) signal. As discussed in more detail below, the WRCK signal may have a period of approximately 20ns-60ns (e.g., between 20ns and 30ns). In some embodiments, the Enable_Counter signal provided to counter 353 may be a vendor-specific command.

[0058] When counter 353 is not enabled using the Enable_Counter signal, the value stored by counter 353 and output to multiplexer 354 is zero or some other initial value. Thus, multiplexer 354 outputs the information received from master WDR 351 to one or more mode latches 355 (e.g., test mode latches, mode registers, etc.). In other words, when counter 353 is not enabled, P1500 circuit 324 operates as if it does not contain shadow WDR 352, and the information loaded into master WDR 351 is output to mode latches 355 by default.

[0059] On the other hand, when counter 353 is enabled using the Enable_Counter signal, the value stored by counter 353 and output to multiplexer 354 can be incremented by a serial chain update command of the UPDATEWR signal executed at various transitions of the WRCK signal (e.g., each transition). As the value of counter 353 increments, the output of multiplexer 354 changes. For example, multiplexer 354 may initially output the information it receives from master WDR 351 to mode latch 355. Then, as the value of counter 353 increments using the Update signal, multiplexer 354 may output the information it receives from one of the shadow WDRs 352 to mode latch 355 (instead of the information it receives from master WDR 351).

[0060] In some embodiments, this process can continue. For example, the value of counter 353 can be incremented at the next execution of UPDATEWR and the transition of the WRCK signal. In embodiments where the P1500 circuit 324 includes multiple shadow WDRs 352, the multiplexer 354 can output the information it receives from the next shadow WDR 352. On the other hand, in embodiments where the P1500 circuit 324 includes a single shadow WDR 352, the value of counter 353 can be reset and / or wrapped back to zero or the initial state of the counter value, and the multiplexer 354 can again output the information it receives from the master WDR 351.

[0061] In this manner, counter 353 and multiplexer 354 can be used to cyclically load information into one or more of the main WDR 351 and / or shadow WDR 352, such that different information can be output to mode latch 355 whenever the UPDATEWR signal is executed at the transition of the WRCK signal. In embodiments where the transition of the WRCK signal occurs approximately every 20ns-30ns, multiplexer 354 can output different information to mode latch 355 every 20ns-30ns. For most (if not all) test, diagnostic, and / or debugging activities of HBM devices, this is entirely within the Test Mode Loading Specification (tMRD).

[0062] In some embodiments, vendor-specific commands can be used to set limits on the values ​​stored and output by counter 353. For example, in an embodiment where P1500 circuit 324 includes three shadow WDRs 352 but the test pattern sequence only needs to provide three different sets of information to pattern latch 355, vendor-specific commands can be input into P1500 circuit 324 (e.g., in counter 353 and / or in the WIR of P1500 circuit 324) to limit the value of counter 353 in the range of 0-2. Continuing this example, when the value of counter 353 is zero, multiplexer 354 can output the information loaded into main WDR 351. The counter value can then increment (to one) at the next transition of the WRCK signal, and multiplexer 354 can output the information loaded into the first shadow WDR 352. The counter value can increment again (to two) at the next transition of the WRCK signal, and multiplexer 354 can output the information loaded into the second shadow WDR 352. Because the counter value is limited to two by a vendor-specific command, the counter value can be reset or wrapped back to its initial state (e.g., to zero) at the next transition of the WRCK signal instead of incrementing to three. Therefore, the information output by multiplexer 354 is loaded into the main WDR 351 instead of the third shadow WDR 352.

[0063] Figure 4 This illustrates various embodiments of operation according to the technology of the present invention. Figure 3 The flowchart shows method 460 of the P1500 circuit 324. In some embodiments, all or a subset of one or more steps of method 460 may be performed by various components of the device (e.g., memory system, HBM device, etc.), such as Figure 1A-1E Any of the devices 100. For example, all or a subset of one or more steps of method 460 may be performed by a host device, processor, package substrate, memory device, internal plug-in, interface die, core die, and / or one or more various circuits disposed thereon (e.g., P1500 circuitry of a P1500 test interface). In these and other embodiments, all or a subset of one or more steps of method 460 may be performed by a device external to the device (e.g., test circuitry, probes, upstream controllers, or processors, etc.) and / or by the device manufacturer or user. Furthermore, any one or more steps of method 460 may be performed in accordance with the discussion above.

[0064] At box 461, method 460 begins by receiving an instruction to preload first information into a shadow register. The shadow register can be... Figure 3The shadow WDR 352. In some embodiments, the instructions may be vendor-specific commands. In these and other embodiments, the instructions may be received at a test interface, such as at the P1500 circuitry of the P1500 test interface. For example, the instructions may be received at the WIR of the P1500 circuitry. In these and other embodiments, the first information may be a first test mode address bit and / or test mode data, and / or the first information may be included in the WSI signal provided to the shadow register. The first information may correspond to a test mode or another operating mode of the HBM device or memory device. In other embodiments, the first information may include one or more commands and / or datasets.

[0065] At block 462, method 460 continues by preloading first information for the shadow register. Preloading the shadow register may include enabling the shadow register. Enabling the shadow register may include receiving a vendor-specific command and / or selecting the shadow register using a vendor-specific command. The vendor-specific command at block 462 may be the same command as the vendor-specific command received at block 461 or a different command. In some embodiments, enabling the shadow register may include enabling only the shadow register or enabling multiple shadow registers (e.g., simultaneously).

[0066] Preloading the first information into the shadow register may include (a) providing the shadow register with a WSI signal containing the first information, and (b) loading the first information into the shadow register (e.g., one bit at a time and / or according to a minimum clock rate specification known as tCKTP). Continuing with the example in brackets, assuming the minimum clock rate specification is 20 ns, loading 15 bits of the first information into the shadow register would take approximately 300 ns. In some embodiments, loading the first information into the shadow register may include storing the first information in the shadow register at least until the first information is invoked or output from the shadow register, and / or until the first information is cleared from the shadow register (e.g., with new information).

[0067] At box 463, method 460 determines whether additional shadow register preload information is required. For example, method 460 may determine to preload an additional shadow register if (a) there is an additional shadow register that has not yet been preloaded, and / or (b) method 460 receives additional instructions (similar to the instructions received at box 461) for loading information into another shadow register. When method 460 determines to preload another shadow register at box 463, method 460 may return to box 461.

[0068] On the other hand, method 460 may determine not to preload additional shadow registers if: (a) there are no other shadow registers for which information has not yet been preloaded, (b) method 460 does not receive additional instructions (similar to the instructions received at block 461) for loading information for another shadow register, and / or (c) method 460 receives instructions for selecting a test mode or other operating mode. When method 460 determines at block 463 that it will not preload additional shadow registers, method 460 may proceed to block 464.

[0069] At block 464, method 460 continues by receiving instructions for selecting a test mode or other operating mode. The instructions may include commands to perform one or more tests or other operations. In these and other embodiments, the instructions may include commands to switch an HBM device or memory device to a specific test mode or other operating mode. In these and other embodiments, the instructions may include instructions for loading second information corresponding to the test mode or another operating mode into a main register. In some embodiments, the instructions received at block 464 may be vendor-specific commands.

[0070] At block 465, method 460 selects a test mode or another operating mode corresponding to the instruction received at block 464. Selecting a test mode or another operating mode may include retrieving or generating second information (e.g., address bits and / or data) corresponding to the selected test mode or operating mode. In these and other embodiments, selecting a test mode or other operating mode may include providing a WSI signal containing the second information to a main register. In these and other embodiments, the second information may be different from, the same as, or similar to one or more first information and / or other information loaded into the shadow register at block 462.

[0071] At box 466, method 460 continues by loading the main register. The main register can be... Figure 3The main WDR351. Loading the main register may include loading second information corresponding to the test mode or other operating mode selected at box 465. In some embodiments, loading the main register may include selecting the main register (e.g., an instruction received at the WIR of the P1500 circuit). Similar to the shadow register, the second information may be loaded into the main register bit by bit at a time, according to the minimum clock rate specification tCKTP and / or at least in part based on the IEEE 1500 package serial port shift (SHIFTWR) signal. Continuing this example, assuming the minimum clock rate specification is 20 ns, loading 15 bits of the second information into the main register would take approximately 300 ns. In these and other embodiments, loading the second information into the main register may include storing the second information in the main register at least until the second information is invoked or output from the main register, and / or until the second information is cleared from the main register (e.g., with new information).

[0072] At box 467, method 460 continues by executing a selected test mode or other operating mode. For example, method 460 can do so by executing a multiplexer (e.g., Figure 3 The multiplexer 354 outputs information loaded into either the main register or a shadow register to execute a selected test mode or other operating mode. As discussed above, the output of the multiplexer can be controlled by a counter such that the information output from the multiplexer depends at least in part on the value output by the counter. When the value of the counter is zero (or another initial value), a second piece of information loaded into the main register can be output by the multiplexer to one or more mode latches (e.g., ...). Figure 3 (Mode latch 355). Other values ​​output by the counter can cause the multiplexer output to load information (e.g., first information) into one of the shadow registers. In these and other embodiments, method 460 can perform a selected test mode or other operating mode by switching the HBM device and / or memory device to a test mode or other operating mode. In these and other embodiments, method 460 can perform a selected test mode or other operating mode by performing one or more test operations or other operations corresponding to the selected test mode or other operating mode.

[0073] At box 468, method 460 continues by determining whether to update the counter's value. For example, as described above relative to... Figure 3In more detail, the counter value can be updated to change the information from the multiplexer output to the pattern latch. In some embodiments, method 460 may determine not to update the counter value when the counter is not enabled using a vendor-specific signal or another signal (e.g., the Enable_Counter signal). In these and other embodiments, method 460 may determine not to update the counter value when the test pattern sequence does not require updating the pattern latch with new information. When method 460 determines not to update the counter value, method 460 may return to blocks 461 and / or 464. In some embodiments, when method 460 returns to blocks 461 and / or 464, the counter value may be reset.

[0074] On the other hand, method 460 may determine when to update the counter value when the counter is enabled using a vendor-specific signal or another signal (e.g., the Enable_Counter signal). In these and other embodiments, method 460 may determine when to update the counter value when the test pattern sequence needs to update the pattern lock store with new information. When method 460 determines to update the counter value, method 460 may proceed to block 469 to update the counter value.

[0075] At block 469, method 460 continues by updating the value of a counter. Updating the counter value may include incrementing the value or resetting the counter value to zero or another initial state (e.g., by wrapping the counter value back to zero or the initial state). In these and other embodiments, updating the counter value may include updating the counter value according to an Update signal (e.g., the UPDATEWR signal). The UPDATEWR signal may be executed at the transition of the WRCK signal (e.g., causing the UPDATEWR signal to execute every 20ns-30ns, thereby updating the counter value at least every 20ns-30ns when the counter is enabled). After updating the counter value, method 460 may return to block 467 (e.g., to output the first information loaded into the shadow register from the multiplexer to the mode latch).

[0076] Although the steps of method 460 are discussed and explained in a specific order, Figure 4Method 460 is not limited thereto. In other embodiments, the steps of method 460 may be performed in a different order. In these and other embodiments, any one of the steps of method 460 may be performed before, during, and / or after any of the other steps of method 460. For example, steps 464-466 may be performed before or during any one or more of steps 461-463. Furthermore, those skilled in the art will readily recognize that method 460 may be modified while still remaining within these and other embodiments of the present invention. For example, in some embodiments, one or more steps of method 460 may be omitted and / or repeated. As a particular example, steps 461-463, 468, and 469 may be omitted when the shadow register is not loaded with information and / or when the counter is not enabled, so that only section 470 of method 460 is performed.

[0077] For clarity and understanding, consider the following example, where: (a) the P1500 circuit includes a main register and a single shadow register, and (b) the test mode sequence requires (i) loading the first information, (ii) clearing the first information, (iii) loading the first information, and (iii) clearing the first information for the mode latch. In an HBN device lacking a shadow register, each change to the information in the mode latch will take approximately 300 ns (assuming a data length of 15 bits and that a bit can be loaded into the main register every 20 ns). Therefore, it would take approximately 1200 ns to execute the test mode sequence in an HBN device lacking a shadow register.

[0078] In contrast, in the HBN device of this invention, the information used to clear the first information from the mode latch can be preloaded into the shadow register (requiring 300 ns), and the first information can be loaded into the main register (requiring 300 ns). The main register can provide the first information to the multiplexer, and the shadow register can provide the information used to clear the first information to the multiplexer. As discussed above, the output of the multiplexer can be controlled by the value output from the counter. Because the value output from the counter is zero or some other initial value, the multiplexer can output the first information to the mode latch after executing the first instance of the UPDATEWR signal. After approximately 20 ns, the value of the counter can increment after executing the second instance of the UPDATEWR signal. Subsequently, the next input of the multiplexer is output from the multiplexer. Here, the next input of the multiplexer is the information preloaded into the shadow register and used to clear the first information from the mode latch. After another 20 ns, the counter value is incremented (or wrapped back to its initial state) after the third instance of the UPDATEWR signal, thereby causing the multiplexer to output the first information received from the master register to the mode latch. After another 20 ns, the counter value is incremented again after the fourth instance of the UPDATEWR signal, thereby causing the multiplexer to output (to the mode latch) the information received from the shadow register and cleared from the mode latch. Therefore, after factoring the amount of time required to load the master register and / or shadow register, the same test mode sequence that takes approximately 1200 ns to complete with an HBM device lacking a shadow register requires approximately 660 ns to complete with an HBM device configured according to various embodiments of the present invention. Furthermore, the mode latch in an HBM device lacking a shadow register may only be updated with new information approximately every 300 ns. In contrast, the HBN device of the present invention helps to update the mode latch with new information approximately every 20-30 ns once information is loaded for the shadow register.

[0079] In the case of an HBM device incorporating multiple shadow registers, the present invention facilitates the rapid execution of test pattern sequences that require loading two or more different sets of information into a pattern latch. Alternatively or concurrently, one or more shadow registers may store and output information currently stored and output by the main register and / or another shadow register. For example, consider the following instance where: (a) a P1500 circuit includes a main register and three shadow registers, and (b) a test pattern sequence requires (i) loading test pattern data, (ii) clearing test pattern data, (iii) loading test pattern data, and (iii) clearing test pattern data for a pattern latch. In this instance, the main register and the second shadow register may be loaded with test pattern data, and the first and third shadow registers may be loaded with data for clearing test pattern data from the pattern latch. As the counter increments from zero to three, the multiplexer output is sequenced through test pattern data (output from the main register); data for clearing test pattern data (output from the first shadow register); test pattern data (output from the second shadow register); and data for clearing test pattern data (output from the third shadow register). Other test pattern sequences and / or other forms of using master registers and shadow registers to store and output information and / or data corresponding to the test pattern sequences are of course possible and within the scope of the present invention.

[0080] Figure 5 This is a schematic diagram of a system including a memory device according to an embodiment of the present invention. (See above reference) Figure 1A-4 Any of the aforementioned memory devices can be incorporated into any of numerous larger and / or more complex systems, a representative example of which is... Figure 5 The system 510 is schematically shown in the diagram. System 510 may include a semiconductor device assembly 511, a power supply 512, a driver 514, a processor 516, and / or other subsystems and components 518. The semiconductor device assembly 511 may include components generally similar to those described in the reference above. Figure 1A-4The described memory device features, and may therefore include various features of preloading information and / or data into one or more shadow registers and subsequently retrieving said information and / or data sequentially (e.g., with information and / or data loaded into the main register). The resulting system 510 can perform any of a wide variety of functions, such as memory storage, data processing, and / or other suitable functions. Accordingly, representative systems 510 may include, but are not limited to, handheld devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, vehicles, electrical appliances, and other products. Components of system 510 may be housed in a single unit or distributed across multiple interconnected units (e.g., via a communication network). Components of system 510 may also include remote devices and any of a wide variety of computer-readable media.

[0081] C. in conclusion

[0082] Based on the foregoing, it should be understood that specific embodiments of the technology have been described herein for illustrative purposes, but well-known structures and functions have not been shown or described in detail so as not to unnecessarily obscure the description of the embodiments of the technology. In the event of any conflict between any material incorporated herein by reference and this disclosure, this disclosure shall prevail. Where the context permits, singular or plural terms may also include plural or singular terms, respectively. Furthermore, unless the word “or” is expressly limited to meaning only a single item exclusive to other items in a list referring to two or more items, the use of “or” in this list shall be understood to include: (a) any single item in the list, (b) all items in the list, or (c) any combination of items in the list. As used herein, the phrase “and / or” in phrases such as “A and / or B” refers to only A, only B, and both A and B. Where the context permits, singular or plural terms may also include plural or singular terms, respectively. Furthermore, the terms “comprising,” “including,” “having,” and “with” are used throughout the text to mean that at least one or more of the described features are included, without excluding any larger number of identical features and / or other features of additional types. Additionally, the terms “connected” and “coupled” are used interchangeably herein and refer to both direct and indirect connection or coupling. For example, where the context permits, “connected” or “coupled” to element B may mean (i) A is directly “connected” or directly “coupled” to B, and / or (ii) A is indirectly “connected” or indirectly “coupled” to B.

[0083] The above detailed description of embodiments of the technology is not intended to be exhaustive or to limit the technology to the precise forms disclosed above. As those skilled in the art will recognize, although specific embodiments and examples of the technology have been described above for illustrative purposes, various equivalent modifications can be made within the scope of the technology. For example, although steps are presented in a given order, alternative embodiments may perform the steps in a different order. As another example, the various components of the technology may be further divided into sub-components, and / or the various components and / or functions of the technology may be combined and / or integrated. Furthermore, although advantages associated with certain embodiments of the technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments necessarily exhibit such advantages to fall within the scope of the technology.

[0084] It should also be noted that other embodiments besides those disclosed herein are also within the scope of this invention. For example, embodiments of this invention may have different configurations, components, and / or programs than those shown or described herein. Furthermore, those skilled in the art will understand that these and other embodiments may not have certain configurations, components, and / or programs shown or described herein without departing from the invention. Accordingly, this disclosure and associated techniques may cover other embodiments not explicitly shown or described herein.

Claims

1. An IEEE 1500 interface, comprising: The main package data register WDR is configured to store the first information received in the first package serial input WSI signal; A shadow WDR, which is configured to store the second information received in the second WSI signal; A multiplexer configured to (a) receive the first information from the master WDR, (b) receive the second information from the shadow WDR, and (c) output the first information or the second information at least in part based on control signals input to the multiplexer; as well as A counter, configured to output the control signal to the multiplexer based at least in part on a value stored in the counter.

2. The IEEE 1500 interface according to claim 1, wherein: The counter is configured to receive an enable signal having a first state and a second state; When the enable signal is in the first state, the counter is disabled so that it does not update the value stored by the counter; as well as When the enable signal is in the second state, the counter is enabled to update the value stored by the counter.

3. The IEEE 1500 interface according to claim 2, wherein, When the enable signal is in the first state, the multiplexer is configured to output the first information received from the master WDR.

4. The IEEE 1500 interface according to claim 2, wherein: The counter is further configured to receive update signals; The update signal includes the IEEE 1500 packaged serial port update UPDATEWR signal; and When the enable signal is in the second state, the counter is configured to update the value stored by the counter whenever the UPDATEWR signal is asserted based on the transition of the IEEE 1500 package serial part clock WRCK signal.

5. The IEEE 1500 interface according to claim 4, wherein: The value stored by the counter is limited; and When the value reaches the limit, the next update of the counter to the value resets the value or causes the value to wrap around to the initial state corresponding to the state of the value when the enable signal is in the first state.

6. The IEEE 1500 interface according to claim 1, wherein the shadow WDR is a copy of the master WDR, such that the shadow WDR has the same register size as the master WDR.

7. The IEEE 1500 interface according to claim 1, wherein: The shadow WDR is configured to receive an enable signal; When the enable signal is in the first state, the shadow WDR is disabled so that it does not load the second information contained in the second WSI signal; and When the enable signal is in the second state, the shadow WDR is enabled to load the second information contained in the second WSI signal.

8. The IEEE 1500 interface according to claim 1, wherein: The shadow WDR is the first shadow WDR; The IEEE 1500 interface further includes a second shadow WDR configured to store third information received in the third WSI signal; and The multiplexer is further configured to (i) receive the third information from the second shadow WDR, and (ii) output the first information, the second information, or the third information at least in part based on the control signal input to the multiplexer.

9. The IEEE 1500 interface according to claim 8, wherein: The first shadow WDR is configured to receive a first enable signal, which, when asserted, enables the first shadow WDR to load the second information received in the second WSI signal; The second shadow WDR is configured to receive a second enable signal, which, when asserted, enables the second shadow WDR to load the third information received in the third WSI signal; and The first enable signal is different from the second enable signal.

10. The IEEE 1500 interface according to claim 1, in addition to the main WDR and the shadow WDR, further includes an encapsulation boundary register WBR and an encapsulation bypass register WBY.

11. A method for operating a serial interface, the method comprising: Load first information into a first register of the serial interface, wherein the first register has a first output that communicates with a first input of a multiplexer of the serial interface; The second information is loaded into the second register of the serial interface, wherein the second register is a copy of the first register, and wherein the second register has a second output that communicates with the second input of the multiplexer; When the control signal input to the multiplexer is in the first state, the first information is output to the mode latch via the output of the multiplexer; as well as When the control signal is in a second state different from the first state, the second information is output to the mode latch via the output of the multiplexer.

12. The method of claim 11, wherein an enable signal comprising asserting the second register is loaded for the second register, such that the second register is enabled to load the second information.

13. The method of claim 11, wherein loading the first register includes loading the first information into the first register in response to receiving an instruction for selecting an operating mode of a memory device including the serial interface.

14. The method of claim 11, further comprising updating the value of the counter such that the control signal transitions from the first state to the second state.

15. The method of claim 14, wherein updating the value of the counter comprises (a) asserting an enable signal to enable the counter to update the value, and (b) asserting an IEEE 1500 package serial port update UPDATEWR signal based on a transition of the IEEE 1500 package serial port clock WRCK signal.

16. The method of claim 15, further comprising (a) de-asserting the enable signal to disable the counter so that it does not update the value, and (b) resetting the value in response to de-asserting the enable signal.

17. The method of claim 14, further comprising holding the control signal in the first state until (a) the counter is enabled and (b) the value of the counter is updated.

18. The method of claim 11, further comprising: Load third information into a third register of the serial interface, wherein the third register is another copy of the first register, wherein the third information is different from the first information or the second information, and wherein the third register has a third output that communicates with a third input of the multiplexer; as well as When the control signal is in a third state, which is different from the first state and the second state, the third information is output to the mode latch via the output of the multiplexer.

19. The method of claim 18, wherein: Loading the second information into the second register includes enabling the second register using a first enable signal; and Loading the third information into the third register includes enabling the third register using a second enable signal that is different from the first enable signal.

20. A high-bandwidth memory (HBM) device comprising a memory device including one or more core dies, mode latches, and an interface die having a serial interface, wherein the serial interface includes: The main register is configured to store the first information received from the first input signal; The shadow register is configured to store the second information received in the second input signal; A multiplexer configured to (a) receive the first information from the main register, (b) receive the second information from the shadow register, and (c) output the first information or the second information to the mode latch at least in part based on control signals input to the multiplexer; as well as A counter, configured to output the control signal to the multiplexer based at least in part on a value stored in the counter.

Images