Semiconductor Structure and Method for Forming the Same

Abstract

An embodiment of the present application provides a semiconductor structure and a method for forming the same. Among them, the method for forming the semiconductor structure includes: providing a substrate; wherein the substrate includes a substrate, a first semiconductor layer, and a second semiconductor layer formed in sequence; forming first isolation structures and second isolation structures distributed at intervals in the substrate; wherein between two adjacent first isolation structures, a source layer formed in the second semiconductor layer and a drain layer formed in the substrate are included, the extending direction of the first isolation structure is a first direction, and the extending direction of the second isolation structure is a second direction; forming a channel layer in the first semiconductor layer, and the channel layer has through holes with an extending direction the same as the first direction between two adjacent first isolation structures; forming a gate structure in the through holes.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and relates to, but is not limited to, a semiconductor structure and a method for forming the same. Background Art

[0002] The Gate All Around Field Effect Transistor (GAAFET) is considered to be the best candidate to replace the traditional field effect transistor because it has better gate control characteristics, can achieve better switching characteristics and more effectively suppress the short-channel effect. However, the process for preparing the GAAFET channel is very complex, and process random fluctuations are very obvious in small sizes. The impact of process fluctuations on the electrical performance of devices and circuits needs to be paid special attention. Summary of the Invention

[0003] This application provides a semiconductor structure and a method for forming the same.

[0004] In a first aspect, an embodiment of this application provides a method for forming a semiconductor structure, including:

[0005] Providing a substrate; wherein, the substrate includes a substrate, a first semiconductor layer and a second semiconductor layer formed in sequence;

[0006] Forming first isolation structures and second isolation structures distributed at intervals in the substrate; wherein, between two adjacent first isolation structures, a source layer formed in the second semiconductor layer and a drain layer formed in the substrate are included, the extending direction of the first isolation structure is a first direction, the extending direction of the second isolation structure is a second direction, the first isolation structure penetrates through the first semiconductor layer and the second semiconductor layer and partially extends into the substrate, and the second isolation structure is located in the substrate;

[0007] Forming a channel layer in the first semiconductor layer, and a through hole having an extending direction the same as the first direction is formed between the channel layer and two adjacent first isolation structures;

[0008] Forming a gate structure in the through hole.

[0009] In a second aspect, an embodiment of this application further provides a semiconductor structure, including:

[0010] A substrate; wherein, the substrate includes a substrate, a first semiconductor layer and a second semiconductor layer formed in sequence;

[0011] First and second isolation structures distributed at intervals in the substrate; wherein, the extending direction of the first isolation structure is a first direction, the extending direction of the second isolation structure is a second direction, the first isolation structure penetrates through the first semiconductor layer and the second semiconductor layer, and partially extends into the substrate, and the second isolation structure is located in the substrate;

[0012] A source layer located in the second semiconductor layer;

[0013] A drain layer located in the substrate;

[0014] A channel layer located in the first semiconductor layer;

[0015] A gate structure having an extending direction the same as the first direction is located between the channel layer and two adjacent first isolation structures.

[0016] The semiconductor structure and its forming method provided by the embodiments of the present application. Among them, the forming method of the semiconductor structure includes: providing a substrate; wherein, the substrate includes a substrate, a first semiconductor layer and a second semiconductor layer formed in sequence; forming first and second isolation structures distributed at intervals in the substrate; wherein, between two adjacent first isolation structures, a source layer formed in the second semiconductor layer and a drain layer formed in the substrate are included, the extending direction of the first isolation structure is a first direction, the extending direction of the second isolation structure is a second direction, the first isolation structure penetrates through the first semiconductor layer and the second semiconductor layer, and partially extends into the substrate, and the second isolation structure is located in the substrate; forming a channel layer in the first semiconductor layer, and a through hole having an extending direction the same as the first direction is located between the channel layer and two adjacent first isolation structures; forming a gate structure in the through hole. In the embodiments of the present application, gate self-alignment is achieved and a fully surrounding gate structure is formed, improving the gate control ability and switching speed. Description of the Drawings

[0017] In the drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The drawings generally illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0018] Figure 1A It is a schematic flow chart of a forming method of the semiconductor structure provided by the embodiments of the present application;

[0019] Figures 1B to 1E It is a schematic structural diagram of the forming process of the semiconductor structure provided by the embodiments of the present application;

[0020] Figure 2A Another flowchart of the method for forming a semiconductor structure provided by an embodiment of the present application;

[0021] Figures 2B to 2K Another structural schematic diagram of the process of forming a semiconductor structure provided by an embodiment of the present application;

[0022] Figure 3A A schematic diagram of a semiconductor structure provided by an embodiment of the present application;

[0023] Figure 3B is Figure 3A A front view of the structure shown;

[0024] Figure 4A Another flowchart of the method for forming a semiconductor structure provided by an embodiment of the present application;

[0025] Figures 4B to 4E Another structural schematic diagram of the process of forming a semiconductor structure provided by an embodiment of the present application. Detailed implementation manners

[0026] Hereinafter, the exemplary embodiments disclosed in the present application will be described in more detail with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present application can be more thoroughly understood and the scope of the present application disclosed can be fully communicated to those skilled in the art.

[0027] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusing the present application, some technical features known to the art are not described; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0028] An embodiment of the present application provides a method for forming a semiconductor structure, as Figure 1A shown, the method includes the following steps:

[0029] Step S101, providing a substrate; wherein, the substrate includes a substrate, a first semiconductor layer, and a second semiconductor layer formed in sequence;

[0030] Wherein, the substrate can be a silicon substrate, a silicon germanium substrate, or a silicon on insulator (SOI) substrate, or a silicon nitride substrate or other suitable substrates.

[0031] The material of the first semiconductor layer can be silicon (Si), germanium (Ge), or silicon germanium (SiGe), silicon carbide (SiC); it can also be silicon on insulator (SOI), germanium on insulator (GOI); or it can also be other materials, such as group III-V compounds like gallium arsenide. In terms of complementary metal oxide semiconductor (CMOS) technology, the cost of SiGe technology is comparable to that of silicon technology, but in terms of heterojunction technology, the cost of SiGe technology is even lower than that of gallium arsenide technology.

[0032] The second semiconductor layer can be a silicon layer or can include other semiconductor elements, such as: germanium (Ge), or can include semiconductor compounds, such as: silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InP) or indium antimonide (InSb), or can include other semiconductor alloys, such as: silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or a combination thereof.

[0033] In some embodiments, the first semiconductor layer and the second semiconductor layer may be formed by epitaxy. The epitaxial growth methods may include Molecular Beam Epitaxy (MBE), the combination of Ultrahigh Vacuum Chemical Vapor Deposition (UHV / CVD) and ultra-low pressure chemical vapor deposition, Ultra Violet Chemical Vapor Deposition (UV / CVD), Atmospheric Pressure Chemical Vapor Deposition (APCVD), Rapid Thermal Chemical Vapor Deposition (RT-CVD), etc. The advantages of these technologies are that they can grow epitaxial layers at low temperatures (300 to 700 degrees Celsius). This ability is not only very important for the formation of doped surfaces, but also enables materials with lattice mismatches to be combined in a coherent manner. In the SiGe alloy, in the quantum well composed of silicon (Si) and SiGe, carriers have a higher mobility, and the electron mobility is almost twice that of pure Si. More importantly, when Si and Ge are alloyed, the independent alloy has a diamond crystal lattice. The lattice constant of this alloy is nearly linearly dependent between the Si and Ge values, with a deviation of approximately 4.17% at room temperature. When such a SiGe layer is epitaxially grown on a substrate with the same lattice constant, such as a Si substrate, the grown layer attempts to modify its in-plane lattice constant in order to form a coherent crystal plane with the substrate layer.

[0034] Step S102: Form first isolation structures and second isolation structures distributed at intervals in the substrate; wherein, between two adjacent first isolation structures, there are a source layer formed in the second semiconductor layer and a drain layer formed in the substrate. The extending direction of the first isolation structure is the first direction, and the extending direction of the second isolation structure is the second direction. The first isolation structure penetrates through the first semiconductor layer and the second semiconductor layer and partially extends into the substrate, and the second isolation structure is located in the substrate.

[0035] Here, in the directions of the top surface and the bottom surface of the substrate (i.e., the plane where the substrate is located), two directions intersecting each other (such as perpendicular to each other) are the first direction and the second direction. For example, the first direction is defined as the X-axis direction, and the second direction is defined as the Y-axis direction. The drain layer and the source layer have opposite conduction types.

[0036] Step S103: Form a channel layer in the first semiconductor layer. There are through holes with an extending direction the same as the first direction between the channel layer and two adjacent first isolation structures.

[0037] Here, the channel layer is located between the drain layer and the source layer.

[0038] Step S104: Form a gate structure in the through hole.

[0039] Here, the first isolation structure is used to isolate the gate structure. The gate structure may include a gate oxide layer and a conductive material on the surface of the gate oxide layer. Among them, the gate oxide layer can be used as a dielectric layer to achieve electrical isolation between the gate structure and the substrate. The gate oxide layer can be formed by high-temperature oxidation, and the temperature of the high-temperature oxidation process can be 900 degrees Celsius to 1200 degrees Celsius. The material of the gate oxide layer can be silicon oxide, silicon nitride, silicon oxynitride, oxide / nitride / oxide (ONO), or a high-k material with a dielectric constant higher than that of the silicon oxide layer, which can effectively block the boron diffusion from the polysilicon, solve the boron penetration problem, and at the same time, a small amount of nitrogen atoms distributed at the interface between the gate oxide layer and the substrate can also improve the characteristics of this interface, enhance the reliability of the gate oxide layer, and reduce the leakage current. For example, the high-k material can have a dielectric constant of about 10 to 25, and can include, for example, hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO3), tantalum oxide (Ta2O3), and / or titanium oxide (TiO2).

[0040] In the embodiment of the present application, by forming the first isolation structure and the second isolation structure in the substrate, forming a channel layer in the first semiconductor layer, and forming a gate structure in the through hole of the channel layer, gate self-alignment is achieved, and a fully surrounding gate structure is formed, improving the gate control ability and the switching speed.

[0041] For steps S101 to S104, please refer to Figures 1B to 1E .

[0042] As Figure 1B shown, the substrate 100 includes a substrate 101, a first semiconductor layer 102, and a second semiconductor layer 103 formed in sequence.

[0043] Combined with Figure 1B and Figure 1C , spaced-apart first isolation structures 104 and second isolation structures 105 are formed in the substrate (refer to the substrate 100 in Figure 1B ); wherein, between two adjacent first isolation structures 104, a source layer 106 formed in the second semiconductor layer (refer to the second semiconductor layer 103 in Figure 1B ) and a substrate (refer to Figure 1BThe drain layer 107 formed in the substrate 101), the extending direction of the first isolation structure 104 is the X-axis direction, the extending direction of the second isolation structure 105 is the Y-axis direction, the first isolation structure 104 penetrates through the first semiconductor layer (see Figure 1B the first semiconductor layer 102) and the second semiconductor layer 103) in, and partially extends into the substrate 101), the second isolation structure 105 is located in the substrate 101).

[0044] As Figure 1D shown, a channel layer 108 is formed in the first semiconductor layer (see Figure 1B the first semiconductor layer 102) in, there is a via hole 109 with the extending direction the same as the first direction between the channel layer 108 and two adjacent first isolation structures 104).

[0045] As Figure 1E shown, a gate structure 110 is formed in the via hole 109 (see Figure 1D the via hole 109) in).

[0046] Based on Figure 1A a method for forming a semiconductor structure provided, an embodiment of the present application provides a semiconductor structure, as Figure 1E shown, this structure includes:

[0047] A substrate (see Figure 1B the substrate 100) in; wherein, the substrate includes a substrate (see Figure 1B the substrate 101), a first semiconductor layer (see Figure 1B the first semiconductor layer 102) and a second semiconductor layer (see Figure 1B the second semiconductor layer 103) formed in sequence;

[0048] The first isolation structure 104 and the second isolation structure 105 which are spaced apart and distributed in the substrate 100); wherein, the extending direction of the first isolation structure 104 is the first direction, the extending direction of the second isolation structure 105 is the second direction, the first isolation structure 104 penetrates through the first semiconductor layer 102 and the second semiconductor layer 103, and partially extends into the substrate 101), the second isolation structure 105 is located in the substrate 101);

[0049] A source layer 106 located in the second semiconductor layer 103);

[0050] A drain layer 107 located in the substrate 101);

[0051] A channel layer 108 located in the first semiconductor layer 102);

[0052] A gate structure 110 having an extension direction the same as the first direction is provided between the channel layer 108 and two adjacent first isolation structures 104.

[0053] In some embodiments, the substrate, the first semiconductor layer, and the second semiconductor layer are a silicon substrate, a silicon germanium layer, and a silicon layer in sequence. Carriers have a higher mobility in the silicon germanium layer, and the electron mobility is twice that of a pure silicon layer.

[0054] In some embodiments, the gate structure includes: a gate oxide layer and a conductive material located on the surface of the gate oxide layer.

[0055] An embodiment of the present application further provides a method for forming a semiconductor structure, as Figure 2A shown, the method includes the following steps:

[0056] Step S201, provide a substrate; wherein, the substrate includes a substrate, a first semiconductor layer, and a second semiconductor layer formed in sequence;

[0057] Step S202, form an initial first isolation structure and an initial second isolation structure in the substrate; wherein, the extension direction of the initial first isolation structure is the first direction, and the extension direction of the initial second isolation structure is the second direction; the initial first isolation structure and the initial second isolation structure penetrate through the first semiconductor layer and the second semiconductor layer, and partially extend into the substrate, so as to form a source layer in the second semiconductor layer and a drain layer in the substrate;

[0058] Step S203, etch the initial first isolation structure to form a first isolation structure, and etch the initial second isolation structure to form a second isolation structure;

[0059] Step S204, form a channel layer in the first semiconductor layer, and a through hole having an extension direction the same as the first direction is provided between the channel layer and two adjacent first isolation structures;

[0060] Step S205, form a gate structure in the through hole.

[0061] Forming the spaced-apart first isolation structure and second isolation structure in the substrate in the above embodiments can be implemented by steps S201 to S203.

[0062] In some embodiments, step S202 can be implemented by step S221 and step S222. Refer to step S221 Figures 2B to 2C , and refer to step S222 Figures 2D to 2E .

[0063] Step S221, refer to Figure 2B , in the substrate (refer toFigure 1B A second isolation structure trench 105a (along the Y-axis direction) is formed in the substrate 100), see Figure 2C , in the second isolation structure trench (see Figure 2B The initial second isolation structure is formed by filling the first dielectric layer 105b in the second isolation structure trench 105a in );

[0064] Step S222, see Figure 2D , in the substrate (such as Figure 2C shown) after the initial second isolation structure 105c is formed, a first isolation structure trench 104a (along the X-axis direction) is formed, see Figure 2E , in the first isolation structure trench (see Figure 2D The initial first isolation structure 104d is formed by filling the second dielectric layer 104b and the third dielectric layer 104c in the first isolation structure trench 104a in ); wherein, the first isolation structure trench (see Figure 2D The first isolation structure trench 104a in ) and the second isolation structure trench (see Figure 2B The second isolation structure trench 105a in ) penetrate through the first semiconductor layer 102 and the second semiconductor layer 103, and partially extend into the substrate 101.

[0065] Here, the first isolation structure trench and the second isolation structure trench can be formed by using self-aligned shallow trench isolation technology, for example, formed by self-aligned double patterning (SADP) process, or can also be formed by self-aligned quadruple patterning (SAQP) process.

[0066] In implementation, a layer of sacrificial material (Sacrifice Layer), generally a CVD material, can be deposited on the substrate surface first. Then, photolithography and etching are carried out to transfer the pattern on the mask to the sacrificial material layer. The pattern on the sacrificial material is also called "mandrel" or "core". Atomic Layer Deposition (ALD) is used to deposit a relatively uniform-thickness thin film (referred to as "spacer" material) on the surface and sides of the "mandrel". The deposited spacer material is etched away using reactive ion etching process, and this step is called "etch back". Due to the geometric effect of the sidewalls of the "mandrel", the materials deposited on both sides of the pattern will remain, forming the so-called spacers. The sacrificial "mandrel" is removed using a highly selective etching solution, leaving only the spacers on the substrate surface. The period of the spacer pattern is half of the photolithography pattern, achieving a doubling of the spatial pattern density. Finally, plasma etching is used to transfer the spacer pattern to the hard mask on the substrate.

[0067] Here, the material used for the first dielectric layer can be silicon oxide, for example, silicon dioxide, silicon oxynitride, or silicon oxide doped with boron and phosphorus, or other suitable materials. The material used for the second dielectric layer can be the same as or different from the material used for the first dielectric layer. Among them, the first dielectric layer can be formed by thermal oxidation, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Plasma Enhanced Atomic Layer Deposition (PEALD), Low Pressure Chemical Vapor Deposition (LPCVD), or other suitable processes; the second dielectric layer can be formed by the same process as the first dielectric layer or by a different process.

[0068] The material used for the third dielectric layer can be nitrides such as silicon nitride, aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN), and can be formed by processes such as low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition (APCVD), or atomic layer deposition.

[0069] In some embodiments, the material of the first dielectric layer includes silicon oxide, and the material of the second dielectric layer is the same as the material of the first dielectric layer.

[0070] In some embodiments, filling the second dielectric layer and the third dielectric layer in the first isolation structure trench to form the initial first isolation structure in step S222 can be implemented through steps S2221 to S2223.

[0071] Step S2221: Fill the second dielectric layer in the first isolation structure trench;

[0072] Step S2222: Remove the second dielectric layer at the bottom of the first isolation structure trench and on the surface of the second semiconductor;

[0073] Step S2223: Fill the third dielectric layer in the first isolation structure trench to form the initial first isolation structure.

[0074] In practical applications, the dry etching process or the wet etching process can be used to remove the second dielectric layer at the bottom of the first isolation structure trench. Among them, the dry etching process can be a plasma etching process, a reactive ion etching process or an ion milling process. Removing the second dielectric layer on the surface of the second semiconductor can be achieved through a Chemical Mechanical Polish (CMP) process.

[0075] In some embodiments, the following steps S222a and S222b are further included between step S2222 and step S2223. See Figure 2F . The steps include:

[0076] Step 222a: Deposit metallic cobalt at the bottom of the first isolation structure trench (see the first isolation structure trench 104a in Figure 2D );

[0077] Step 222b: Perform an annealing process to form a silicide in the substrate 101 to form a buried bit line 114; wherein, the drain layer 107 is located between the channel layer (see the channel layer 108 in Figure 1E ) and the buried bit line 114, and the initial second isolation structure penetrates through the buried bit line 114.

[0078] In practical applications, the material deposited at the bottom of the first isolation structure trench is not limited to metallic cobalt, and can also be any one of titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), platinum (Pt) and palladium (Pd); the above metals can be deposited by CVD or ALD.

[0079] In practical applications, annealing allows the metal and substrate to react and form silicide. Rapid thermal annealing can be used, performed at varying temperatures depending on the type of deposited metal and substrate. For example, if the metal material is cobalt, the annealing temperature can range from 400°C to 800°C. The metal silicide formed after silicide can serve as a buried bit line.

[0080] Metal silicide is a material with a lower resistance than polysilicon. Using such a material, the buried bit line has a low resistance. The buried bit line can be formed via a silicidation process. In addition, the buried bit line can be formed via a full silicidation process. The full silicidation process is a process for fully silicideing a silicon-containing material to a desired depth. The buried bit line can be formed using near-noble metals such as titanium silicide (TiSix), tungsten silicide (WSix), cobalt silicide (CoSix), and nickel silicide (NiSix), or metal silicides such as refractory metals. The metal silicide can be obtained by forming a conductive material via a sputtering process, a CVD process, or an ALD process and then performing a silicidation process. The conductive material can include a near-noble metal or a refractory metal. Fully silicideing the buried bit line can reduce the resistance of the buried bit line.

[0081] In some embodiments, step S203 may be implemented by steps S231 to S233, where steps S231 to S232 refer to Figures 2G to 2I .

[0082] Step S231, see Figure 2E , etching the second dielectric layer 104b in the initial first isolation structure 104d in the second semiconductor layer 103 and the first dielectric layer 105b in the initial second isolation structure (see the description of step S221), thereby forming Figure 2G The structure shown;

[0083] Step S232, see Figure 2G , the initial first isolation structure after etching the second semiconductor layer 103 (see Figure 2E The fourth dielectric layer 104e is filled in the initial first isolation structure 104d) in the first isolation structure 104d, so that Figure 2H The structure shown;

[0084] Step S233, see Figure 2H , respectively etching the initial first isolation structure in the first semiconductor layer 102 (see Figure 2Ethe second dielectric layer 104b in the initial first isolation structure 104d) and the first dielectric layer 105b in the initial second isolation structure (see the description of step S221) to form the first isolation structure 104 and the second isolation structure 105, thus forming Figure 2I the structure shown.

[0085] Here, the first isolation structure 104 includes a second dielectric layer 104b, a third dielectric layer 104c, and a fourth dielectric layer 104e.

[0086] In some embodiments, the material of the third dielectric layer includes silicon nitride, and the material of the fourth dielectric layer is the same as that of the third dielectric layer.

[0087] In some embodiments, after step S233, it further includes: step S234, see Figure 2I , etching a part of the first semiconductor layer (see Figure 2H the first semiconductor layer 102 in Figure 2J ) to form the channel layer 108 shown; wherein, there are through holes 109 with an extending direction the same as the first direction between the channel layer 108 and two adjacent first isolation structures 104.

[0088] During implementation, the first semiconductor layer can be etched along the first direction (i.e., the X-axis direction) by using an isotropic quasi-atomic layer etching technique to form the channel layer. The size of the channel layer can be controlled to improve the control of the gate structure over the channel and simultaneously improve the switching speed.

[0089] Execute step S205, after forming a gate structure in the through hole, form the structure as shown in Figure 2K shown.

[0090] Based on the structure formed by the above method as shown in Figure 2K , an embodiment of the present application provides a semiconductor structure, and the structure includes:

[0091] a substrate (see Figure 1B the substrate 100 in Figure 1B ); wherein, the substrate includes a substrate formed in sequence (see Figure 1B the substrate 101 in Figure 1B ), a first semiconductor layer (see

[0092] First isolation structures 104 and second isolation structures 105 that are spaced apart and distributed in the substrate; wherein, the extending direction of the first isolation structure 104 is a first direction, the extending direction of the second isolation structure 105 is a second direction, the first isolation structure 104 penetrates through the first semiconductor layer and the second semiconductor layer, and partially extends into the substrate, and the second isolation structure 105 is located in the substrate; the first isolation structure 104 includes: a second dielectric layer 104b located in the substrate, a fourth dielectric layer 104e located in the second semiconductor layer, and a third dielectric layer 104c that penetrates through the first semiconductor layer and the second semiconductor layer and partially extends into the substrate; wherein, the sidewalls of the third dielectric layer 104c are in contact with the second dielectric layer 104b and the fourth dielectric layer 104e; the second isolation structure 105 includes a first dielectric layer 105b located in the substrate.

[0093] A source layer 106 located in the second semiconductor layer;

[0094] A drain layer 107 located in the substrate;

[0095] A channel layer 108 located in the first semiconductor layer;

[0096] A gate structure 110 having an extending direction the same as the first direction is located between the channel layer 108 and two adjacent first isolation structures 104;

[0097] A buried bit line 114 located in the substrate and penetrated by the second isolation structure 105; wherein, the drain layer 107 is located between the channel layer 108 and the buried bit line 114, and the height of the part of the first isolation structure 104 extending into the substrate is less than the height of the part of the second isolation structure 105 located in the substrate.

[0098] An embodiment of the present application further provides a method for forming a semiconductor structure, and the method includes the following steps:

[0099] Step S301, as Figure 1B shown, provide a substrate 100; wherein, the substrate includes a substrate 101, a first semiconductor layer 102, and a second semiconductor layer 103 formed in sequence.

[0100] Step S302, perform ion doping on the second semiconductor layer 103 and a part of the substrate 101 to form a drain doping region in the substrate 101 and a source doping region in the second semiconductor layer 103.

[0101] Here, the dopant used for ion doping can be an N-type dopant, such as phosphorus (P), arsenic (As), silicon (Si), germanium (Ge), carbon (C), oxygen (O), sulfur (S), selenium (Se), tellurium (Te), or antimony (Sb), etc.; or it can be a P-type dopant, such as boron (B), boron fluoride (BF2), Si, Ge, C, zinc (Zn), cadmium (Cd), beryllium (Be), magnesium (Mg), or indium (In), etc.

[0102] Step S303, as Figure 1C shown, form spaced-apart first isolation structures 104 and second isolation structures 105 in the substrate (see the substrate 100 in Figure 1B ); wherein, between two adjacent first isolation structures 104, there are a source layer 106 formed in the second semiconductor layer 103 and a drain layer 107 formed in the substrate 101. The extending direction of the first isolation structure 104 is the first direction, the extending direction of the second isolation structure 105 is the second direction. The first isolation structure 104 penetrates through the first semiconductor layer 102 and the second semiconductor layer 103 and partially extends into the substrate 101, and the second isolation structure is located in the substrate 101;

[0103] Step S304, as Figure 1D shown, form a channel layer 108 in the first semiconductor layer 102. There is a via hole 109 with an extending direction the same as the first direction between the channel layer 108 and two adjacent first isolation structures 104;

[0104] Step S305, as Figure 1E shown, form a gate structure 110 in the via hole (see the via hole 109 in Figure 1D );

[0105] Step S306, as Figure 3A shown, fill a fifth dielectric layer 111 in the second semiconductor layer 103, and the top surface of the fifth dielectric layer 111 is flush with the top surface of the second semiconductor 103;

[0106] Here, the material used for the fifth dielectric layer can be nitrides such as silicon nitride, aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN), etc., and can be formed by processes such as low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or atomic layer deposition.

[0107] Step S307, as Figure 3A shown, sequentially form a contact node 112 and a capacitor 113 on each source layer 106.

[0108] Here, the capacitor can be a columnar capacitor, which can be not limited to a cylindrical capacitor, but also a square capacitor or other columnar capacitors of other shapes; the contact node can have the shape of a cylinder or a concave structure.

[0109] In some embodiments, step S305 can be implemented by step S3051 and step S3052.

[0110] Step S3051: Form a gate oxide layer in the through hole by thermal oxidation;

[0111] Step S3052: Fill a conductive material on the surface of the gate oxide layer to form the gate structure.

[0112] In practical applications, the conductive material can be a metal, such as tungsten (W), or a metal nitride, such as titanium nitride.

[0113] In some embodiments, the capacitor can include an electrode plate and a dielectric layer. Among them, the material of the electrode plate can be titanium nitride (TiN) or aluminum foil, and the material of the dielectric layer can be a composite material of zirconia (ZrO) and Al2O3, a ZrO material, an Al2O3 material, or other materials with a dielectric constant higher than that of SiO2.

[0114] In the embodiments of the present application, by forming a first isolation structure and a second isolation structure in the substrate, a channel layer is formed in the first semiconductor layer, and a gate structure is formed in the through hole of the channel layer, thereby forming a fully depleted surround gate structure, improving the gate control ability and switching speed.

[0115] The semiconductor structure formed by the above method is as Figure 3A and Figure 3B shown. Based on Figure 3A , the embodiments of the present application provide a semiconductor structure, including: a substrate (see the substrate 100 in Figure 1B ); among them, the substrate includes a substrate 101, a first semiconductor layer 102, and a second semiconductor layer 103 formed in sequence;

[0116] First isolation structures 104 and second isolation structures 105 distributed at intervals in the substrate; among them, the extending direction of the first isolation structure 104 is the first direction, the extending direction of the second isolation structure 105 is the second direction, the first isolation structure 104 penetrates through the first semiconductor layer 102 and the second semiconductor layer 103, and partially extends into the substrate 101, and the second isolation structure 105 is located in the substrate;

[0117] A source layer 106 located in the second semiconductor 103 layer;

[0118] A drain layer 107 located in the substrate 101;

[0119] A channel layer 108 located in the first semiconductor layer 102;

[0120] A gate structure 110 having an extending direction the same as the first direction is located between the channel layer 108 and two adjacent first isolation structures 104;

[0121] A fifth dielectric layer 111 located in the second semiconductor layer 103; wherein, the top surface of the fifth dielectric layer 111 is flush with the top surface of the second semiconductor layer 103;

[0122] A contact node 112 and a capacitor 113 located on each source layer 106.

[0123] In some embodiments, as Figure 3A shown, the structure further includes: a buried bit line 114 penetrated by the second isolation structure 105 in the substrate (see Figure 3A the substrate 101 in); wherein, the drain layer 107 is located between the channel layer 108 and the buried bit line 114, and the height of the part of the first isolation structure 104 extending into the substrate is less than the height of the part of the second isolation structure 105 located in the substrate.

[0124] The embodiment of the present application further provides a method for forming a semiconductor structure, see Figure 4A , the method includes the following steps:

[0125] Step S401, see Figure 1B , provide a substrate 100, the substrate 100 includes a substrate 101, a first semiconductor layer 102 and a second semiconductor layer 103 formed in sequence.

[0126] Step S402, see Figure 2B , form a second isolation structure trench 105a in the substrate (see Figure 1B the substrate 100 in); see Figure 2C , fill a first dielectric layer 105b in the second isolation structure trench (see Figure 2C the second isolation structure trench 105a in) to form the initial second isolation structure;

[0127] Wherein, the second isolation structure trench 105a penetrates the first semiconductor layer 102 and the second semiconductor layer 103, and partially extends into the substrate 101.

[0128] Step S403, see Figure 2D, a first isolation structure trench 104a is formed in the substrate after the formation of the initial second isolation structure; wherein, the first isolation structure trench 104a penetrates through the first semiconductor layer 102 and the second semiconductor layer 103 and partially extends into the substrate 101, and between two adjacent first isolation structure trenches 104a, there are a source layer 106 formed in the second semiconductor layer 103 and a drain layer 107 formed in the substrate 101.

[0129] Step S404, refer to Figure 2D and 4B , in Figure 2D , the second dielectric layer 104b is filled in the first isolation structure trench 104a, thus forming the structure shown in Figure 4B .

[0130] Step S405, refer to Figure 4B , the second dielectric layer 104b at the bottom of the first isolation structure trench (refer to the first isolation structure trench 104a in Figure 2D ) and on the surface of the second semiconductor 103 is removed, thus forming the structure shown in Figure 4C .

[0131] Step S406, deposit cobalt metal at the bottom of the first isolation structure trench (refer to the first isolation structure trench 104a in Figure 4A ); refer to Figure 2F , annealing treatment is carried out to form silicide in the substrate to form a buried bit line 114.

[0132] Step S407, refer to Figure 4D , the third dielectric layer 104c is filled in the first isolation structure trench (refer to the first isolation structure trench 104a in Figure 2D ) to form the initial first isolation structure 104d.

[0133] Step S408, refer to Figure 2E , etch the second dielectric layer 104b in the initial first isolation structure in the second semiconductor layer 103 (refer to the initial first isolation structure 104d in Figure 4D ) and the first dielectric layer 105b in the initial second isolation structure (refer to the description of step S221), thus forming the structure shown in Figure 2G .

[0134] Step S409, refer to Figure 2G , fill the fourth dielectric layer 104e in the etched initial first isolation structure in the second semiconductor layer 103 (refer to the initial first isolation structure 104d in Figure 4D ), thus forming the structure shown in Figure 2HThe structure shown.

[0135] Step S410, refer to Figure 2H , etch the second dielectric layer 104b in the initial first isolation structure (refer to the initial first isolation structure 104d in Figure 4D ) in the first semiconductor layer 102 and the first dielectric layer 105b in the initial second isolation structure (refer to the description in step S221) to form the first isolation structure 104 and the second isolation structure 105, thus forming Figure 2I The structure shown.

[0136] Step S411, refer to Figure 2I , etch a part of the first semiconductor layer (refer to the first semiconductor layer 102 in Figure 2H ) to form Figure 2J The channel layer 108 shown; wherein, there is a through hole 109 with an extending direction the same as the first direction between the channel layer 108 and two adjacent first isolation structures 104, and the width of the channel layer 108 in the second direction is less than the widths of the source layer 106 and the drain layer 107 in the second direction, and the drain layer 107 is located between the channel layer 108 and the buried bit line 114.

[0137] Step S412, refer to Figure 2K , form a gate oxide layer 110a in the through hole (refer to the through hole 109 in Figure 2J ) by thermal oxidation;

[0138] Step S413, continue to refer to Figure 2K , fill a conductive material 110b on the surface of the gate oxide layer 110a to form the gate structure 110;

[0139] Step S414, refer to Figure 4E , fill a fifth dielectric layer 111 in the second semiconductor layer 103, and the top surface of the fifth dielectric layer 111 is flush with the top surface of the second semiconductor 103;

[0140] Step S415, continue to refer to Figure 4E , form a contact node 112 and a capacitor 113 on each source layer 106 in sequence.

[0141] The description of the above semiconductor structure embodiments is similar to the description of the above method embodiments and has similar beneficial effects to the method embodiments. For the technical details not disclosed in the semiconductor structure embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0142] In several embodiments provided by the present application, it should be understood that the disclosed structures and methods can be implemented in a non-targeted manner. The structural embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the couplings between the various components shown or discussed are either direct couplings or indirect couplings through some interfaces.

[0143] The units described above as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0144] The features disclosed in several method or structural embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments or structural embodiments.

[0145] The above is only some embodiments of the embodiments of the present application, but the protection scope of the embodiments of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed in the embodiments of the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the embodiments of the present application. Therefore, the protection scope of the embodiments of the present application should be subject to the protection scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, the method comprises: providing a substrate; wherein, the substrate comprises a substrate, a first semiconductor layer and a second semiconductor layer formed in sequence; forming first isolation structures and second isolation structures distributed at intervals in the substrate; wherein, between two adjacent first isolation structures, a source layer formed in the second semiconductor layer and a drain layer formed in the substrate are included, the extending direction of the first isolation structure is a first direction, the extending direction of the second isolation structure is a second direction, the first isolation structure penetrates through the first semiconductor layer and the second semiconductor layer and partially extends into the substrate, and the second isolation structure is located in the substrate; forming a channel layer in the first semiconductor layer, and there are through holes with an extending direction the same as the first direction between the channel layer and two adjacent first isolation structures; forming a gate structure in the through holes.

2. The method according to claim 1, characterized in that, before forming the first isolation structures and the second isolation structures distributed at intervals in the substrate, it further comprises: performing ion doping on the second semiconductor layer and a part of the substrate to form a drain doping region in the substrate and a source doping region in the second semiconductor layer.

3. The method according to claim 1, characterized in that, forming the first isolation structures and the second isolation structures distributed at intervals in the substrate comprises: forming an initial first isolation structure and an initial second isolation structure in the substrate; wherein, the extending direction of the initial first isolation structure is the first direction, and the extending direction of the initial second isolation structure is the second direction; the initial first isolation structure and the initial second isolation structure penetrate through the first semiconductor layer and the second semiconductor layer and partially extend into the substrate to form the source layer in the second semiconductor layer and the drain layer in the substrate; etching the initial first isolation structure to form the first isolation structure, and etching the initial second isolation structure to form the second isolation structure.

4. The method according to claim 3, characterized in that, forming the initial first isolation structure and the initial second isolation structure in the substrate comprises: forming a second isolation structure trench in the substrate, and filling a first dielectric layer in the second isolation structure trench to form the initial second isolation structure; forming a first isolation structure trench in the substrate after forming the initial second isolation structure, and filling a second dielectric layer and a third dielectric layer in the first isolation structure trench to form the initial first isolation structure; wherein, the first isolation structure trench and the second isolation structure trench penetrate through the first semiconductor layer and the second semiconductor layer and partially extend into the substrate.

5. The method according to claim 4, characterized in that, filling the second dielectric layer and the third dielectric layer in the first isolation structure trench to form the initial first isolation structure comprises: filling the second dielectric layer in the first isolation structure trench; Remove the second dielectric layer at the bottom of the trench of the first isolation structure and on the surface of the second semiconductor; Fill the trench of the first isolation structure with the third dielectric layer to form the initial first isolation structure.

6. The method according to claim 5, wherein etching the initial first isolation structure to form the first isolation structure and etching the initial second isolation structure to form the second isolation structure includes: etching the second dielectric layer in the initial first isolation structure and the first dielectric layer in the initial second isolation structure in the second semiconductor layer; fill the etched initial first isolation structure in the second semiconductor layer with a fourth dielectric layer; etch the second dielectric layer in the initial first isolation structure and the first dielectric layer in the initial second isolation structure in the first semiconductor layer respectively to form the first isolation structure and the second isolation structure.

7. The method according to claim 6, wherein after etching the second dielectric layer in the initial first isolation structure and the first dielectric layer in the initial second isolation structure in the first semiconductor layer respectively, it includes: etch a part of the first semiconductor layer to form the channel layer; wherein, there is a through hole with an extension direction the same as the first direction between the channel layer and two adjacent first isolation structures, and the width of the channel layer in the second direction is smaller than the widths of the source layer and the drain layer in the second direction.

8. The method according to claim 5, wherein after removing the second dielectric layer at the bottom of the trench of the first isolation structure and on the surface of the second semiconductor, before filling the trench of the first isolation structure with the third dielectric layer, it further includes: deposit cobalt metal at the bottom of the trench of the first isolation structure; perform an annealing process to form a silicide in the substrate to form a buried bit line; wherein, the drain layer is located between the channel layer and the buried bit line, the height of the part of the first isolation structure extending into the substrate is smaller than the height of the part of the second isolation structure located in the substrate, and the second isolation structure penetrates through the buried bit line.

9. The method according to any one of claims 1 to 8, wherein forming the gate structure in the through hole includes: forming a gate oxide layer in the through hole by thermal oxidation; fill a conductive material on the surface of the gate oxide layer to form the gate structure.

10. The method according to claim 9, wherein the method further includes: fill the second semiconductor layer with a fifth dielectric layer, and the top surface of the fifth dielectric layer is flush with the top surface of the second semiconductor; form a contact node and a capacitor on each source layer in sequence.

11. The method according to claim 7, wherein the material of the first dielectric layer includes silicon oxide, and the material of the second dielectric layer is the same as that of the first dielectric layer; the material of the third dielectric layer includes silicon nitride, and the material of the fourth dielectric layer is the same as that of the third dielectric layer.

12. The method according to claim 10, wherein the material of the gate oxide layer includes silicon oxide, and the material of the fifth dielectric layer includes silicon nitride.

13. A semiconductor structure formed by using the method for forming the semiconductor structure according to claim 1, wherein the structure includes: a substrate; wherein the substrate includes a substrate, a first semiconductor layer, and a second semiconductor layer formed in sequence; first isolation structures and second isolation structures spaced apart from each other in the substrate; wherein the first isolation structure extends in a first direction, the second isolation structure extends in a second direction, the first isolation structure penetrates through the first semiconductor layer and the second semiconductor layer, and partially extends into the substrate, and the second isolation structure is located in the substrate; a source layer located in the second semiconductor layer; a drain layer located in the substrate; a channel layer located in the first semiconductor layer; a gate structure having an extension direction the same as the first direction is located between the channel layer and two adjacent first isolation structures.

14. The structure according to claim 13, wherein the first isolation structure includes: a second dielectric layer located in the substrate, a fourth dielectric layer located in the second semiconductor layer, and a third dielectric layer that penetrates through the first semiconductor layer and the second semiconductor layer and partially extends into the substrate; wherein the sidewall of the third dielectric layer is in contact with the second dielectric layer and the fourth dielectric layer; the second isolation structure includes a first dielectric layer located in the substrate.

15. The structure according to claim 14, wherein further includes: a buried bit line located in the substrate and penetrated by the second isolation structure; wherein the drain layer is located between the channel layer and the buried bit line, and the height of the part of the first isolation structure extending into the substrate is less than the height of the part of the second isolation structure located in the substrate.

16. The structure according to claim 13, wherein the substrate, the first semiconductor layer, and the second semiconductor layer are a silicon substrate, a silicon germanium layer, and a silicon layer in sequence.

17. The structure according to claim 16, wherein the gate structure includes: a gate oxide layer and a conductive material located on the surface of the gate oxide layer.

18. The structure according to any one of claims 13 to 17, wherein further includes: a fifth dielectric layer located in the second semiconductor layer; wherein the top surface of the fifth dielectric layer is flush with the top surface of the second semiconductor layer; contact nodes and capacitors located on each of the source layers.

19. The structure according to claim 14, wherein the material of the first dielectric layer includes silicon oxide, and the material of the second dielectric layer is the same as that of the first dielectric layer; the material of the third dielectric layer includes silicon nitride, and the material of the fourth dielectric layer is the same as that of the third dielectric layer.

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