Method of manufacturing electronic chips and electronic device

Abstract

The present disclosure relates to a method for manufacturing an electronic chip, the method comprising in sequence: a. forming a metal contact on one side of a first face of a semiconductor substrate in which and on which a plurality of integrated circuits have been previously formed; b. depositing a first protective resin on the metal contact and the first face of the semiconductor substrate; c. forming a first trench of a first width on a second face side of the semiconductor substrate; d. depositing a second protective resin in the first trench and on the second face of the semiconductor substrate; e. forming a second trench of a second width, the second width being smaller than the first width, opposite the first trench up to the metal contact; and f. forming a third trench opposite the second trench, the third trench extending through the metal contact.

Description

Technical Field

[0001] This invention relates to the manufacture of electronic chips. More specifically, this disclosure relates to the manufacture of chips known as surface-mount chips, i.e., chips that have one or more connections metallized on at least one side of a surface, intended to be soldered to corresponding connection pads on the connection surface of an external device such as a printed circuit board or another chip. Background Technology

[0002] Typically, the interconnect metallization of surface-mount chips is located on the lower surface of the chip, that is, the side of the chip facing the interconnects to external devices. Once assembled, the interconnect metallization is thus hidden by the chip. However, for some applications, surface-mount chips are required that allow visual inspection of the quality of the chip solder joints, and more specifically, their metallization on external devices. This need exists in fields such as automotive or medical, and more generally, in fields where the reliability of electrical connections needs to be ensured once the circuit is installed in its environment.

[0003] It is hoped that certain aspects of known methods for manufacturing electronic chips can be improved, at least in part.

[0004] There is particular interest in manufacturing chips encapsulated in chip-scale type packages (CSPs). More specifically, there is a desire to produce CSP-type chips that allow for visual inspection of solder joint quality using a camera placed above the chip. Summary of the Invention

[0005] One embodiment provides a method for manufacturing an electronic chip, the method comprising, in sequence:

[0006] a. A metal contact is formed on one side of a first surface of a semiconductor substrate, wherein multiple integrated circuits have been pre-formed in and on the semiconductor substrate, and each metal contact extends directly over at least two adjacent integrated circuits;

[0007] b. Deposit a first protective resin on the first surface of the metal contact and the semiconductor substrate;

[0008] c. A first trench of a first width is formed on a side flank of a second surface of the semiconductor substrate opposite to the first surface, the first trench extending between the integrated circuits over the entire thickness of the semiconductor substrate;

[0009] d. Deposit a second protective resin in the first trench and on the second surface of the semiconductor substrate;

[0010] e. Forming a second groove with a second width smaller than the first width in the second protective resin opposite to the first groove, the second groove extending to the metal contact; and

[0011] f. Forming a third trench of a third width, the third width being smaller than the second width opposite to the second trench, the third trench extending through the metal contact to cut the electronic chip.

[0012] According to one embodiment, the method sometimes includes a step of thinning the first protective resin to expose the metal contacts after step b. According to one embodiment, the thinning of the first protective resin may occur after step d, so that the metal contacts are exposed after the second protective resin has been deposited in the first trench and on the second surface of the semiconductor substrate.

[0013] According to one embodiment, the method includes, prior to step a, forming a reconnection post on a side of a first surface of a semiconductor substrate, and during step a, forming and contacting a metal contact on and with the reconnection post.

[0014] According to one embodiment, the height of the metal contact is between 20 μm and 150 μm.

[0015] According to one embodiment, the third width is less than 20 μm.

[0016] According to one embodiment, the second width is between 30 μm and 310 μm.

[0017] According to one embodiment, the method includes, after step a, a step of thinning the semiconductor substrate through its second surface.

[0018] According to one embodiment, the step of thinning the semiconductor substrate is performed before step c.

[0019] According to one embodiment, the step of thinning the semiconductor substrate is performed after step d.

[0020] An embodiment provides an electronic chip including an integrated circuit formed in and on a semiconductor substrate, the sidewalls of the substrate being coated with a second protective resin, the chip including at least one metal contact disposed on a first surface of the semiconductor substrate and extending laterally beyond the sidewalls of the second protective resin.

[0021] According to one embodiment, the at least one metal contact has a flat connection surface that extends continuously beneath the semiconductor substrate and laterally beyond the sidewalls of the second protective resin. Attached Figure Description

[0022] The foregoing features and advantages, as well as other features and advantages, will be set forth in the following detailed description of embodiments by way of illustration rather than limitation, with reference to the accompanying drawings, in which:

[0023] Figure 1 An example of an embodiment of a surface-mounted electronic chip is shown in a cross-sectional view and a view from below;

[0024] Figure 2 The cross-sectional view illustrates the manufacturing process. Figure 1 One step of an example of a method for an electronic chip is shown;

[0025] Figure 3 The cross-sectional view illustrates the manufacturing process. Figure 1 Another step in the example method for the electronic chip shown;

[0026] Figure 4 The cross-sectional view shows the process of manufacturing. Figure 1 Another step in an example of the method for the electronic chip shown;

[0027] Figure 5 The cross-sectional view illustrates the manufacturing process. Figure 1 Another step in an example of the method for the electronic chip shown;

[0028] Figure 6 The cross-sectional view shows the process of manufacturing. Figure 1 Another step in an example of the method for the electronic chip shown;

[0029] Figure 7 The cross-sectional view shows the process of manufacturing. Figure 1 Another step in an example of the method for the electronic chip shown;

[0030] Figure 8 The cross-sectional view shows the process of manufacturing. Figure 1 Another step in the example method for the microchip shown, and

[0031] Figure 9 The cross-sectional view illustrates the manufacturing process. Figure 1 This is another step in the example method for the electronic chip shown. Detailed Implementation

[0032] In the various figures, the same features are indicated by the same reference numerals. In particular, common structural and / or functional features in the various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0033] For clarity, only the operations and elements that can be used to understand the embodiments described herein have been detailed and described. In particular, the manufacture of the integrated circuits present in the electronic chip has not been described in detail.

[0034] Unless otherwise stated, when referring to two elements connected together, it means that there is no direct connection between them except for the conductor, and when referring to two elements connected together, it means that the two elements can be connected or they can be coupled through one or more other elements.

[0035] In the following disclosure, unless otherwise indicated, when referring to absolute position qualifiers (such as the terms “front,” “back,” “top,” “bottom,” “left,” “right,” etc.) or relative position qualifiers (such as the terms “upper,” “lower,” “higher,” “lower,” etc.) or orientation qualifiers (such as “horizontal,” “vertical,” etc.), the orientation of the corresponding cross-sectional view in the accompanying drawings will be referred to, unless otherwise indicated.

[0036] Unless otherwise stated, the expressions “about,” “approximately,” “basically,” and “in the order of” indicate within 10%, preferably within 5%.

[0037] Surface mount chips with interconnect metallization extending to the chip's flanks have been proposed. These are referred to as wettable flank fragments. When the chip is mounted on an external device such as a printed circuit board, the chip interconnect metallization is soldered or brazed to the corresponding metal tracks or components of the external device. Some solder material then rises to the chip's flanks, allowing for visual inspection of the solder quality.

[0038] Wettable wing chips typically have relatively high (thick) interconnect metallization, making it easy to inspect chip soldering.

[0039] This height can limit the miniaturization possibilities of electronic circuits based on this chip.

[0040] According to one aspect of the embodiments described below, it is envisioned that the interconnect metallization extends horizontally beyond the chip housing. This allows for visual inspection of interconnect quality while limiting the thickness of the interconnect metallization on the chip.

[0041] Figure 1 An embodiment of the electronic chip is shown by means of cross-sectional view A and view B from below, where view A is a cross-sectional view based on section AA of view B.

[0042] Electronic chip 1 (also referred to as chip 1) includes a semiconductor substrate 11 (also referred to as substrate 11), in which and on the semiconductor substrate 11, an integrated circuit 13 is formed. Substrate 11 is made of a semiconductor material such as silicon. On the lower surface side of substrate 11 (in the direction of view A), a stack of insulating conductive layers, referred to as interconnect stack 15, is coated and contacts the substrate 11, forming interconnect elements of components of circuit 13. Interconnect stack 15 also includes one or more conductive reconnection posts 17, such as metal openings at the surface of interconnect stack 15. In the example shown, the chip includes six posts 17. However, the described embodiment is not limited to this specific case. In variations, chip 1 may include multiple posts 17 in addition to six, such as five posts 17 or eight posts 17. Figure 1 As shown, pillar 17 is located on the periphery of interconnect stack 15. For example, the spacing between two pillars 17 is greater than 50 μm.

[0043] The pillar 17 extends laterally beyond the structure formed by the substrate 11 and the interconnect stack 15. In other words, the lateral edge of the structure formed by the substrate 11 and the interconnect stack 15 is not aligned with the lateral edge of the pillar 17.

[0044] For example, the structure formed by the substrate 11 and the interconnect stack 15 has a parallelepiped shape.

[0045] Figure 1 The chip 1 shown also includes connection metallization or metal contacts 19. Each metal contact 19 is formed on and contacts the reconnection post 17. The post 17 is preferably entirely covered by at least a portion of the metal contact 19. The metal contacts 19 extend laterally beyond the side flanks 31 of the structure formed by the substrate 11 and the interconnect stack 15. The portion of the structure formed by the substrate 11, the interconnect stack 15, and the reconnection post 17 that is not covered by the metal contacts 19 is covered by an electrically insulating protective resin to form a chip housing. For example, a portion of the upper surface and lateral edges of the structure is covered by resin region 25, and a portion of the lower surface of the structure is covered by resin 21. For example, the protective resin exposes only the metal contacts 19 of the chip. In this example, the metal contacts 19 are flush with the lower surface side of the resin 21, which is based on... Figure 1 The orientation of chip 1 is shown.

[0046] According to one aspect of the embodiment, the metal contacts 19 extend laterally beyond the side wing 33 (e.g., sidewall, side surface, etc.) of the housing formed of protective resin. For example, when viewed from below, a portion 19b of each metal contact 19 extends beyond the side wing of the housing by a distance L1, for example, between 10 μm and 150 μm (in a direction orthogonal to the side wing of the chip housing). In other words, each metal contact 19 extends partially beneath the substrate 11 and laterally beyond the chip housing. Thus, each metal contact 19 has a flat lower contact surface that extends continuously, partially beneath the substrate 11, and laterally beyond the side wing of the chip housing.

[0047] The bracket 19b protruding from the side of chip 1 forms a connection bracket, which allows the quality of the chip connection to be visually inspected at an external device.

[0048] For example, the length L2 of the portion of the metal contact 19 located below the chip housing is greater than 50 μm. Figure 1 As shown in the embodiment of chip 1, the length L2 is greater than the length L1.

[0049] For example, soldering the chip 1 to the metal contact 19 is performed by depositing solder on the lower surface of the metal contact 19. Figure 1 The external device shown.

[0050] One advantage of the presence of the bracket 19b, which protrudes from the side of the chip housing 1 and is used for the metallization 19, is that visual control of the soldering quality is possible when the chip 1 is soldered to an external device. In particular, during assembly, a portion of the solder material can rise on the upper surface of the side and the bracket 19b, which facilitates visual inspection of the connection.

[0051] Figures 2 to 9 This shows the method for manufacturing bonding. Figure 1 A cross-sectional view of the successive steps of an example method for an electronic chip of the aforementioned type.

[0052] Figure 2 This is a cross-sectional view of a structure including a semiconductor substrate 11, in which an integrated circuit 13 has been pre-formed. For example, the circuit 13 is identical throughout the fabrication process. The substrate 11 may correspond to a wafer of a semiconductor material such as silicon. The thickness T1 of the substrate 11 is between 50 μm and 900 μm, for example, between 50 μm and 500 μm, such as approximately 500 μm.

[0053] Figure 2The structure also includes an interconnect stack comprising an insulating layer and a conductive layer coated on the upper surface of the substrate 11. The insulating and conductive layers of the interconnect stack 15 can be stacked on top of each other; for example, the interconnect stack 15 may include one or more insulating layers and one or more conductive layers stacked on top of each other. The interconnect stack 15 also includes reconnection pillars 17 for each integrated circuit 13. Each reconnection pillar 17 may be on the upper surface of a corresponding metal contact 19. For example, the reconnection pillar 17 may be shared for several integrated circuits 13. Identical reconnection pillars 17 may extend, for example, on at least two adjacent integrated circuits 13 and in a cut-off region located between two integrated circuits. The reconnection pillar 17 may comprise a stack of one or more metal layers. For example, the contact pillar 17 is under-bump metallization (UBM).

[0054] For example, each integrated circuit 13 includes one or more electronic components (transistors, diodes, thyristors, triacs, etc.).

[0055] exist Figure 2 The diagram shows three integrated circuits 13. It can be understood that the number of integrated circuits 13 formed in and on the substrate 11 may be different than three. In fact, the substrate 11 is a wafer of a semiconductor material such as silicon, and dozens, hundreds, or even thousands of integrated circuits 13 are formed in and on the substrate 11. The integrated circuits 13 are then organized into an array of rows and columns, for example, a regular grid pattern.

[0056] In the remainder of this specification, Figure 2 In this orientation, the lower surface of the structure is considered the rear surface, and the upper surface of the structure is considered the front surface.

[0057] Figure 3 The cross-sectional diagram illustrates the... Figure 2 The step of forming a metal contact 19 on the front side of the structure shown.

[0058] More specifically, in Figure 3 In the steps shown, the metal contact 19 is formed to align with and contact each contact reconnection post 17. For example, the metal contact 19 covers the entire surface of the contact reconnection post 17. For example, when viewed from above, the outline of the metal contact 19 matches the outline of the reconnection post 17.

[0059] For example, the metal contact 19 is manufactured by electrolytic growth from the upper surface of the pillar 17. The height (thickness) of the metal contact 19 is greater than or equal to 20 μm, for example, such as greater than or equal to 50 μm. As an example, the height H1 of the metal contact 19 is between 20 μm and 150 μm.

[0060] The metal contact 19 may be made of a tin-based alloy, such as a tin / silver (tin-silver alloy) based alloy. In a variation, the metal contact 19 may be a copper, gold, silver, nickel-based alloy such as nickel-palladium and / or nickel-electrolytic gold alloy, or any alloy based on one or more of these materials.

[0061] Figure 4 The cross-sectional diagram shows that... Figure 3 The step of depositing protective resin 21 on the front side of the structure shown.

[0062] During this step, the front side of the structure, particularly the upper surface of the metal contacts 19 and the interconnect stack 15, is completely covered (full board) with resin 21. Resin 21 is, for example, epoxy resin. Resin 21 provides the front side of the final chip (i.e., Figure 1 Electrical insulation of the lower surface (in view A). Resin 21 may be referred to as first resin, first resin layer, first protective resin layer, or some other suitable type of resin 21.

[0063] Resin 21 preferably has a relatively large thickness to reinforce the structure for subsequent steps. Resin 21 then serves as a mechanical support, particularly for the following steps and the cutting steps. As an example, resin 21 is deposited from the upper surface of the interconnect stack 15 with a thickness between 100 μm and 500 μm.

[0064] Figure 5 The cross-sectional diagram illustrates the process from... Figure 4 The step of forming the first cutting groove 23 on the back side of the structure shown.

[0065] It should be noted that, Figure 5 In this example, the structural orientation is reversed relative to the cross-sectional view of the previous diagram.

[0066] For example, in the step of forming trench 23, the structure is supported by a support membrane (not shown), which supports... Figure 5 The orientation is arranged on the lower surface of resin 21.

[0067] Trench 23 extends between circuits 13 such that each circuit 13 is laterally separated from its adjacent circuits by trench 23. For example, each circuit 13 is completely laterally defined by trench 23. For example, viewed from above, trench 23 may form a continuous grid extending between integrated circuits 13.

[0068] In the example shown, trench 23 extends from the back side of substrate 11 (i.e., Figure 5The trench 23 extends vertically (from the upper surface of the orientation) and extends into the substrate 11 at least through its thickness. The trench 23 extends into, for example, all or part of the thickness of the stacked interconnect 15, and into, for example, all or part of the thickness of the pillar 17. For example, the trench 23 opens onto or into the pillar 17. In a variant, the trench 23 opens onto or into the metal contact 19. In the example shown, the trench 23 opens onto the upper surface of the pillar 17, i.e., on the surface of the pillar 17 opposite to the metal contact 19.

[0069] The groove 23 is formed, for example, by plasma cutting. In a variant, the groove 23 is formed by sawing with a blade.

[0070] The groove 23 has a width L3, for example, between 50 μm and 400 μm.

[0071] Figure 6 The cross-sectional diagram shows that... Figure 5 The step of depositing protective resin 25 on the back side of the structure shown. Protective resin 25 may be referred to as a second resin, a second resin layer, a second protective resin layer, or some other suitable type of protective resin 25.

[0072] During this step, Figure 5 The upper surface of the structure shown is completely covered by resin 25 (full plate), and specifically, the trenches 23 are filled, and the rear surface of the substrate 11 (in) Figure 6 The upper surface of the substrate 11 is covered. For example, resin 25 is the same as resin 21. In variations, resins 21 and 25 may be different. Resin 25 is, for example, epoxy resin. Resin 25 covers the edges and back surface of the final chip (i.e., Figure 1 The upper surface of view A is electrically insulated, and more specifically, the semiconductor substrate 11 is electrically insulated.

[0073] Figure 7 Shown by cross-sectional diagram Figure 6 The planarization steps for the front surface of the structure shown.

[0074] It should be noted that, Figure 7 In the example, structural orientation relative to Figure 5 and 6 The cross-sectional view is upside down.

[0075] During this step, a portion of the resin 21 is removed to expose the metal contact 19. Planarization is performed, for example, by mechanical polishing or by chemical mechanical polishing (CMP).

[0076] At the end of this step, the metal contacts 19 are no longer covered by the resin 21, and the resin 21 remains only between the metal contacts 19. Therefore, in Figure 7In the orientation shown, each surface of the metal contact 19 is substantially flush with or coplanar with the lower surface of the resin 21.

[0077] Figure 8 The cross-sectional diagram illustrates the thinning process via the back side. Figure 7 Optional steps for the structure shown.

[0078] It should be noted that, Figure 8 In the example, structural orientation relative to Figure 7 The cross-sectional view is upside down.

[0079] In this step, a portion of the thickness of resin 25 is removed. This can be achieved, for example, by mechanical polishing or by chemical / mechanical polishing.

[0080] exist Figure 8 At the end of the steps shown, the thickness of the structure is equal to the desired thickness of the electronic chip.

[0081] In the example shown, the thinning is interrupted before reaching the back side of substrate 11. Therefore, the protective resin layer 25 remains on the back side of substrate 11.

[0082] In one variant, if the thickness of substrate 11 is too large relative to the desired final chip thickness, thinning can continue until some of the thickness of substrate 11 is reduced from its rear surface (i.e., at...). Figure 8 The upper surface of the substrate 11 in its orientation is removed. A third protective resin can then be deposited on the upper surface of the structure after thinning to protect the back side of the thinned substrate 11. For example, the third resin is the same as the second resin 25. In variations, the third resin may differ from the second resin. The third resin is, for example, an epoxy resin. In variations, the third resin may be replaced by another protective material, such as a solid film or any other organic or inorganic material deposited by spraying.

[0083] In another embodiment, the step of thinning the substrate 11 may be performed before forming the trench 23 (e.g., after depositing the resin 21). In one embodiment, the step of thinning the substrate 11 may be performed before the step of depositing the first resin 21.

[0084] Figure 9 The cross-sectional diagram shows the... Figure 8 The steps of forming the second cutting groove 27 and the third cutting groove 29 on the back side of the structure shown.

[0085] exist Figure 9 At the end of the illustrated steps, the structure corresponds to individual chips, each chip comprising a single integrated circuit 13. Prior to this step, the structure was constructed through its front surface (on... Figure 9 The lower surface of the orientation is attached to Figure 9 On the support membrane not shown in the figure.

[0086] In this step, a second groove 27 is first formed in the protective resin 25 opposite to the first groove 23. The groove 27 is formed opposite to all grooves 23 along the entire length of the first groove 23. The groove 27 extends into the resin 25 until it reconnects to the post 17 or the metal contact 19. In other words, the second groove extends from... Figure 9 The upper surface of the structure shown extends through the entire thickness of the resin 25. For example, the groove 27 opens on or in the reconnecting post 17. In a variant, the groove 27 opens onto or into the metal contact 19.

[0087] Trench 27 has a width L4. Width L4 is smaller than width L3, such that the substrate 11 of each chip remains covered by resin 25 on its four sides. Trench 27 can be manufactured, for example, by cutting with a cutting blade smaller in width than that used to manufacture trench 23. In a variant, trench 27 can be formed by laser ablation. For example, trench 27 and trench 23 are aligned along the same central axis.

[0088] To cut the structure into individual chips, each comprising a single integrated circuit 13, a third trench 29 is formed in the metal contact 19 opposite to the second trench 27. More specifically, the trench 29 is formed opposite to each of the second trenches 27 and parallel to the trenches 27. In this example, the trench 29 extends along the entire length of the trench 27. The trench 29 extends vertically such that the metal contact 19 and the post 17 (if applicable) are cut opposite to the second trench 27. The trench 29 has a width L5 less than the width L4, such that each metal contact in each chip has a free bracket 19b protruding from the side flanks of the transverse protective resin layer 25 of the chip housing.

[0089] The groove 29 can be manufactured, for example, by cutting with a cutting blade smaller in width than that used to manufacture the groove 27. In a variant, the groove 29 can be made by laser ablation.

[0090] In this example, on the one hand, the difference between widths L4 and L5 is chosen to be large enough to allow the bracket 19b of the metal contact 19 to be released; on the other hand, width L5 must be small enough so that the maximum number of chips can be manufactured from a single semiconductor wafer. The difference between widths L4 and L5 is twice the length L1 of the bracket 19b.

[0091] The width L5 is less than 20 μm, preferably 10 μm or even less than 10 μm. Then the width L4 is preferably between 30 μm and 310 μm, such that the difference between the widths L4 and L5 is between 20 μm and 300 μm, that is, the bracket length L1 is between 10 μm and 150 μm.

[0092] At the end of this step, the resulting structure corresponds to one consisting only of a supporting membrane ( Figure 9 Multiple electronic chips (not shown) are connected. The chips can then be removed from the support film so that they can be installed in an external device.

[0093] One advantage of the described embodiments and implementation methods is that they allow electronic chips to be easily mounted on printed circuit boards.

[0094] Another advantage of the described embodiments and implementation methods is that they allow for visual inspection of solder joints when the chip is mounted on a printed circuit board, without the need for expensive techniques such as X-ray inspection.

[0095] Another advantage of the described embodiments and implementation methods is that they allow for a reduction in the thickness of surface-mount chips, and thus a reduction in the thickness of printed circuit boards.

[0096] Another advantage of the described embodiments and implementation methods is that they allow for the fabrication of small electronic chips with lateral electrical connection brackets. In particular, this makes it possible to fabricate electrical connection side brackets without requiring a relatively large metal support frame.

[0097] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will be apparent to those skilled in the art. In particular, the embodiments are not limited to the examples of dimensions and materials described above.

[0098] The described embodiments are not limited to the specific arrangement of the reconnection posts 17 and metal contacts 19 shown in the figures. In one variation, in addition to the metal contacts 19 located on the periphery of the chip, the metal contacts 19 have a bracket 19b extending laterally beyond the chip housing, and each chip may include one or more metal contacts located in the central portion of the chip's connection surface, these contacts thus not having lateral overhangs. The connection quality of these central metal contacts to external devices cannot be directly inspected by visual inspection. However, in practice, inspecting the connection quality of the peripheral contacts is sufficient to detect possible assembly defects. If necessary, the connection quality of the central metal contacts can be inspected using X-ray inspection techniques.

[0099] The metal contact 19 may be referred to as a conductive contact, an electrical contact, or some other similar or suitable type associated with the metal contact 19.

[0100] Finally, based on the functional descriptions provided above, the actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art.

[0101] A method for manufacturing an electronic chip (1) can be summarized as including, in sequence:

[0102] a. A metal contact (19) is formed on one side of a first surface of a semiconductor substrate (11), in which and on which a plurality of integrated circuits (13) have previously been formed, each metal contact extending directly over at least two adjacent integrated circuits;

[0103] b. Deposit a first protective resin (21) on the first surface of the metal contact (19) and the semiconductor substrate (11).

[0104] c. A first trench (23) having a first width (L3) is formed on one side of the second surface of the semiconductor substrate (11) opposite to the first surface, the first trench (23) extending between the integrated circuits (13) over the entire thickness of the semiconductor substrate (11);

[0105] d. Deposit a second protective resin (25) in the first trench (23) and on the second surface of the semiconductor substrate (11);

[0106] e. A second groove (27) with a second width (L4) smaller than the first width (L3) is formed in the second protective resin (25) opposite to the first groove (23), the second groove extending to the metal contact (19); and

[0107] f. Form a third groove (29) with a third width (L5) smaller than the second width (L4) opposite to the second groove (27), the third groove extending through the metal contact (19) to cut the electronic chip (1).

[0108] Following step b, the method may include thinning the first protective resin (21) to expose the metal contact (19). Thinning the first protective resin (21) to expose the metal contact (19) may occur after step d. Prior to step a, the method may include forming a reconnection post (17) on a side of a first surface of the semiconductor substrate (11), during which the metal contact (19) is formed on and in contact with the reconnection post (17). The height of the metal contact (19) may be between 20 μm and 150 μm. The third width (L5) may be less than 20 μm. The second width (L4) may be between 30 μm and 310 μm.

[0109] Following step a, the method may further include a step of thinning the semiconductor substrate (11) through its second surface. The step of thinning the semiconductor substrate (11) may be performed before step c. The step of thinning the semiconductor substrate (11) may be performed after step d.

[0110] An electronic chip (1) can be summarized as including an integrated circuit (13) formed in and on a semiconductor substrate (11), the sidewalls of the substrate being coated with a second protective resin (25), the chip including at least one metal contact (19) disposed on a first surface of the semiconductor substrate (11) and extending laterally beyond the sidewalls of the second protective resin (25). The at least one metal contact (19) may have a flat connection surface that extends continuously beneath the semiconductor substrate (11) and laterally beyond the sidewalls of the second protective resin (25).

[0111] The various embodiments described above can be combined to provide other embodiments. If desired, aspects of the embodiments can be modified to incorporate concepts from various patents, applications, and publications to provide other embodiments.

[0112] Based on the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of the authorized equivalents of these claims. Therefore, the claims are not limited to this disclosure.

Claims

1. A method for manufacturing an electronic chip, comprising: Metal contacts are formed on a first surface of a semiconductor substrate comprising multiple integrated circuits, each metal contact extending in an overlapping manner with at least two adjacent integrated circuits in the integrated circuits; A first protective resin is formed on the first surface of the metal contact and the semiconductor substrate; A first trench of a first width is formed, the first trench extending into a second surface of the semiconductor substrate opposite to the first surface of the semiconductor substrate and extending completely through the semiconductor substrate, and each of the first trenches extends between at least two adjacent integrated circuits in the integrated circuit and overlaps with at least one of the metal contacts; A second protective resin is formed in the first trench and on the second surface of the semiconductor substrate; A second trench of a second width is formed in the second protective resin opposite to the first trench. The second width is smaller than the first width. The second trench extends to the metal contact such that a first surface of the metal contact is exposed and a wing is formed by the second protective resin. The first surface of the metal contact is located on the same side as the first surface of the semiconductor substrate. as well as A third groove with a third width opposite to the second groove is formed, the third width being smaller than the second width, the third groove extending through the metal contact to cut one or more electronic chips, and to form a bracket portion of the metal contact that protrudes from the side wing.

2. The method according to claim 1, further comprising: After the first protective resin is formed on the first surface of the metal contact and the semiconductor substrate, the first protective resin is thinned to expose the second surface of the metal contact opposite to the first surface.

3. The method according to claim 1, further comprising: Before forming the metal contact on the first surface of the semiconductor substrate, a reconnection post is formed on the first surface of the semiconductor substrate.

4. The method of claim 3, wherein forming the metal contact on the first surface of the semiconductor substrate comprises forming each of the metal contacts on one of the reconnection pillars and contacting the reconnection pillar of the reconnection pillar.

5. The method of claim 1, wherein the metal contact has a height between 20 μm and 150 μm.

6. The method according to claim 1, wherein the third width is less than 20 μm.

7. The method of claim 1, wherein the second width is between 30 μm and 310 μm.

8. The method according to claim 1, further comprising: After the metal contact is formed on the first surface of the semiconductor substrate, the semiconductor substrate is thinned along the second surface of the semiconductor substrate.

9. The method of claim 8, wherein the semiconductor substrate is thinned before forming the first trench of the first width extending into the second surface of the substrate.

10. The method of claim 8, wherein after the second protective resin is formed in the first trench and on the first surface of the semiconductor substrate, the thinning of the semiconductor substrate is performed.

11. A device manufactured by the method of claim 1, comprising: The first side and the second side opposite to the first side; A first resin, at the first side, the first resin includes side wings; The second resin is located on the second side; An integrated circuit is encapsulated within the first resin and the second resin; as well as The metal contact, on the second side, includes a bracket portion protruding from the side wing of the first resin.

12. The device of claim 11, wherein the metal contact is in the second resin.

13. The device according to claim 11, wherein: The metal contact portion further includes an encapsulation portion in the second resin, the encapsulation portion having a first length extending from the bracket portion to a first end of the encapsulation portion in the second resin, the first length being transverse to the side wing of the first resin; as well as The bracket portion has a second length extending from the side wing of the first resin to a second end of the bracket portion opposite the first end of the encapsulation portion, the second length being less than the first length and transverse to the side wing of the first resin.

14. The device of claim 11, wherein the metal contact is one of a plurality of metal contacts.

15. An electronic device, comprising: The first side and the second side opposite to the first side; A first resin layer, at the first side, includes a first surface and side wings transverse to the first surface; The second resin layer is located on the second side; A metal contact element, located on the second side, comprises: The second surface is flush with the first surface of the first resin layer; The third side, opposite to the second side; and The bracket portion protrudes from the side wing; Then connect the post on the third surface of the metal contact; Interconnect stacks, on the reconnection posts; and The integrated circuit is located within the first resin layer and on the interconnect stack.

16. The electronic device according to claim 15, wherein: The metal contact portion further includes an encapsulation portion in the second resin layer, the encapsulation portion having a first length extending from the bracket portion to a first end of the encapsulation portion in the second resin layer, the first length being transverse to the side flange of the first resin layer; and The bracket portion has a second length extending from the side wing of the first resin layer to a second end of the bracket portion opposite to the first end of the encapsulation portion. The second length is less than the first length and is transverse to the side wing of the first resin layer.

17. The electronic device of claim 15, wherein the metal contact is one of a plurality of metal contacts.

18. The electronic device of claim 15, wherein the first resin layer has a first height and the second resin layer has a second height, and the first height is greater than the first height.

19. The electronic device of claim 15, wherein the integrated circuit is encapsulated within the first resin and the second resin.

20. The electronic device of claim 15, wherein the integrated circuit is coupled to the metal contact via the reconnection post and the interconnect stack.

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