Silicon carbide semiconductor device based on modulation region, electronic chip, and electronic device

Abstract

This application provides a silicon carbide semiconductor device, electronic chip, and electronic device based on a modulation region. The silicon carbide semiconductor device includes a substrate, a buffer layer, a drift region, a JFET region, and a modulation region. The buffer layer, drift region, and JFET region are sequentially stacked on the front side of the substrate, and the modulation region is located inside the JFET region, with its surface flush with the surface of the JFET region. This application reduces the current density at the center of the JFET region's internal surface by using the modulation region, alleviating heat concentration at the center of the JFET region's internal surface. This fundamentally solves the problem of heat accumulation caused by carrier transport within the silicon carbide semiconductor device, reducing the likelihood of damage and extending the device's lifespan. It also improves the short-circuit withstand capability of the silicon carbide semiconductor device.

Description

Technical Field

[0001] This application relates to the field of power semiconductor technology, specifically to a silicon carbide semiconductor device, electronic chip, and electronic device based on a modulation region. Background Technology

[0002] With the rapid development of semiconductor technology, silicon carbide and other semiconductor devices have been widely used. When a silicon carbide device experiences a short circuit, the JFET region exhibits a high concentration of electric field and current, with a peak surface current density reaching 10⁻⁶. 4 The temperature is on the order of A / cm², causing the local junction temperature to rise rapidly to over 1500K in a submicrosecond time, triggering thermal runaway and gate oxide electric field breakdown. The short-circuit withstand time is only about 3μs, which is insufficient to meet the system reliability requirements of key areas such as grid connection of new energy power generation and high-voltage direct current transmission.

[0003] Existing silicon carbide semiconductor devices respond to faults through rapid detection protection circuits or drive parameter adjustments. This is essentially external, passive protection and cannot fundamentally solve problems such as heat accumulation caused by internal carrier transport in silicon carbide semiconductor devices, easily leading to damage. While existing technologies can also control the doping of the JFET region to moderately suppress short-circuit current, they are limited by the performance trade-off between on-resistance and short-circuit withstand capability, resulting in poor short-circuit withstand capability of silicon carbide semiconductor devices. Summary of the Invention

[0004] To address the problems of easy damage and poor short-circuit withstand capability of silicon carbide semiconductor devices in the prior art, this application provides a silicon carbide semiconductor device, electronic chip, and electronic device based on a modulation region.

[0005] On one hand, this application provides a silicon carbide semiconductor device based on a modulation region, which may include: A silicon carbide semiconductor device based on a modulation region is characterized by comprising a substrate, a buffer layer, a drift region, a JFET region, and a modulation region.

[0006] A buffer layer, a drift region, and a JFET region are stacked sequentially on the front side of the substrate. The modulation region is located inside the JFET region, and the surface of the modulation region is flush with the surface of the JFET region.

[0007] In some possible implementations, the modulation region includes a P-type doped region, a first N-type doped region, and a second N-type doped region.

[0008] The P-type doped region and the second N-type doped region are stacked inside the JFET region. The first N-type doped region is disposed around the P-type doped region and the second N-type doped region, and a predetermined gap is left between the first N-type doped region and the P-type doped region and the second N-type doped region. The surfaces of the P-type doped region and the first N-type doped region are flush with the surface of the JFET region.

[0009] Furthermore, semiconductor devices also include a P-type body region, an N-type source region, and a P-type body contact region.

[0010] The P-type body region, N-type source region, and P-type body contact region are all located on the front of the drift region and outside the JEFT region. The N-type source region and P-type body contact region are both located inside the P-type body region and are both set perpendicular to the P-type body region.

[0011] In some other possible implementations, the semiconductor device also includes a gate oxide layer and a polysilicon layer. The gate oxide layer and the polysilicon layer are stacked on the surface of the JFET region, with the polysilicon layer located away from the JFET region.

[0012] In some other possible implementations, the semiconductor device also includes a first metal layer and a second metal layer.

[0013] The first metal layer is stacked on the surface of the N-type source region and the P-type body contact region, and the second metal layer is stacked on the back side of the substrate.

[0014] Optionally, the doping concentration of the P-type doped region is greater than the doping concentration of the P-type bulk region.

[0015] The doping concentration of the first N-type doped region is greater than the doping concentration of the drift region.

[0016] The doping concentration in the second N-type doped region is less than that in the drift region.

[0017] Optionally, the doping concentration of the P-type doped region is 1×10⁻⁶. 19 cm -3 ~1×10 21 cm -3 The doping concentration of the first N-type doped region is 1 × 10⁻⁶. 16 cm -3 ~1×10 21 cm -3 The doping concentration of the second N-type doped region is 1×10⁻⁶. 14 cm -3 ~1×10 16 cm -3 .

[0018] The widths of the P-type doped region, the first N-type doped region, and the second N-type doped region are all 0.2µm to 1µm.

[0019] The depths of the P-type doped region, the first N-type doped region, and the second N-type doped region are all 0.2µm to 2µm.

[0020] Furthermore, this application also provides an electronic chip, which may include a circuit board and the aforementioned silicon carbide semiconductor device. The silicon carbide semiconductor device is disposed on the circuit board.

[0021] Furthermore, this application also provides an electronic device including the aforementioned electronic chip. Of course, the electronic device may also include other components, and this application does not limit its scope.

[0022] Compared with the prior art, the beneficial effects of this application are as follows: The silicon carbide semiconductor device based on a modulation region provided in this application includes a substrate, a buffer layer, a drift region, a JFET region, and a modulation region. The buffer layer, drift region, and JFET region are sequentially stacked on the front side of the substrate, and the modulation region is located inside the JFET region, with its surface flush with the surface of the JFET region. This application reduces the current density at the center of the JFET region's internal surface by using the modulation region, alleviating heat concentration at this location. This fundamentally solves the problem of heat accumulation caused by carrier transport within the silicon carbide semiconductor device, reducing the likelihood of damage and extending the device's lifespan. It also improves the short-circuit withstand capability of the silicon carbide semiconductor device.

[0023] This application increases the on-current of silicon carbide semiconductor devices by modulating the region, thereby improving the short-circuit withstand capability of silicon carbide semiconductor devices while effectively reducing the specific on-resistance and on-loss of silicon carbide semiconductor devices.

[0024] This application optimizes the electric field distribution by modulating the region, transferring the peak electric field intensity from the surface of the gate oxide layer to the bulk, optimizing the forward conduction characteristics, reducing the risk of gate oxide layer breakdown, and improving the long-term reliability of silicon carbide semiconductor devices.

[0025] The technical solution provided in this application is compatible with the fabrication process of silicon carbide semiconductor devices. It can be achieved through standard steps such as ion implantation without the need for additional complex processes, and has wide applicability. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1This is a schematic structural diagram of a silicon carbide semiconductor device based on a modulation region, as described in an embodiment of this application. Figure 2 This is a schematic diagram of the depletion region expansion of a silicon carbide semiconductor device during normal operation in an embodiment of this application; Figure 3 This is a diagram showing the depletion region expansion of a silicon carbide semiconductor device under short-circuit conditions in an embodiment of this application. Detailed Implementation

[0028] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0029] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for distinguishing purposes only and should not be construed as indicating or implying relative importance or order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0030] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0031] This application provides a silicon carbide semiconductor device based on a modulation region, such as Figure 1 As shown. The silicon carbide semiconductor device 100 may include a substrate (which may be a silicon carbide substrate, etc.) 1, a buffer layer (which may be an N+ doped buffer layer) 2, a drift region (which may be an N- drift region) 3, a JFET region 7, and a modulation region 8.

[0032] The buffer layer 2, the drift region 3 and the JFET region 7 are stacked sequentially on the front side of the substrate 1. The modulation region 8 is located inside the JFET region 7, and the surface of the modulation region 8 is flush with the surface of the JFET region 7.

[0033] Among some possible implementations, refer to Figure 1 The modulation region 8 includes a P-type doped region 81, a first N-type doped region 82, and a second N-type doped region 83.

[0034] P-type doped region 81 and second N-type doped region 83 are stacked inside the JFET region. A first N-type doped region 82 is disposed around the P-type doped region 81 and the second N-type doped region 83, with a predetermined gap between the first N-type doped region 82 and the P-type doped region 81 and the second N-type doped region 83. The surfaces of both the P-type doped region 81 and the first N-type doped region 82 are flush with the surface of the JFET region.

[0035] The P-type doped region 81 can be used to improve the electric field and current distribution of the semiconductor device 100 and protect the gate oxide layer (see below). The first N-type doped region 82 can be used to optimize the conduction characteristics of the semiconductor device 100. The second N-type doped region 83 can be used to suppress short-circuit saturation current.

[0036] Understandably, the P-type doped region 81, the first N-type doped region 82, and the second N-type doped region 83 are all heavily doped. Therefore, the P-type doped region 81 can also be called the P++ doped region, the first N-type doped region 82 can also be called the N++ doped region, and the second N-type doped region 83 can also be called the N-- doped region.

[0037] Further reference Figure 1 The semiconductor device 100 also includes a P-type body region (also called Pbody region) 4, an N-type source region (which can be an N+ source region) 5, and a P-type body contact region (which can be a P+ body contact region) 6.

[0038] P-type body region 4, N-type source region 5 and P-type body contact region 6 are all located on the front of drift region 3 and are all located outside of JEFT region 7. N-type source region 5 and P-type body contact region 6 are both located inside P-type body region 4 and are both set perpendicular to P-type body region 4.

[0039] In some other possible implementations, the semiconductor device 100 further includes a gate oxide layer 9 and a polysilicon layer (which may be a gate) 10. The gate oxide layer 9 and the polysilicon layer 10 are stacked on the surface of the JFET region 7, with the polysilicon layer 10 located away from the JFET region 7.

[0040] In some other possible implementations, the semiconductor device 100 also includes a first metal layer 11 and a second metal layer 12.

[0041] The first metal layer 11 is stacked on the surface of the N-type source region 5 and the P-type body contact region 6, and the second metal layer 12 is stacked on the back side of the substrate 1.

[0042] In this embodiment, the first metal layer 11 can be used as the source and the second metal layer 12 can be used as the drain.

[0043] Optionally, the doping concentration of the P-type doped region 81 is greater than the doping concentration of the P-type body region 4.

[0044] The doping concentration of the first N-type doped region 82 is greater than that of the drift region 3.

[0045] The doping concentration of the second N-type doped region 83 is less than that of the drift region 3.

[0046] Optionally, the doping concentration of the P-type doped region 81 is 1×10⁻⁶. 19 cm -3 ~1×10 21 cm -3 The doping concentration of the first N-type doped region 82 can be 1×10⁻⁶. 16 cm -3 ~1×10 21 cm -3 The doping concentration of the second N-type doped region 83 can be 1×10⁻⁶. 14 cm -3 ~1×10 16 cm -3 In this embodiment, the doping concentration of the P-type doped region 81 is 2 × 10⁻⁶. 20 cm -3 The doping concentration of the first N-type doped region 82 is 2 × 10⁻⁶. 16 cm -3 The doping concentration of the second N-type doped region 83 is 1×10⁻⁶. 15 cm -3 .

[0047] The widths of the P-type doped region 81, the first N-type doped region 82, and the second N-type doped region 83 can all be 0.2µm to 1µm. In this embodiment, the width of the P-type doped region 81 is 0.5µm, the width of the first N-type doped region 82 is 1µm, and the width of the second N-type doped region 83 is 0.5µm.

[0048] The depths of the P-type doped region 81, the first N-type doped region 82, and the second N-type doped region 83 can all be 0.2µm to 2µm. In this embodiment, the depth of the P-type doped region 81 can be 0.1µm, the depth of the first N-type doped region 82 can be 0.2µm, and the depth of the second N-type doped region 83 can be 0.1µm.

[0049] The doping concentration of substrate 1 is 1×10⁻⁶. 14 cm -3 ~1×10 19 cm -3The thickness is 300µm~500µm. In the embodiments of this application, the doping concentration of substrate 1 is 1×10⁻⁶. 18 cm -3 The thickness is 350µm.

[0050] The doping concentration of buffer layer 2 is 1×10 14 cm -3 ~1×10 18 cm -3 The thickness is 1µm to 10µm. In the embodiments of this application, the doping concentration of the buffer layer 2 is 2×10⁻⁶. 17 cm -3 The thickness is 2µm.

[0051] The doping concentration of drift region 3 can be 1×10 14 cm -3 ~1×10 16 cm -3 The thickness is set to 5µm~150µm according to the required blocking voltage. In this embodiment, the doping concentration of drift region 3 is 2.3×10⁻⁶. 15 cm -3 It has a thickness of 35µm and can withstand a blocking voltage of 3300V.

[0052] The doping concentration of P-type body region 4 can be 1×10⁻⁶. 16 cm -3 ~1×10 19 cm -3 The depth is 0.5µm to 2µm. In the embodiments of this application, the doping concentration of the P-type body region 4 is 3×10⁻⁶. 17 cm -3 The thickness is 1.2µm.

[0053] The doping concentration of N-type source region 5 is 1×10⁵. 18 cm -3 ~1×10 21 cm -3 The depth is 0.2µm to 2µm. In this embodiment, the doping concentration of the N-type source region 5 is 1×10⁻⁶. 19 cm -3 The thickness is 0.4µm.

[0054] The doping concentration of P-type body contact region 6 is 1×10⁶. 18 cm -3 ~1×10 21 cm -3 The depth is 0.2µm to 2µm. In this embodiment, the doping concentration of the P-type body contact region 6 is 1×10⁻⁶. 19 cm -3 The thickness is 0.4µm.

[0055] The doping concentration of JFET region 7 is consistent with that of N-drift region 3, meaning they have the same doping concentration. The doping concentration of JFET region 7 can also be 1 to 5 times that of drift region 3. In this embodiment, the doping concentration of JFET region 7 is 2.3 × 10⁻⁶. 15 cm -3 .

[0056] The gate oxide layer 9 can be made of silicon dioxide or the like, with a thickness of 30 nm to 100 nm. In the embodiments of this application, the thickness of the gate oxide layer 9 is 50 nm.

[0057] In the embodiments of this application, N-type doped ions include nitrogen or phosphorus, etc., and P-type doped ions include aluminum or boron, etc.

[0058] Figure 2 A schematic diagram of the depletion region expansion of a silicon carbide semiconductor device during normal operation is shown. It can be seen that the P-type doped region 81 and the second N-type doped region 83 introduce additional depletion regions; therefore, the on-state current will expand and flow through the JFET region (7) excluding the P-type doped region 81. Furthermore, since a low-resistance first N-type doped region 82 is added to both sides of the P-type doped region 81, the specific on-resistance of the semiconductor device during normal operation can be reduced, increasing the current-carrying capacity of the semiconductor device and reducing the conduction loss of the semiconductor device.

[0059] Figure 3 This diagram illustrates the depletion region expansion of a silicon carbide semiconductor device during a short circuit. When a higher bias voltage is applied to the second metal layer 12, the depletion region generated by the PN junction formed by the P-type body region 4 and the JFET region 7 still expands towards the JFET region 7, which has a lower doping concentration. However, due to the presence of the modulation region 8, the additional depletion region generated by the PN junction formed by the P-type doped region 81 and the JFET region 7 will expand towards the JFET region 7, but the presence of the first N-type doped region 82 can suppress further expansion of this depletion region.

[0060] The additional depletion region generated by the PN junction formed by the P-type doped region 81 and the second N-type doped region 83 will significantly extend towards the second N-type doped region 83. This causes the short-circuit current to no longer be highly concentrated at the center of the inner surface of the JFET region 7, but to diffuse laterally to the left and right sides of the modulation region 8, and then flow into the inversion layer of the P-type body region 4, and then through the N-type source region 5 to the first metal layer 11. The dispersion of the current path results in a larger current distribution area, which alleviates the current accumulation at the center of the inner surface of the JFET region 7 and reduces the surface current density of the JFET region 7. On the other hand, the short-circuit current flows through the second N-type doped region 83 with higher resistance, further reducing the current density of the JFET region 7, reducing power loss during short circuits, and slowing down the temperature accumulation at the center of the inner surface of the JFET region 7, thereby extending the short-circuit withstand time of the device and improving the short-circuit withstand capability of the device.

[0061] In addition, the semiconductor device provided in this application has the function of protecting the gate oxide layer. The P-type doped region 81 and the JEFT region 7 form a vertical PN junction, which, together with the P-type bulk region 4, depletes the conductive region, forcing the depletion region to preferentially merge in the bulk rather than on the surface. This causes the electric field peak to shift from the surface of the gate oxide layer 9 to the lower edge of the P-type doped region 81, significantly reducing the electric field strength of the gate oxide layer and improving the reliability of the gate oxide layer.

[0062] In summary, the embodiments of this application improve the short-circuit characteristics of semiconductor devices, reduce the forward ratio on-resistance and on-loss, and lower the electric field strength of the gate oxide layer by adjusting the electric field and current distribution in the JFET region, thus providing an effective way to optimize the overall performance of the device.

[0063] This application also provides an electronic chip, which may include a circuit board and the aforementioned silicon carbide semiconductor device. The silicon carbide semiconductor device is disposed on the circuit board.

[0064] Of course, the electronic chip can also have other components, and this application does not limit the embodiments.

[0065] This application also provides an electronic device including the aforementioned electronic chip. Of course, the electronic device may include other components, and this application does not limit its scope.

[0066] The above are merely embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application shall be included within the scope of the claims of this application pending approval.

Claims

1. A silicon carbide semiconductor device based on a modulation region, characterized in that, Includes substrate, buffer layer, drift region, JFET region and modulation region; The buffer layer, the drift region, and the JFET region are sequentially stacked on the front side of the substrate. The modulation region is located inside the JFET region, and the surface of the modulation region is flush with the surface of the JFET region.

2. The silicon carbide semiconductor device according to claim 1, characterized in that, The modulation region includes a P-type doped region, a first N-type doped region, and a second N-type doped region; The P-type doped region and the second N-type doped region are stacked inside the JFET region; the first N-type doped region is disposed around the P-type doped region and the second N-type doped region, and a preset gap is left between the first N-type doped region and the P-type doped region and the second N-type doped region; the surfaces of the P-type doped region and the first N-type doped region are flush with the surface of the JFET region.

3. The silicon carbide semiconductor device according to claim 2, characterized in that, The semiconductor device further includes a P-type body region, an N-type source region, and a P-type body contact region; The P-type body region, the N-type source region, and the P-type body contact region are all located on the front of the drift region and outside the JEFT region. The N-type source region and the P-type body contact region are both located inside the P-type body region and are both perpendicular to the P-type body region.

4. The silicon carbide semiconductor device according to claim 3, characterized in that, The doping concentration of the P-type doped region is greater than the doping concentration of the P-type body region; The doping concentration of the first N-type doped region is greater than the doping concentration of the drift region; The doping concentration of the second N-type doped region is less than the doping concentration of the drift region.

5. The silicon carbide semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a gate oxide layer and a polysilicon layer; the gate oxide layer and the polysilicon layer are stacked on the surface of the JFET region, with the polysilicon layer located away from the JFET region.

6. The silicon carbide semiconductor device according to claim 3, characterized in that, The semiconductor device further includes a first metal layer and a second metal layer; The first metal layer is stacked on the surface of the N-type source region and the P-type body contact region, and the second metal layer is stacked on the back side of the substrate.

7. The silicon carbide semiconductor device according to claim 2, characterized in that, The doping concentration of the P-type doped region is 1×10⁻⁶. 19 cm -3 ~1×10 21 cm -3 ; The doping concentration of the first N-type doped region is 1×10 16 cm -3 ~1×10 21 cm -3 ; The doping concentration of the second N-type doped region is 1×10 14 cm -3 ~1×10 16 cm -3 .

8. The silicon carbide semiconductor device according to claim 2, characterized in that, The widths of the P-type doped region, the first N-type doped region, and the second N-type doped region are all 0.2µm to 1µm.

9. The silicon carbide semiconductor device according to claim 2, characterized in that, The depths of the P-type doped region, the first N-type doped region, and the second N-type doped region are all 0.2µm to 2µm.

10. An electronic chip, characterized in that, It includes a circuit board and a silicon carbide semiconductor device as described in any one of claims 1 to 9; the silicon carbide semiconductor device is disposed on the circuit board.

11. An electronic device, characterized in that, Including the electronic chip as described in claim 10.

Images