Display panel

Abstract

This invention provides a display panel including an active layer, a first scan line, and a first reset line. A first electrical connection portion in the active layer is connected between a first sub-active pattern and a second sub-active pattern disposed opposite to each other. A connecting portion of the first electrical connection portion extends along a first direction, with both ends connected to the first sub-active pattern and the second sub-active pattern, respectively. An overlapping portion of the first electrical connection portion extends along a second direction intersecting the first direction and is connected to the connecting portion. The first sub-active pattern and the second sub-active pattern are located on opposite sides of the overlapping portion, respectively. The first scan line extends along the first direction and overlaps with a first channel portion of the first sub-active pattern and a second channel portion of the second sub-active pattern. The first reset line is located on one side of the first scan line and at least partially overlaps with the overlapping portion to form a coupling capacitor, thereby improving low-frequency flicker by utilizing a first reset signal transmitted through the first reset line and the coupling capacitor.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to a display panel. Background Technology

[0002] When an LTPS (Low Temperature Poly-silicon) backplane drives a light-emitting device, the leakage current of the transistor affects the brightness stability of the device. Specifically, a significant leakage current exists between the first reset line (used to reset the gate of the first transistor) and the gate of the first transistor. When the display panel is driven at a low refresh rate, the gate voltage of the driving transistor is affected by the leakage current, causing large fluctuations in the current flowing through the light-emitting device. This results in significant variations in brightness, leading to flickering issues on the display panel. Summary of the Invention

[0003] This invention provides a display panel that can improve the low-frequency flicker problem of display panels.

[0004] This invention provides a display panel including an active layer, a first scan line, and a first reset line. The active layer includes a first sub-active pattern and a second sub-active pattern disposed opposite to each other, and a first electrical connection portion connecting the first sub-active pattern and the second sub-active pattern. The first electrical connection portion includes a connecting portion and an overlapping portion. The first sub-active pattern and the second sub-active pattern are located on opposite sides of the connecting portion, respectively, with the overlapping portion. The connecting portion extends along a first direction, and its two ends are respectively connected to the first sub-active pattern and the second sub-active pattern. The overlapping portion extends along a second direction intersecting the first direction and is connected to the connecting portion. The first sub-active pattern includes a first channel portion, and the second sub-active pattern includes a second channel portion. The first scan line extends along the first direction and overlaps with the first channel portion and the second channel portion. The first reset line is located on one side of the first scan line and at least partially overlaps with the overlapping portion.

[0005] Optionally, in some embodiments of the present invention, the active layer further includes a third sub-active pattern, the third sub-active pattern including a third channel portion; the display panel further includes a second scan line, the second scan line being located on the side of the first reset line away from the first scan line, and overlapping with the third channel portion. The third sub-active pattern is electrically connected between the first reset line and the first electrical connection portion.

[0006] Optionally, in some embodiments of the present invention, the active layer further includes a fourth sub-active pattern and a second electrical connection portion connected between the third sub-active pattern and the fourth sub-active pattern. Both the third and fourth sub-active patterns are located between the first and second electrical connection portions. The fourth sub-active pattern includes a fourth channel portion, and the second scan line overlaps with the fourth channel portion. The first reset line is electrically connected to a portion of the third sub-active pattern located on the side of the first scan line closest to the second scan line via a bridging portion that is separate from the active layer.

[0007] Optionally, in some embodiments of the present invention, a light-emitting device and a pixel driving circuit are further included. The pixel driving circuit includes: a driving transistor connected in series with the light-emitting device between a first power line and a second power line; a compensation transistor including a first sub-transistor and a second sub-transistor connected in series, wherein one of the source and drain of the first sub-transistor is electrically connected to the gate of the driving transistor, the other of the source and drain of the first sub-transistor is electrically connected to one of the source and drain of the second sub-transistor through a connection node, and the other of the source and drain of the second sub-transistor is electrically connected to one of the source and drain of the driving transistor. The gates of both the first sub-transistor and the second sub-transistor are electrically connected to the first scan line. The first sub-transistor includes a first sub-active pattern, and the second sub-transistor includes a second sub-active pattern.

[0008] Optionally, in some embodiments of the present invention, the pixel driving circuit further includes: a reset transistor, comprising a third sub-transistor and a fourth sub-transistor connected in series, wherein one of the source and drain of the third sub-transistor is electrically connected to the first reset line, one of the source and drain of the fourth sub-transistor is electrically connected to the connection node, the other of the source and drain of the third sub-transistor is electrically connected to the other of the source and drain of the fourth sub-transistor, and the gates of the third sub-transistor and the fourth sub-transistor are both electrically connected to the second scan line. The third sub-transistor includes the third sub-active pattern, and the fourth sub-transistor includes the fourth sub-active pattern.

[0009] Optionally, in some embodiments of the present invention, the display panel further includes: a second reset line, located on the side of the second scan line away from the first reset line, and overlapping with the second electrical connection portion.

[0010] Optionally, in some embodiments of the present invention, the second reset line and one of the source and drain of the initialization transistor included in the previous pixel driving circuit adjacent to the pixel driving circuit along the second direction are electrically connected, and the other of the source and drain of the initialization transistor is electrically connected to the anode of the corresponding light-emitting device.

[0011] Optionally, in some embodiments of the present invention, the first reset line and the second reset line are in the same layer and made of the same material.

[0012] Optionally, in some embodiments of the present invention, the pixel driving circuit further includes a data transistor, the source and drain of which are electrically connected between a data line and the other of the source and drain of the driving transistor, and the gate of which is electrically connected to a third scan line. The first reset line is used to transmit a first reset signal, which has a first potential and a second potential; the moment the first reset signal transitions from the first potential to the second potential is the same as the moment the data transistor is turned off; and the difference between the first potential and the gate potential of the driving transistor is greater than the difference between the second potential and the gate potential of the driving transistor.

[0013] Optionally, in some embodiments of the present invention, the second potential is equal to the gate potential of the driving transistor.

[0014] This invention provides a display panel including an active layer, a first scan line, and a first reset line. A first electrical connection portion in the active layer is connected between a first sub-active pattern and a second sub-active pattern disposed opposite to each other. A connecting portion of the first electrical connection portion extends along a first direction, with both ends connected to the first sub-active pattern and the second sub-active pattern, respectively. An overlapping portion of the first electrical connection portion extends along a second direction intersecting the first direction and is connected to the connecting portion. The first sub-active pattern and the second sub-active pattern are located on opposite sides of the overlapping portion, respectively. The first scan line extends along the first direction and overlaps with a first channel portion of the first sub-active pattern and a second channel portion of the second sub-active pattern. The first reset line is located on one side of the first scan line and at least partially overlaps with the overlapping portion to form a coupling capacitor, thereby improving low-frequency flicker by utilizing a first reset signal transmitted through the first reset line and the coupling capacitor. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1A This is a magnified view of the overlap between the first reset line and the capacitive active pattern.

[0017] Figure 1B yes Figure 1A A sectional view cut along p-p';

[0018] Figure 1C yes Figure 1A A sectional view cut along z-z'.

[0019] Figure 2 This is a schematic diagram of the pixel driving circuit provided in an embodiment of the present invention;

[0020] Figure 3 This is a timing diagram of the pixel driving circuit provided in an embodiment of the present invention;

[0021] Figure 4 This is a schematic diagram of display brightness changes provided in an embodiment of the present invention;

[0022] Figure 5 This is a schematic diagram of the film structure of the pixel driving circuit provided in an embodiment of the present invention;

[0023] Figure 6 This is a schematic diagram of the active layer structure provided in an embodiment of the present invention;

[0024] Figure 7 This is a schematic diagram of the structure of the first conductive layer provided in an embodiment of the present invention;

[0025] Figure 8 This is a schematic diagram of the structure of the second conductive layer provided in an embodiment of the present invention;

[0026] Figure 9 This is a schematic diagram of the structure of the third conductive layer provided in an embodiment of the present invention;

[0027] Figure 10 This is a schematic diagram of the structure of the fourth conductive layer provided in an embodiment of the present invention. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of the present invention and are not intended to limit the present invention. In the present invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0029] Specifically, such as Figure 1A This is a magnified view of the overlap between the first reset line and the capacitive active pattern. Figure 1B yes Figure 1A A sectional view cut along p-p'. Figure 1C yes Figure 1A A cross-sectional view taken along z-z'. The present invention provides a display panel, including a substrate 100, an active layer 101, a first scan line SL1, and a first reset line VL1.

[0030] Optionally, the substrate 100 includes a rigid substrate and a flexible substrate. Optionally, the substrate 100 includes glass, polyimide, quartz, etc. Optionally, a buffer layer 100a is also provided on the substrate 100.

[0031] An active layer 101 is located on a substrate 100. The active layer 101 includes a first sub-active pattern and a second sub-active pattern disposed opposite to each other, and a first electrical connection portion connecting the first sub-active pattern and the second sub-active pattern. The first sub-active pattern includes a first channel portion Cp1, and the second sub-active pattern includes a second channel portion Cp2. The first electrical connection portion includes a connection portion Cn1 and an overlapping portion Cn2. The first sub-active pattern and the second sub-active pattern are located on opposite sides of the overlapping portion Cn2, respectively. The connection portion Cn1 extends along a first direction x, and its two ends are respectively connected to the first sub-active pattern and the second sub-active pattern. The overlapping portion Cn2 extends along a second direction y that intersects the first direction x, and is connected to the connection portion Cn1.

[0032] Optionally, the active layer 101 comprises a silicon semiconductor material or an oxide semiconductor material. Optionally, the silicon semiconductor material includes monocrystalline silicon, polycrystalline silicon, etc.; the oxide semiconductor material may include indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), or indium gallium zinc tin oxide (IGZTO), etc. Optionally, the active layer 101 is fabricated using a low-temperature polycrystalline silicon process.

[0033] The first scan line SL1 extends along the first direction x and overlaps with the first channel portion Cp1 and the second channel portion Cp2.

[0034] The first reset line VL1 is located on one side of the first scan line SL1, and the first reset line VL1 overlaps with the first electrical connection portion to form the two electrodes of the coupling capacitor Co. Optionally, the first reset line VL1 overlaps with the connection portion Cn1 and / or the overlapping portion Cn2, so that the capacitance value of the coupling capacitor meets the design requirements. Optionally, the first reset line VL1 and the overlapping portion Cn2 at least partially overlap to form a coupling capacitor, thereby utilizing the first reset signal Vi1 transmitted by the first reset line VL1 and the coupling capacitor to achieve a solution to improve the flicker problem.

[0035] Alternatively, please continue reading Figures 1B-1C The first reset line VL1 is located on or below the active layer 101. Optionally, the display panel further includes a first conductive layer 102 located on the active layer 101, the first conductive layer 102 including the first reset line VL1. Optionally, the first conductive layer 102 includes at least one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). Optionally, the first conductive layer 102 can be a single-layer film structure, or a stacked structure such as Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Cu / Mo, Cu / Ti, Cu / MoTi, or Cu / MoNb.

[0036] Optionally, the display panel further includes an insulating layer located between the first conductive layer 102 and the active layer 101. Optionally, the insulating layer includes a first insulating layer 1001 and a second insulating layer 1002. Optionally, the first insulating layer 1001 and the second insulating layer 1002 may respectively include silicon compounds, metal oxides, etc. Further, the first insulating layer 1001 and the second insulating layer 1002 may respectively include silicon oxide, silicon nitride, silicon nitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc.

[0037] Figures 1B-1C 100b in the text refers to a multilayer composite insulation layer (which includes an interlayer dielectric layer and a first planarization layer, etc.).

[0038] Please continue reading. Figure 1AThe active layer 101 further includes a third sub-active pattern, which includes a third channel portion Cp3. The display panel also includes a second scan line SL21, which is located on the side of the first reset line VL1 away from the first scan line SL1 and overlaps with the third channel portion Cp3. The third sub-active pattern Cp3 is electrically connected between the first reset line VL1 and the first electrical connection portion to adjust the potential of the first electrical connection portion using the first reset signal Vi1 transmitted by the first reset line VL1.

[0039] Optionally, the first reset line VL1 is electrically connected to the portion of the third sub-active pattern located on the side of the first scan line SL1 near the second scan line SL21 via a bridging portion F3 that is different from the first reset line VL1 and the active layer 101, so that the first reset line VL1 and the third sub-active pattern are electrically connected via the bridging portion F3.

[0040] Optionally, the active layer 101 further includes a fourth sub-active pattern and a second electrical connection portion Cn3 connecting the third and fourth sub-active patterns. Both the third and fourth sub-active patterns are located between the first and second electrical connection portions Cn3. The fourth sub-active pattern includes a fourth channel portion Cp4, and the second scan line SL21 overlaps with the fourth channel portion Cp4. Optionally, the two ends of the overlapping portion Cn2 are connected between the fourth sub-active pattern and the connection portion Cn1.

[0041] Optionally, the display panel also includes a second reset line VL22, which is located on the side of the second scan line SL21 away from the first reset line VL1 and overlaps with the second electrical connection Cn3 to form another capacitor to further improve the flicker problem.

[0042] like Figure 2 This is a schematic diagram of the pixel driving circuit provided in an embodiment of the present invention. Figure 3 This is a timing diagram of the pixel driving circuit provided in an embodiment of the present invention. The display panel also includes multiple light-emitting devices D, multiple pixel driving circuits, and multiple signal lines.

[0043] Multiple light-emitting devices D and multiple pixel driving circuits are electrically connected, and the multiple pixel driving circuits are used to drive the multiple light-emitting devices D to emit light. Optionally, the light-emitting devices D include organic light-emitting diodes, sub-millimeter light-emitting diodes, micro light-emitting diodes, etc.

[0044] Optionally, the multiple signal lines include multiple scan lines, multiple data lines DL, multiple light emission control lines EML, a first reset line VL1, a first sub-reset line VL21, and a second reset line VL22.

[0045] Multiple scan lines are used to transmit multiple scan signals. These scan lines include multiple first scan lines SL1, multiple second scan lines SL21, multiple third scan lines SL22, and multiple fourth scan lines SL23. First scan line SL1 transmits the first scan signal S1, while second scan lines SL21, SL22, and SL23 transmit the second scan signal S2. Multiple data lines DL transmit multiple data signals, and multiple light emission control lines EML transmit multiple light emission control signals. A first reset line VL1 transmits the first reset signal Vi1, and first sub-reset lines VL21 and VL22 transmit the second reset signal.

[0046] Optionally, the frequency of the first scan signal S1 is lower than the frequency of the second scan signal S2. Optionally, the effective pulse of the first scan signal S1 is located within the write frame WF of a display cycle, and the effective pulse of the second scan signal S2 is located within the write frame WF and the hold frame HF of a display cycle. Wherein, when a display cycle includes the hold frame HF, the display panel employs a low refresh rate driving method.

[0047] Optionally, the display panel further includes multiple gating drive circuits, including multiple cascaded first gating drive circuits, multiple cascaded second gating drive circuits, and multiple cascaded third gating drive circuits. The multiple cascaded first gating drive circuits are electrically connected to multiple first scan lines SL1 to provide multiple first scan signals S1 to the multiple first scan lines SL1; the multiple cascaded second gating drive circuits are electrically connected to multiple second scan lines SL21, multiple third scan lines SL22, and multiple fourth scan lines SL23 to provide multiple second scan signals S2 to the multiple second scan lines SL21, multiple third scan lines SL22, and multiple fourth scan lines SL23; and the multiple cascaded third gating drive circuits are electrically connected to multiple light emission control lines EML to provide multiple light emission control signals EM to the multiple light emission control lines EML.

[0048] Each pixel driving circuit is electrically connected to the corresponding scan line, the corresponding data line DL, the corresponding light emission control line EML, the first reset line VL1, and the first sub-reset line VL21, so as to control the corresponding light emission device D to emit light according to the corresponding scan signal, data signal, light emission control signal, and reset signal.

[0049] Please continue reading. Figure 2 At least one pixel driving circuit includes a driving transistor T1, a compensation transistor, a reset transistor, and a coupling capacitor Co.

[0050] The source and drain of the driving transistor T1 are connected in series with the light-emitting device D between the first power line VDD and the second power line VSS, and are used to generate a driving current to drive the light-emitting device D to emit light according to the data signal transmitted to the gate of the driving transistor T1.

[0051] The compensation transistor includes a first sub-transistor TL1 and a second sub-transistor TL2 connected in series, with a connection node A between them. One of the source and drain of the first sub-transistor TL1 is electrically connected to the gate of the driving transistor T1. The other of the source and drain of the first sub-transistor TL1 is electrically connected to one of the source and drain of the second sub-transistor TL2 via connection node A. The other of the source and drain of the second sub-transistor TL2 is electrically connected to one of the source and drain of the driving transistor T1. The gates of both the first sub-transistor TL1 and the second sub-transistor TL2 are electrically connected to a first scan line SL1. The first sub-transistor TL1 includes a first sub-active pattern, and the second sub-transistor TL2 includes a second sub-active pattern. Optionally, when driving the light-emitting device D in the nth row, the first scan line SL1, where the gates of the first sub-transistor TL1 and the second sub-transistor TL2 are electrically connected, transmits the first scan signal S1(n) of the nth stage. Here, n is greater than or equal to 1.

[0052] The source and drain of the reset transistor are electrically connected between the first reset line VL1 and the connection node A, and the gate of the reset transistor is electrically connected to the second scan line SL21. The reset transistor is used to transmit the first reset signal Vi1 to the connection node A according to the second scan signal transmitted by the second scan line SL21.

[0053] Optionally, the reset transistor includes a third sub-transistor TL3 and a fourth sub-transistor TL4 connected in series. One of the source and drain of the third sub-transistor TL3 is electrically connected to the first reset line VL1. One of the source and drain of the fourth sub-transistor TL4 is electrically connected to the connection node A. The other of the source and drain of the fourth sub-transistor TL4 is electrically connected to the other of the source and drain of the third sub-transistor TL3. The gates of both the third sub-transistor TL3 and the fourth sub-transistor TL4 are electrically connected to the second scan line SL21. The third sub-transistor TL3 includes a third sub-active pattern, and the fourth sub-transistor TL4 includes a fourth sub-active pattern.

[0054] The coupling capacitor Co is connected in series between the first reset line VL1 and the connection node A to maintain the potential of the connection node A.

[0055] Since the coupling capacitor Co is connected in series between the first reset line VL1 and the connection node A, and the source and drain of the reset transistor are electrically connected between the first reset line VL1 and the connection node A, when the reset transistor is turned on, the first reset signal Vi1 can be directly transmitted to the connection node A via the reset transistor. When the reset transistor is not turned on, the first reset signal Vi1 can be coupled to the connection node A via the coupling capacitor Co.

[0056] Please continue reading. Figure 2 The at least one pixel driving circuit also includes a data transistor T2. The source and drain of the data transistor T2 are electrically connected between the data line DL and the other of the source and drain of the driving transistor T1. The gate of the data transistor T2 is electrically connected to the third scan line SL22. The data transistor T2 is used to transmit a data signal to the gate of the driving transistor T1 according to the second scan signal S2 transmitted by the third scan line SL22. The second scan signal transmitted by the third scan line SL22 is valid after the second scan signal transmitted by the second scan line SL21. That is, when driving the light-emitting device D in the nth row, the third scan line SL22, to which the gate of the data transistor T2 is electrically connected, transmits the second scan signal S2(n) of the nth level, and the second scan line SL21, to which the gate of the reset transistor is electrically connected, transmits the second scan signal S2(n-1) of the (n-1)th level.

[0057] Optionally, the first reset signal Vi1 has a first potential V1 and a second potential V2. The first reset signal Vi1 transitions from the first potential V1 to the second potential V2 after the data signal is transmitted to the gate of the driving transistor T1. The difference between the first potential V1 and the gate potential of the driving transistor T1 is greater than the difference between the second potential V2 and the gate potential of the driving transistor T1. This reduces the leakage current between the connection node A and the gate of the driving transistor T1 during the light-emitting phase when the driving transistor T1 drives the light-emitting device D to emit light, thereby improving the low-frequency flicker problem.

[0058] Optionally, the second potential V2 is close to the gate potential of the driving transistor T1. Optionally, the second potential V2 is equal to the gate potential of the driving transistor T1, so that during the light-emitting stage when the driving transistor T1 drives the light-emitting device D to emit light, the leakage current between the connection node A and the gate of the driving transistor T1 is reduced by making the connection node A and the gate of the driving transistor T1 at the same potential, thereby improving the low-frequency flicker problem. It is understood that, due to the influence of signal transmission, manufacturing process and other factors, the second potential V2 being equal to the gate potential of the driving transistor T1 should be understood as the second potential V2 being basically close to the gate potential of the driving transistor T1, that is, the difference between the second potential V2 and the gate potential of the driving transistor T1 may not be zero.

[0059] Optionally, the moment when the first reset signal Vi1 jumps from the first potential V1 to the second potential V2 is the same as the moment when the data transistor T2 is turned off, so that after the data signal is transmitted to the gate of the driving transistor T1, the difference between the potential of the first node A and the gate potential of the driving transistor T1 is immediately reduced, thereby reducing the influence of the potential of the first node A on the gate potential of the driving transistor T1, and consequently reducing the brightness variation of the light-emitting device D.

[0060] Optionally, the data signal transitions from a third potential to a fourth potential at the moment the write frame WF switches to the hold frame HF. The third potential is lower than the fourth potential, so that the driving transistor T1 is biased and turned on using the fourth potential within the hold frame HF, thereby improving the hysteresis effect of the driving transistor T1 and facilitating stable drive current. Optionally, the first reset signal Vi1 transitions from the first potential V1 to the second potential V2 at the same time as the data signal transitions from the third potential to the fourth potential, so as to reduce the difference between the potential of the first node A and the gate potential of the driving transistor T1 within the hold frame HF. The write frame WF includes the stage where the data signal is transmitted to the gate of the driving transistor T1, while the hold frame HF does not include the stage where the data signal is transmitted to the gate of the driving transistor T1.

[0061] After the first reset signal Vi1 jumps from the first potential V1 to the second potential V2, the potential at connection node A changes due to the coupling capacitance Co. Furthermore, one of the source and drain terminals of the reset transistor also receives the first reset signal Vi1. Therefore, the voltage difference between the source and drain of the reset transistor decreases, making the potential of the one electrically connected to the first reset signal Vi1 in the reset transistor close to the potential of connection node A. Consequently, there is no leakage path between the gate of the driving transistor T1 and the first reset line connected via the reset transistor. The degree of leakage from connection node A to the first reset line via the reset transistor is reduced, further reducing the degree of leakage from the gate of the driving transistor T1 to the first reset line via the reset transistor. In other words, compared to the prior art design where the source and drain of the reset transistor are electrically connected to the other of the source and drain of the second sub-transistor TL2 and the first reset line VL1, this application can reduce the degree of leakage from the gate of the driving transistor T1 to the first reset line VL1 via the reset transistor, thus improving the low-frequency drive flicker problem.

[0062] Please continue reading. Figure 2 The at least one pixel driving circuit also includes a compensation transistor T3, a first switching transistor T4, a second switching transistor T5, an initialization transistor T6, and a storage capacitor Cst.

[0063] The source and drain of compensation transistor T3 are electrically connected between one of the source and drain of driving transistor T1 and the other of the source and drain of second sub-transistor TL2. The gate of compensation transistor T3 is electrically connected to the third scan line SL22. Compensation transistor T3 is used to cooperate with data transistor T2 to transmit the data signal to the gate of driving transistor T1 according to the second scan signal S2 transmitted by the third scan line SL22.

[0064] The source and drain of the first switching transistor T4 are electrically connected between the other of the source and drain of the driving transistor T1 and the first power supply line VDD. The source and drain of the second switching transistor T5 are electrically connected between the one of the source and drain of the driving transistor T1 and the first node B. The gates of both the first switching transistor T4 and the second switching transistor T5 are electrically connected to the light-emitting control line EML. The first switching transistor T4 and the second switching transistor T5 are used to drive the driving transistor T1 to drive the light-emitting device D to emit light according to the light-emitting control signal EM transmitted by the light-emitting control line EML. Optionally, when driving the light-emitting device D in the nth row, the light-emitting control line EML, to which the gates of the first switching transistor T4 and the second switching transistor T5 are electrically connected, transmits the light-emitting control signal EM(n) of the nth level.

[0065] The source and drain of the initialization transistor T6 are electrically connected between the first sub-reset line VL21 and the first node B, and the gate of the initialization transistor T6 is electrically connected to the fourth scan line SL23. The initialization transistor T6 is used to transmit the second reset signal transmitted by the first sub-reset line VL21 to the first node B according to the second scan signal transmitted by the fourth scan line SL23. Optionally, when driving the light-emitting device D in the nth row, the fourth scan line SL23, to which the gate of the initialization transistor T6 is electrically connected, transmits the second scan signal SL2(n) of the nth level or the second scan signal SL2(n-1) of the (n-1)th level.

[0066] The light-emitting device D is electrically connected between the first node B and the second power line VSS. The storage capacitor Cst is connected in series between the first power line VDD and the gate of the driving transistor T1 to maintain the gate potential of the driving transistor T1.

[0067] Understandably, a single-pixel driving circuit can also drive multiple light-emitting devices D. Optionally, when a single-pixel driving circuit drives multiple light-emitting devices D, the multiple light-emitting devices D can be connected in parallel and / or in series. Each transistor in the pixel driving circuit comprises a silicon semiconductor material. Optionally, the silicon semiconductor material includes polycrystalline silicon, monocrystalline silicon, etc.

[0068] Please continue reading. Figures 2-3Taking the pixel driving circuit as an example where each transistor in the pixel driving circuit is a P-type transistor and the pixel driving circuit drives the light-emitting device D in the nth row to emit light, the working principle of the pixel driving circuit is explained.

[0069] During the reset phase t1, the first scan signal S1(n) transmitted by the first scan line SL1 and the second scan signal S2(n-1) transmitted by the second scan line SL21 are valid. The first sub-transistor TL1, the second sub-transistor TL2, the third sub-transistor TL3 and the fourth sub-transistor TL4 are turned on. The first reset signal Vi1 transmitted by the first reset line VL1 is transmitted to the gate of the driving transistor T1 through the third sub-transistor TL3, the fourth sub-transistor TL4 and the first sub-transistor TL1 to reset the gate potential of the driving transistor T1.

[0070] During the data writing phase t2, the first scan signal S1(n) transmitted by the first scan line SL1 and the second scan signal S2(n) transmitted by the third scan line SL22 and the fourth scan line SL23 are active. The first sub-transistor TL1, the second sub-transistor TL2, the data transistor T2, the compensation transistor T3, and the initialization transistor T6 are turned on. The data signal transmitted by the data line DL is transmitted to the gate of the driving transistor T1 via the data transistor T2, the compensation transistor T3, the second sub-transistor TL2, and the first sub-transistor TL1. The second reset signal transmitted by the first sub-reset line VL21 is transmitted to the first node B via the initialization transistor T6 to reset the anode potential of the light-emitting device D.

[0071] During the light-emitting stage t3, the light-emitting control signal EM(n) transmitted by the light-emitting control line EML is valid. The first switching transistor T4 and the second switching transistor T5 turn on in response to the light-emitting control signal EM(n), and the driving transistor T1 generates the driving current to drive the light-emitting device D to emit light.

[0072] When driving the display using low frequency, a display cycle includes at least one hold frame HF, and the data displayed in the hold frame HF is consistent with the data displayed in the write frame WF. Therefore, it can be understood that the light emission stage t3 extends from the write frame WF to the hold frame HF. The effective pulse of the second scan signal in the hold frame HF can correct the gate potential of the driving transistor T1 in the hold frame HF, thereby adjusting the brightness of the light-emitting device D. Specifically, in the hold frame HF, the driving transistor T1 is biased and turned on using the data transistor T2 and the data signal with the fourth potential to improve the hysteresis effect of the driving transistor T1; the first node B is reset using the initialization transistor T6 and the second reset signal; the connection node A is reset using the reset transistor and the first reset signal with the second potential V2, so that the potential of the connection node A is continuously corrected and pulled to a potential close to the gate potential of the driving transistor T1. Furthermore, when the reset transistor is in the off state according to the invalid pulse of the second scan signal, the potential of the connection node A can be maintained by the coupling capacitor Co, thereby reducing the leakage current between the gate of the driving transistor T1 and the connection node A, as well as reducing the leakage current of the gate of the driving transistor T1 to the first reset line VL1 through the reset transistor, thereby improving the low-frequency drive flicker problem and improving the display quality during low-frequency drive.

[0073] Optionally, the frequency of the light-emitting control signal EM(n) is greater than the frequency of the first scan signal S1(n) to improve the low-frequency flicker problem by continuously changing the brightness of the light-emitting device D. By setting the coupling capacitor Co, the potential of the connection node A after reset can be stabilized, which helps to reduce the leakage current between the gate of the driving transistor T1 and the connection node A, thereby improving the flicker problem caused by large brightness fluctuations during the light-emitting phase and improving the display effect of low-frequency driving.

[0074] like Figure 4 This is a schematic diagram of display brightness variation provided by an embodiment of the present invention; wherein, L1 represents the display brightness variation curve obtained by driving the light-emitting device using the pixel driving circuit of the present application, which varies with the gate potential of the driving transistor T1; and L2 represents the display brightness variation curve obtained by driving the light-emitting device using a pixel driving circuit in the prior art (the pixel driving circuit in the prior art has a design without coupling capacitors), which varies with the gate potential of the driving transistor T1. By comparison, it can be seen that within one display cycle (1 Display), the brightness variation amplitude of the light-emitting device D corresponding to L1 is smaller than the brightness variation amplitude of the light-emitting device corresponding to L2, that is, the brightness variation amount ΔL1 of the light-emitting device D corresponding to L1 is smaller than the brightness variation amount ΔL2 of the light-emitting device corresponding to L2. Therefore, the low-frequency driving flicker problem can be improved.

[0075] like Figure 5 This is a schematic diagram of the film structure of the pixel driving circuit provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of the active layer structure provided in an embodiment of the present invention. A first electrical connection portion is connected between a first sub-active pattern and a second sub-active pattern to serve as a connection node A. The conductivity of the first electrical connection portion is higher than that of the first sub-active pattern and the second sub-active pattern, so that the first sub-active pattern and the second sub-active pattern can be electrically connected by the first electrical connection portion.

[0076] The two ends of the connecting part Cn1 are respectively connected to the first end STL1 of the first sub-active pattern and the second end DTL2 of the second sub-active pattern. The overlapping part Cn2 is connected to the connecting part Cn1 and is located on the side of the connecting part Cn1 away from the first sub-active pattern and the second sub-active pattern.

[0077] Optionally, the active layer 101 further includes a first active pattern of driving transistor T1, a second active pattern of data transistor T2, a third active pattern of compensation transistor T3, a fourth active pattern of first switching transistor T4, a fifth active pattern of second switching transistor T5, and a sixth active pattern of initialization transistor T6, so that the display panel can be fabricated using existing manufacturing processes, thereby achieving a lower manufacturing cost than LTPO backplane.

[0078] Optionally, the two ends of the second electrical connection portion Cn3 are respectively connected to the first end STL3 of the third sub-active pattern and the second end DTL4 of the fourth sub-active pattern. The second end DTL3 of the third sub-active pattern is electrically connected to the first reset line VL1, and the first end STL4 of the fourth sub-active pattern is connected to the end of the overlapping portion Cn2 away from the connection portion Cn1.

[0079] The first end ST1 of the first active pattern is connected to the second end DT2 of the second active pattern and the second end DT4 of the fourth active pattern; the second end DT1 of the first active pattern is connected to the first end ST3 of the third active pattern and the first end ST5 of the fifth active pattern, and the second end DT5 of the fifth active pattern is connected to the first end ST6 of the sixth active pattern. The second and third active patterns both extend along the second direction y and are spaced apart, and the second end DT3 of the third active pattern is connected to the first end ST12 of the second sub-active pattern.

[0080] like Figure 7This is a schematic diagram of the structure of the first conductive layer provided in an embodiment of the present invention. The first conductive layer 102 further includes a first reset line VL1. Optionally, the first reset line VL1 includes a first sub-part VL11, a second sub-part VL12, and a third sub-part VL13. The first sub-part VL11 and the second sub-part VL12 extend along a first direction x, and the third sub-part VL13 connects between the first sub-part VL11 and the second sub-part VL12. Wherein, when the capacitance value of the required coupling capacitor Co is small, the third sub-part VL13 partially overlaps with the overlapping part Cn2, and the extension line between the first sub-part VL11 and the second sub-part VL12 overlaps with the connecting part Cn1.

[0081] The first reset line VL1 and the second reset line VL22 are in the same layer and made of the same material. Optionally, the first conductive layer 102 further includes the second reset line VL22, which is electrically connected to one of the source and drain of the initialization transistor in the previous pixel driving circuit adjacent to the pixel driving circuit along the second direction y. The other of the source and drain of the initialization transistor is electrically connected to the anode of the corresponding light-emitting device D. That is, the second reset line VL22 is the first sub-reset line of the previous pixel driving circuit.

[0082] Optionally, a portion of the second reset line VL22 overlaps with the second electrical connection Cn3 to form another capacitor, thereby maintaining the intermediate node between the third sub-transistor TL3 and the fourth sub-transistor TL4 (i.e., Figure 2 The potential of point C in the middle reduces the influence of the intermediate node potential of the third sub-transistor TL3 and the fourth sub-transistor TL4 on the gate potential of the driving transistor T1.

[0083] Optionally, the first conductive layer 102 further includes a first sub-reset line VL21, a first power line VDD, and a first electrode portion E1 connected to and electrically connected to the first power line VDD. The first power line VDD is located between the first sub-reset line VL21 and the first reset line VL1; the first electrode portion E1 is located on the side of the first power line VDD away from the first reset line VL1, and the first electrode portion E1 overlaps with the first active pattern.

[0084] like Figure 8 This is a schematic diagram of the structure of the second conductive layer provided in an embodiment of the present invention; the display panel further includes a second conductive layer, which is located between the first insulating layer 1001 and the second insulating layer 1002. Optionally, the second conductive layer includes a first scan line SL1, a second scan line SL21, a third scan line SL22, a fourth scan line SL23, and a light emission control line EML.

[0085] The first scan line SL1 and the first reset line VL1 are spaced apart. The first scan line SL1 is located on one side of the first reset line VL1. The second scan line SL21 is located on the side of the first reset line VL1 away from the first scan line SL1. The second sub-reset line VL22 is located on the side of the second scan line SL21 away from the first reset line VL1. The third scan line SL22 is located between the first power line VDD and the first scan line SL1. The light emission control line EML is located between the first power line VDD and the first sub-reset line VL21. The fourth scan line SL23 is located on the side of the first sub-reset line VL21 away from the light emission control line EML. The first electrode part E1 is located on the side of the first power line VDD away from the third scan line SL22.

[0086] The portion of the first scan line SL1 that overlaps with the first sub-active pattern serves as the gate of the first sub-transistor TL1, and the portion of the first scan line SL1 that overlaps with the second sub-active pattern serves as the gate of the second sub-transistor TL2. The portion of the second scan line SL21 that overlaps with the third sub-active pattern serves as the gate of the third sub-transistor TL3, and the portion of the second scan line SL21 that overlaps with the fourth sub-active pattern serves as the gate of the fourth sub-transistor TL4. A portion of the third scan line SL22 overlaps with both the second and third active patterns; the portion of the third scan line SL22 that overlaps with the second active pattern serves as the gate of the data transistor T2, and the portion of the third scan line SL22 that overlaps with the third active pattern serves as the gate of the compensation transistor T3. A portion of the light-emitting control line EML overlaps with both the fourth and fifth active patterns; the portion of the light-emitting control line EML that overlaps with the fourth active pattern serves as the gate of the first switching transistor T4, and the portion of the light-emitting control line EML that overlaps with the fifth active pattern serves as the gate of the second switching transistor T5. A portion of the fourth scan line SL23 overlaps with a portion of the sixth active pattern, and the overlapping portion of the fourth scan line SL23 and the sixth active pattern is used as the gate of the initialization transistor T6.

[0087] Optionally, the second conductive layer further includes a second electrode portion E2 overlapping the first active pattern, the second electrode portion E2 serving as the gate of the driving transistor T1. The first electrode portion E1 and the second electrode portion E2 overlap to serve as the two electrodes of the storage capacitor Cst.

[0088] The connecting portion Cn1 is located between the first scan line SL1 and the third sub-part VL13. The second end DTL1 of the first sub-active pattern and the first end STL2 of the second sub-active pattern are both located on the side of the first scan line SL1 away from the first reset line VL1. Optionally, the first end ST2 of the second active pattern, the second end DT3 of the third active pattern, the second end DTL1 of the first sub-active pattern, and the first end STL2 of the second sub-active pattern are all located between the third scan line SL22 and the first scan line SL1. The second end DTL3 of the third sub-active pattern and the first end STL4 of the fourth sub-active pattern are both located between the first reset line VL1 and the second scan line SL21.

[0089] The first active pattern is located between the third scan line SL22 and the light emission control line EML. The first end ST4 of the fourth active pattern and the second end DT5 of the fifth active pattern are both located between the light emission control line EML and the first sub-reset line VL21. The second end DT6 of the sixth active pattern is located on the side of the fourth scan line SL23 away from the first sub-reset line VL21. Optionally, the first active pattern is U-shaped.

[0090] like Figure 9 This is a schematic diagram of the structure of the third conductive layer provided in an embodiment of the present invention; the display panel also includes an interlayer dielectric layer and a third conductive layer located on the first conductive layer. The third conductive layer includes a first conductive portion F1, a second conductive portion F2, a bridging portion F3, a fourth conductive portion F4, a fifth conductive portion F5, and a sixth conductive portion F6.

[0091] The first conductive portion F1 extends along the second direction y and is electrically connected between the second electrode portion E2 and the second end DTL1 of the first sub-active pattern, thereby realizing the electrical connection between the gate of the driving transistor T1 and the first sub-transistor TL1. Specifically, the first electrode portion E1 includes a first opening that exposes the second electrode portion E2, and the first conductive portion F1 is electrically connected to the second electrode portion E2 through the first opening and a via penetrating the interlayer dielectric layer and the second insulating layer (e.g., Figure 9 At CNT1 in the diagram, the second terminal DTL1 of the first sub-active pattern is electrically connected through a via penetrating the interlayer dielectric layer, the second insulating layer, and the first insulating layer 1001 (e.g., at CNT1 in the diagram). Figure 9 (CNT2 in the middle).

[0092] The second conductive portion F2 overlaps with the first end ST2 of the second active pattern to serve as the source of the data transistor T2. Specifically, the second conductive portion F2 is electrically connected to the first end ST2 of the second active pattern through a via penetrating the interlayer dielectric layer, the second insulating layer 1002, and the first insulating layer 1001 (e.g., ...). Figure 9 (at CNT3 in the transistor) to be used as the source of data transistor T2.

[0093] The bridging portion F3 is electrically connected between the second terminal DTL3 of the third sub-active pattern and the first reset line VL1 to achieve an electrical connection between the third sub-transistor TL3 and the first reset line VL1. Specifically, the bridging portion F3 is electrically connected to the second terminal DTL3 of the third sub-active pattern through a via penetrating the interlayer dielectric layer, the second insulating layer 1002, and the first insulating layer 1001 (e.g., ...). Figure 9 At CNT4 in the middle, it is electrically connected to the first reset line VL1 through a via penetrating the interlayer dielectric layer (e.g., at CNT4 in the middle). Figure 9 (CNT5 in the middle).

[0094] The fourth conductive portion F4 extends along the second direction y and is electrically connected between the first electrode portion E1 and the first end ST4 of the fourth active pattern to achieve electrical connection between the first switching transistor T4 and the first power line VDD. Specifically, the fourth conductive portion F4 is electrically connected to the first electrode portion E1 through a via penetrating the interlayer dielectric layer (e.g., ...). Figure 9 At CNT6 in the diagram, it is electrically connected to the first end ST4 of the fourth active pattern via a via penetrating the interlayer dielectric layer, the second insulating layer 1002, and the first insulating layer 1001 (e.g., at CNT6 in the diagram). Figure 9 (CNT7 in the middle).

[0095] The fifth conductive portion F5 extends along the second direction y and overlaps with the first electrode portion E1, the light-emitting control line EML, and the fifth active pattern portion, and is electrically connected to the second end DT5 of the fifth active pattern to serve as the first node B. Specifically, the fifth conductive portion F5 is electrically connected to the second end DT5 of the fifth active pattern through a via penetrating the interlayer dielectric layer, the second insulating layer 1002, and the first insulating layer 1001 (e.g., ...). Figure 9 (CNT8 in the middle).

[0096] The sixth conductive portion F6 is electrically connected between the second terminal DT6 of the sixth active pattern and the first sub-reset line VL21 to realize the electrical connection between the initialization transistor T6 and the first sub-reset line VL21. Specifically, the sixth conductive portion F6 is electrically connected to the second terminal DT6 of the sixth active pattern through a via penetrating the interlayer dielectric layer, the second insulating layer 1002, and the first insulating layer 1001 (e.g., Figure 9 At CNT9 in the middle), it is electrically connected through the first sub-reset line VL21 via the via penetrating the interlayer dielectric layer (e.g., at CNT9). Figure 9 (CNT10 in the middle).

[0097] Optionally, the third conductive layer further includes a seventh conductive portion F7, which overlaps with the first end STL2 of the second sub-active pattern and the second end DT3 of the third active pattern, and is electrically connected to the first end STL2 of the second sub-active pattern and the second end DT3 of the third active pattern. The seventh conductive portion F7 serves as a connection node between the compensation transistor T3 and the second sub-transistor TL2. Specifically, the seventh conductive portion F7 is electrically connected to the first end STL2 of the second sub-transistor TL2 and the second end DT3 of the compensation transistor T3 through a via penetrating the interlayer dielectric layer, the second insulating layer 1002, and the first insulating layer 1001 (e.g., ...). Figure 9 (CNT11 in the middle).

[0098] in, Figure 9 CNT12 in the diagram represents the electrical connection between the bridge section F3 and the first reset line VL1 in the leftmost pixel driving circuit adjacent to the pixel driving circuit along the first direction x.

[0099] Figure 10 This is a schematic diagram of the structure of the fourth conductive layer provided in an embodiment of the present invention; please continue reading. Figures 4 to 10 The driving circuit layer also includes a first planarization layer and a fourth conductive layer located on the third conductive layer. The fourth conductive layer includes the data line DL and the third power line VDD1.

[0100] The data cable DL includes a first main body DL1, a second main body DL2, a first clearance portion DL3, and an extension portion DL4. Both the first main body DL1 and the second main body DL2 extend along the second direction y. The extension portion DL4 is located on the side of the first main body DL1 closest to the second conductive portion F2 and overlaps with the second conductive portion F2. The extension portion DL4 is electrically connected to the second conductive portion F2. The first clearance portion DL3 connects between the extension portion DL4 and the second main body DL2. The first clearance portion DL3 is correspondingly electrically connected to the bridging portion F3 in the leftmost pixel driving circuit adjacent to the pixel driving circuit along the first direction x. Specifically, the extension portion DL4 is electrically connected to the second conductive portion F2 through a via penetrating the first planarization layer (e.g., ...). Figure 10 (at PLN1 in the middle).

[0101] The third power line VDD1 is spaced apart from the data line DL, including a third main body VD1 extending along the second direction y, a fourth main body VD2, and a second clearance portion VD3 located between the third main body VD1 and the fourth main body VD2 and corresponding to the extension portion DL4. A portion of the fourth main body VD2 overlaps with and is electrically connected to the fourth conductive portion F4, so that one of the source and drain of the first switching transistor T4 is electrically connected to the first power line VDD. Specifically, the fourth main body VD2 is electrically connected to the fourth conductive portion F4 through a via penetrating the first planarization layer (e.g., ...). Figure 10(at PLN2 in the middle).

[0102] Optionally, the fourth conductive layer further includes a node connection portion B1, which is located on the side of the third power line VDD1 away from the data line DL, and overlaps with and is electrically connected to the fifth conductive portion F5. Specifically, the node connection portion B1 is electrically connected to the fifth conductive portion F5 through a via penetrating the first planarization layer (e.g., Figure 10 (at PLN3 in the middle).

[0103] It is understandable that the dimensions of the corresponding vias in each conductive layer and active layer can be larger than the dimensions of the non-corresponding vias in each conductive layer and active layer.

[0104] Multiple light-emitting devices are electrically connected to the first node B of multiple pixel driving circuits. The source and drain of the light-emitting device and the corresponding driving transistor T1 in the pixel driving circuit are electrically connected between a first voltage terminal and a second voltage terminal. Optionally, the first power supply line VDD is electrically connected between the first voltage terminal and one of the source and drain of the driving transistor T1, and the second power supply line VSS is electrically connected between the cathode of the light-emitting device and the second voltage terminal.

[0105] The present invention also provides a display device, which includes any of the above-described driving circuits or any of the above-described display panels. It is understood that the display device includes portable display devices (such as laptops, mobile phones, etc.), fixed terminals (such as desktop computers, televisions, etc.), measuring devices (such as fitness trackers, thermometers, etc.), etc.

[0106] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A display panel, characterized in that, include: An active layer includes a first sub-active pattern and a second sub-active pattern disposed opposite to each other, and a first electrical connection portion connecting the first sub-active pattern and the second sub-active pattern; the first electrical connection portion includes a connecting portion and an overlapping portion, the first sub-active pattern and the second sub-active pattern being located on opposite sides of the connecting portion with respect to the overlapping portion; the connecting portion extends along a first direction, and its two ends are respectively connected to the first sub-active pattern and the second sub-active pattern; the overlapping portion extends along a second direction intersecting the first direction and is connected to the connecting portion; the first sub-active pattern includes a first channel portion, and the second sub-active pattern includes a second channel portion; The first scan line extends along the first direction and overlaps with the first channel portion and the second channel portion; as well as The first reset line is located on one side of the first scan line and at least partially overlaps with the overlapping portion.

2. The display panel according to claim 1, characterized in that, The active layer further includes a third sub-active pattern, the third sub-active pattern including a third channel portion; the display panel further includes a second scan line, the second scan line being located on the side of the first reset line away from the first scan line, and overlapping with the third channel portion; The third sub-active pattern is electrically connected between the first reset line and the first electrical connection portion.

3. The display panel according to claim 2, characterized in that, The active layer further includes a fourth sub-active pattern and a second electrical connection portion connected between the third sub-active pattern and the fourth sub-active pattern. The third sub-active pattern and the fourth sub-active pattern are both located between the first electrical connection portion and the second electrical connection portion. The fourth sub-active pattern includes a fourth channel portion, and the second scan line overlaps with the fourth channel portion. The first reset line is electrically connected to the portion of the third sub-active pattern located on the side of the first scan line near the second scan line via a bridging portion that is connected to the first reset line and the active layer.

4. The display panel according to claim 3, characterized in that, It also includes a light-emitting device and a pixel driving circuit, wherein the pixel driving circuit includes: A driving transistor is connected in series with the light-emitting device between the first power line and the second power line; The compensation transistor includes a first sub-transistor and a second sub-transistor connected in series. One of the source and drain of the first sub-transistor is electrically connected to the gate of the driving transistor. The other of the source and drain of the first sub-transistor is electrically connected to one of the source and drain of the second sub-transistor through a connection node. The other of the source and drain of the second sub-transistor is electrically connected to one of the source and drain of the driving transistor. The gates of both the first sub-transistor and the second sub-transistor are electrically connected to the first scan line. The first sub-transistor includes a first sub-active pattern, and the second sub-transistor includes a second sub-active pattern.

5. The display panel according to claim 4, characterized in that, The pixel driving circuit also includes: A reset transistor includes a third sub-transistor and a fourth sub-transistor connected in series. One of the source and drain of the third sub-transistor is electrically connected to the first reset line. One of the source and drain of the fourth sub-transistor is electrically connected to the connection node. The other of the source and drain of the third sub-transistor is electrically connected to the other of the source and drain of the fourth sub-transistor. The gates of the third sub-transistor and the fourth sub-transistor are both electrically connected to the second scan line. The third sub-transistor includes the third sub-active pattern, and the fourth sub-transistor includes the fourth sub-active pattern.

6. The display panel according to claim 5, characterized in that, Also includes: The second reset line is located on the side of the second scan line away from the first reset line and overlaps with the second electrical connection portion.

7. The display panel according to claim 6, characterized in that, The second reset line and the previous pixel driving circuit adjacent to the pixel driving circuit along the second direction include one of the source and drain of the initialization transistor, and the other of the source and drain of the initialization transistor is electrically connected to the anode of the corresponding light-emitting device.

8. The display panel according to claim 7, characterized in that, The first reset line and the second reset line are in the same layer and made of the same material.

9. The display panel according to claim 4, characterized in that, The pixel driving circuit further includes a data transistor, the source and drain of which are electrically connected between a data line and the other of the source and drain of the driving transistor, and the gate of which is electrically connected to a third scan line. The first reset line is used to transmit a first reset signal, which has a first potential and a second potential. The moment when the first reset signal jumps from the first potential to the second potential is the same as the moment when the data transistor is turned off. The difference between the first potential and the gate potential of the driving transistor is greater than the difference between the second potential and the gate potential of the driving transistor.

10. The display panel according to claim 9, characterized in that, The second potential is equal to the gate potential of the driving transistor.

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