Display device

Abstract

The invention relates to a display device. The display device comprises a light-emitting device and a pixel circuit. The pixel circuit comprises an amplitude modulation module, a pulse width modulation module and a switch module. A first capacitor in the pulse width modulation module is used for storing a first electric charge quantity corresponding to a pulse width data signal received by the pulse width modulation module. And a second capacitor in the amplitude modulation module is used for storing a second electric charge quantity corresponding to the amplitude data signal received by the driving unit. A connection node of the first capacitor and the driving unit is a first node, a connection node of the second capacitor and the pulse width control unit is a second node, and the switch module is connected between the first node and the second node and used for conducting the first node and the second node before a reset stage so as to neutralize charges stored in the first capacitor and the second capacitor. Therefore, the voltage of the first node is reduced, the influence on the reset signal is reduced, the problem that the light-emitting device emits light abnormally in the reset stage is solved, and the display effect of the display device is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display device. Background Technology

[0002] LED (light-emitting diode) devices have gradually become commonly used light-emitting devices in display devices, especially Mini LED and Micro LED. They have the characteristics of high brightness, wide color gamut, and high reliability, and are easy to realize flexible display, transparent display, free splicing and sensor integration functions.

[0003] The pixel circuit in the display device can drive the LED device to emit light through pulse width modulation (PWM) and pulse amplitude modulation (PAM). Specifically, the amplitude modulation module in the pixel circuit determines the current value of the driving current based on the PAM signal, thereby determining the light intensity of the LED device during the light emission process; the pulse width modulation module controls the timing of the amplitude modulation module in generating the driving current, thereby determining the light emission time of the LED device within each frame display cycle, and thus determining the brightness of the LED device within each frame display cycle.

[0004] However, the display devices in the related technologies have a "brightness in dark fields" problem, that is, the LED devices emit brightness when they do not need to emit light (such as during the reset phase), which affects the display effect of the display device. Summary of the Invention

[0005] Therefore, it is necessary to provide a display device to improve the display effect.

[0006] This application provides a display device, including: a light-emitting device and a pixel circuit; the pixel circuit includes an amplitude modulation module, a pulse width modulation module, and a switching module; wherein...

[0007] The pulse width modulation module includes a pulse width control unit and a first capacitor; the pulse width control unit is used to receive pulse width data signals, store a first charge quantity corresponding to the pulse width data signals in the first capacitor, and output pulse width modulation signals according to the first charge quantity.

[0008] The amplitude modulation module includes a driving unit, a second capacitor, a first reset unit, and a second reset unit. The driving unit receives an amplitude data signal, stores a second charge corresponding to the amplitude data signal in the second capacitor, and outputs a driving signal to the light-emitting device based on the second charge and the pulse width modulation signal. The duty cycle of the driving signal is determined based on the pulse width modulation signal. The first reset unit is connected to a reset signal input terminal and the light-emitting device, and is used to reset the light-emitting device according to the reset signal received at the reset signal input terminal during the reset phase. The second reset unit is connected to the reset signal input terminal and a first node, and is used to reset the first node according to the reset signal during the reset phase. The first node is the connection node between the second capacitor and the driving unit.

[0009] The switching module is connected between the first node and the second node and is used to turn on the first node and the second node before the reset phase to neutralize the charge stored in the first capacitor and the second capacitor; the second node is the connection node between the first capacitor and the pulse width control unit.

[0010] The aforementioned display device includes a light-emitting device and a pixel circuit. The pixel circuit includes an amplitude modulation module, a pulse width modulation module, and a switching module. A first capacitor in the pulse width modulation module stores a first charge corresponding to the pulse width data signal received by the pulse width modulation module. A second capacitor in the amplitude modulation module stores a second charge corresponding to the amplitude data signal received by the driving unit. The connection node between the first capacitor and the driving unit is called a first node, and the connection node between the second capacitor and the pulse width control unit is called a second node. The switching module is connected between the first node and the second node and is used to turn on the first node and the second node before the reset phase to neutralize the charge stored in the first capacitor and the second capacitor, thereby reducing the voltage of the first node. Therefore, during the reset phase, the lower voltage of the first node reduces the impact on the reset signal received when the first reset unit and the second reset unit are turned on, allowing the reset signal to effectively reset the driving unit and the light-emitting device, significantly improving the problem of abnormal brightness of the light-emitting device during the reset phase, and enhancing the display effect of the display device.

[0011] In one embodiment, the switch module is used to receive a charging scan signal; the charging scan signal is enabled during the charging phase to turn on the switch module.

[0012] In this embodiment, a charging phase is added between the comparison light-emitting phase and the reset phase of the next cycle. During the charging phase, the charging scan signal is enabled, causing the switching module to turn on the first and second nodes. The charges stored in the first and second capacitors are neutralized, thereby pulling down the first node. This reduces the impact on the reset signal received when the first and second reset units are turned on, allowing the reset signal to effectively reset the driving unit and the light-emitting device. This significantly improves the problem of abnormal brightness of the light-emitting device during the reset phase and enhances the display effect of the display device.

[0013] In one embodiment, the first capacitor is also used to receive a ramp signal; during the comparison and illumination phase, the voltage of the ramp signal decreases, and under the action of the first capacitor, the voltage of the second node decreases with the ramp signal to control the potential of the pulse width modulation signal output by the pulse width modulation module; the comparison and illumination phase is located before the charging phase;

[0014] During the charging phase, the voltage of the ramp signal decreases, and under the action of the first capacitor, the voltage of the second node decreases to a preset lower limit voltage along with the ramp signal.

[0015] In this embodiment, by continuously reducing the voltage of the ramp signal during the charging phase, the voltage of the second node can be gradually reduced, thereby lowering the voltage of the first node as much as possible, thus improving the abnormal lighting situation during the reset phase and enhancing the display effect of the display device.

[0016] In one embodiment, the preset lower limit voltage is a negative voltage.

[0017] In this embodiment, when the second node is at a negative voltage, it can attract more positive charges, thereby neutralizing more positive charges in the second capacitor, making the voltage of the first node lower, reducing its influence on the reset signal during the reset phase, and improving the reset effect.

[0018] In one embodiment, the first capacitor is also used to receive a ramp signal; during the comparison and illumination phase, the voltage of the ramp signal decreases, and under the action of the first capacitor, the voltage of the second node decreases with the ramp signal to control the potential of the pulse width modulation signal output by the pulse width modulation module; the comparison and illumination phase is located before the charging phase;

[0019] During the charging phase, the voltage of the ramp signal remains unchanged.

[0020] In this embodiment, by keeping the voltage of the ramp signal constant, the continuously changing ramp signal is prevented from affecting the charge neutralization process between the two capacitors, thus ensuring a smooth transition in the charge neutralization process and improving the stability of the circuit operation.

[0021] In one embodiment, the charging scan signal is in an enabled state during the reset phase, turning on the switch module, and the second reset unit resets the second node via the first node and the switch module.

[0022] In this embodiment, by enabling the charging scan signal during the reset phase, the reset signal can be transmitted to the second node without setting a separate reset unit, thereby resetting the second node, which simplifies the circuit structure and reduces the circuit cost.

[0023] In one embodiment, the pixel circuit further includes a third reset unit connected to the second node, and the third reset unit is also connected to a reset signal input terminal;

[0024] During the reset phase, the charge scan signal is in an inactive state, causing the switch module to disconnect the connection between the first node and the second node; the third reset unit resets the second node according to the reset signal.

[0025] In this embodiment, resetting the second node using a third reset unit results in a better reset effect. This third reset unit has the same control timing as the first and second reset units, which simplifies the control timing of the pixel circuit.

[0026] In one embodiment, the pixel circuit further includes a first light-emitting control unit; the first light-emitting control unit is connected between the driving unit and the light-emitting device, and the first light-emitting control unit is also used to receive a first light-emitting control signal;

[0027] The first light emission control signal is enabled during the comparison light emission phase; before the charging phase, the first light emission control signal is deactivated; the comparison light emission phase is located before the charging phase.

[0028] In this embodiment, before the charging stage, the first light-emitting control signal is converted to an enabled invalid state. Even during the charging stage, if the voltage of the first node decreases, causing the state of the driving unit to be unstable and there is a driving signal output, the light-emitting device cannot be driven due to the disconnection of the current transmission path, thereby ensuring that the light-emitting device does not emit light and improving the display effect.

[0029] In one embodiment, the pixel circuit further includes a second light-emitting control unit; the second light-emitting control unit is connected between the pulse width control unit and the driving unit; the second light-emitting control unit is also used to receive a second light-emitting control signal, which is in an enabled state during the comparison light-emitting phase;

[0030] Before the charging phase, the second light emission control signal is switched to an enabled-disabled state; the second light emission control signal is switched to an enabled-disabled state earlier than the first light emission control signal.

[0031] In this embodiment, before the charging phase, the second light emission control signal EMIT2 is switched to an inactive state. During the subsequent charging phase, the charge neutralization process in the two capacitors is not affected by the pulse width control unit, resulting in better charging performance.

[0032] In one embodiment, the switching module includes a charging transistor; the first terminal of the charging transistor is connected to the first node, the second terminal of the charging transistor is connected to the second node, and the control terminal of the charging transistor is used to receive the charging scan signal.

[0033] In this embodiment, the conduction or disconnection of the two nodes is controlled by the charging transistor, resulting in a simple circuit structure that is easy to implement. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a structural diagram of a pixel circuit according to an embodiment of this application;

[0036] Figure 2 This is a waveform diagram of the reset signal for a pixel circuit in some scenarios;

[0037] Figure 3 This is a structural diagram of a pixel circuit according to another embodiment of this application;

[0038] Figure 4 This is a structural diagram of a pixel circuit according to another embodiment of this application;

[0039] Figure 5 This is a signal timing diagram of one embodiment of the present application;

[0040] Figure 6 This is a circuit structure diagram of the pixel circuit in one embodiment of this application;

[0041] Figure 7 This is a circuit structure diagram of the pixel circuit during the reset phase in one embodiment of this application;

[0042] Figure 8 This is a circuit structure diagram of the pixel circuit during the data writing stage in one embodiment of this application;

[0043] Figure 9 This is a circuit structure diagram of a pixel circuit in one state of the comparison light emission stage in an embodiment of this application;

[0044] Figure 10 This is a circuit structure diagram of the pixel circuit in another state of the comparison light emission stage in one embodiment of this application;

[0045] Figure 11 This is a circuit structure diagram of the pixel circuit during the charging stage in one embodiment of this application;

[0046] Figure 12 This is a schematic diagram of the equivalent circuit of the pixel circuit in one embodiment of this application. Detailed Implementation

[0047] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0049] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0050] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0051] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0052] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0053] This embodiment provides a display device, including a light-emitting device and a pixel circuit, wherein the pixel circuit is used to drive the light-emitting device to emit light. In some embodiments, the light-emitting device may be MicroLED, MiniLED, or other LEDs.

[0054] In some embodiments, such as Figure 1 As shown, the pixel circuit includes a pulse width modulation module 100, an amplitude modulation module 200, and a switching module 300. The amplitude modulation module 200 outputs a driving signal to drive the light-emitting device D to emit light. The pulse width modulation module 100 outputs a pulse width modulation signal to the amplitude modulation module 200, controlling the duration of the driving signal output by the amplitude modulation module 200 to adjust the light-emitting time of the light-emitting device D within the driving cycle.

[0055] The pulse width modulation module 100 includes a pulse width control unit 110 and a first capacitor C1. The pulse width control unit 110 and the first capacitor C1 are connected, and the connection node between the pulse width control unit 110 and the first capacitor C1 is the second node N1.

[0056] The pulse width control unit 110 receives the pulse width data signal PWM_Data, stores a first charge quantity corresponding to the pulse width data signal PWM_Data in the first capacitor C1, and outputs a pulse width modulation signal according to the first charge quantity. Exemplarily, the first terminal of the first capacitor C1 is connected to the second node N1, and the second terminal is connected to the ramp signal SWEEP. The ramp signal SWEEP is a voltage signal whose amplitude decreases linearly with time at a constant rate. The voltage magnitudes of the pulse width data signal PWM_Data and the ramp signal SWEEP can be set according to actual conditions. During the comparison illumination phase, the voltage of the ramp signal SWEEP gradually decreases. Under the action of the first capacitor C1, the voltage of the second node N1 gradually decreases. The pulse width modulation module 100 adjusts the duration of its output signal (pulse width modulation signal) being high-level according to the first charge quantity and the voltage of the second node N1.

[0057] The amplitude modulation module 200 includes a driving unit 210, a second capacitor C2, a first reset unit 220, and a second reset unit 230. The driving unit 210 is connected to the pulse width control unit 110, the second capacitor C2, and the light-emitting device D. The connection node between the driving unit 210, the pulse width control unit 110, and the second capacitor C2 is the first node Q1. Specifically, the driving unit 210 is connected to the anode of the light-emitting device D and the first terminal of the second capacitor C2. The second terminal of the second capacitor C2 is connected to the first power supply voltage PAM_VDD, and the cathode of the light-emitting device D is connected to the second power supply voltage PVEE.

[0058] The driving unit 210 receives the amplitude data signal PAM_Data, stores a second charge quantity corresponding to the amplitude data signal PAM_Data in the second capacitor C2, and outputs a driving signal based on the second charge quantity and the pulse width modulation signal. The duty cycle of the driving signal is determined based on the pulse width modulation signal.

[0059] The first reset unit 220 is connected to the reset signal input terminal and the light-emitting device D, and is used to reset the light-emitting device D according to the reset signal VREF received at the reset signal input terminal during the reset phase. Specifically, the first reset unit 220 is connected to the anode of the light-emitting device D, and resets the anode of the light-emitting device D during the reset phase. This improves the light emission abnormalities caused by residual circuit conditions and enhances the reliability of the display.

[0060] The second reset unit 230 is connected to the reset signal input terminal and the first node Q1, and is used to reset the first node Q1 according to the reset signal VREF during the reset phase. This ensures that the first node Q1 is in a defined initial voltage state in each driving cycle, reducing the impact of residual circuit states on the driving signal output by the driving unit 210, and further improving the reliability of the display.

[0061] The magnitude of the current in the drive signal output by the drive unit 210 is related to the voltage of the amplitude data signal PAM_Data. When a higher brightness is required for the light-emitting device D, the voltage value of the amplitude data signal PAM_Data can be increased, resulting in a larger drive current. Therefore, by adjusting the voltage of the amplitude data signal PAM_Data, the brightness of the emitted light can be controlled.

[0062] The pulse width modulation (PWM) signal output by the pulse width modulation module 100 is used to adjust the duty cycle of the drive signal output by the drive unit 210. As an example, when the PWM signal is low, the first node Q1 is low, and the drive unit 210 outputs a drive signal based on the second charge stored in the second capacitor C2, driving the light-emitting device D to emit light. When the PWM signal changes to a high level, the first node Q1 also changes to a high level, the drive unit 210 turns off, stops outputting the drive signal, and the light-emitting device D stops emitting light, thereby adjusting the light-emitting time of the light-emitting device D within the drive cycle.

[0063] It should be noted that when the light-emitting device D stops emitting light, the second capacitor C2 stores the high level of the first node Q1. When the next reset phase arrives, the second reset unit 230 is turned on, and the second capacitor C2 pulls the reset signal VREF high through the second reset unit 230. For example... Figure 2 As shown, the voltage waveform of the reset signal VREF exhibits a significant spike (it can be pulled high by 6V-8V). Since both the second reset unit 230 and the first reset unit 220 are connected to the reset signal input terminal, the pulled-high reset signal VREF will "re-feed back" to the light-emitting device D through the first reset unit 220, pulling up the anode of the light-emitting device D. This results in a voltage difference across the light-emitting device D, causing abnormal brightness when the light-emitting device D is not needed. It is understandable that the display device contains multiple light-emitting devices D and multiple pixel circuits. As the trace of the reset signal VREF extends to both sides (the extension of the trace increases the load on the reset signal VREF), the magnitude by which the reset signal VREF is pulled high by the pixel circuits on both sides gradually increases, increasing the voltage difference across the light-emitting devices D on both sides, making the abnormal brightness at both ends of the display device more pronounced.

[0064] In this embodiment, the switch module 300 is connected between the first node Q1 and the second node N1, and is used to turn on the first node Q1 and the second node N1 before the reset phase to neutralize the charge stored in the first capacitor C1 and the second capacitor C2.

[0065] After the emission phase ends, the first node Q1 is at a high level, and the second node N1 is at a low level under the influence of the ramp voltage SWEEP. By turning on the switch module 300 before reset, the first node Q1 and the second node N1 can be connected, and the charge between the first node Q1 and the second node N1 is neutralized, thereby reducing the voltage of the first node Q1 and thus reducing the influence of the first node Q1 on the reset signal VREF during the reset phase.

[0066] The aforementioned display device includes a light-emitting device D and a pixel circuit. The pixel circuit includes an amplitude modulation module 200, a pulse width modulation module 100, and a switching module 300. The first capacitor C1 in the pulse width modulation module 100 stores a first charge corresponding to the pulse width data signal PWM_Data received by the pulse width modulation module 100. The second capacitor C2 in the amplitude modulation module 200 stores a second charge corresponding to the amplitude data signal PAM_Data received by the driving unit 210. The connection node between the first capacitor C1 and the driving unit 210 is a first node Q1, and the connection node between the second capacitor C2 and the pulse width control unit 110 is a second node N1. The switching module 300 is connected between the first node Q1 and the second node N1 and is used to turn on the first node Q1 and the second node N1 before the reset phase to neutralize the charge stored in the first capacitor C1 and the second capacitor C2, thereby reducing the voltage of the first node Q1. Therefore, during the reset phase, the lower voltage of the first node Q1 can reduce the impact on the reset signal VREF connected when the first reset unit 220 and the second reset unit 230 are turned on. This allows the reset signal VREF to effectively reset the driving unit 210 and the light-emitting device D, significantly improving the problem of abnormal brightness of the light-emitting device D during the reset phase and enhancing the display effect of the display device. Moreover, by neutralizing the charge stored in the first capacitor C1 and the second capacitor C2, the overall power consumption of the display device can be reduced.

[0067] In some embodiments, such as Figure 3 As shown, the switch module 300 is used to receive the charging scan signal S3. The charging scan signal S3 is enabled during the charging phase, so that the switch module 300 is turned on.

[0068] It is understandable that the driving cycle of a pixel circuit typically includes a reset phase, a data writing phase, and a comparison and light emission phase. After the comparison and light emission phase ends, the first node Q1 is at a high level. If the reset phase of the next driving cycle is entered directly, the reset signal VREF will be pulled high by the first node Q1.

[0069] In this embodiment, a charging phase is added between the comparison light emission phase and the reset phase of the next cycle. During the charging phase, the charging scan signal S3 is in an enabled state, which enables the switch module 300 to conduct the first node Q1 and the second node N1. The charges stored in the first capacitor C1 and the second capacitor C2 are neutralized, thereby pulling down the first node Q1.

[0070] The charging phase can occur after the comparison and emission phase, meaning the driving cycle sequentially includes the reset phase, data writing phase, comparison and emission phase, and charging phase. Alternatively, the charging phase can occur before the reset phase, meaning the driving cycle sequentially includes the charging phase, reset phase, data writing phase, and comparison and emission phase. Regardless of the order of the phases in the driving cycle, it can be guaranteed that the first node Q1 has been pulled low before the reset phase. Optionally, having the driving cycle sequentially include the reset phase, data writing phase, comparison and emission phase ensures that the first node Q1 is at the expected low potential at the end of the current driving cycle, reducing the impact of the current cycle on the next cycle.

[0071] In some embodiments, after the charging phase ends, the charging scan signal S3 is in an inactive state, which turns off the switch module 300. The switch module 300 will not affect the state of the pulse width modulation module 100 and the amplitude modulation module 200 in other phases, thus ensuring the independence and stability of the functions of each module of the pixel circuit.

[0072] In this embodiment, by adding a charging phase, and controlling the switching module 300 to conduct by the charging scan signal S3, which is in an enabled state during the charging phase, the charges stored in the first capacitor C1 and the second capacitor C2 are neutralized, thus lowering the voltage of the first node Q1. During the reset phase, the lower voltage of the first node Q1 reduces the pull-up effect on the reset signal VREF, significantly improving the abnormal brightness of the display device, especially in the edge areas, caused by the large pull-up of the reset signal VREF, thereby enhancing the overall display effect.

[0073] In some embodiments, the first capacitor C1 is used to connect the ramp signal SWEEP. During the comparison and light emission stage, the voltage of the ramp signal SWEEP decreases. Under the action of the first capacitor C1, the voltage of the second node N1 decreases with the ramp signal SWEEP to control the potential of the pulse width modulation signal output by the pulse width control unit 110. The comparison and light emission stage is located before the charging stage.

[0074] It can be understood that during the light-emitting phase, the pulse width modulation module 100 outputs a low-level pulse width modulation signal to the first node Q1, and the driving unit 210 outputs a driving signal to drive the light-emitting device D to emit light. As the voltage of the ramp signal SWEEP decreases, under the coupling effect of the first capacitor C1, the voltage of the second node N1 decreases accordingly, and the magnitude of the decrease in the voltage of the second node N1 is the same as the magnitude of the decrease in the voltage of the ramp signal SWEEP. When the voltage of the second node N1 is at the expected low level, the pulse width control unit 110 outputs a high-level signal, controlling the driving unit 210 to stop outputting the driving signal, and the light-emitting device D stops emitting light.

[0075] In some embodiments, during the charging phase following the comparison light emission phase, the voltage of the ramp signal SWEEP decreases, and under the action of the first capacitor C1, the voltage of the second node N1 decreases to a preset lower limit voltage along with the ramp signal SWEEP.

[0076] In this embodiment, at the end of the charging phase, the voltage of the second node N1 drops to a preset lower limit voltage. The preset lower limit voltage represents the voltage value of the second node N1 at the end of the charging phase, which is its lowest value within the current driving cycle. It is related to the voltage value of the pulse width data signal PWM_Data written in the current driving cycle and the voltage change of the ramp signal SWEEP. As an example, if the change in the ramp signal SWEEP is 10V and the voltage of the pulse width data signal PWM_Data written in the current cycle is 5V, then at the end of the charging phase, the lower limit voltage of the second node N1 is -5V.

[0077] By continuously reducing the voltage of the ramp signal SWEEP during the charging phase, the voltage of the second node N1 can be gradually reduced, thereby lowering the voltage of the first node Q1 as much as possible. This improves the abnormal lighting during the reset phase and enhances the display effect of the display device.

[0078] In some embodiments, the preset lower limit voltage is a negative voltage.

[0079] It is understandable that when the second node N1 is at a negative voltage, it can attract more positive charges, thereby neutralizing more positive charges in the second capacitor C2, making the voltage of the first node Q1 lower, reducing its impact on the reset signal VREF during the reset phase, and improving the reset effect.

[0080] In some embodiments, the voltage of the ramp signal SWEEP remains constant during the charging phase. By keeping the voltage of the ramp signal SWEEP constant, the influence of continuously changing ramp signals on the charge neutralization process between the two capacitors is avoided, allowing the charge neutralization process to transition smoothly and improving the stability of the circuit operation.

[0081] In some embodiments, the charge scan signal S3 is in an enabled state during the reset phase, which turns on the switch module 300, and the second reset unit 230 resets the second node N1 through the first node Q1 and the switch module 300.

[0082] In this embodiment, by enabling the charging scan signal S3 during the reset phase, the reset signal VREF can be transmitted to the second node N1 without setting a separate reset unit, thereby resetting the second node N1, which makes the circuit structure simpler and the circuit cost lower.

[0083] In some embodiments, such as Figure 4As shown, the pulse width modulation module 100 also includes a third reset unit 120 connected to the second node N1. The third reset unit 120 is also connected to the reset signal input terminal to receive the reset signal VREF.

[0084] During the reset phase, the charge scan signal S3 is in an inactive state, causing the switch module 300 to disconnect the connection between the first node Q1 and the second node N1. During this phase, the third reset unit 120 resets the second node N1 according to the reset signal VREF.

[0085] In this embodiment, the second node N1 is reset by the third reset unit 120, resulting in a better reset effect. The control timing of the third reset unit 120 is the same as that of the first reset unit 220 and the second reset unit 230, which can simplify the control timing of the pixel circuit.

[0086] In some embodiments, the pixel circuit further includes a first light-emitting control unit 240. The first light-emitting control unit 240 is connected between the driving unit 210 and the light-emitting device D, and the first light-emitting control unit 240 is also used to receive a first light-emitting control signal EMIT1.

[0087] The first light emission control signal EMIT1 is enabled during the comparison light emission phase, and is deactivated before the charging phase. The comparison light emission phase occurs before the charging phase.

[0088] In some embodiments, such as Figure 5 As shown, the driving cycle of the pixel circuit includes a reset phase t1, a data writing phase t2, a comparison and light emission phase t3, and a charging phase t4. The low level state of the first light emission control signal EMIT1 is the enable valid state, and the high level state is the enable invalid state.

[0089] During the comparison light emission stage t3, by enabling the first light emission control signal EMIT1, the first light emission control unit 240 can be controlled to connect the drive unit 210 and the light emission device D, so that the drive signal output by the drive unit 210 is transmitted to the light emission device D, and the light emission device D emits light.

[0090] Before the charging phase t4, the first light-emitting control signal EMIT1 is switched to an enabled-disabled state. Specifically, this can be achieved during the light-emitting comparison phase t3, after the light emission ends (after the pulse width modulation signal switches to a high level), when the first light-emitting control signal EMIT1 switches to a high level. The high-level first light-emitting control signal EMIT1 can control the first light-emitting control unit 240 to disconnect the drive unit 210 from the light-emitting device D. Even if the voltage of the first node Q1 decreases during the charging phase t4, causing the drive unit 210 to become unstable and output a drive signal, the light-emitting device D cannot be driven due to the disconnection of the current transmission path, thus ensuring that the light-emitting device D does not emit light and improving the display effect.

[0091] In some embodiments, the pixel circuit further includes a second light-emitting control unit 130. The second light-emitting control unit 130 is connected between the pulse width control unit 110 and the driving unit 210. The second light-emitting control unit 130 is also used to receive a second light-emitting control signal EMIT2, which is enabled during the comparison light-emitting phase t3. Before the charging phase t4, the second light-emitting control signal EMIT2 is deactivated. The second light-emitting control signal EMIT2 is deactivated earlier than the first light-emitting control signal EMIT1.

[0092] During the comparison light emission stage t3, by enabling the second light emission control signal EMIT2, the connection between the second light emission control unit 130 and the pulse width control unit 110 and the drive unit 210 can be controlled, so that the pulse width control unit 110 outputs a pulse width modulation signal to control the duration of the drive signal output by the drive unit 210.

[0093] Before the charging phase, the second light-emitting control signal EMIT2 is switched to an inactive state. For example... Figure 5 In the timing diagram shown, the low-level state of the second light-emitting control signal EMIT2 indicates an enabled state, and the high-level state indicates an disabled state. Specifically, the second light-emitting control signal EMIT2 can be switched to a high level after the light-emitting phase t3 ends (after the pulse width modulation signal switches to a high level). Therefore, in the subsequent charging phase t4, the charge neutralization process in the two capacitors is not affected by the pulse width control unit 110, resulting in better charging performance. By switching the second light-emitting control signal EMIT2 to an disabled state first, the current path between the pulse width control unit 110 and the first node Q1 can be cut off, reducing power consumption.

[0094] The amplitude modulation module 200 also includes a third light-emitting control unit 250, which is connected between the first power supply voltage PAM_VDD and the driving unit 210. The third light-emitting control unit 250 is also used to receive the first light-emitting control signal EMIT1. Under the action of the first light-emitting control signal EMIT1, the third light-emitting control unit 250 turns on the connection between the driving unit 210 and the first power supply voltage PAM_VDD during the comparison light-emitting phase, and disconnects the connection between the driving unit 210 and the first power supply voltage PAM_VDD during the reset phase. The on and off states of the third light-emitting control unit 250 are synchronized with the first light-emitting control unit 240.

[0095] In some embodiments, the pulse width modulation module 100 further includes a fourth light-emitting control unit 140 connected between the pulse width control unit 110 and the third power supply voltage PWM_VDD. The fourth light-emitting control unit 140 is also used to receive a second light-emitting control signal EMIT2. Under the action of the second light-emitting control signal EMIT2, the connection between the pulse width control unit 110 and the third power supply voltage PWM_VDD is turned on or off.

[0096] The circuit structures of each unit in the switching module 300, pulse width modulation module 100, and amplitude modulation module 200 can be configured according to actual conditions during implementation. In some embodiments, such as Figure 6 As shown, the switching module 300 includes a charging transistor T0. The first terminal of the charging transistor T0 is connected to the first node Q1, the second terminal of the charging transistor T0 is connected to the second node N1, and the control terminal of the charging transistor T0 is used to connect to the charging scan signal S3.

[0097] The charging transistor T0 is turned on or off under the action of the charging scan signal S3, so as to turn on or off the connection between the first node Q1 and the second node N1.

[0098] In this embodiment, the conduction or disconnection of the two nodes is controlled by the charging transistor T0, resulting in a simple circuit structure that is easy to implement.

[0099] In some embodiments, the driving unit 210 includes a driving transistor T1, a data writing transistor T2, and a threshold compensation transistor T3. The control electrode of the driving transistor T1 is connected to the first node Q1, and the first electrode of the driving transistor T1 is connected to the first power supply voltage PAM_VDD through the third light-emitting control unit 250. The first electrode of the driving transistor T1 is also connected to the first electrode of the data writing transistor T2. The second electrode of the data writing transistor T2 is used to connect to the amplitude data signal PAM_Data, and the control electrode of the data writing transistor T2 is connected to the write scan signal S2. The second electrode of the driving transistor T1 is connected to the first electrode of the threshold compensation transistor T3, and the second electrode of the threshold compensation transistor T3 is connected to the control electrode of the driving transistor T1. The control electrode of the threshold compensation transistor T3 is also connected to the write scan signal S2. The second electrode of the driving transistor T1 is also used to connect to the light-emitting device D. Exemplarily, the second electrode of the driving transistor T1 is connected to the anode of the light-emitting device D through the first light-emitting control unit 240.

[0100] During the data writing phase, the write scan signal S2 is enabled. Under the action of the write scan signal S2, both the data writing transistor T2 and the threshold compensation transistor T3 are turned on to transmit the amplitude data signal PAM_Data to the first node Q1 and store it in the second capacitor C2.

[0101] In this embodiment, during the data writing stage, the amplitude data signal PAM_Data is transmitted to the first node Q1 through the data writing transistor T2 and the threshold compensation transistor T3. During the transmission process, threshold voltage compensation for the driving transistor T1 is achieved, which can improve the uniformity of the display.

[0102] In some embodiments, the first reset unit 220 includes a first reset transistor T4. The first terminal of the first reset transistor T4 is connected to the reset signal input terminal, the second terminal of the first reset transistor T4 is connected to the anode of the light-emitting device D, and the control terminal of the first reset transistor T4 is connected to the reset scan signal S1.

[0103] The second reset unit 230 includes a second reset transistor T5. The first terminal of the second reset transistor T5 is connected to the reset signal input terminal, the second terminal of the second reset transistor T5 is connected to the first node Q1, and the control terminal of the second reset transistor T5 is connected to the reset scan signal output terminal.

[0104] The third reset unit 120 includes a third reset transistor T6. The first terminal of the third reset transistor T6 is connected to the reset signal input terminal, the second terminal of the third reset transistor T6 is connected to the second node N1, and the control terminal of the third reset transistor T6 is connected to the reset scan signal output terminal.

[0105] The reset scan signal output terminal is used to receive the reset scan signal S1, which is enabled during the reset phase t1. Under the action of the reset scan signal S1, the first reset transistor T4 is turned on, transmitting the reset signal VREF to the anode of the light-emitting device D, resetting the light-emitting device D. The second reset transistor T5 is turned on, transmitting the reset signal VREF to the first node Q1, resetting the first node Q1. The third reset transistor T6 is turned on, transmitting the reset signal VREF to the second node N1, resetting the second node N1.

[0106] In this embodiment, each reset unit has a simple structure, few components, and low cost. Moreover, the first reset transistor T4, the second reset transistor T5, and the third reset transistor T6 are all controlled by the reset scan signal S1, which simplifies the control timing of the pixel circuit.

[0107] In some embodiments, the pulse width control unit 110 includes a first transistor T7, a second transistor T8, and a third transistor T9. The first terminal of the second transistor T8 is connected to a third power supply voltage PWM_VDD via a fourth light-emitting control unit 140. The first terminal of the second transistor T8 is also connected to the first terminal of the first transistor T7. The second terminal of the first transistor T7 is connected to the pulse width data signal PWM_Data, and the control terminal of the first transistor T7 is connected to the write scan signal S2. The second terminal of the second transistor T8 is connected to a first node Q1 via a second light-emitting control unit 130. The second terminal of the second transistor T8 is also connected to the first terminal of the third transistor T9. The control terminal of the third transistor T9 is connected to the write scan signal S2, and the second terminal of the third transistor T9 is connected to a second node N1.

[0108] During the data writing phase, under the action of the write scan signal S2, the first transistor T7 and the third transistor T9 are turned on. The pulse width data signal PWM_Data is transmitted to the second node N1 through the first transistor T7, the second transistor T8, and the third transistor T9, and stored in the first capacitor C1. In this process, the writing of the pulse width data signal PWM_Data and the threshold voltage compensation of the second transistor T8, which acts as the pulse width modulation transistor, are completed.

[0109] During the light-emitting phase t3, as the ramp signal SWEEP gradually decreases and the coupling effect of the first capacitor C1 occurs, the potential of the second node N1 gradually decreases until the second transistor T8 is turned on. After the second transistor T8 is turned on, the third power supply voltage PWM_VDD is transmitted and output to the first node Q1 through the second light-emitting control unit 130, thereby controlling the drive transistor T1 to turn off.

[0110] In this embodiment, the pulse width control unit 110 can adjust the proportion of its output signal being at a high potential according to the pulse width data signal PWM_Data during the comparison light emission stage, thereby controlling the light emission duration of the light-emitting device D.

[0111] In some embodiments, the first light-emitting control unit 240 includes a first light-emitting control transistor T10, the first electrode of the first light-emitting control transistor T10 is connected to the second electrode of the driving transistor T1, the second electrode of the first light-emitting control transistor T10 is connected to the anode of the light-emitting device D, and the control electrode of the first light-emitting control transistor T10 is connected to the first light-emitting control signal EMIT1.

[0112] The third light-emitting control unit 250 includes a second light-emitting control transistor T11. The first terminal of the second light-emitting control transistor T11 is connected to the first power supply voltage PAM_VDD. The second terminal of the second light-emitting control transistor T11 is connected to the first terminal of the driving transistor T1. The control terminal of the second light-emitting control transistor T11 is connected to the first light-emitting control signal EMIT1.

[0113] The second light-emitting control unit 130 includes a third light-emitting control transistor T12. The first terminal of the third light-emitting control transistor T12 is connected to the second transistor T8 and the third transistor T9. The second terminal of the third light-emitting control transistor T12 is connected to the first node Q1. The control terminal of the third light-emitting control transistor T12 is connected to the second light-emitting control signal EMIT2.

[0114] The fourth light-emitting control unit 140 includes a fourth light-emitting control transistor T13. The first terminal of the fourth light-emitting control transistor T13 is connected to the third power supply voltage PWM_VDD. The second terminal of the fourth light-emitting control transistor T13 is connected to the first transistor T7 and the second transistor T8. The control terminal of the fourth light-emitting control transistor T13 is connected to the second light-emitting control signal EMIT2.

[0115] In this embodiment, during the light-emitting phase, both the first light-emitting control signal EMIT1 and the second light-emitting control signal EMIT2 are enabled, turning on the first light-emitting control transistor T10, the second light-emitting control transistor T11, the third light-emitting control transistor T12, and the fourth light-emitting control transistor T13. During the non-light-emitting phase, both the first light-emitting control signal EMIT1 and the second light-emitting control signal EMIT2 are disabled, turning off the first light-emitting control transistor T10, the second light-emitting control transistor T11, the third light-emitting control transistor T12, and the fourth light-emitting control transistor T13 to prevent the light-emitting device D from emitting light, thus improving the reliability of light-emitting control.

[0116] To better understand the above embodiments, an optional embodiment will be explained in detail below. Please refer to... Figures 5-11In one embodiment, the display device includes a pixel circuit and a light-emitting device D. The pixel circuit includes a pulse width modulation module 100, an amplitude modulation module 200, and a switching module 300.

[0117] The switching module 300 includes a charging transistor T0. The amplitude modulation module 200 includes a driving unit 210, a second capacitor C2, a first reset unit 220, a second reset unit 230, a first light-emitting control unit 240, and a third light-emitting control unit 250. The driving unit 210 includes a driving transistor T1, a data writing transistor T2, and a threshold compensation transistor T3. The first reset unit 220 includes a first reset transistor T4. The second reset unit 230 includes a second reset transistor T5. The first light-emitting control unit 240 includes a first light-emitting control transistor T10. The third light-emitting control unit 250 includes a second light-emitting control transistor T11.

[0118] The pulse width modulation module 100 includes a first capacitor C1, a pulse width control unit 110, a third reset unit 120, a second light emission control unit 130, and a fourth light emission control unit 140. Specifically, the pulse width control unit 110 includes a first transistor T7, a second transistor T8, and a third transistor T9; the third reset unit 120 includes a third reset transistor T6; the second light emission control unit 130 includes a third light emission control transistor T12; and the fourth light emission control unit 140 includes a fourth light emission control transistor T13.

[0119] It should be noted that all the transistors mentioned above can be TFTs (Thin Film Transistors). The type of each transistor can be set according to specific circumstances; it can be a P-type transistor or an N-type transistor. The gate is the control electrode of each transistor, and the first and second electrodes can be determined according to the specific type of transistor.

[0120] Based on the above pixel circuit structure, its working process mainly includes a reset stage, a data writing stage, a comparison and light emission stage, and a charging stage. Figure 5 This embodiment illustrates the waveform changes of the reset scan signal S1, write scan signal S2, charge scan signal S3, first light emission control signal EMIT1, second light emission control signal EMIT2, and ramp signal SWEEP during one frame display cycle. The control process of the pixel circuit in this embodiment will be described in detail below based on these four stages and the circuit structure of the pixel circuit described above (taking all transistors as P-type transistors as an example).

[0121] During the reset phase t1, refer to Figure 7 ( Figure 7 A cross in the middle indicates that the transistor is not conducting.

[0122] When the reset scan signal S1 is enabled, the first reset transistor T4, the second reset transistor T5, and the third reset transistor T6 are turned on, pulling the potentials of the anode of the light-emitting device D, the first node Q1, and the second node N1 down to the potential of the reset signal VREF.

[0123] During data writing phase t2, refer to Figure 8 ( Figure 8 A cross in the middle indicates that the transistor is not conducting.

[0124] When the write scan signal S2 is enabled, the drive transistor T1, data write transistor T2, and threshold compensation transistor T3 are turned on. The amplitude data signal PAM_Data is transmitted to the first node Q1 via the data write transistor T2, drive transistor T1, and threshold compensation transistor T3, and stored in the second capacitor C2. During the transmission process, threshold voltage compensation is achieved for the drive transistor T1, and the voltage written to the first node Q1 is V. PAM_Data -V th1 The second capacitor C2 stores this voltage. That is, the second charge stored in the second capacitor C2, corresponding to the amplitude data signal PAM_Data, is V. PAM_Data -V th1 The amount of charge. Where, V PAM_Data The voltage, V, represents the amplitude data signal PAM_Data. th1 This represents the threshold voltage for driving transistor T1.

[0125] During this stage, the first transistor T7, the second transistor T8, and the third transistor T9 are turned on. The pulse width data signal PWM_Data is transmitted to the second node N1 via the first transistor T7, the second transistor T8, and the third transistor T9, and stored in the first capacitor C1. This process completes the writing of the pulse width data signal PWM_Data and the threshold voltage compensation of the second transistor T8, which acts as the pulse width modulation transistor. The voltage written to the second node N1 is V. PWM_Data -V th2 The first capacitor C1 stores this voltage. That is, the first capacitor C1 stores the first charge corresponding to the pulse width data signal PWM_Data, which is V. PWM_Data -V th2 The amount of charge. Where, V PWM_Data This represents the voltage of the pulse width data signal PWM_Data, in V. th2 This indicates the threshold voltage of the second transistor T8.

[0126] During the comparison luminescence stage t3, reference Figures 9-10 ( Figures 9-10 A cross in the middle indicates that the transistor is not conducting.

[0127] The voltage of the ramp signal SWEEP suddenly rises, and the potential of the second node N1 changes to V. PAM_Data -V th1 +V SWEEP Simultaneously, the second light-emitting control signal EMIT2 goes low, and the third power supply voltage PWM_VDD is written to the first terminal (source) of the second transistor T8 via the first transistor T7. The voltage Vgs between the gate and source of the second transistor T8 is greater than 0, and the second transistor T8 is turned off. Subsequently, the first light-emitting control signal EMIT1 goes low, and the first power supply voltage PAM_VDD is written to the driving transistor T1. The driving transistor T1 outputs a driving signal, and the light-emitting device D emits light.

[0128] Reference Figure 10 As the slope signal SWEEP voltage decreases, the potential of the second node N1 continues to decrease. When the voltage V of the second node N1... N1 When -PWM_VDD-Vth2<0, the second transistor T8 is turned on, and the third power supply voltage PWM_VDD is input to the first node Q1 (the first node Q1 is at a positive potential), causing the driving transistor T1 to turn off, and the light-emitting device D stops emitting light.

[0129] During the charging phase t4, refer to... Figure 11 ( Figure 11 A cross in the middle indicates that the transistor is not conducting.

[0130] The reset scan signal S1, write scan signal S2, first light emission control signal EMIT1, and second light emission control signal EMIT2 are all at high potentials. The charge scan signal S3 goes low, and the charge transistor T0 is turned on, so that the first node Q1 and the second node N1 are turned on. After the positive and negative charges of the first capacitor C1 and the second capacitor C2 are neutralized, the potential of the first node Q1 decreases. In some embodiments, the voltage range of the reset signal VREF can be -6V to -8V, the voltage change amplitude of the ramp signal SWEEP is 10V, the voltage of the amplitude data signal PAM_Data is about 5V, and the second node N1 can reach about -5V at the end of the charge phase t4.

[0131] The equivalent circuit diagram for this stage can be as follows: Figure 12As shown, the charging transistor T0 is equivalent to a switch between the first node Q1 and the second node N1, controlled by the charging scan signal S3. The third reset transistor T6 is equivalent to a switch between the second node N1 and the applied reset signal VREF, controlled by the reset scan signal S1. The first reset transistor T4 and the second reset transistor T5 are equivalent to a switch between the first node Q1 and the light-emitting device D, controlled by the reset scan signal S1. During this stage, the charging scan signal S3 is active, connecting the first node Q1 and the second node N1 together. Through the neutralization of positive and negative charges, the absolute potential values ​​of the first node Q1 and the second node N1 are reduced.

[0132] By neutralizing and charging the charge during the charging phase, the potential difference between the first node Q1 and the reset signal VREF is very small during the reset phase of the next driving cycle. The voltage rise of the reset signal VREF is small and insufficient to create a conduction voltage difference across the light-emitting device D, thereby preventing the light-emitting device D from emitting light.

[0133] The aforementioned display device utilizes the positive and negative potentials of the first node Q1 and the second node N1 after the light-emitting phase ends. By establishing a discharge channel (switching module 300), the charges of the two nodes connected to the first capacitor C1 and the second capacitor C2 are neutralized in advance. This reduces the voltage rise on the reset signal VREF trace during the subsequent reset phase, preventing the light-emitting device D from lighting up during the reset phase. This ensures the uniformity of the display and the subsequent Demura process, while also reducing the overall power consumption of the panel. Furthermore, the charge scan signal S3 is a global signal and has virtually no impact on the light-emitting time.

[0134] It should be noted that, in the embodiments of this application, "display device" refers to any device with screen display and data processing capabilities. For example, display devices include, but are not limited to, smart TVs, mobile terminals, computers, monitors, advertising screens, wearable devices, virtual reality devices, and augmented reality devices.

[0135] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0136] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0137] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A display device, characterized in that, include: The light-emitting device and pixel circuit; the pixel circuit includes an amplitude modulation module, a pulse width modulation module, and a switching module; wherein... The pulse width modulation module includes a pulse width control unit and a first capacitor; the pulse width control unit is used to receive pulse width data signals, store a first charge quantity corresponding to the pulse width data signals in the first capacitor, and output pulse width modulation signals according to the first charge quantity. The amplitude modulation module includes a driving unit, a second capacitor, a first reset unit, and a second reset unit. The driving unit receives an amplitude data signal, stores a second charge corresponding to the amplitude data signal in the second capacitor, and outputs a driving signal to the light-emitting device based on the second charge and the pulse width modulation signal. The duty cycle of the driving signal is determined based on the pulse width modulation signal. The first reset unit is connected to a reset signal input terminal and the light-emitting device, and is used to reset the light-emitting device according to the reset signal received at the reset signal input terminal during the reset phase. The second reset unit is connected to the reset signal input terminal and a first node, and is used to reset the first node according to the reset signal during the reset phase. The first node is the connection node between the second capacitor and the driving unit. The switching module is connected between the first node and the second node and is used to turn on the first node and the second node before the reset phase to neutralize the charge stored in the first capacitor and the second capacitor; the second node is the connection node between the first capacitor and the pulse width control unit.

2. The display device according to claim 1, characterized in that, The switching module is used to receive a charging scan signal; the charging scan signal is enabled during the charging phase to turn on the switching module.

3. The display device according to claim 2, characterized in that, The first capacitor is also used to receive the ramp signal; during the comparison light emission stage, the voltage of the ramp signal decreases, and under the action of the first capacitor, the voltage of the second node decreases with the ramp signal to control the potential of the pulse width modulation signal output by the pulse width modulation module. The comparative light emission stage is located before the charging stage; During the charging phase, the voltage of the ramp signal decreases, and under the action of the first capacitor, the voltage of the second node decreases to a preset lower limit voltage along with the ramp signal.

4. The display device according to claim 3, characterized in that, The preset lower limit voltage is a negative voltage.

5. The display device according to claim 2, characterized in that, The first capacitor is also used to receive the ramp signal; during the comparison light emission stage, the voltage of the ramp signal decreases, and under the action of the first capacitor, the voltage of the second node decreases with the ramp signal to control the potential of the pulse width modulation signal output by the pulse width modulation module. The comparative light emission stage is located before the charging stage; During the charging phase, the voltage of the ramp signal remains unchanged.

6. The display device according to claim 2, characterized in that, The charging scan signal is enabled during the reset phase, which turns on the switch module. The second reset unit resets the second node via the first node and the switch module.

7. The display device according to claim 2, characterized in that, The pixel circuit also includes a third reset unit connected to the second node, and the third reset unit is also connected to a reset signal input terminal; During the reset phase, the charge scan signal is in an inactive state, causing the switch module to disconnect the connection between the first node and the second node; the third reset unit resets the second node according to the reset signal.

8. The display device according to claim 2, characterized in that, The pixel circuit also includes a first light-emitting control unit; the first light-emitting control unit is connected between the driving unit and the light-emitting device, and the first light-emitting control unit is also used to receive a first light-emitting control signal; The first light emission control signal is enabled during the comparison light emission phase; before the charging phase, the first light emission control signal is deactivated; the comparison light emission phase is located before the charging phase.

9. The display device according to claim 8, characterized in that, The pixel circuit further includes a second light-emitting control unit; the second light-emitting control unit is connected between the pulse width control unit and the driving unit; the second light-emitting control unit is also used to receive a second light-emitting control signal, which is in an enabled state during the comparison light-emitting phase. Before the charging phase, the second light emission control signal is switched to an enabled-disabled state; the second light emission control signal is switched to an enabled-disabled state earlier than the first light emission control signal.

10. The display device according to claim 2, characterized in that, The switching module includes a charging transistor; the first terminal of the charging transistor is connected to the first node, the second terminal of the charging transistor is connected to the second node, and the control terminal of the charging transistor is used to receive the charging scan signal.

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