A clock-controlled switch relay

Abstract

A clock control switch relay provided by the present invention; it includes an input control circuit, a delay circuit, and a switch circuit. The switch circuit includes two MOS switch lines. The output control circuit includes a thyristor and a magnetic latching relay. The delay circuit is arranged between the input control circuit and the switch circuit. The present invention controls the charging and discharging of the MOS switch through the thyristor to control the magnetic latching relay, thereby controlling the output load voltage. The load capacity provided at the output end is strong, making it applicable to both large and small power occasions; and it does not involve software, so that the circuit does not require additional power supply.

Description

Technical Field

[0001] The present invention relates to a clock-controlled switch relay. Background Art

[0002] Currently, clock-controlled switch relays often use a single-chip microcomputer and a memory to implement the clock and control the internal circuit. Generally, common clock-controlled relays control the subsequent switch to turn on and off through the control terminal clock, thereby controlling the on and off of the load. However, in some scenarios, the load power supply is directly used as the control clock. For such clock-controlled relays, the method of implementing the clock through a single-chip microcomputer and a memory often uses the I / O port of the single-chip microcomputer for output. This method has limited output capacity and cannot be applied to scenarios with a large load current. In order to implement the control of the clock-controlled switch relay in scenarios with a large current, many circuits use thyristors to control the circuit. For example, a relay switch buffer circuit applied to power industry products with the publication number CN113782388A controls an AND-OR gate through a signal generated by a triode, and controls the switching of the relay contacts through an exclusive-OR gate to achieve the turn-off of the circuit. However, its pulse signals are respectively input into the delay circuit and the relay control circuit, and the delay time and the on-off time of the relay will be inconsistent. Summary of the Invention

[0003] To solve the above technical problems, the present invention provides a clock-controlled switch relay.

[0004] The present invention is achieved through the following technical solutions.

[0005] A clock-controlled switch relay provided by the present invention includes an input control circuit, a delay circuit, and a switch circuit. The switch circuit includes two MOS switch lines. The input control circuit includes a thyristor and a magnetic latching relay. The delay circuit is arranged between the input control circuit and the switch circuit;

[0006] The magnetic latching relay includes a post-excitation coil J2 and a pre-excitation coil J1. One ends of the post-excitation coil J2 and the pre-excitation coil J1 are connected to the positive input line, and the other ends are respectively connected to the anodes of the thyristor Q4 and the thyristor Q5. The cathodes of the thyristor Q4 and the thyristor Q5 are connected to the negative input line; the control terminals of the thyristor Q4 and the thyristor Q5 are respectively connected to the cathodes of the diode D5 and the diode D6. The anodes of the diode D5 and the diode D6 are respectively connected to two static contacts of the magnetic latching relay contact group K1. The moving contacts of the magnetic latching relay contact group K1 are respectively connected to the resistor R4 and the resistor R9. The other ends of the resistor R4 and the resistor R9 are respectively connected to the positive input line and the negative input line;

[0007] The two-way MOS switch circuit respectively includes MOS switch transistors Q2 and Q3. The bases of MOS switch transistors Q2 and Q3 are respectively connected to two static contacts of the magnetic latching relay contact group K2. The collectors are respectively connected to the output line OUT2 and the output line OUT1, and the emitters are respectively connected to the positive input line auxiliary circuit; the moving contact of the magnetic latching relay contact group K2 is connected to the positive input line;

[0008] The delay circuit includes a resistor R1 and a capacitor C1. The resistor R1 and the capacitor C1 are connected in parallel between the positive input line and the positive input line auxiliary circuit and in front of the moving contact of the magnetic latching relay contact group K2.

[0009] It further includes a fast discharge circuit. The fast discharge circuit includes a diode D1 and a thyristor Q1. The diode D1 is arranged on the positive input line auxiliary circuit. The base and the emitter of the thyristor Q1 are respectively connected to the positive electrode and the negative electrode of the diode D1, and the collector and the emitter of the thyristor Q1 are respectively connected to the positive input line and the positive input line auxiliary circuit.

[0010] It further includes an anti-mis-switching circuit. The anti-mis-switching circuit includes a capacitor C2, a resistor R10, a capacitor C3, and a resistor R11. The capacitor C2 and the resistor R10 are connected in parallel between the control terminal of the thyristor Q4 and the negative input line, and the capacitor C3 and the resistor R11 are connected in parallel between the control terminal of the thyristor Q5 and the negative input line.

[0011] The front poles of the positive input line and the positive input line auxiliary circuit are both connected to the negative electrode of the diode D2, and the positive electrode of the diode D2 is connected to the voltage input in+.

[0012] The beneficial effects of the present invention are as follows: The magnetic latching relay is controlled by the thyristor to control the charging and discharging of the MOS switch, thereby controlling the output load voltage. The load capacity provided by the output end is strong, making it applicable to both large and small power occasions; and it does not involve software, so the circuit does not require additional power supply. Description of the Drawings

[0013] Figure 1 is a schematic diagram of the circuit structure of the present invention;

[0014] Figure 2 is a schematic diagram of the relay principle of the present invention;

[0015] Figure 3 is a schematic diagram of the pulse timing of the present invention;

[0016] Figure 4 is a schematic diagram of the circuit principle of the present invention. Detailed Embodiments

[0017] The technical solution of the present invention will be further described below, but the scope of protection is not limited thereto.

[0018] As Figure 1 and 2 shown, through the anti-mis-switching circuit of the present application, when the output terminal 1 needs to be turned on during the power-on of the product, a pulse does not appear first, and the input control circuit may be converted, resulting in the conduction of the output terminal 2 during power-on.

[0019] Before the input terminal is powered on, the magnetic latching relay contacts are at the output terminal 1. After power-on, the control makes the output 1 conduct, and the contacts switch to the output 2 control terminal. After the input terminal is powered off, the contact state is maintained. After power-on again, the control makes the output 2 conduct, and the magnetic latching relay contacts switch to the output 1 control terminal.

[0020] The delay circuit: The output terminal switch is controlled by an MOS transistor, and there is a switching time of 3 ms when the internal control terminal is switched. During the switching, the output terminal may be mis-conducted. Therefore, a delay circuit is set between the control circuit and the output circuit to prevent mis-conduction, and the delay time is set to 4 ms.

[0021] The fast discharge circuit: Since the input and output share the power supply, the delay capacitor discharges slowly after power-off, resulting in slow turn-off of the output terminal. Therefore, a fast discharge circuit is added.

[0022] As Figure 3 shown, it is the pulse timing diagram of the in+ input.

[0023] Embodiment 1: As Figure 4 shown, before power-on, when no pulse signal is input to the circuit, for the two sets of switching contacts of the magnetic latching relay, the contact group K1 is connected to the control terminal of Q4, the contact group K2 is connected to Q2, and the output terminal OUT1 conducts.

[0024] Embodiment 2: As Figure 4 shown, after power-on, at the first pulse, when thyristor 4 conducts and triggers the exciting coil, the contact group K1 switches to the control terminal of thyristor Q5. At this time, since thyristor Q4 remains conducting, the control voltage of thyristor Q5 is pulled down, and thyristor Q5 does not conduct. First, the exciting coil does not act, and the contact group 2 is connected to the control terminal of thyristor Q3. Thyristor Q3 conducts, and the output terminal 1 outputs the control voltage. After power-off, thyristor Q3 disconnects, and the contact state of the magnetic latching relay remains unchanged (the contact group 1 is connected to thyristor Q5, and the contact group 2 is connected to thyristor Q3).

[0025] Embodiment 3: As Figure 4As shown, at the second pulse, thyristor Q5 conducts to trigger the pre-excitation coil. The contact group 1 switches to the control terminal of thyristor Q4. At this time, since thyristor Q5 remains conducting, it pulls down the control voltage of thyristor Q4, and thyristor Q4 still does not conduct, so the post-excitation coil does not operate. The contact group 2 is connected to the control terminal of thyristor Q2, and thyristor Q2 conducts, and the control voltage is output at the output terminal 2. After power-off, thyristor Q2 disconnects, and the contact state of the magnetic latching relay remains unchanged.

[0026] Embodiment 4: As Figure 4 shown, a resistor R1 and a capacitor C1 are added in front of thyristor Q2 and thyristor Q3. When the contact group K2 switches, the capacitor C1 will charge at the front end of the circuit, and the circuit will conduct only after 4 ms, avoiding premature power-on of the circuit during the switching of the contact group K2.

[0027] Embodiment 5: As Figure 4 shown, a triode D1 is connected in parallel across the capacitor C1. The triode D1 will quickly turn off the capacitor C1 during the switching of the contact group K2, accelerating the discharge speed of the capacitor.

[0028] Embodiment 6: A capacitor C2 and a resistor R10 are connected in parallel to thyristor Q4, and a capacitor C3 and a resistor R11 are connected in parallel to the control terminal of thyristor Q5. The capacitor C2 and the capacitor C3 respectively filter out the first pulse that appears when the circuit is powered on, ensuring that the MOS switch is correctly turned on when the product is powered on.

Claims

1. A clock-controlled switch relay, characterized in that: It includes an input control circuit, a delay circuit, and a switch circuit. The switch circuit includes two MOS switch lines. The input control circuit includes a thyristor and a magnetic latching relay. The delay circuit is arranged between the input control circuit and the switch circuit; The magnetic latching relay includes a post-excitation coil J2 and a pre-excitation coil J1. One ends of the post-excitation coil J2 and the pre-excitation coil J1 are connected to the positive input line, and the other ends are respectively connected to the anodes of the thyristor Q4 and the thyristor Q5. The cathodes of the thyristor Q4 and the thyristor Q5 are connected to the negative input line; the control ends of the thyristor Q4 and the thyristor Q5 are respectively connected to the cathodes of the diode D5 and the diode D6. The anodes of the diode D5 and the diode D6 are respectively connected to two static contacts of the magnetic latching relay contact group K1. The moving contacts of the magnetic latching relay contact group K1 are respectively connected to the resistor R4 and the resistor R9. The other ends of the resistor R4 and the resistor R9 are respectively connected to the positive input line and the negative input line; The two MOS switch lines respectively include an MOS switch tube Q2 and an MOS switch tube Q3. The bases of the MOS switch tube Q2 and the MOS switch tube Q3 are respectively connected to two static contacts of the magnetic latching relay contact group K2. The collectors are respectively connected to the output line OUT2 and the output line OUT1. The emitters are respectively connected to the auxiliary road of the positive input line; the moving contact of the magnetic latching relay contact group K2 is connected to the positive input line; The delay circuit includes a resistor R1 and a capacitor C1. The resistor R1 and the capacitor C1 are connected in parallel between the positive input line and the auxiliary road of the positive input line and in front of the moving contact of the magnetic latching relay contact group K2.

2. The clock control switch relay according to claim 1, characterized in that: It also includes a fast discharge circuit. The fast discharge circuit includes a diode D1 and a thyristor Q1. The diode D1 is arranged on the auxiliary road of the positive input line. The base and the emitter of the thyristor Q1 are respectively connected to the anode and the cathode of the diode D1. The collector and the emitter of the thyristor Q1 are respectively connected to the positive input line and the auxiliary road of the positive input line.

3. The clock control switch relay according to claim 1, wherein: It also includes an anti-mis-switching circuit. The anti-mis-switching circuit includes a capacitor C2, a resistor R10, a capacitor C3, and a resistor R11. The capacitor C2 and the resistor R10 are connected in parallel between the control end of the thyristor Q4 and the negative input line. The capacitor C3 and the resistor R11 are connected in parallel between the control end of the thyristor Q5 and the negative input line.

4. The clock control switch relay according to claim 1, wherein: The front poles of the positive input line and the auxiliary road of the positive input line are both connected to the cathode of the diode D2. The anode of the diode D2 is connected to the voltage input in+.

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