Display substrate, preparation method thereof and display device

Abstract

The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a substrate and a driving structure layer disposed on the substrate, the driving structure layer includes a first transistor and a second transistor disposed side by side, the first transistor includes a low-temperature polysilicon transistor, and the second transistor includes an oxide transistor; the first transistor includes a first bottom gate electrode serving as a shielding layer, the second transistor includes a second bottom gate electrode serving as a shielding layer, and the first bottom gate electrode and the second bottom gate electrode are disposed in the same layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, and in particular to a display substrate, a manufacturing method thereof, and a display device. BACKGROUND

[0002] An organic light emitting diode (OLED) is an active light emitting display device, which has the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, a flexible display device with an OLED as a light emitting device and a thin film transistor (TFT) for signal control has become a mainstream product in the current display field. SUMMARY

[0003] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0004] In one aspect, the present disclosure provides a display substrate, comprising a substrate and a driving structure layer disposed on the substrate, the driving structure layer comprising a first transistor and a second transistor disposed side by side, the first transistor comprising a low-temperature polysilicon transistor, and the second transistor comprising an oxide transistor; the first transistor comprises a first bottom gate electrode serving as a shielding layer, the second transistor comprises a second bottom gate electrode serving as a shielding layer, and the first bottom gate electrode and the second bottom gate electrode are disposed in the same layer.

[0005] In an exemplary embodiment, the driving structure layer comprises a first conductive layer disposed on the substrate, an active structure layer disposed on a side of the first conductive layer away from the substrate, and a source-drain structure layer disposed on a side of the active structure layer away from the substrate; the first conductive layer comprises a first bottom gate electrode and a second bottom gate electrode disposed in the same layer.

[0006] In an exemplary embodiment, the active structure layer comprises a first insulating layer covering the first conductive layer, a first active layer of the first transistor disposed on a side of the first insulating layer away from the substrate, a second insulating layer covering the first active layer, a first top gate electrode of the first transistor disposed on a side of the second insulating layer away from the substrate, a second active layer of the second transistor disposed on a side of the second insulating layer away from the substrate, a third insulating layer covering the first top gate electrode and the second active layer, and a second top gate electrode of the second transistor disposed on a side of the third insulating layer away from the substrate.

[0007] In an example embodiment, the active structure layer comprises: a first insulating layer covering the first conductive layer, a first active layer of the first transistor disposed on a side of the first insulating layer away from the substrate, a second insulating layer covering the first active layer, a second active layer of the second transistor disposed on a side of the second insulating layer away from the substrate, a third insulating layer covering the second active layer, a first top gate electrode of the first transistor and a second top gate electrode of the second transistor disposed on a side of the third insulating layer away from the substrate; the first top gate electrode and the second top gate electrode are disposed in the same layer.

[0008] In an example embodiment, the source-drain structure layer comprises: a fourth insulating layer disposed on a side of the active structure layer away from the substrate, a source-drain metal layer disposed on the fourth insulating layer, the source-drain metal layer comprising a first source electrode, a first drain electrode, a second source electrode, a second drain electrode, and a first connecting electrode, the first source electrode and the first drain electrode being connected to the first active layer of the first transistor through a first via, the second source electrode and the second drain electrode being connected to the second active layer of the second transistor through a second via, the first connecting electrode being connected to the first bottom gate electrode of the first transistor through a third via.

[0009] In an example embodiment, the depth of the first via is to The depth of the second via is to

[0010] In an example embodiment, the difference between the depth of the first via and the depth of the second via is less than or equal to

[0011] In an example embodiment, the fourth insulating layer comprises a silicon oxide sub-layer and a silicon nitride sub-layer stacked, and the thickness of the silicon nitride sub-layer is less than or equal to 1.5 times the thickness of the silicon oxide sub-layer.

[0012] In an example embodiment, the thickness of the first insulating layer is greater than or equal to 3 times the thickness of the second insulating layer.

[0013] In an example embodiment, a recess is disposed on the substrate, at least part of the second bottom gate electrode is disposed in the recess, at least part of the second active layer of the second transistor is disposed in the recess, and the second top gate electrode of the second transistor is disposed in the recess.

[0014] In an example embodiment, the depth of the recess is greater than or equal to The width of the recess is greater than or equal to 1.2 times the distance between the source region and the drain region of the second active layer of the second transistor.

[0015] In another aspect, the present disclosure also provides a display device comprising the aforementioned display substrate.

[0016] In yet another aspect, the present disclosure also provides a method for manufacturing a display substrate, comprising:

[0017] forming a driving structure layer on a substrate, the driving structure layer comprising a first transistor and a second transistor arranged side by side, the first transistor comprising a low-temperature polysilicon transistor, and the second transistor comprising an oxide transistor; the first transistor comprising a first bottom gate electrode serving as a shielding layer, and the second transistor comprising a second bottom gate electrode serving as a shielding layer, the first bottom gate electrode and the second bottom gate electrode being arranged in the same layer and formed simultaneously by a same patterning process.

[0018] In an exemplary embodiment, forming a driving structure layer on a substrate comprises:

[0019] forming a first conductive layer on a substrate, the first conductive layer comprising a first bottom gate electrode and a second bottom gate electrode arranged in the same layer and formed simultaneously by a same patterning process;

[0020] forming an active structure layer on the first conductive layer, the active structure layer comprising a first active layer and a first top gate electrode of the first transistor, and a second active layer and a second top gate electrode of the second transistor;

[0021] forming a source-drain structure layer on the active structure layer, the source-drain structure layer comprising a first source electrode, a first drain electrode and a first connection electrode of the first transistor, and a second source electrode and a second drain electrode of the second transistor, the first source electrode and the first drain electrode being connected to the first active layer through a first via, the second source electrode and the second drain electrode being connected to the second active layer through a second via, and the first connection electrode being connected to the first bottom gate electrode through a third via, the first via, the second via and the third via being formed simultaneously by a same patterning process.

[0022] In an exemplary embodiment, forming a first conductive layer on a substrate comprises:

[0023] forming a substrate, the substrate comprising a first flexible layer, a first barrier layer, a second flexible layer and a second barrier layer stacked in sequence, the second barrier layer being provided with a recess, the depth of the recess being greater than or equal to

[0024] forming a first conductive layer on the substrate, the first conductive layer comprising a first bottom gate electrode and a second bottom gate electrode arranged in the same layer and formed simultaneously by a same patterning process, at least part of the second bottom gate electrode being arranged in the recess.

[0025] In an example embodiment, forming an active structure layer on the first conductive layer comprises:

[0026] forming a first insulating layer covering the first conductive layer, and a first active layer of the first transistor disposed on the first insulating layer;

[0027] forming a second insulating layer covering the first active layer, and a first top gate electrode of the first transistor disposed on the second insulating layer;

[0028] performing a doping process with the first top gate electrode as a shield;

[0029] forming a second active layer of the second transistor on the second insulating layer;

[0030] forming a third insulating layer covering the first top gate electrode and the second active layer, and a second top gate electrode of the second transistor disposed on the third insulating layer.

[0031] In an example embodiment, forming an active structure layer on the first conductive layer comprises:

[0032] forming a first insulating layer covering the first conductive layer, and a first active layer of the first transistor disposed on the first insulating layer;

[0033] forming a second insulating layer covering the first active layer, and a photoresist shielding pattern disposed on the second insulating layer;

[0034] performing a doping process with the photoresist shielding pattern as a shield;

[0035] forming a second active layer of the second transistor on the second insulating layer;

[0036] forming a third insulating layer covering the second semiconductor layer, and a first top gate electrode of the first transistor and a second top gate electrode of the second transistor disposed on the third insulating layer.

[0037] In an example embodiment, the first via has a depth of to the second via has a depth of to a difference between the depth of the first via and the depth of the second via is less than or equal to

[0038] Other aspects can become apparent after consideration of the drawing and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0039] The accompanying drawings are used to provide further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect true proportions, and the purpose is only to schematically illustrate the present disclosure.

[0040] Figure 1 It is a structural schematic diagram of a display device;

[0041] Figure 2 It is a planar structural schematic diagram of a display substrate;

[0042] Figure 3 It is an equivalent circuit schematic diagram of a pixel driving circuit;

[0043] Figure 4 It is a working timing diagram of a pixel driving circuit;

[0044] Figure 5 It is a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0045] Figure 6 It is a structural schematic diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0046] Figure 7 It is a schematic diagram of another display substrate after forming a base according to the present disclosure;

[0047] Figure 8 It is a schematic diagram of another display substrate after forming a first conductive layer pattern according to the present disclosure;

[0048] Figure 9 It is a schematic diagram of another display substrate after forming a first semiconductor layer pattern according to the present disclosure;

[0049] Figure 10 It is a schematic diagram of another display substrate after forming a second conductive layer pattern according to the present disclosure;

[0050] Figure 11 It is a schematic diagram of another display substrate after forming a second semiconductor layer pattern according to the present disclosure;

[0051] Figure 12 It is a schematic diagram of another display substrate after forming a third conductive layer pattern according to the present disclosure;

[0052] Figure 13 It is a schematic diagram of another display substrate after forming a fourth insulating layer pattern according to the present disclosure;

[0053] Figure 14 It is a schematic diagram of another display substrate after forming a fourth conductive layer pattern according to the present disclosure;

[0054] Figure 15 Another schematic view of a display substrate after forming a first planarization layer pattern according to the present disclosure;

[0055] Figure 16 Another schematic view of a display substrate after forming a fifth conductive layer pattern according to the present disclosure;

[0056] Figure 17 Another schematic view of a display substrate after forming a second planarization layer pattern according to the present disclosure;

[0057] Figure 18 Another schematic view of a display substrate after forming an anode pattern according to the present disclosure;

[0058] Figure 19 Another schematic view of a display substrate according to an exemplary embodiment of the present disclosure;

[0059] Figure 20 Another schematic view of a display substrate according to an exemplary embodiment of the present disclosure;

[0060] Figure 21 Another schematic view of a display substrate after doping according to the present disclosure;

[0061] Figure 22 Another schematic view of a display substrate after forming a second semiconductor layer pattern according to the present disclosure;

[0062] Figure 23 Another schematic view of a display substrate after forming a third conductive layer pattern according to the present disclosure;

[0063] Figure 24 Another schematic view of a display substrate after forming a fourth insulating layer pattern according to the present disclosure;

[0064] Figure 25 Another schematic view of a display substrate after forming a fourth conductive layer pattern according to the present disclosure.

[0065] Explanation of Reference Numerals:

[0066] 1 - glass substrate; 10 - base; 11 - first insulating layer;

[0067] 12 - second insulating layer; 13 - third insulating layer; 14 - fourth insulating layer;

[0068] 15 - first planarization layer; 16 - second planarization layer; 20 - first transistor;

[0069] 21 - first bottom gate electrode; 22 - first active layer; 23 - first top gate electrode;

[0070] 24 - first source electrode; 25 - first drain electrode; 26 - first connection electrode;

[0071] 27 - second connection electrode; 28 - anode; 30 - second transistor;

[0072] 31 - second bottom gate electrode; 32 - second active layer; 33 - second top gate electrode;

[0073] 34 - second source electrode; 35 - second drain electrode; 36 - shielding layer;

[0074] 91 - first recess; 92 - second recess; 93 - third recess;

[0075] 100 - driving structure layer. DETAILED DESCRIPTION

[0076] For the purpose of making the objects, technical solutions and advantages of the present disclosure clearer, below the embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments can be implemented in multiple different forms. It is easily understood by those skilled in the art that the modes and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the content described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other as long as there is no conflict. In order to keep the following description of the embodiments of the present disclosure clear and concise, the detailed description of some known functions and known components is omitted in the present disclosure. The drawings of the embodiments of the present disclosure only involve the structures related to the embodiments of the present disclosure, and other structures can be referred to the generally designed structures

[0077] In the drawings, the size of each constituent element, the thickness of each layer, or the area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and the shape and size of each component in the drawings do not reflect the actual scale. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shape or value shown in the drawings.

[0078] The ordinal numbers "first", "second", "third", and the like in the present specification are used for the purpose of avoiding confusion of the constituent elements, and are not intended to be limiting in number.

[0079] In this specification, terms of "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the positional or directional relationship of the components are used to describe the positional relationship of the components with reference to the drawings for the convenience of explanation and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0080] In this specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements inside. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0081] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region through which current mainly flows.

[0082] In this specification, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in the circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in this specification, "source electrode" and "drain electrode" can be exchanged with each other.

[0083] In this specification, "electrically connected" includes the case where the components are connected together through an element having a certain electrical action. The element having a certain electrical action is not particularly limited as long as it can transmit and receive an electrical signal between the components to be connected. Examples of the element having a certain electrical action include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0084] In this specification, "parallel" means a state where an angle formed by two straight lines is -10° or more and 10° or less, and thus, an angle of -5° or more and 5° or less is also included. In addition, "perpendicular" means a state where an angle formed by two straight lines is 80° or more and 100° or less, and thus, a state where an angle of 85° or more and 95° or less is also included.

[0085] In this specification, "film" and "layer" can be interchanged with each other. For example, "a conductive layer" can be sometimes interchanged with "a conductive film". Similarly, "an insulating film" can be sometimes interchanged with "an insulating layer".

[0086] "About" in this disclosure means not strictly limited to a boundary, allowing a range of values within process and measurement errors.

[0087] Figure 1 A structure diagram of a display device. As Figure 1As shown, the OLED display device can include a timing controller, a data signal driver, a scan signal driver, a light emission signal driver, and a pixel array, and the pixel array can include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), a plurality of light emission signal lines (E1 to Eo), and a plurality of sub-pixels Pxij. In an exemplary embodiment, the timing controller can provide a gray scale value and a control signal suitable for the specification of the data signal driver to the data signal driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan signal driver to the scan signal driver, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emission signal driver to the light emission signal driver. The data signal driver can generate a data voltage to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray scale value and the control signal received from the timing controller. For example, the data signal driver can sample the gray scale value using the clock signal, and apply a data voltage corresponding to the gray scale value to the data signal lines D1 to Dn in units of a pixel row, n can be a natural number. The scan signal driver can generate a scan signal to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan signal driver can sequentially provide the scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan signal driver can be configured in the form of a shift register, and can generate the scan signal in such a manner that the scan start signal provided in the form of an on-level pulse is sequentially transferred to a next stage circuit under the control of the clock signal, m can be a natural number. The light emission signal driver can generate an emission signal to be provided to the light emission signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emission signal driver can sequentially provide the emission signal having an off-level pulse to the light emission signal lines E1 to Eo. For example, the light emission signal driver can be configured in the form of a shift register, and can generate the light emission signal in such a manner that the light emission stop signal provided in the form of an off-level pulse is sequentially transferred to a next stage circuit under the control of the clock signal, o can be a natural number. The pixel array can include a plurality of sub-pixels Pxij. Each sub-pixel Pxij can be connected to a corresponding data signal line, a corresponding scan signal line, and a corresponding light emission signal line, i and j can be natural numbers. The sub-pixel Pxij can refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and to the j-th data signal line.

[0088] Figure 2 FIG. 1 is a schematic view of a planar structure of a display substrate. As shown in FIG. 1, the display substrate can include a plurality of scan signal lines S1 to Sm, a plurality of data signal lines D1 to Dn, and a plurality of light emission signal lines E1 to Eo, m and n can be natural numbers, and o can be a natural number. The display substrate can include a plurality of sub-pixels Pxij, i and j can be natural numbers. The sub-pixel Pxij can refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and to the j-th data signal line. Figure 2As shown, the display substrate may include multiple pixel units P arranged in a matrix. At least one of the multiple pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting devices in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0089] In an exemplary embodiment, a pixel unit P may include red (R) sub-pixels, green (G) sub-pixels, and blue (B) sub-pixels, or it may include red, green, blue, and white sub-pixels; this disclosure does not limit the scope of the invention. In an exemplary embodiment, the shape of the sub-pixels in a pixel unit may be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the three sub-pixels may be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement. When a pixel unit includes four sub-pixels, the four sub-pixels may be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement; this disclosure does not limit the scope of the invention.

[0090] In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Figure 3 This is a schematic diagram of an equivalent circuit for a pixel driving circuit. (Example) Figure 3 As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C, and 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emission signal line E, initial signal line INIT, first power supply line VDD, and second power supply line VSS).

[0091] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3.

[0092] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When an on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits an initialization voltage to the control electrode of the third transistor T3 to initialize the amount of charge of the control electrode of the third transistor T3.

[0093] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When an on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode and the second electrode of the third transistor T3.

[0094] The control electrode of the third transistor T3 is connected to the second node N2, i.e., the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.

[0095] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be referred to as a switching transistor, a scan transistor, or the like, and when an on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 inputs a data voltage of the data signal line D to the pixel driving circuit.

[0096] The control electrode of the fifth transistor T5 is connected to the emission signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the emission signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as emission transistors. When an on-level emission signal is applied to the emission signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0097] The control electrode of the seventh transistor T7 is connected with the first scan signal line S1, the first electrode of the seventh transistor T7 is connected with the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected with the first electrode of the light emitting device. When the turn-on level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits the initialization voltage to the first electrode of the light emitting device, so as to initialize the amount of charge accumulated in the first electrode of the light emitting device or release the amount of charge accumulated in the first electrode of the light emitting device.

[0098] In the example implementation, the second electrode of the light emitting device is connected with the second power supply line VSS, the signal of the second power supply line VSS is a low-level signal, and the signal of the first power supply line VDD is a high-level signal continuously provided. The first scan signal line S1 is a scan signal line in the display row pixel driving circuit, and the second scan signal line S2 is a scan signal line in the pixel driving circuit of the previous display row, i.e., for the nth display row, the first scan signal line S1 is S(n), the second scan signal line S2 is S(n-1), and the second scan signal line S2 of the current display row is the same signal line as the first scan signal line S1 in the pixel driving circuit of the previous display row, which can reduce the signal lines of the display panel and realize a narrow frame of the display panel.

[0099] In the example implementation, the first transistor T1 to the seventh transistor T7 can be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementation, the first transistor T1 to the seventh transistor T7 can include P-type transistors and N-type transistors.

[0100] In the example implementation, the first scan signal line S1, the second scan signal line S2, the light emitting signal line E, and the initial signal line INIT extend along the horizontal direction, and the second power supply line VSS, the first power supply line VDD, and the data signal line D extend along the vertical direction.

[0101] In the example implementation, the light emitting device can be an organic electroluminescence diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0102] Figure 4 FIG. 8 is a timing diagram of a pixel driving circuit according to an example embodiment of the present disclosure. Figure 3 The working process of the example pixel driving circuit is used to illustrate the example embodiment of the present disclosure, Figure 3The pixel driving circuit in the pixel driving circuit includes seven transistors (first transistor T1 to sixth transistor T7), one storage capacitor C and seven signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light-emitting signal line E, initial signal line INIT, first power supply line VDD and second power supply line VSS), and the seven transistors are P-type transistors.

[0103] In the exemplary embodiment, the working process of the pixel driving circuit can include:

[0104] In the first stage A1, referred to as a reset stage, the signal of the second scan signal line S2 is a low-level signal, and the signals of the first scan signal line S1 and the light-emitting signal line E are high-level signals. The signal of the second scan signal line S2 is a low-level signal, so that the first transistor T1 is turned on, and the signal of the initial signal line INIT is provided to the second node N2, so that the storage capacitor C is initialized and the original data voltage in the storage capacitor is cleared. The signals of the first scan signal line S1 and the light-emitting signal line E are high-level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off, and the OLED does not emit light in this stage.

[0105] In the second stage A2, referred to as a data writing stage or threshold compensation stage, the signal of the first scan signal line S1 is a low-level signal, the signals of the second scan signal line S2 and the light-emitting signal line E are high-level signals, and the data signal line D outputs a data voltage. In this stage, the second end of the storage capacitor C is low, so that the third transistor T3 is turned on. The signal of the first scan signal line S1 is a low-level signal, so that the second transistor T2, the fourth transistor T4 and the seventh transistor T7 are turned on. The second transistor T2 and the fourth transistor T4 are turned on, so that the data voltage output by the data signal line D is provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3 and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the second end (the second node N2) of the storage capacitor C is Vd-|Vth|, Vd is the data voltage output by the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, so that the initial voltage of the initial signal line INIT is provided to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), the pre-stored voltage in the first electrode is cleared, the initialization is completed, and it is ensured that the OLED does not emit light. The signal of the second scan signal line S2 is a high-level signal, so that the first transistor T1 is turned off. The signal of the light-emitting signal line E is a high-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned off.

[0106] The third stage A3, referred to as a light emitting stage, has a low signal of the light emitting signal line E and high signals of the first scan signal line S1 and the second scan signal line S2. The low signal of the light emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, so as to drive the OLED to emit light.

[0107] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between the gate electrode and the first electrode of the third transistor T3. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0108] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0109] wherein I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0110] In the exemplary embodiments, the first transistor T1 to the seventh transistor T7 can be low temperature poly-silicon thin film transistors, or can be oxide thin film transistors, or can be low temperature poly-silicon thin film transistors and oxide thin film transistors. The active layer of the low temperature poly-silicon thin film transistor adopts low temperature poly-silicon (LTPS), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. Integrating the low temperature poly-silicon thin film transistor and the oxide thin film transistor on one display substrate forms a low temperature poly-crystalline oxide (LTPO) display substrate, which can take advantage of both and can realize low frequency driving, reduce power consumption (save 5% to 15% of power), and improve display quality.

[0111] The display substrate provided by the present disclosure includes a substrate and a driving structure layer disposed on the substrate, the driving structure layer includes a first transistor and a second transistor disposed side by side, the first transistor includes a low-temperature polysilicon transistor, and the second transistor includes an oxide transistor; the first transistor includes a first bottom gate electrode serving as a shielding layer, the second transistor includes a second bottom gate electrode serving as a shielding layer, and the first bottom gate electrode and the second bottom gate electrode are disposed in the same layer.

[0112] In an example embodiment, the driving structure layer can include a first conductive layer disposed on the substrate, an active structure layer disposed on a side of the first conductive layer away from the substrate, and a source-drain structure layer disposed on a side of the active structure layer away from the substrate; the first conductive layer includes a first bottom gate electrode and a second bottom gate electrode disposed in the same layer.

[0113] In an example embodiment, the active structure layer can include a first insulating layer covering the first conductive layer, a first active layer of the first transistor disposed on a side of the first insulating layer away from the substrate, a second insulating layer covering the first active layer, a first top gate electrode of the first transistor disposed on a side of the second insulating layer away from the substrate, a second active layer of the second transistor disposed on a side of the second insulating layer away from the substrate, a third insulating layer covering the first top gate electrode and the second active layer, and a second top gate electrode of the second transistor disposed on a side of the third insulating layer away from the substrate.

[0114] In an example embodiment, the active structure layer can include a first insulating layer covering the first conductive layer, a first active layer of the first transistor disposed on a side of the first insulating layer away from the substrate, a second insulating layer covering the first active layer, a second active layer of the second transistor disposed on a side of the second insulating layer away from the substrate, a third insulating layer covering the second active layer, a first top gate electrode of the first transistor and a second top gate electrode of the second transistor disposed on a side of the third insulating layer away from the substrate; the first top gate electrode and the second top gate electrode are disposed in the same layer.

[0115] Figure 5 A structural schematic diagram of a display substrate is provided for an example embodiment of the present disclosure. As shown in FIG. 1, the display substrate includes a substrate 1 and a driving structure layer 2 disposed on the substrate 1. The driving structure layer 2 includes a first transistor T1 and a second transistor T2 disposed side by side. The first transistor T1 includes a low-temperature polysilicon transistor, and the second transistor T2 includes an oxide transistor. The first transistor T1 includes a first bottom gate electrode 21 serving as a shielding layer, and the second transistor T2 includes a second bottom gate electrode 22 serving as a shielding layer. The first bottom gate electrode 21 and the second bottom gate electrode 22 are disposed in the same layer. Figure 5As shown, the display substrate can include a substrate 10 and a drive structure layer 100 disposed on the substrate 10, the drive structure layer 100 can include a first transistor 20 and a second transistor 30 disposed side by side. The first transistor 20 can include a first bottom gate electrode 21, a first active layer 22, a first top gate electrode 23, a first source electrode 24 and a first drain electrode 25, the first bottom gate electrode 21 simultaneously serving as a shielding layer of the first transistor 20. The second transistor 30 can include a second bottom gate electrode 31, a second active layer 32, a second top gate electrode 33, a second source electrode 34 and a second drain electrode 35, the second bottom gate electrode 31 simultaneously serving as a shielding layer of the second transistor 30.

[0116] In an example embodiment, the first bottom gate electrode 21 and the second bottom gate electrode 31 are disposed in the same layer and are formed simultaneously by the same patterning process.

[0117] In an example embodiment, the drive structure layer 100 of the present example embodiment can include: a first conductive layer disposed on the substrate 10, the first conductive layer at least including the first bottom gate electrode 21 and the second bottom gate electrode 31; a first insulating layer 11 covering the first conductive layer, a first semiconductor layer disposed on the first insulating layer 11, the first semiconductor layer at least including the first active layer 22; a second insulating layer 12 covering the first semiconductor layer, a second conductive layer and a second semiconductor layer disposed on the second insulating layer 12, the second conductive layer at least including the first top gate electrode 23, the second semiconductor layer at least including the second active layer 32; a third insulating layer 13 covering the second conductive layer and the second semiconductor layer, a third conductive layer disposed on the third insulating layer 13, the third conductive layer at least including the second top gate electrode 33; a fourth insulating layer 14 covering the third conductive layer, a fourth conductive layer disposed on the fourth insulating layer 14, the fourth conductive layer at least including the first source electrode 24, the first drain electrode 25, the second source electrode 34, the second drain electrode 35 and the first connection electrode 26, the first source electrode 24 and the first drain electrode 25 being connected to the first active layer 22 through vias respectively, the second source electrode 34 and the second drain electrode 35 being connected to the second active layer 32 through vias respectively, and the first connection electrode 26 being connected to the first bottom gate electrode 21 through a via.

[0118] In an example embodiment, the drive structure layer 100 can include a first planar layer 15 covering the fourth conductive layer, a fifth conductive layer disposed on the first planar layer 15, and a second planar layer 16 covering the fifth conductive layer. The fifth conductive layer at least includes a second connection electrode 27 and a shielding layer 36, the second connection electrode 27 being connected to the first drain electrode 25 through a via, and the shielding layer 36 serving as a shielding layer of the second transistor 30, a normal projection of the shielding layer 36 on the substrate containing a normal projection of the second active layer 32 on the substrate. The second planar layer 16 is provided with a via, and the via exposes the second connection electrode 27.

[0119] In an exemplary embodiment, the display substrate may include a light-emitting structure layer, which may include an anode, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode is disposed on a second planarization layer and connected to a second connection electrode 27 through a via. A pixel opening is formed on the pixel definition layer, exposing the surface of the anode. The organic light-emitting layer is connected to the anode through the pixel opening, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the drive of the anode and cathode.

[0120] In an exemplary embodiment, the display substrate may include an encapsulation layer, which may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer to ensure that external moisture cannot enter the light-emitting structure layer.

[0121] In an exemplary embodiment, the material of the first active layer 22 may include low-temperature polycrystalline silicon, and the material of the second active layer 32 may include oxide.

[0122] Figure 6 This is a schematic diagram of the structure of another display substrate as an exemplary embodiment of this disclosure. Figure 6 As shown, the display substrate may include a substrate 10 and a driving structure layer 100 disposed on the substrate 10. The driving structure layer 100 includes a first transistor 20 and a second transistor 30 disposed in parallel. The first transistor 20 may be a low-temperature polysilicon transistor, and the second transistor 30 may be an oxide transistor. The first bottom gate electrode 21 of the first transistor 20 and the second bottom gate electrode 31 of the second transistor 30 are disposed in the same layer and formed simultaneously by the same patterning process. Figure 5 Unlike the structure shown, the driving structure layer 100 of this exemplary embodiment is provided with a groove, which is located in the area where the second transistor 20 is located.

[0123] In the example embodiment, the driving structure layer 100 of the example embodiment can include: a first groove provided on the substrate 10, the first groove being provided in an area where the second transistor 20 is located; a first conductive layer provided on the substrate 10, the first conductive layer including at least a first bottom gate electrode 21 and a second bottom gate electrode 31, a middle area of the second bottom gate electrode 31 being provided in the first groove; a first insulating layer 11 covering the first conductive layer; a first semiconductor layer provided on the first insulating layer 11, the first semiconductor layer including at least a first active layer 22; a second insulating layer 12 covering the first semiconductor layer; a second conductive layer and a second semiconductor layer provided on the second insulating layer 12, the second conductive layer including at least a first top gate electrode 23, the second semiconductor layer including at least a second active layer 32, a middle area of the second active layer 32 being provided in the first groove; a third insulating layer 13 covering the second conductive layer and the second semiconductor layer; a third conductive layer provided on the third insulating layer 13, the third conductive layer including at least a second top gate electrode 33, the second top gate electrode 33 being provided in the first groove; a fourth insulating layer 14 covering the third conductive layer; a fourth conductive layer provided on the fourth insulating layer 14, the fourth conductive layer including at least a first source electrode 24, a first drain electrode 25, a second source electrode 34, a second drain electrode 35, and a first connection electrode 26, the first source electrode 24 and the first drain electrode 25 being connected to the first active layer 22 through vias respectively, the second source electrode 34 and the second drain electrode 35 being connected to the second active layer 32 through vias respectively, the first connection electrode 26 being connected to the first bottom gate electrode 21 through a via; a first planar layer 15 covering the fourth conductive layer, the first planar layer 15 being provided with a second groove, a position of the second groove corresponding to a position of the first groove; a fifth conductive layer provided on the first planar layer 15, the fifth conductive layer including at least a second connection electrode 27 and a shielding layer 36, the second connection electrode 27 being connected to the first drain electrode 25 through a via, a middle area of the shielding layer 36 being provided in the second groove, the shielding layer 36 serving as a shielding layer of the second transistor 30, a normal projection of the shielding layer 36 on the substrate containing a normal projection of the second active layer 32 on the substrate; and a second planar layer 16 covering the fifth conductive layer, the second planar layer 16 being provided with a via, the via exposing the second connection electrode 27.

[0124] The preparation process of the substrate is exemplarily illustrated below by the present exemplary embodiment. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and the like for metal material, inorganic material or transparent conductive material, and includes coating organic material, mask exposure and development and the like for organic material. The deposition can adopt any one or more of sputtering, evaporation, chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited by the present disclosure. The "thin film" refers to a thin film of a certain material on a substrate made by deposition, coating or other processes. If the "thin film" does not need a patterning process in the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" needs a patterning process in the entire manufacturing process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the present exemplary embodiment, "the orthographic projection of A contains the orthographic projection of B" or "the orthographic projection of B is within the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0125] Figures 7 to 18 A schematic diagram of a preparation process of a display substrate. In the exemplary embodiment, the preparation process of the display substrate can include the following operations.

[0126] (A1) A substrate 10 is prepared on a glass carrier plate 1. In an exemplary embodiment, the substrate 10 can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on the glass carrier plate 1. The material of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc., the material of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, the first and second inorganic material layers are also called barrier layers, and the material of the semiconductor layer can be amorphous silicon (a-si). In an exemplary embodiment, taking the stack structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, the preparation process can include: first, coating a layer of polyimide on the glass carrier plate 1, and after curing to form a film, a first flexible (PI1) layer 10A is formed; then depositing a layer of barrier film on the first flexible layer to form a first barrier (Barrier1) layer 10B covering the first flexible layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer 10C covering the first barrier layer; then coating a layer of polyimide on the amorphous silicon layer, and after curing to form a film, a second flexible (PI2) layer 10D is formed; then depositing a layer of barrier film on the second flexible layer to form a second barrier (Barrier2) film covering the second flexible layer, and the second barrier film is patterned by a patterning process to form a second barrier layer 10E provided with a first groove 91, and the preparation of the substrate 10 is completed, as shown in Figure 7 .

[0127] In an exemplary embodiment, the depth h of the first groove 91 can be greater than or equal to

[0128] In an exemplary embodiment, the second barrier film in the first groove 91 is etched away, and the surface of the second flexible layer 10D can be exposed.

[0129] In an exemplary embodiment, the width L of the first groove 91 can be greater than or equal to 1.2 times the distance between the source region and the drain region in the subsequently formed second active layer.

[0130] (A2) A first conductive layer pattern is formed. In an exemplary embodiment, forming the first conductive layer pattern can include: depositing a first metal film on the substrate 10, and patterning the first metal film by a patterning process to form a first conductive layer pattern on the substrate 10, the first conductive layer pattern at least including a first bottom gate electrode 21 and a second bottom gate electrode 31, the middle region of the second bottom gate electrode 31 being arranged in the first groove 91, and the edge region being arranged on the substrate 10 (second barrier layer), as shown in Figure 8 .

[0131] In the example embodiment, the first bottom gate electrode 21 can serve as both a shield layer of the first transistor and a bottom gate electrode of the first transistor, and the second bottom gate electrode 31 can serve as both a shield layer of the second transistor and a bottom gate electrode of the second transistor.

[0132] In the example embodiment, the first conductive layer can be referred to as a light shield layer (LS), and the thickness of the first conductive layer can be about 1000-3000 nm. to For example, the thickness of the first conductive layer can be about 1000-3000 nm.

[0133] (A3) Forming a first semiconductor layer pattern. In the example embodiment, forming the first semiconductor layer pattern can include: sequentially depositing a first insulating thin film and a first semiconductor thin film on the substrate on which the aforementioned pattern is formed, patterning the first semiconductor thin film by a patterning process, forming a first insulating layer 11 covering the entire substrate 10 and a first semiconductor layer pattern disposed on the first insulating layer 11, the first semiconductor layer pattern including at least a first active layer 22, as shown in FIG. 2. Figure 9

[0134] In the example embodiment, the first active layer 22 can be a low-temperature polysilicon active layer, and the orthographic projection of the first active layer 22 on the substrate is within the range of the orthographic projection of the first bottom gate electrode 21 on the substrate.

[0135] In the example embodiment, patterning the first semiconductor thin film by the patterning process can include: first forming an amorphous silicon (a-si) thin film on the first insulating thin film, performing dehydrogenation treatment on the amorphous silicon thin film, performing crystallization treatment on the amorphous silicon thin film after the dehydrogenation treatment to form a polysilicon thin film. Subsequently, the polysilicon thin film is patterned to form the first semiconductor layer pattern. Since a large amount of hydrogen in amorphous silicon can cause defects in subsequent processes, a process for removing hydrogen needs to be performed after the amorphous silicon thin film is formed. The crystallization process is a process for crystallizing amorphous silicon to form polysilicon (p-si). For example, the crystallization process can be performed by an excimer laser annealing (ELA) process. Since the annealing process for forming polysilicon can damage the oxide, the preparation of the first active layer of low-temperature polysilicon is arranged before the preparation of the second active layer of metal oxide.

[0136] In the example embodiment, the first insulating layer can be referred to as a buffer layer, and is used to improve the water-oxygen resistance of the substrate. The first insulating layer can be silicon oxide (SiOx) or silicon nitride (SiNx), can be a single layer, or can be a stack of SiOx / SiNx, and the thickness of the first insulating layer can be about 100-1000 nm. to ​

[0137] (A4) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern can include: on the substrate on which the aforementioned patterns are formed, sequentially depositing a second insulating thin film and a second metal thin film, patterning the second metal thin film by a patterning process, forming a second insulating layer 12 covering the first semiconductor layer pattern, and a second conductive layer pattern disposed on the second insulating layer 12, the second conductive layer pattern at least including a first top gate electrode 23, as shown in FIG. 2B. Figure 10

[0138] In an exemplary embodiment, the orthographic projection of the first top gate electrode 23 on the substrate is within the range of the orthographic projection of the first active layer 22 on the substrate.

[0139] In an exemplary embodiment, the second conductive layer can be referred to as a first gate metal layer (GATE1). The thickness of the second conductive layer can be about to For example, the thickness of the second conductive layer can be about

[0140] In an exemplary embodiment, the second insulating layer can be referred to as a gate insulating (GI) layer. The second insulating layer can be SiOx or SiNx, can be a single layer, or can be a stack of SiOx / SiNx. The thickness of the second insulating layer can be about to and the thickness of the second insulating layer is less than or equal to one third of the thickness of the first insulating layer, i.e. the thickness of the first insulating layer is greater than or equal to 3 times the thickness of the second insulating layer.

[0141] In an exemplary embodiment, after forming the second conductive layer pattern, a doping process and an activation process are performed on the two side regions of the first active layer 22 that are not shielded by the first top gate electrode 23, using the second conductive layer pattern as a shield, so that the middle region of the first active layer 22 that is shielded by the first top gate electrode 23 forms a channel, and the two side regions that are not shielded by the first top gate electrode 23 are processed into doped regions, the doped regions being respectively a source region and a drain region of the first active layer 22, and the source region and the drain region being configured to be connected to the first source electrode and the first drain electrode formed subsequently.

[0142] (A5) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern can include: on the substrate on which the aforementioned patterns are formed, depositing a second semiconductor thin film, patterning the second semiconductor thin film by a patterning process, forming a second semiconductor layer pattern on the second insulating layer 12, the second semiconductor layer pattern at least including a second active layer 32, as shown in FIG. 2C. Figure 11

[0143] ​​In the example embodiment, the second active layer 32 is located corresponding to the position of the second bottom gate electrode 31, the middle region of the second active layer 32 is arranged in the first recess 91, and the edge region is arranged on the second insulating layer 12. The orthographic projection of the second active layer 32 on the substrate is within the orthographic projection of the second bottom gate electrode 31 on the substrate.

[0144] In the example embodiment, the second active layer 32 can be an oxide active layer, and the oxide can be any one or more of indium gallium zinc oxide (InGaZnO), indium gallium zinc nitride oxide (InGaZnON), zinc oxide (ZnO), zinc nitride oxide (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper oxide sulfur oxide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). In some possible implementations, the second active layer 32 can employ indium gallium zinc oxide (IGZO), and the electron mobility of the indium gallium zinc oxide (IGZO) is higher than that of amorphous silicon.

[0145] In the example embodiment, the thickness of the second active layer 32 can be about to For example, the thickness of the second active layer 32 can be about

[0146] In the example embodiment, the distance between the middle region of the second active layer 32 located in the first recess 91 and the substrate can be less than the distance between the first active layer 22 and the substrate, and the distance between the edge region of the second active layer 32 located outside the first recess 91 and the substrate can be greater than the distance between the first active layer 22 and the substrate.

[0147] (A6) Forming a third conductive layer pattern. In the example embodiment, forming the third conductive layer pattern can include: sequentially depositing a third insulating thin film and a third metal thin film on the substrate on which the aforementioned patterns are formed, patterning the third metal thin film by a patterning process, forming a third insulating layer 13 covering the second active layer pattern and the second conductive layer pattern, and a third conductive layer pattern arranged on the third insulating layer 13, the third conductive layer pattern at least including a second top gate electrode 33, as shown in Figure 12 .

[0148] In the example embodiment, the second top gate electrode 33 is arranged in the first recess 91, and the orthographic projection of the second top gate electrode 33 on the substrate is within the orthographic projection of the second active layer 32 on the substrate.

[0149] In an example embodiment, the third conductive layer can be referred to as a second gate metal layer (GATE2). The thickness of the third conductive layer can be about 1000-2000 A. to For example, the thickness of the third conductive layer can be about 1000-2000 A.

[0150] In an example embodiment, the third insulating layer can be referred to as a gate insulating (GI) layer. The third insulating layer can employ SiOx, and the thickness of the third insulating layer can be about 1000-2000 A. to

[0151] (A7) Forming a fourth insulating layer pattern. In an example embodiment, forming the fourth insulating layer pattern can include: on the substrate on which the aforementioned patterns are formed, depositing a fourth insulating thin film, patterning the fourth insulating thin film through a patterning process, forming a fourth insulating layer 14 pattern covering the third conductive layer pattern, the fourth insulating layer 14 being provided with a plurality of vias, the plurality of vias can include: a first via K1 located at both ends of the first active layer 22 respectively, a second via K2 located at both ends of the second active layer 32 respectively, and a third via K3 located at one side of the first bottom gate electrode 21, as shown in Figure 13 .

[0152] In an example embodiment, the fourth insulating layer 14, the third insulating layer 13 and the second insulating layer 12 in the first via K1 are etched away, exposing the surfaces of the source and drain regions on both sides of the first active layer 22, and the first via K1 can be referred to as a low temperature poly-silicon (CNT-L) via. The second via K2 is located outside the first groove 91, and the fourth insulating layer 14 and the third insulating layer 13 in the second via K2 are etched away, exposing the surfaces of the source and drain regions on both sides of the second active layer 32, and the second via K2 can be referred to as an oxide (CNT-O) via. The fourth insulating layer 14, the third insulating layer 13, the second insulating layer 12 and the first insulating layer 11 in the third via K3 are etched away, exposing the surface of the first bottom gate electrode 21. In an example embodiment, the second via K2 exposes a distance of 1.2 times between the source region and the drain region of the second active layer 32, which can be less than or equal to the width L of the first groove 91, to ensure the shielding effect of the second bottom gate electrode on the channel region of the second active layer.

[0153] In an example embodiment, the fourth insulating layer can be referred to as an interlayer insulating (ILD) layer. The fourth insulating layer can employ a stack of SiOx / SiNx, i.e., the fourth insulating layer includes a stacked SiOx sub-layer and a SiNx sub-layer, and the overall thickness of the fourth insulating layer can be about 1000-2000 A. to and the thickness of the SiNx sub-layer is less than or equal to 1.5 times the thickness of the SiOx sub-layer.

[0154] In the example embodiment, since the first bottom gate electrode and the second bottom gate electrode as the lower light shielding layer are prepared simultaneously in the same patterning process, the number of insulating layers is reduced, and the depth difference between the CNT-L via hole and the CNT-O via hole is reduced to be less than or equal to The depth of the CNT-L via hole is about to That is, the total thickness of the second insulating layer, the third insulating layer and the fourth insulating layer, the depth of the CNT-O via hole is about to That is, the total thickness of the third insulating layer and the fourth insulating layer. The reduction of the depth difference between the CNT-L via hole and the CNT-O via hole is beneficial to reduce the process requirement of synchronous etching, reduce the process difficulty, so that the CNT-L via hole and the CNT-O via hole can be formed simultaneously in the same patterning process, reduce the number of patterning processes, simplify the process, and save the production cost.

[0155] In the example embodiment, after forming the plurality of via holes, annealing treatment can be performed to improve the material properties of the first active layer and the second active layer through a high-temperature annealing process to improve the electrical performance of the transistor. After the annealing process, cleaning treatment can be performed to remove the oxide on the surface of the first active layer in the first via hole by using a cleaning liquid to improve the connection quality of the first active layer and the subsequently formed first source electrode and first drain electrode.

[0156] (A8) Forming a fourth conductive layer pattern. In the example embodiment, forming the fourth conductive layer pattern can include: depositing a fourth metal thin film on the substrate on which the aforementioned patterns are formed, patterning the fourth metal thin film through a patterning process, and forming a fourth conductive layer pattern on the fourth insulating layer 14, the fourth conductive layer pattern at least including a first source electrode 24, a first drain electrode 25, a second source electrode 34, a second drain electrode 35 and a first connection electrode 26, the first source electrode 24 and the first drain electrode 25 being connected with the source region and the drain region of the first active layer 22 through the first via hole K1 respectively, the first connection electrode 26 being connected with the first bottom gate electrode 21 through the third via hole K3, the second source electrode 34 and the second drain electrode 35 being connected with the source region and the drain region of the second active layer 32 through the second via hole K2 respectively, as shown in Figure 14 .

[0157] In the example embodiment, the fourth conductive layer can be referred to as a first source-drain metal layer (SD1). The thickness of the fourth conductive layer can be about to For example, the thickness of the fourth conductive layer can be about

[0158] In the example embodiment, the first bottom gate electrode 21, the first active layer 22, the first top gate electrode 23, the first source electrode 24 and the first drain electrode 25 constitute the first transistor 20, the first bottom gate electrode 21 serves as both a lower shielding layer and a bottom gate electrode of the first transistor 20, and the first transistor 20 can be a low-temperature polysilicon transistor. The second bottom gate electrode 31, the second active layer 32, the second top gate electrode 33, the second source electrode 34 and the second drain electrode 35 constitute the second transistor 30, the second bottom gate electrode serves as both a lower shielding layer and a bottom gate electrode of the second transistor 30, and the second transistor 30 can be an oxide transistor. In the example embodiment, the first transistor can be a driving transistor in a pixel driving circuit, and the second transistor can be at least one of a plurality of switching transistors in the pixel driving circuit. In the example embodiment of the present disclosure, the pixel driving circuit of the display substrate includes at least one low-temperature polysilicon transistor and at least one oxide transistor, and the at least one oxide transistor adopts the preparation process of the example embodiment.

[0159] In the example embodiment, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can adopt a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0160] In the example embodiment, the fourth conductive layer can adopt a Ti / Al / Ti three-layer composite structure, the aluminum layer is located between the first titanium layer and the second titanium layer, the first titanium layer is located on the side of the aluminum layer adjacent to the substrate, and the second titanium layer is located on the side of the aluminum layer away from the substrate. In the example embodiment, the thickness of the first titanium layer can be about 5-50 nm, for example, about 10 nm. to The thickness of the aluminum layer can be about 5-50 nm, for example, about 10 nm. to The thickness of the second titanium layer can be about 5-50 nm, for example, about 10 nm. to For example, the thickness of the first titanium layer can be about 5-50 nm, for example, about 10 nm. The thickness of the aluminum layer can be about 5-50 nm, for example, about 10 nm. The thickness of the second titanium layer can be about 5-50 nm, for example, about 10 nm.

[0161] (A9) Forming a first planarization layer pattern. In the example embodiment, forming the first planarization layer pattern can include: on the substrate on which the aforementioned patterns are formed, coating a first planarization film, and patterning the first planarization film by a patterning process to form a first planarization layer 15 pattern covering the fourth conductive layer pattern, the first planarization layer 15 being provided with the fourth via hole K4 and the second groove 92, such as Figure 15As shown.

[0162] In an exemplary embodiment, the first planar film within the fourth via K4 is removed to expose the surface of the first drain electrode of the first transistor 20. The first planar film within the second recess 92 is partially removed, and the position of the second recess 92 corresponds to the position of the first recess 91.

[0163] In an exemplary embodiment, a passivation (PVX) layer can be provided between the fourth insulating layer and the first planar layer.

[0164] (A10) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer pattern can include: depositing a fifth metal film on a substrate on which the aforementioned patterns are formed, patterning the fifth metal film by a patterning process, and forming the fifth conductive layer pattern on the first planar layer 15, the fifth conductive layer pattern at least including the second connection electrode 27 and the shielding layer 36, the second connection electrode 27 being connected to the first drain electrode of the first transistor 20 through the fourth via K4, the shielding layer 36 having a middle region provided within the second recess 92 and a peripheral region provided on the first planar layer 15, as shown in Figure 16 As shown.

[0165] In an exemplary embodiment, the shielding layer 36 serves as an upper shielding layer of the second transistor 30, and the orthogonal projection of the shielding layer 36 on the substrate contains the orthogonal projection of the second active layer on the substrate.

[0166] In an exemplary embodiment, the fourth conductive layer can be referred to as a second source-drain metal layer (SD2). The thickness of the fifth conductive layer can be about to For example, the thickness of the fifth conductive layer can be about

[0167] (A11) Forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern can include: coating a second planar film on a substrate on which the aforementioned patterns are formed, patterning the second planar film by a patterning process, and forming the second planar layer 16 pattern covering the second connection electrode 27, the second planar layer 16 being provided with a fifth via K5 and a third recess 93, as shown in Figure 17 As shown.

[0168] In an exemplary embodiment, the second planar film within the fifth via K5 is removed to expose the surface of the second connection electrode 27. The second planar film within the third recess 93 is partially removed, and the position of the third recess 93 corresponds to the position of the second recess 92.

[0169] (A12) forming an anode pattern. In an exemplary embodiment, forming an anode pattern can include: on the substrate on which the aforementioned pattern is formed, depositing a conductive thin film, patterning the conductive thin film through a patterning process, forming an anode 28 pattern on the second planar layer 16, the anode 28 being connected with the second connecting electrode 27 through the fifth via hole K5, as shown in Figure 18

[0170] An exemplary embodiment of the present disclosure shows that in the preparation of the display substrate, processes such as sequentially forming a pixel definition layer, an organic light-emitting layer, a cathode, and an encapsulation layer can be included, the pixel definition layer has a pixel opening formed thereon, the pixel opening exposes the anode, the organic light-emitting layer is connected with the anode through the pixel opening, and the cathode is connected with the organic light-emitting layer.

[0171] In an exemplary embodiment, the organic light-emitting layer can include a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a light-emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL) stacked. In an exemplary embodiment, the hole injection layer of all sub-pixels can be a common layer connected together, the electron injection layer of all sub-pixels can be a common layer connected together, the hole transport layer of all sub-pixels can be a common layer connected together, the electron transport layer of all sub-pixels can be a common layer connected together, the hole blocking layer of all sub-pixels can be a common layer connected together, the light-emitting layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated, and the electron blocking layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated. In an exemplary embodiment, the encapsulation layer can include a stacked structure of a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer, the first encapsulation layer adopts an inorganic material, the second encapsation layer adopts an organic material, and the third encapsation layer adopts an inorganic material, the second encapsation layer is arranged between the first encapsation layer and the third encapsation layer, and can ensure that external water vapor cannot enter the light-emitting structure layer.

[0172] In an exemplary embodiment, the preparation process of the display substrate can further include: peeling the display substrate from the glass carrier plate 1 through a peeling process, attaching a back film to the back of the display substrate (the surface of the substrate 10 away from the film layer) in a roll-to-roll manner, cutting along the cutting groove by using a cutting device, and the like, which are not limited by the present disclosure.

[0173] ​A display substrate of a traditional structure is formed by 14 times of patterning process, and the preparation process of the display substrate comprises: (1) forming a first insulating layer and an LTPS active layer on a substrate; (2) forming a second insulating layer and a first top gate electrode; (3) forming a third insulating layer and a shielding layer; (4) forming a fourth insulating layer and an Oxide active layer; (5) forming a fifth insulating layer and a second top gate electrode; (6) forming a sixth insulating layer, and forming a low-temperature polycrystalline silicon (CNT-L) via hole in the sixth insulating layer to expose the LTPS active layer; (7) forming an oxide (CNT-O) via hole in the sixth insulating layer to expose the Oxide active layer; (8) forming a first drain-source electrode and a second drain-source electrode; (9) forming a seventh insulating layer, and forming a via hole in the seventh insulating layer to expose the first drain electrode; (10) forming a first planar layer, and forming a via hole in the first planar layer to expose the first drain electrode; (11) forming a connecting electrode; (12) forming a second planar layer, and forming a via hole in the second planar layer to expose the connecting electrode; (13) forming an anode; and (14) forming a pixel definition layer and an isolation column. In the preparation process, the depth of the CNT-L via hole is relatively deep (the via hole depth is about the sum of the thicknesses of the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer), the depth of the CNT-O via hole is relatively shallow (the via hole depth is about the sum of the thicknesses of the fifth insulating layer and the sixth insulating layer), and the depth difference between the CNT-L via hole and the CNT-O via hole is relatively large, so that the synchronous etching process is required to be very high, and the process difficulty is relatively large. Therefore, the CNT-L via hole and the CNT-O via hole are formed by different patterning processes, which not only increases the number of patterning processes and the production cost, but also leads to poor transistor performance.

[0174] The display substrate provided in this exemplary embodiment reduces the number of insulating layers by simultaneously fabricating the first bottom gate electrode of the first transistor and the second bottom gate electrode of the second transistor in the same patterning process. This reduces the depth difference between CNT-L and CNT-O vias, lowers the process difficulty, and allows CNT-L and CNT-O vias to be formed simultaneously in the same patterning process, reducing the number of patterning steps, simplifying the process, and saving production costs. By reducing the number of insulating layers, the overall thickness of the display substrate is effectively reduced, which is beneficial for thinner and lighter designs. Furthermore, it avoids excessive backplane stress caused by too many inorganic film layers, which is beneficial for flexibility. By reducing the number of insulating layers, the first connection electrode can be directly connected to the first bottom gate electrode through a via, instead of using the traditional bridging method where the first connection electrode is connected to the first bottom gate electrode through the first gate metal layer. This effectively avoids defects such as increased resistance caused by bridging. Furthermore, by creating a groove in the region where the second transistor is located, this disclosure not only further reduces the overall thickness of the display substrate, facilitating thinner and more flexible designs, but also enhances the shielding effect through the upper and lower shielding layers, ensuring the electrical performance of the second transistor and improving display quality. Moreover, for bent display substrates, creating a groove in the region where the second transistor is located helps improve the electrical stability of the second active layer during bending.

[0175] Figure 19 This is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure. Figure 19 As shown, the display substrate may include a substrate 10 and a driving structure layer 100 disposed on the substrate 10. The driving structure layer 100 may include a first transistor 20 and a second transistor 30 disposed in parallel. The first transistor 20 may include a first bottom gate electrode 21, a first active layer 22, a first top gate electrode 23, a first source electrode 24, and a first drain electrode 25. The first bottom gate electrode 21 also serves as a shielding layer for the first transistor 20. The second transistor 30 may include a second bottom gate electrode 31, a second active layer 32, a second top gate electrode 33, a second source electrode 34, and a second drain electrode 35. The second bottom gate electrode 31 also serves as a shielding layer for the second transistor 30.

[0176] In an exemplary embodiment, the first bottom gate electrode 21 and the second bottom gate electrode 31 are disposed on the same layer and formed simultaneously through the same patterning process. The first transistor 20 can be a low-temperature polysilicon transistor, and the second transistor 30 can be an oxide transistor. Figure 5 The difference in the structure shown is that the first top gate electrode 23 and the second top gate electrode 33 in this exemplary embodiment are disposed in the same layer and are formed simultaneously by the same patterning process.

[0177] In an exemplary embodiment, the driving structure layer 100 of this exemplary embodiment may include: a first conductive layer disposed on a substrate 10, the first conductive layer including at least a first bottom gate electrode 21 and a second bottom gate electrode 31; a first insulating layer 11 covering the first conductive layer, a first semiconductor layer disposed on the first insulating layer 11, the first semiconductor layer including at least a first active layer 22; a second insulating layer 12 covering the first semiconductor layer, a second semiconductor layer disposed on the second insulating layer 12, the second semiconductor layer including at least a second active layer 32; a third insulating layer 13 covering the second semiconductor layer, a third conductive layer disposed on the third insulating layer 13, the third conductive layer including at least a first top gate electrode 23 and a second top gate electrode 33; a fourth insulating layer 14 covering the third conductive layer, a fourth conductive layer disposed on the fourth insulating layer 14, the fourth conductive layer including at least a first source electrode 24 and a first... The system includes a drain electrode 25, a second source electrode 34, a second drain electrode 35, and a first connection electrode 26. The first source electrode 24 and the first drain electrode 25 are connected to the first active layer 22 via vias, the second source electrode 34 and the second drain electrode 35 are connected to the second active layer 32 via vias, and the first connection electrode 26 is connected to the first bottom gate electrode 21 via a via. A first planarization layer 15 covers the fourth conductive layer, and a fifth conductive layer is disposed on the first planarization layer 15. The fifth conductive layer includes at least a second connection electrode 27 and a shielding layer 36. The second connection electrode 27 is connected to the first drain electrode 25 via a via, and the shielding layer 36 serves as a shielding layer for the second transistor 30. The orthographic projection of the shielding layer 36 onto the substrate includes the orthographic projection of the second active layer 32 onto the substrate. A second planarization layer 16 covers the fifth conductive layer, and a via is disposed on the second planarization layer 16, exposing the second connection electrode 27.

[0178] Figure 20 This is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure. Figure 20 As shown, the display substrate may include a substrate 10 and a driving structure layer 100 disposed on the substrate 10. The driving structure layer 100 includes a first transistor 20 and a second transistor 30 disposed in parallel. The first transistor 20 may be a low-temperature polysilicon transistor, and the second transistor 30 may be an oxide transistor. The first bottom gate electrode 21 of the first transistor 20 and the second bottom gate electrode 31 of the second transistor 30 are disposed in the same layer and formed simultaneously by the same patterning process. The first top gate electrode 23 of the first transistor 20 and the second top gate electrode 33 of the second transistor 30 are disposed in the same layer and formed simultaneously by the same patterning process. Figure 19 Unlike the structure shown, the driving structure layer 100 of this exemplary embodiment is provided with a groove, which is located in the area where the second transistor 20 is located.

[0179] In the exemplary embodiment, the driving structure layer 100 of the present exemplary embodiment can include: a first recess provided on the substrate 10, the first recess being provided in a region where the second transistor 20 is located; a first conductive layer provided on the substrate 10, the first conductive layer including at least a first bottom gate electrode 21 and a second bottom gate electrode 31, a middle region of the second bottom gate electrode 31 being provided in the first recess; a first insulating layer 11 covering the first conductive layer; a first semiconductor layer provided on the first insulating layer 11, the first semiconductor layer including at least a first active layer 22; a second insulating layer 12 covering the first semiconductor layer; a second semiconductor layer provided on the second insulating layer 12, the second semiconductor layer including at least a second active layer 32, a middle region of the second active layer 32 being provided in the first recess; a third insulating layer 13 covering the second semiconductor layer; a third conductive layer provided on the third insulating layer 13, the third conductive layer including at least a first top gate electrode 23 and a second top gate electrode 33, the second top gate electrode 33 being provided in the first recess; a fourth insulating layer 14 covering the third conductive layer; a fourth conductive layer provided on the fourth insulating layer 14, the fourth conductive layer including at least a first source electrode 24, a first drain electrode 25, a second source electrode 34, a second drain electrode 35, and a first connection electrode 26, the first source electrode 24 and the first drain electrode 25 being connected to the first active layer 22 through vias respectively, the second source electrode 34 and the second drain electrode 35 being connected to the second active layer 32 through vias respectively, the first connection electrode 26 being connected to the first bottom gate electrode 21 through a via; a first planarization layer 15 covering the fourth conductive layer, the first planarization layer 15 being provided with a second recess, the second recess being located at a position corresponding to the position of the first recess; a fifth conductive layer provided on the first planarization layer 15, the fifth conductive layer including at least a second connection electrode 27 and a shielding layer 36, the second connection electrode 27 being connected to the first drain electrode 25 through a via, a middle region of the shielding layer 36 being provided in the second recess, the shielding layer 36 serving as a shielding layer of the second transistor 30, and a normal projection of the shielding layer 36 on the substrate containing a normal projection of the second active layer 32 on the substrate; and a second planarization layer 16 covering the fifth conductive layer, the second planarization layer 16 being provided with a via exposing the second connection electrode 27.

[0180] The preparation process of the substrate is exemplarily illustrated below by the present exemplary embodiment. Figures 21 to 25 A schematic diagram of another preparation process of the substrate is shown. In the exemplary embodiment, the preparation process of the substrate of the present exemplary embodiment can include the following operations.

[0181] (B1) to (B3) A substrate provided with a first recess is prepared on a glass carrier plate, and a first conductive layer and a first semiconductor layer pattern are sequentially formed on the substrate. The preparation process can be the same as the preparation process (A1) to (A3) of the foregoing embodiment.

[0182] (B4) performing a doping process on the first active layer. In an exemplary embodiment, performing the doping process on the first active layer can include: on the substrate on which the aforementioned patterns are formed, first depositing a second insulating thin film to form a second insulating layer 12 covering the first semiconductor layer pattern, then coating a layer of photoresist on the second insulating thin film, forming a photoresist pattern on the second insulating layer 12 by exposing and developing the photoresist, the photoresist pattern including at least the first shielding pattern 41 and the second shielding pattern 42. Subsequently, using the photoresist pattern as a shield, performing a doping process on the two side regions of the first active layer 22 that are not shielded by the first shielding pattern 41, so that the middle region of the first active layer 22 that is shielded by the first shielding pattern 41 forms a channel, and the two side regions that are not shielded by the first shielding pattern 41 are processed into doped regions, which are respectively a source region and a drain region of the first active layer 22, and the source region and the drain region are configured to be connected to the first source electrode and the first drain electrode formed subsequently, as shown in Figure 21 Subsequently, peeling off the photoresist pattern, and performing an activation process on the first active layer 22.

[0183] In an exemplary embodiment, the position, shape, and material of the first active layer 22 can be the same as in the aforementioned embodiments.

[0184] In an exemplary embodiment, the first shielding pattern 41 and the second shielding pattern 42 are configured to shield during the doping process. The orthographic projection of the first shielding pattern 41 on the substrate is within the orthographic projection of the first active layer 22 on the substrate, and the position and shape of the first shielding pattern 41 can be similar to the position and shape of the first top gate electrode formed subsequently. The orthographic projection of the second shielding pattern 42 on the substrate is within the orthographic projection of the second bottom gate electrode 31 on the substrate, and the position and shape of the second shielding pattern 42 can be similar to the position and shape of the second active layer formed subsequently. In an exemplary embodiment, the second shielding pattern 42 can reduce the number of ions in the second insulating layer 12 within its shielding range, so as to reduce the influence of the second insulating layer 12 on the second active layer formed subsequently, and improve the electrical performance of the second transistor.

[0185] (B5) forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern can include: on the substrate on which the aforementioned patterns are formed, depositing a second semiconductor thin film, and patterning the second semiconductor thin film by a patterning process to form a second semiconductor layer pattern on the second insulating layer 12, the second semiconductor layer pattern including at least the second active layer 32, as shown in Figure 22 .

[0186] In an exemplary embodiment, the position, shape, and material of the second active layer 32 can be the same as in the aforementioned embodiments.

[0187] (B6) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern can include: on the substrate on which the aforementioned patterns are formed, sequentially depositing a third insulating thin film and a third metal thin film, patterning the third metal thin film by a patterning process, forming a third insulating layer 13 covering the second active layer pattern, and a third conductive layer pattern disposed on the third insulating layer 13, the third conductive layer pattern including at least a first top gate electrode 23 and a second top gate electrode 33, as shown in FIG. 3B. Figure 23

[0188] In an exemplary embodiment, the orthographic projection of the first top gate electrode 23 on the substrate is within the range of the orthographic projection of the first active layer 22 on the substrate, and the second top gate electrode 33 is disposed within the first recess 91, and the orthographic projection of the second top gate electrode 33 on the substrate is within the range of the orthographic projection of the second active layer 32 on the substrate.

[0189] In an exemplary embodiment, the material and thickness, etc. of the third conductive layer can be the same as in the aforementioned embodiments.

[0190] (B7) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern can include: on the substrate on which the aforementioned patterns are formed, depositing a fourth insulating thin film, patterning the fourth insulating thin film by a patterning process, forming a fourth insulating layer 14 pattern covering the second conductive layer pattern, the fourth insulating layer 14 having a plurality of vias disposed thereon, the plurality of vias including: a first via K1 disposed at each end of the first active layer 22, a second via K2 disposed at each end of the second active layer 32, and a third via K3 disposed at the end of the first bottom gate electrode 21, as shown in FIG. 3C. Figure 24

[0191] In an exemplary embodiment, the material and thickness, etc. of the fourth insulating layer can be the same as in the aforementioned embodiments.

[0192] In an exemplary embodiment, the fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12 within the first via K1 (CNT-L via) are etched away, exposing the surfaces of the source and drain regions on both sides of the first active layer 22, the fourth insulating layer 14 and the third insulating layer 13 within the second via K2 (CNT-O via) are etched away, exposing the surfaces of the source and drain regions on both sides of the second active layer 32, and the fourth insulating layer 14, the third insulating layer 13, the second insulating layer 12, and the first insulating layer 11 within the third via K3 are etched away, exposing the surface of the first bottom gate electrode 21.

[0193] ​​In an exemplary embodiment, since the first bottom gate electrode and the second bottom gate electrode, which serve as the lower light-shielding layer, are fabricated simultaneously in the same patterning process, and the first top gate electrode and the second top gate electrode are fabricated simultaneously in the same patterning process, the number of insulating layers is reduced. This reduces the depth difference between CNT-L vias and CNT-O vias, and the depth difference between CNT-L vias and CNT-O vias is less than or equal to... The depth of the CNT-L via is approximately to This refers to the total thickness of the second, third, and fourth insulating layers. The depth of the CNT-O via is approximately... to This refers to the total thickness of the third and fourth insulating layers. Reducing the depth difference between CNT-L and CNT-O vias helps lower the process requirements for simultaneous etching, reduces the process difficulty, and allows CNT-L and CNT-O vias to be formed simultaneously in the same patterning process, reducing the number of patterning processes, simplifying the process, and saving production costs.

[0194] (B8) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth metal thin film on a substrate on which the aforementioned pattern is formed, patterning the fourth metal thin film using a patterning process, and forming a fourth conductive layer pattern on the fourth insulating layer 14. The fourth conductive layer pattern includes at least a first source electrode 24, a first drain electrode 25, a second source electrode 34, a second drain electrode 35, and a first connection electrode 26. The first source electrode 24 and the first drain electrode 25 are respectively connected to the source region and drain region of the first active layer 22 through a first via K1. The first connection electrode 26 is connected to the first bottom gate electrode 21 through a third via K3. The second source electrode 34 and the second drain electrode 35 are respectively connected to the source region and drain region of the second active layer 32 through a second via K2. Figure 25 As shown.

[0195] In an exemplary embodiment, the material and thickness of the fourth conductive layer may be the same as in the foregoing embodiments.

[0196] In the example embodiment, the first bottom gate electrode 21, the first active layer 22, the first top gate electrode 23, the first source electrode 24 and the first drain electrode 25 constitute the first transistor 20, the first bottom gate electrode 21 serves as both a lower shielding layer and a bottom gate electrode of the first transistor 20, and the first transistor 20 can be a low-temperature polysilicon transistor. The second bottom gate electrode 31, the second active layer 32, the second top gate electrode 33, the second source electrode 34 and the second drain electrode 35 constitute the second transistor 30, the second bottom gate electrode serves as both a lower shielding layer and a bottom gate electrode of the second transistor 30, and the second transistor 30 can be an oxide transistor. In the example embodiment, the first transistor can be a driving transistor in a pixel driving circuit, and the second transistor can be at least one of a plurality of switching transistors in the pixel driving circuit. In the example embodiment of the present disclosure, the pixel driving circuit of the display substrate includes at least one low-temperature polysilicon transistor and at least one oxide transistor, and the at least one oxide transistor is prepared by using the preparation process of the example embodiment.

[0197] (B9) to (B12) form the first planar layer, the fifth conductive layer, the second planar layer and the anode pattern, and the preparation process can be the same as the preparation process (A9) to (A12) of the foregoing embodiment.

[0198] In the preparation of the display substrate in the example embodiment of the present disclosure, processes such as sequentially forming a pixel definition layer, an organic light-emitting layer, a cathode and an encapsulation layer can be included, which are not described herein again.

[0199] The display substrate provided by the example embodiment of the present disclosure has the following advantages. The first bottom gate electrode of the first transistor and the second bottom gate electrode of the second transistor are prepared at the same time in the same patterning process, and the first top gate electrode of the first transistor and the second top gate electrode of the second transistor are prepared at the same time in the same patterning process. This not only reduces the number of insulating layers, reduces the depth difference between the CNT-L via hole and the CNT-O via hole, and reduces the process difficulty, but also enables the CNT-L via hole and the CNT-O via hole to be formed at the same time in the same patterning process. Furthermore, the number of patterning processes is further reduced, the process is simplified, and the production cost is saved. By reducing the number of insulating layers, the overall thickness of the display substrate is effectively reduced, which is conducive to lightening and thinning. Moreover, the excessive inorganic film layer can be avoided to cause excessive stress on the back plate, which is conducive to flexibility. In addition, by arranging the groove in the region where the second transistor is located, the overall thickness of the display substrate is further reduced, which is conducive to lightening, thinning and flexibility. Moreover, the shielding effect is increased by the upper shielding layer and the lower shielding layer, the electrical performance of the second transistor is ensured, and the display quality is improved. In addition, for the bending display substrate, the electrical stability of the second active layer during the bending process is improved by arranging the groove in the region where the second transistor is located.

[0200] The display substrate provided by the example embodiments of the present disclosure greatly reduces the process difficulty, greatly reduces the process requirement, simplifies the process, reduces the number of patterning processes, and saves the production cost through a reasonable process flow. The preparation process of the display substrate of the example embodiments of the present disclosure is simple, has good process compatibility, is conducive to ensuring the uniformity of the two transistors, improves the yield, and reduces the production cost.

[0201] The structure shown in the present disclosure and the preparation process thereof are only exemplary descriptions, and in the example embodiments, the corresponding structure can be changed and the patterning process can be increased or reduced according to actual needs. For example, the material of the first active layer can include an oxide, and the material of the second active layer can include low-temperature polysilicon. For another example, other electrodes or leads can be further arranged in the related film layer. For another example, the pixel driving circuit in the display substrate can be 6T1C, 8T2C, 9T2C, etc., which is not limited in the present disclosure.

[0202] The present disclosure further provides a preparation method of a display substrate. In the example embodiments, the preparation method can include:

[0203] forming a driving structure layer on the substrate, the driving structure layer including the first transistor and the second transistor arranged side by side, the first transistor including a low-temperature polysilicon transistor, and the second transistor including an oxide transistor; the first transistor including a first bottom gate electrode serving as a shielding layer, the second transistor including a second bottom gate electrode serving as a shielding layer, the first bottom gate electrode and the second bottom gate electrode being arranged in the same layer and being formed at the same time through the same patterning process.

[0204] In the example embodiments, forming a first conductive layer on the substrate can include:

[0205] S1, forming a first conductive layer on the substrate, the first conductive layer including a first bottom gate electrode and a second bottom gate electrode arranged in the same layer and formed at the same time through the same patterning process;

[0206] S2, forming an active structure layer on the first conductive layer, the active structure layer including a first active layer and a first top gate electrode of the first transistor, and a second active layer and a second top gate electrode of the second transistor;

[0207] S3, forming a source-drain structure layer on the active structure layer, the source-drain structure layer comprising a first source electrode, a first drain electrode and a first connecting electrode of the first transistor, and a second source electrode and a second drain electrode of the second transistor, the first source electrode and the first drain electrode being connected with the first active layer through a first via, the second source electrode and the second drain electrode being connected with the second active layer through a second via, the first connecting electrode being connected with the first bottom gate electrode through a third via; the first via, the second via and the third via being formed simultaneously through a same patterning process.

[0208] In an example embodiment, step S1 can comprise:

[0209] forming a substrate comprising a first flexible layer, a first barrier layer, a second flexible layer and a second barrier layer stacked in sequence, the second barrier layer being provided with a groove, the depth of the groove being greater than

[0210] forming a first conductive layer on the substrate, the first conductive layer comprising a first bottom gate electrode and a second bottom gate electrode provided in the same layer and formed simultaneously through a same patterning process, at least part of the second bottom gate electrode being provided in the groove.

[0211] In an example embodiment, step S2 can comprise:

[0212] forming a first insulating layer covering the first conductive layer, and a first active layer of the first transistor provided on the first insulating layer;

[0213] forming a second insulating layer covering the first active layer, and a first top gate electrode of the first transistor provided on the second insulating layer;

[0214] performing a doping treatment with the first top gate electrode as a shield;

[0215] forming a second active layer of the second transistor on the second insulating layer;

[0216] forming a third insulating layer covering the first top gate electrode and the second active layer, and a second top gate electrode of the second transistor provided on the third insulating layer.

[0217] In an example embodiment, step S2 can comprise:

[0218] forming a first insulating layer covering the first conductive layer, and a first active layer of the first transistor provided on the first insulating layer;

[0219] forming a second insulating layer covering the first active layer, and a photoresist shielding pattern provided on the second insulating layer;

[0220] performing a doping treatment with the photoresist shielding pattern as a shield;

[0221] forming a second active layer of the second transistor on the second insulating layer;

[0222] forming a third insulating layer covering the second semiconductor layer, and a first top gate electrode of the first transistor and a second top gate electrode of the second transistor disposed on the third insulating layer.

[0223] In an example embodiment, the first via has a depth of to The second via has a depth of to The difference between the depth of the first via and the depth of the second via is less than or equal to

[0224] In an example embodiment, the fourth insulating layer includes a silicon oxide sublayer and a silicon nitride sublayer stacked, and the thickness of the silicon nitride sublayer is less than or equal to 1.5 times the thickness of the silicon oxide sublayer.

[0225] In an example embodiment, the thickness of the first insulating layer is greater than or equal to 3 times the thickness of the second insulating layer.

[0226] The preparation method of the display substrate provided by the example embodiments of the present disclosure greatly reduces the process difficulty, greatly reduces the process requirement, simplifies the process, reduces the number of patterning processes, and saves the production cost through a reasonable process flow. The preparation process of the display substrate of the example embodiments of the present disclosure is simple, has good process compatibility, is conducive to ensuring the uniformity of the two transistors, improves the yield, and reduces the production cost.

[0227] The present disclosure also provides a display device including the display substrate of the foregoing embodiments. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, or a navigator.

[0228] Although the embodiments disclosed in the present disclosure are as described above, the content described above is only an embodiment adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure. The patent protection scope of the present application shall be subject to the scope defined by the attached claims.

Claims

1. A display substrate, comprising a substrate and a driving structure layer disposed on the substrate, the driving structure layer comprising a first transistor and a second transistor disposed side by side, the first transistor comprising a low-temperature polysilicon transistor, and the second transistor comprising an oxide transistor; the first transistor comprising a first bottom gate electrode serving as a shielding layer, and the second transistor comprising a second bottom gate electrode serving as a shielding layer; the driving structure layer comprising a first conductive layer disposed on the substrate, an active structure layer disposed on a side of the first conductive layer away from the substrate, and a source-drain structure layer disposed on a side of the active structure layer away from the substrate; the first conductive layer comprising a first bottom gate electrode and a second bottom gate electrode disposed in the same layer and formed simultaneously by a same patterning process; the source-drain structure layer comprising a fourth insulating layer disposed on a side of the active structure layer away from the substrate, and a source-drain metal layer disposed on the fourth insulating layer, the source-drain metal layer comprising a first connection electrode; the first connection electrode being directly connected to the first bottom gate electrode of the first transistor through a third via. 2.The display substrate of claim 1, wherein, the active structure layer comprising a first insulating layer covering the first conductive layer, a first active layer of the first transistor disposed on a side of the first insulating layer away from the substrate, a second insulating layer covering the first active layer, a first top gate electrode of the first transistor disposed on a side of the second insulating layer away from the substrate, a second active layer of the second transistor disposed on a side of the second insulating layer away from the substrate, a third insulating layer covering the first top gate electrode and the second active layer, and a second top gate electrode of the second transistor disposed on a side of the third insulating layer away from the substrate. 3.The display substrate of claim 1, wherein, the active structure layer comprising a first insulating layer covering the first conductive layer, a first active layer of the first transistor disposed on a side of the first insulating layer away from the substrate, a second insulating layer covering the first active layer, a second active layer of the second transistor disposed on a side of the second insulating layer away from the substrate, a third insulating layer covering the second active layer, a first top gate electrode of the first transistor and a second top gate electrode of the second transistor disposed on a side of the third insulating layer away from the substrate; the first top gate electrode and the second top gate electrode being disposed in the same layer. 4.The display substrate of claim 1, wherein, the source-drain metal layer further comprising a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode, the first source electrode and the first drain electrode being connected to the first active layer of the first transistor through a first via, and the second source electrode and the second drain electrode being connected to the second active layer of the second transistor through a second via. 5.The display substrate of claim 4, wherein, a depth of the first via is 5000 Å to 9000 Å, and a depth of the second via is 4000 Å to 7000 Å. 6.The display substrate of claim 4, wherein, a difference between the depth of the first via and the depth of the second via is less than or equal to 2000 Å. 7.The display substrate of claim 4, wherein, the fourth insulating layer comprising a silicon oxide sublayer and a silicon nitride sublayer stacked together, and a thickness of the silicon nitride sublayer being less than or equal to 1.5 times a thickness of the silicon oxide sublayer. 8.The display substrate of claim 2, wherein, The thickness of the first insulating layer is greater than or equal to 3 times the thickness of the second insulating layer. 9.The display substrate according to any one of claims 1 to 8, wherein The substrate is provided with a groove, at least part of the second bottom gate electrode is arranged in the groove, at least part of the second active layer of the second transistor is arranged in the groove, and the second top gate electrode of the second transistor is arranged in the groove. 10.The display substrate of claim 9, wherein, The depth of the groove is greater than or equal to 4000 Å, and the width of the groove is greater than or equal to 1.2 times the distance between the source region and the drain region of the second active layer in the second transistor.

11. A display device comprising the display substrate according to any one of claims 1 to 10.

12. A method for manufacturing a display substrate, comprising: forming a driving structure layer on a substrate, the driving structure layer comprising a first transistor and a second transistor arranged side by side, the first transistor comprising a low-temperature polysilicon transistor, and the second transistor comprising an oxide transistor; the first transistor comprising a first bottom gate electrode serving as a shielding layer, and the second transistor comprising a second bottom gate electrode serving as a shielding layer, the first bottom gate electrode and the second bottom gate electrode being arranged in the same layer and formed simultaneously through a same patterning process; wherein forming the driving structure layer on the substrate comprises: forming a first conductive layer on the substrate, the first conductive layer comprising the first bottom gate electrode and the second bottom gate electrode arranged in the same layer and formed simultaneously through the same patterning process; forming an active structure layer on the first conductive layer, the active structure layer comprising a first active layer and a first top gate electrode of the first transistor, and a second active layer and a second top gate electrode of the second transistor; and forming a source-drain structure layer on the active structure layer, the source-drain structure layer comprising a first connection electrode, the first connection electrode being directly connected to the first bottom gate electrode through a third via.

13. The production method according to claim 12, wherein The source-drain structure layer further comprises a first source electrode and a first drain electrode of the first transistor, and a second source electrode and a second drain electrode of the second transistor, the first source electrode and the first drain electrode being connected to the first active layer through a first via, and the second source electrode and the second drain electrode being connected to the second active layer through a second via; the first via, the second via and the third via being formed simultaneously through the same patterning process.

14. The production method according to claim 13, wherein forming a first conductive layer on a substrate, comprising: forming a substrate, the substrate comprising a first flexible layer, a first barrier layer, a second flexible layer and a second barrier layer arranged in a stack, the second barrier layer being provided with a groove, the depth of the groove being greater than or equal to 4000 Å; forming a first conductive layer on the substrate, the first conductive layer comprising the first bottom gate electrode and the second bottom gate electrode arranged in the same layer and formed simultaneously through the same patterning process, and at least part of the second bottom gate electrode being arranged in the groove.

15. The method of making according to claim 13, wherein, forming an active structure layer on the first conductive layer, comprising: forming a first insulating layer covering the first conductive layer, and a first active layer of the first transistor arranged on the first insulating layer; forming a second insulating layer covering the first active layer, and a first top gate electrode of the first transistor arranged on the second insulating layer; Doping treatment is performed with the first top gate electrode as a shield; A second active layer of the second transistor is formed on the second insulating layer; A third insulating layer covering the first top gate electrode and the second active layer is formed, and a second top gate electrode of the second transistor is arranged on the third insulating layer.

16. The method of making according to claim 13, wherein, An active structure layer is formed on the first conductive layer, including: A first insulating layer covering the first conductive layer is formed, and a first active layer of the first transistor is arranged on the first insulating layer; A second insulating layer covering the first active layer is formed, and a photoresist shielding pattern is arranged on the second insulating layer; Doping treatment is performed with the photoresist shielding pattern as a shield; A second active layer of the second transistor is formed on the second insulating layer; A third insulating layer covering the second active layer is formed, and a first top gate electrode of the first transistor and a second top gate electrode of the second transistor are arranged on the third insulating layer.

17. The method of making according to claim 13, wherein, The depth of the first via is 5000 Å to 9000 Å, the depth of the second via is 4000 Å to 7000 Å, and the difference between the depth of the first via and the depth of the second via is less than or equal to 2000 Å.

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