A method for realizing asynchronous signal sampling based on FPGA

Abstract

The present invention relates to a method for implementing asynchronous signal sampling based on FPGA, which includes the following steps: a sampling signal receiving module receives a sampling signal at a frequency N times the original signal frequency, the sampling signal including a sampling clock signal and a sampling data signal corresponding to the sampling clock signal; using a rising edge signal data compression algorithm, compressing N consecutive sampling points in the sampling signal into one sampling point to obtain a target signal; and sending the target signal to a user terminal. When compressing the sampling clock signal, the present invention can not only find the rising edge signal located in each group, but also find the rising edge signal located at the junction of two groups, avoiding the signal distortion caused by the inability to accurately find the rising edge signal when the rising edge signal is located at the junction of two groups in the prior art, so that the target signal obtained has higher consistency with the information represented by the sampling signal.

Description

Technical Field

[0001] The invention belongs to the technical field of data acquisition and processing, and in particular to a method for realizing asynchronous signal sampling based on FPGA. Background Art

[0002] Currently, in the field of high-speed digital signal acquisition, there are two methods: synchronous signal sampling and asynchronous signal sampling. Synchronous signal sampling involves extracting a clock signal from the chip (or PCB) to be sampled to the sampling device, which then operates according to this clock to achieve synchronous signal acquisition. In other words, synchronous signal acquisition ensures that the sampling device's acquisition frequency matches the target signal's frequency. Asynchronous signal acquisition, on the other hand, adjusts the acquisition frequency to a multiple of the target signal's frequency. This method of sampling achieves higher signal accuracy. However, this asynchronous signal acquisition method cannot achieve time synchronization between the signal transmitter and the user terminal.

[0003] A method for implementing asynchronous signal sampling based on FPGA is disclosed in the patent document with publication number CN111665756A. The patent specifically discloses receiving a sampling signal, wherein the frequency of the sampling signal is N times the target frequency; compressing N consecutive sampling points in the sampling signal into one sampling point according to a preset data compression algorithm to obtain the target signal, wherein the information represented by the target signal is consistent with the information represented by the sampling signal; sending the target signal to a user terminal; the sampling signal includes a sampling clock signal, and compressing N consecutive sampling points in the sampling signal into one sampling point according to a preset data compression algorithm includes: determining whether there is a target signal in the N consecutive sampling points of the sampling clock signal; At two consecutive sampling points constituting a first direction conversion signal, wherein the first direction conversion signal is a rising edge signal; if so, replacing N consecutive sampling points of the sampling clock signal with a sampling point representing a high level, the sampling signal including a sampled data signal corresponding to the sampling clock signal. After replacing the N consecutive sampling points of the sampling clock signal with the sampling point representing a high level, the method further includes obtaining a sampling point representing a high level among the two consecutive sampling points constituting the first direction conversion signal in the sampling clock signal, obtaining a level state of a sampling point of the sampled data signal corresponding to the sampling point representing the high level, and replacing the N consecutive sampling points in the sampled data signal with the sampling point representing the level state.

[0004] The solution in this patent first expands the frequency of the sampling signal to N times the target frequency; then compresses the sampling signal, compressing N consecutive sampling points into one sampling point. This method achieves time synchronization of data between the signal transmitter and the user terminal. However, a disadvantage of this solution is that because the sampling frequency is expanded to N times the target frequency, the resulting signal is more accurate. However, during the signal compression process, problems with the compression algorithm may cause distortion of the compressed signal. For example, in the compression algorithm in the embodiment of this patent, the frequency of the sampling signal is expanded to 4 times the target frequency, and then four consecutive sampling points of the sampling signal are compressed into one sampling point. If a first direction transition signal (i.e., a rising edge signal from 0 to 1) is present, the four sampling points are compressed to 1; if the first direction transition signal is not present, the four sampling points are compressed to 0. There is no problem in compressing the signal 0011 0001 1000 0001 1100 into 11010 as exemplified in the patent. However, if the 4th and 5th bits of the signal are 01, the first direction conversion signal cannot be identified using the patented method. For example, the signal 1100 1110 1100 1000 1111 will be compressed into 0000 according to the patented method. However, in fact, there are 4 rising edge signals in this signal segment. Therefore, the use of the patented method will result in errors at 4 consecutive sampling points, causing distortion of the sampling signal. Summary of the Invention

[0005] The purpose of the present invention is to provide a method for implementing asynchronous signal sampling based on FPGA that can solve the problem that the asynchronous signal sampling method in the prior art described in the background art may cause distortion of the sampled signal.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solutions: a method for implementing asynchronous signal sampling based on FPGA, which includes the following steps:

[0007] S1, the sampling signal receiving module receives the sampling signal at a frequency N times the original signal frequency, the sampling signal includes a sampling clock signal and a sampling data signal corresponding to the sampling clock signal;

[0008] S2. Compress N consecutive sampling points in the sampled signal into one sampling point according to a data compression algorithm to obtain a target signal;

[0009] S3. Sending a target signal to the user terminal;

[0010] In the above step S2, the specific algorithm for compressing N consecutive sampling points in the sampled signal into one sampling point is:

[0011] The sampling clock signal in the sampling signal is divided into groups of N sampling points in sequence, and it is determined whether there is a rising edge signal in each group of sampling points plus the first sampling point of the next group, a total of N + 1 sampling points; if there is no rising edge signal, the N sampling points in the group are represented by a low level sampling point; if there is a rising edge signal, and this rising edge signal appears in the N sampling points in the group, the N sampling points in the group are replaced with a sampling point representing a high level; if this rising edge signal appears between the last sampling point in the group and the first sampling point in the next group, the N sampling points in the group are represented by a low level, and the N sampling points in the next group are represented by a high level;

[0012] Divide the sampled data signal into a group of N sampling points in sequence, and make the grouping of the sampled data signal correspond to the grouping of the sampling clock signal;

[0013] Obtaining the level state of the sampling point corresponding to the high level of the rising edge of the sampling clock signal in the sampled data signal, and using the level state to characterize the N sampling points in the group to which it belongs;

[0014] In the sampling clock signal, the sampling point groups of the sampling data signal corresponding to the remaining sampling points without rising edges are all represented by a low level.

[0015] In the above solution, in step S1, the sampling signal receiving module receives the sampling signal at a frequency four times the target signal frequency.

[0016] In the above scheme, the sampling signal receiving module is an FPGA module, which is provided with a processor module, a storage module and a bus. The processor module and the storage module communicate with each other through the bus. The algorithm and the collected data are stored in the storage module. When the processor module runs, it calls the algorithm and the sampling clock signal and the sampling data signal in the storage module. After compressing the sampling clock signal and the sampling data signal, the target signal is obtained and stored in the storage module.

[0017] The beneficial effects of the present invention are as follows: when compressing the sampling clock signal, the present invention can not only find the rising edge signal located in each group, but also find the rising edge signal located at the intersection of two groups, thereby avoiding the signal distortion caused by the inability to accurately find the rising edge signal when the rising edge signal is located at the intersection of two groups in the prior art, thereby making the target signal and the information represented by the sampling signal more consistent. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagram of the principle of the asynchronous signal sampling method of the present invention. DETAILED DESCRIPTION

[0019] The technical solutions of the present invention are described clearly and completely below through examples. It is obvious that the examples described are only some examples of the present invention, not all examples. All other examples derived by persons of ordinary skill in the art based on the examples of the present invention without creative effort are within the scope of protection of the present invention.

[0020] like Figure 1 As shown, the present invention provides a method for implementing asynchronous signal sampling based on FPGA, which includes the following steps:

[0021] S1, the sampling signal receiving module receives the sampling signal at a frequency N times the original signal frequency, the sampling signal includes a sampling clock signal and a sampling data signal corresponding to the sampling clock signal;

[0022] S2. Compress N consecutive sampling points in the sampled signal into one sampling point according to a data compression algorithm to obtain a target signal;

[0023] S3. Sending a target signal to the user terminal;

[0024] In the above step S2, the specific algorithm for compressing N consecutive sampling points in the sampled signal into one sampling point is:

[0025] The sampling clock signal in the sampling signal is divided into groups of N sampling points in sequence, and it is determined whether there is a rising edge signal in each group of sampling points plus the first sampling point of the next group, a total of N + 1 sampling points; if there is no rising edge signal, the N sampling points in the group are represented by a low level sampling point; if there is a rising edge signal, and this rising edge signal appears in the N sampling points in the group, the N sampling points in the group are replaced with a sampling point representing a high level; if this rising edge signal appears between the last sampling point in the group and the first sampling point in the next group, the N sampling points in the group are represented by a low level, and the N sampling points in the next group are represented by a high level;

[0026] Divide the sampled data signal into a group of N sampling points in sequence, and make the grouping of the sampled data signal correspond to the grouping of the sampling clock signal;

[0027] Obtaining the level state of the sampling point corresponding to the high level of the rising edge of the sampling clock signal in the sampled data signal, and using the level state to characterize the N sampling points in the group to which it belongs;

[0028] In the sampling clock signal, the sampling point groups of the sampling data signal corresponding to the remaining sampling points without rising edges are all represented by a low level.

[0029] In the above solution, in step S1, the sampling signal receiving module receives the sampling signal at a frequency four times the target signal frequency.

[0030] In the above scheme, the sampling signal receiving module is an FPGA module, which is provided with a processor module, a storage module and a bus. The processor module and the storage module communicate with each other through the bus. The algorithm and the collected data are stored in the storage module. When the processor module runs, it calls the algorithm and the sampling clock signal and the sampling data signal in the storage module. After compressing the sampling clock signal and the sampling data signal, the target signal is obtained and stored in the storage module.

[0031] The sampling method of the present invention is illustrated below. For example, a sampling signal receiving module receives a sampling signal at a frequency four times the original signal frequency. The obtained sampling clock signal and sampling data signal are sequentially divided into several groups of four sampling points. Since the frequency of the obtained sampling signal is four times that of the original signal, it is necessary to compress the sampling points. Compressing the sampling points to one-fourth of the original signal frequency can make the target signal have the same frequency as the original signal. During compression, it is first determined whether there is a rising edge signal among the four sampling points in each group and the first sampling point of the next group, a total of five sampling points. If there is no rising edge signal, a sampling point representing a low level is used to represent the sampling point of the group. If there is a rising edge signal and this rising edge signal is located in the group, a sampling point representing a high level is used to represent the sampling point of the group. If there is a rising edge signal and this rising edge signal is located between the first sampling point of the group and the next group, a low level sampling point is used to represent the sampling point of the group, and a high level sampling point is used to represent the sampling point of the next group. In this way, the sampling clock signal can be compressed to a signal with the same frequency as the original signal. After the sampling clock signal is compressed, the group corresponding to the low level in the sampling clock signal is found in the sampled data signal, and a low level is used to represent the corresponding group in the sampling clock signal. The sampling point corresponding to the high level sampling point of the rising edge of the sampling clock signal is found in the sampled data signal, and the level of the sampling point is used to represent the sampling point of the group where the sampling point is located. Through such compression, the sampled data signal can be compressed into a signal of the same frequency.

[0032] Specifically, for example, the sampling clock signal is 11001000010011001011, and the sampling data signal is 00101011001011010100. First, the four sampling points in the sampling clock signal and the sampling data signal are divided into one group. Then, the sampling clock signal is grouped as 1100 1000 0100 1100 0011, and the sampling data signal is grouped as 0010 1011 00101101 0100; then find the rising edge signal in the sampling clock signal group. It can be seen that there is no rising edge in the first group 1100, so it is represented by 0, but there is a rising edge between the last bit 0 of the first group and the first bit 1 of the second group, so the second group is represented by 1. There is a rising edge in the third group, so it is represented by 1. The last bit of the third group is between the first bit of the fourth group, so the fourth group is represented by 1. There is a rising edge in the fifth group, so the fifth group is represented by 1. Therefore, the above sampling clock signal becomes 01111 after compression. Because the first bit of the sampling clock signal is low, and the second, third, fourth, and fifth bits are high, the first bit of the sampling data signal is 01111. The first group is represented by 0. The rising edge of the second group 1000 of the sampling clock signal is at the first bit, so the second group 1011 of the sampled data signal is represented by the first bit 1. The rising edge of the third group 0100 of the sampling clock signal is at the second bit, so the third group 0010 of the sampled data signal is represented by the second bit 0. The rising edge of the fourth group 1100 of the sampling clock signal is at the first bit, so the fourth group 1101 of the sampled data signal is represented by the first bit 1. The rising edge of the fifth group 0011 of the sampling clock signal is at the third bit, so the fifth group 0100 of the sampled data signal is represented by the third bit 0. The compressed sampled data signal is 01010. Therefore, the clock signal in the obtained target signal is 01111, and the data signal is 01010.

[0033] However, using the compression method in the prior art, the rising edges between groups of sampling clock signals are not considered during compression. Therefore, the sampling clock signal 1100 1000 0100 1100 0011 is compressed to 00101, and the sampling data signal 00101011 0010 1101 0100 is compressed to 00000. That is, the clock signal in the obtained target signal is 00101, and the data signal is 00000. In this way, the high-level sampling point data of the second and fourth sampling points are lost, resulting in distortion between the obtained target signal and the original signal.

[0034] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A method for implementing asynchronous signal sampling based on FPGA, characterized in that: It includes the following steps: S1, the sampling signal receiving module receives the sampling signal at a frequency N times the original signal frequency, the sampling signal includes a sampling clock signal and a sampling data signal corresponding to the sampling clock signal; S2. Using a data compression algorithm, compress N consecutive sampling points in the sampled signal into one sampling point to obtain a target signal; S3. Sending a target signal to the user terminal; In the above step S2, the specific algorithm for compressing N consecutive sampling points in the sampled signal into one sampling point is: The sampling clock signal in the sampling signal is divided into groups of N sampling points in sequence, and it is determined whether there is a rising edge signal among the N + 1 sampling points in each group of sampling points plus the first sampling point of the next group; if there is no rising edge signal, the low-level sampling point is used to represent the N sampling points in the group; If there is a rising edge signal, and this rising edge signal appears in the N sampling points of the group, then the N sampling points of the group are replaced with a sampling point representing a high level. If this rising edge signal appears at the last sampling point of the group and the first sampling point of the next group, then the N sampling points of the group are represented by a low level, and the N sampling points of the next group are represented by a high level. Divide the sampled data signal into a group of N sampling points in sequence, and make the grouping of the sampled data signal correspond to the grouping of the sampling clock signal; Obtaining the level state of the sampling point corresponding to the high level of the rising edge of the sampling clock signal in the sampled data signal, and using the level state to characterize the N sampling points in the group to which it belongs; In the sampling clock signal, the sampling point groups of the sampling data signal corresponding to the remaining sampling points without rising edges are all represented by a low level.

2. The method for implementing asynchronous signal sampling based on FPGA according to claim 1, wherein: In step S1, the sampling signal receiving module receives the sampling signal at a frequency four times the target signal frequency.

3. The method for implementing asynchronous signal sampling based on FPGA according to claim 1, wherein: The sampling signal receiving module is an FPGA module, which is provided with a processor module, a storage module and a bus. The processor module and the storage module communicate with each other through the bus. The algorithm and the collected data are stored in the storage module. When the processor module is running, the algorithm, sampling clock signal and sampling data signal in the storage module are called. After compressing the sampling clock signal and the sampling data signal, the target signal is obtained and stored in the storage module.

Images