Control system, method, apparatus, electronic device, and readable storage medium

Abstract

Embodiments of the present application provide a control system, method, device, electronic equipment and readable storage medium. The control system is applied to a server, and the control system comprises a clock generator and a detection module. In the clock generator, a plurality of clock signal output pins are connected to a plurality of corresponding control pins through lines to form a plurality of differential signal lines in the clock generator. The detection module is connected to the plurality of differential signal lines in the clock generator. The detection module is used for detecting whether the differential signal lines in the clock generator form a complete loop to obtain a detection result. According to the detection result, a result signal is returned to the clock generator. The clock generator is used for controlling whether the clock signal output pin corresponding to the differential signal line outputs the clock signal according to the received result signal. Through the control system of the embodiment, whether the clock signal is output can be automatically controlled, and the electromagnetic compatibility of the product can be improved while reducing the power consumption of the product.

Description

Technical Field

[0001] This invention relates to the field of clock signal technology, and more particularly to a control system, method, apparatus, electronic device, and readable storage medium. Background Technology

[0002] With the continuous development of technology, clock signals have become the driving force behind the development of circuits, because electronic products can only function properly with the presence of clock signals. Regarding clock signals, such as... Figure 1 As shown, Figure 1 This is a schematic diagram of a pulse signal in the prior art, wherein, Figure 1 A square wave in a circuit is called a pulse, similar to a human pulse. For each square pulse, the line where the voltage or current rises from 0 to its maximum value is called the rising edge; conversely, the line where the voltage or current gradually decreases is called the falling edge. A pulse is called a clock signal, or clock pulse, and one pulse period is called a clock period. The clock signal oscillates once in one clock period.

[0003] Currently, all clock signals generated by the clock generator in the server are always in an output state. However, the clock signals are not always in use, which leads to invalid clock signal output and wastes energy. Summary of the Invention

[0004] This invention provides a control system, method, apparatus, electronic device, and readable storage medium for automatically controlling whether a clock signal is output.

[0005] A first aspect of this invention provides a control system applied to a server. The control system includes a clock generator and a detection module. In the clock generator, multiple clock signal output pins are respectively connected to corresponding multiple control pins via lines, forming multiple differential signal lines in the clock generator. The detection module is connected to the multiple differential signal lines in the clock generator.

[0006] The detection module is used to detect whether the differential signal lines in the clock generator form a complete loop, and obtain the detection result; based on the detection result, it returns a result signal to the clock generator.

[0007] The clock generator is used to control whether the clock signal output pin corresponding to the differential signal line outputs a clock signal based on the received result signal.

[0008] A second aspect of this invention provides a control method applied to a detection module, the method comprising:

[0009] The detection results are obtained by detecting whether the differential signal lines in the clock generator form a complete loop.

[0010] Based on the detection result, a result signal is returned to the clock generator, so that the clock generator controls whether the clock signal output pin corresponding to the differential signal line outputs a clock signal according to the received result signal;

[0011] The detection module is connected to multiple differential signal lines in the clock generator; the multiple differential signal lines in the clock generator are multiple lines that connect multiple clock signal output pins in the clock generator to multiple corresponding control pins.

[0012] A third aspect of this invention provides a control method applied to a clock generator, the method comprising:

[0013] Receive the result signal returned by the detection module; the result signal is generated by the detection module based on the detection result obtained by the detection module according to whether the differential signal lines in the detection clock generator form a complete loop;

[0014] Based on the result signal, control whether the clock signal output pin corresponding to the differential signal line outputs a clock signal;

[0015] The detection module is connected to multiple differential signal lines in the clock generator; the multiple differential signal lines in the clock generator are multiple lines that connect multiple clock signal output pins in the clock generator to multiple corresponding control pins.

[0016] A fourth aspect of the present invention provides a control device applied to a detection module, the device comprising:

[0017] The detection module is used to detect whether the differential signal lines in the clock generator form a complete loop and obtain the detection result.

[0018] The return module is used to return a result signal to the clock generator based on the detection result, so that the clock generator controls whether the clock signal output pin corresponding to the differential signal line outputs a clock signal according to the received result signal.

[0019] The detection module is connected to multiple differential signal lines in the clock generator; the multiple differential signal lines in the clock generator are multiple lines that connect multiple clock signal output pins in the clock generator to multiple corresponding control pins.

[0020] A fifth aspect of the present invention provides a control device applied to a clock generator, the device comprising:

[0021] The receiving module is used to receive the result signal returned by the detection module; the result signal is generated by the detection module based on the detection result obtained by the detection module according to whether the differential signal lines in the detection clock generator form a complete loop;

[0022] The control module is used to control whether the clock signal output pin corresponding to the differential signal line outputs a clock signal based on the result signal.

[0023] The detection module is connected to multiple differential signal lines in the clock generator; the multiple differential signal lines in the clock generator are multiple lines that connect multiple clock signal output pins in the clock generator to multiple corresponding control pins.

[0024] A sixth aspect of the present invention provides an electronic device, including a processor, a memory, and a computer program stored in the memory and executable on the processor. When executed by the processor, the computer program implements the steps of the control method as described in the second aspect of the present invention, or implements the steps of the control method as described in the third aspect of the present invention.

[0025] A seventh aspect of the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the control method as described in the second aspect of the present invention, or implements the steps of the control method as described in the third aspect of the present invention.

[0026] The control system of this invention includes a clock generator and a detection module. In the clock generator, multiple clock signal output pins are connected to corresponding control pins via lines, forming multiple differential signal lines in the clock generator. The detection module is connected to the multiple differential signal lines in the clock generator. Through this control system, the detection module can detect whether the differential signal lines in the clock generator form a complete loop, obtain the detection result, and return the result signal to the clock generator. This allows the clock generator to control whether the clock signal output pins corresponding to the differential signal lines output clock signals based on the received result signal. This achieves intelligent control by controlling the clock signal output when an external electronic component is connected to the clock signal output pin of the differential signal line, and suppressing the clock signal output when no external electronic component is connected. This reduces the wasted power of the server and saves a significant amount of energy, resulting in substantial economic benefits in today's society. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of a pulse signal in the prior art;

[0029] Figure 2 This is a schematic diagram of a conventional design scheme for a clock generator in the existing technology;

[0030] Figure 3 This is a schematic diagram of an existing design scheme for an external small card for a clock generator;

[0031] Figure 4 This is a schematic diagram of the radiation emission design of an external small card for a clock generator in the existing technology;

[0032] Figure 5 This is a structural block diagram of a control system according to an embodiment of the present invention;

[0033] Figure 6 This is a flowchart illustrating a control method according to an embodiment of the present invention;

[0034] Figure 7 This is a flowchart illustrating a control method according to an embodiment of the present invention;

[0035] Figure 8 This is a schematic diagram illustrating an optimized clock generator circuit design according to an embodiment of the present invention;

[0036] Figure 9 This is a structural block diagram of a control device provided in an embodiment of the present invention;

[0037] Figure 10 This is a structural block diagram of a control device provided in an embodiment of the present invention;

[0038] Figure 11 This is a schematic diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] With the advancement of technology, in related technologies, the provision of clock signals has evolved from conventional crystal oscillators to clock generator integrated circuits. Common clock generator integrated circuits include clk buffers and clk generators. A clock generator can generate multiple outputs from one input, and a clock signal can be output by having one clock generator drive three clock generators. Figure 2 This is a schematic diagram of a conventional design scheme for a clock generator in the prior art, such as... Figure 2 As shown, this is a clock generator chip with one input and ten outputs. The input crystal oscillator Y1 has a frequency of 25MHz, and the output clock signals are 50MHz and 100MHz for the CPU, OCP, PCIE, and NVME devices, respectively.

[0041] In the output clock signals, taking clock signals CLK_50M_NSSC_CPU0_DP and CLK_50M_NSSC_CPU0_DN as an example: CLK_50M_NSSC_CPU0_DP and CLK_50M_NSSC_CPU0_DN are a pair of clock signals, where _DP represents the positive terminal (input) and _DN represents the negative terminal (output). They serve as one output, acting as the 50MHz clock signal input for the CPU0 NSSC signal. Correspondingly, CLK_50M_NSSC_CPU1_DP and CLK_50M_NSSC_CPU1_DN are for CPU1. The NSSC signal is a 50MHz clock input; CLK_100M_DB2001_1_DP, CLK_100M_DB2001_1_DN, CLK_100M_DB2001_2_DP, and CLK_100M_DB2001_2_DN are the 100MHz clock inputs for the motherboard DB2001 signal; CLK_100M_CPU0_MCIO_0_DP and CLK_100M_CPU0_MCIO_0_DN are the 100MHz clock inputs for the CPU0 MCIO signal; CLK_100M_CPU1_MCIO_0_DP and CLK_100M_CPU1_MCIO_0_DN are the CPU1... 100MHz clock input for MCIO signals; CLK_50M_CPU1_OE0_OCP1_0_DP, CLK_50M_CPU1_OE0_OCP1_0_DN are the 50MHz clock input for the OCP card; CLK_100M_CPU1_OE1_PCIE1_0_DP, CLK_100M_CPU1_OE1_PCIE1_0_DN are the 100MHz clock input for the PCIE card; CLK_50M_CP U1_OE2_NVME1_0_DP and CLK_50M_CPU1_OE2_NVME1_0_DN are the 50MHz clock inputs of the NVME card. If all functions are temporarily implemented, then pins A18 and A19 of the chip are 4 empty pins (i.e., NC pins). At this time, no electronic components are connected to pins A18 and A19, and there is no need to receive clock signals. However, pins A18 and A19 will still output clock signals as usual, thus wasting resources.

[0042] In related technologies, during server product planning, OCP cards, PCIe cards, and NVMe cards are all expansion cards for servers, serving to extend the server's basic functions. Therefore, during server product planning, technicians will plan multiple pins for OCP cards, PCIe cards, and NVMe cards in the clock generator. When customers need OCP cards, PCIe cards, or NVMe cards, they can directly add these cards to the corresponding pins to meet their actual needs. However, if customers do not need this function, they can omit the OCP cards, PCIe cards, and NVMe cards and simply add the corresponding server brackets in the corresponding positions. This results in the reservation of expansion cards. Furthermore, sometimes technicians plan general-purpose servers with 4 or 2 CPU interfaces, but in reality, only a single or dual CPU configuration is used; that is, there are CPUs that are not actually used. Figure 3 As shown, Figure 3 This is a schematic diagram of an existing design scheme for an external clock generator card. However, when the customer does not have an actual need for an OCP card, PCIe card, NVMe card, or CPU, the clock signal continues to be output, resulting in a waste of clock signal resources.

[0043] Based on the characteristics of the clock signal, the clock generator will produce a voltage of approximately 1V on the differential signal. There will be corresponding resistors inside the chip and on the PCB traces. In conventional designs, the chip's internal resistance can be controlled at 20Ω. The external traces of the clock generator are HCSL signals, and their resistance should be controlled at 85Ω. Therefore, for customers who do not have actual usage requirements for OCP cards, PCIe cards, or NVMe cards, and only reserve expansion cards, the power generated by one OCP / PCIe / NVMe clock signal is P = U² / R = 12 / 10⁵ = 0.0095W. The clock generator has 20 clock outputs. In actual use, if unused clock signals are generated (such as...), Figure 3 (A18 and A19 are empty pins). Because the clock generator will generate a voltage of about 1V on the differential signal, in a conventional design the internal resistance of the chip can be controlled at 20Ω. The power generated by the unused clock signal is P = U2 / R = 12 / 20 = 0.05W.

[0044] Currently, most server clock generators have a total of 80 clock signals (clk). Statistics show that only about 50% of the clock signals are actually in use, with the remaining pins (such as empty pins) being the majority. Figure 3The clock signal of the empty pins A18 and A19 accounts for 20% of the total clock signal, and the reserved clock signal accounts for 30% of the total clock signal. According to the formula, the energy waste generated in one year is W = Pt = 0.0095 * 80 * 0.3 * 365 * 24 * 60 * 60 + 0.05 * 80 * 0.2 * 365 * 24 * 60 * 60 = 7190208 + 25228800 = 32419008 joules.

[0045] The calculations above show that if a server cannot manage the clock generator signal, it will result in a huge waste of resources during server use.

[0046] Furthermore, changing voltage generates an electric field, and changing current generates a magnetic field. These electromagnetic fields are interconvertible, so the clock signal generated by a clock generator produces a very strong electromagnetic field. Clock generators are a significant source of electromagnetic compatibility (EMC) violations in servers. For example... Figure 4 As shown, Figure 4 This is a schematic diagram of the radiated emission design of an external small card for a clock generator in existing technology. Among them, Figure 4 CLK_50M_CPU1_OE0_OCP1_0_DN and CLK_50M_CPU1_OE0_OCP1_0_DP are clock signals. It can be seen that clock signals, whether valid or invalid, will generate corresponding electromagnetic radiation.

[0047] Furthermore, OCP cards, PCIe cards, and NVMe cards are external cards, and their clock generators are generally placed in the center of the motherboard. Therefore, the clock generator to the OCP card, PCIe card, or NVMe card will typically have a long trace on the motherboard. This trace, which can generate strong radiation, passes through the PCB, and many structures are transferred from one PCB to another via cable. The clock signal in the trace and cable will pollute the entire chassis during the routing process. If there is a weak point in the shielding effectiveness of the server chassis, or if the clock trace or cable passes through an interface, it will likely cause problems with the shielding effectiveness of the entire chassis, resulting in the radiation emission of the entire server exceeding the regulatory limits.

[0048] In summary, all clock signals generated by the clock generator in the server are currently in an output state. However, the clock signals are not always in use. This leads to two problems: firstly, because the server is used for a long time, the unused clock signals continue to output energy, resulting in a waste of resources; secondly, the unused clock signals are more likely to generate radiation energy, causing the machine's radiation emissions to exceed the standard, which may ultimately affect product certification.

[0049] Therefore, in order to at least partially solve one or more of the above-mentioned problems and other potential problems, embodiments of the present invention propose a control system. This control system uses a detection module to detect whether the differential signal lines in a clock generator form a complete loop, and returns the detection result signal to the clock generator. The clock generator in the control system controls whether the clock signal output pins corresponding to the differential signal lines output clock signals based on the received result signal. This achieves intelligent control where: when an electronic component is connected to the clock signal output pin corresponding to the differential signal line, a clock signal is output; when no electronic component is connected to the clock signal output pin corresponding to the differential signal line, no clock signal is output. This avoids invalid clock signal output, significantly reduces product power consumption, saves a large amount of energy, reduces product electromagnetic radiation, improves product performance, and generates substantial economic benefits.

[0050] Please refer to Figure 5 , Figure 5 This is a structural block diagram of a control system according to an embodiment of the present invention. The control system of this embodiment can be applied to a server, and includes a clock generator and a detection module. In the clock generator, multiple clock signal output pins are respectively connected to corresponding control pins via lines, forming multiple differential signal lines in the clock generator; the detection module is connected to the multiple differential signal lines in the clock generator. The control pins of the clock generator are OE pins. It should be noted that... Figure 5 The diagram illustrates that the clock generator 501 and the detection module 502 have a communication relationship, but does not restrict the circuit connection relationship between the clock generator 501 and the detection module 502.

[0051] The detection module is used to detect whether the differential signal lines in the clock generator form a complete loop and obtain a detection result; based on the detection result, it returns a result signal to the clock generator.

[0052] In this embodiment, the detection module can detect whether the differential signal lines in the clock generator form a complete loop, that is, whether the clock signal output from the clock signal output pin returns to the corresponding control pin through the differential signal lines to form a complete loop, thus obtaining the detection result for the differential signal lines. After obtaining the detection result, the detection module can generate a corresponding result signal based on the detection result and return the result signal to the clock generator through the differential signal lines. Since the detection module in the server is connected to multiple differential signal lines in the server's clock generator, the detection module can simultaneously detect all differential signal lines in the clock generator, or it can detect any one or more differential signal lines in the clock generator; this embodiment does not impose any limitations on this.

[0053] In a preferred embodiment, the detection module may detect the differential signal lines in the clock generator in real time or at preset time intervals, generate a detection signal, and then determine whether the differential signal lines corresponding to the detection signal form a complete loop by judging the high or low level of the detection signal. Specifically, when the level of the detection signal is high, the detection module can determine that the differential signal lines do not form a complete loop, and the detection result of the detection module for the differential signal lines is: no external electronic components are connected to the clock signal output pin corresponding to the differential signal lines; when the level of the detection signal is low, the detection module can determine that the differential signal lines form a complete loop, and the detection result of the detection module for the differential signal lines is: an external electronic component is connected to the clock signal output pin corresponding to the differential signal lines.

[0054] In a preferred embodiment, if the detection result indicates that no external electronic component is connected to the clock signal output pin corresponding to the differential signal line, the detection module generates a result signal indicating that the electronic component is not in place, and returns this result signal to the control pin corresponding to the differential signal line in the clock generator. The result signal indicating that no external electronic component is connected to the clock signal output pin corresponding to the currently detected differential signal line indicates that the clock signal output pin is unused; for example, the clock signal output pin corresponding to the currently detected differential signal line may be a "reserved" pin or an empty pin.

[0055] If the detection result indicates that an electronic component is connected to the clock signal output pin corresponding to the differential signal line, the detection module generates a signal indicating that the electronic component is present and returns this signal to the control pin corresponding to the differential signal line in the clock generator. The signal indicating that the electronic component is present signifies that an electronic component is connected to the clock signal output pin corresponding to the currently detected differential signal line, and the clock signal output pin is in use. In this embodiment, the electronic component includes at least one or more of the following: CPU, OCP card, PCIe card, and NVMe card.

[0056] The clock generator is used to control whether the clock signal output pin corresponding to the differential signal line outputs a clock signal based on the received result signal.

[0057] In this embodiment, the clock generator in the server receives a result signal returned by the detection module. This result signal is generated by the detection module based on the detection result obtained by detecting whether the differential signal lines in the clock generator form a complete loop. After receiving the result signal returned by the detection module, the clock generator can control the clock signal output pin corresponding to the differential signal line according to the result signal, so as to control whether the clock signal output pin corresponding to the differential signal line outputs a clock signal.

[0058] In a preferred embodiment, the detection module can return the result signal generated for the differential signal line to the corresponding control pin via the differential signal line. The clock generator receives the result signal via the corresponding control pin and parses it to obtain the parsing result. The clock generator then generates a control command based on the parsing result to control whether the clock signal output pin corresponding to the differential signal line outputs a clock signal.

[0059] In the case where the received result signal is an electronic component presence signal, the clock generator generates a control command that allows clock signal output based on the obtained analysis result. The clock generator then controls the clock signal output pin corresponding to the differential signal line to output the clock signal to the electronic component connected to the clock signal output pin according to the control command.

[0060] When the received result signal is an electronic component not in position signal, the clock generator generates a control command that does not allow clock signal output based on the obtained analysis result. The clock generator controls the clock signal output pin corresponding to the differential signal line not to generate a clock signal according to the control command, thereby suppressing the clock signal output pin corresponding to the differential signal line from outputting a clock signal.

[0061] In this embodiment, the detection module in the control system detects whether the differential signal lines in the clock generator form a complete loop, and returns the detection result signal to the clock generator. The clock generator in the control system then controls whether the clock signal output pin corresponding to the differential signal line outputs a clock signal based on the received result signal. This achieves intelligent control: when an electronic component is connected to the clock signal output pin corresponding to the differential signal line, a clock signal is output; when no electronic component is connected to the clock signal output pin corresponding to the differential signal line, no clock signal is output. This avoids invalid clock signal output, significantly reduces product power consumption, saves a large amount of energy, reduces product electromagnetic radiation, improves product performance, and generates substantial economic benefits.

[0062] In conjunction with the above embodiments, in one embodiment, the present invention also provides a control system. In the differential signal lines of this control system, a first resistor is connected in series between the clock signal output pin and the control pin, and a second resistor is connected in series between the differential signal lines and the power supply.

[0063] In this embodiment, in each of the multiple differential signal lines in the clock generator, a first resistor is connected in series between the clock signal output pin corresponding to the differential signal line and the control pin corresponding to the differential signal line, and a second resistor is connected in series between the differential signal line and the power supply. Specifically, the first resistor is the resistor connected in series between the clock signal output pin and the control pin on the differential signal line, and the second resistor is the resistor connected in series between the differential signal line and the power supply.

[0064] In this embodiment, considering that the detection module needs to ensure that the current on the differential signal line is in an operating state when detecting the differential signal line, and that the voltage requirement on the differential signal line loop is relatively low, generally around a few tenths of a volt, the first resistor can be in the tens of ohms range. For example, the reference value of the first resistor can be 50Ω, and this embodiment does not impose any restrictions on this. Furthermore, the resistance values ​​of the multiple first resistors on multiple differential signal lines can be the same or different, and this embodiment does not impose any restrictions on this either.

[0065] Accordingly, the voltage of the differential signal line connected to the power supply is generally 3.3V, which requires a relatively high voltage. Therefore, the second resistor can be in the kiloohm range, such as a reference value of 4.7kΩ. This embodiment does not impose any limitation on this. Furthermore, the resistance values ​​of the multiple second resistors on multiple differential signal lines can be the same or different, and this embodiment also does not impose any limitation on this. Based on this, in a preferred embodiment, the resistance value of the second resistor is 100 times the resistance value of the first resistor.

[0066] In conjunction with the above embodiments, in one embodiment, the present invention also provides a control system. In this control system, the detection module is a Complex Programmable Logic Device (CPLD). Specifically, a CPLD can be developed by a technician to detect whether differential signal lines form a complete loop, obtain the detection result, and return a result signal to a clock generator based on the detection result, thereby enabling loop monitoring of the clock generator.

[0067] Please refer to Figure 6 , Figure 6 This is a flowchart illustrating a control method according to an embodiment of the present invention. The control method of this embodiment can be applied to a detection module in a control system; wherein, the control system includes a detection module and a clock generator, and the detection module is connected to multiple differential signal lines in the clock generator; the multiple differential signal lines in the clock generator are multiple lines connecting multiple clock signal output pins in the clock generator to corresponding multiple control pins. For example... Figure 6 As shown, the control method of this embodiment may include steps S11 and S12:

[0068] Step S11: Detect whether the differential signal lines in the clock generator form a complete loop and obtain the detection result.

[0069] In this embodiment, the detection module can detect whether the differential signal lines in the clock generator form a complete loop, that is, whether the clock signal output from the clock signal output pin returns to the corresponding control pin through the differential signal lines to form a complete loop, and obtain the detection result for that differential signal line. Since the detection module in the server is connected to multiple differential signal lines in the server's clock generator, the detection module can simultaneously detect all differential signal lines in the clock generator, or it can detect any one or more differential signal lines in the clock generator; this embodiment does not impose any limitations on this.

[0070] Step S12: Based on the detection result, return a result signal to the clock generator so that the clock generator controls whether the clock signal output pin corresponding to the differential signal line outputs a clock signal according to the received result signal.

[0071] In this embodiment, after the detection module obtains the detection result, it can generate a corresponding result signal based on the detection result and return the result signal to the clock generator through the differential signal line. This allows the clock generator to control the clock signal output pin corresponding to the differential signal line based on the received result signal, thereby controlling whether the clock signal output pin corresponding to the differential signal line outputs a clock signal.

[0072] In this embodiment, the detection module can detect whether the differential signal lines in the clock generator form a complete loop, that is, whether the clock signal output from the clock signal output pin returns to the corresponding control pin through the differential signal lines to form a complete loop. This provides the detection result, which is then returned to the clock generator. The clock generator can then control whether the clock signal output pin corresponding to the differential signal line outputs a clock signal based on the received result signal. This enables intelligent control of the clock signal output when an external electronic component is connected to the clock signal output pin, and suppressing the clock signal output when no external electronic component is connected. This reduces the server's useless power, lowers its electromagnetic radiation, and improves the overall electromagnetic compatibility performance of the server.

[0073] In conjunction with the above embodiments, in one embodiment, the present invention also provides a control method. In this method, step S11 may specifically include steps S21 and S22:

[0074] Step S21: Detect the differential signal line in the clock generator in real time or at preset time intervals to generate a detection signal.

[0075] In this embodiment, the detection module can detect the differential signal lines in the clock generator in real time or at preset time intervals. The preset time interval can be set beforehand based on human experience, such as 5 seconds, 10 seconds, or 1 second; this embodiment does not impose any restrictions on this. The detection module, by detecting the differential signal lines in the clock generator in real time or at preset time intervals, will generate corresponding detection signals for each differential signal line.

[0076] Step S22: Determine whether the differential signal lines form a complete loop by measuring the level of the detection signal.

[0077] In this embodiment, after the detection module generates a detection signal, it can determine whether the differential signal line forms a complete loop by judging the level of the detection signal. Specifically, when the level of the detection signal is high, the detection module can determine that the differential signal line does not form a complete loop; that is, the detection module can determine that the clock signal output from the clock signal output pin has not returned to the corresponding control pin through the differential signal line to form a complete loop. The detection result obtained by the detection module is that no external electronic components are connected to the clock signal output pin corresponding to the differential signal line. When the level of the detection signal is low, the detection module can determine that the differential signal line forms a complete loop; that is, the detection module can determine that the clock signal output from the clock signal output pin has returned to the corresponding control pin through the differential signal line to form a complete loop. The detection result obtained by the detection module is that an external electronic component is connected to the clock signal output pin corresponding to the differential signal line.

[0078] In this embodiment, the detection module can accurately determine whether the differential signal lines form a complete loop by measuring the high and low levels of the detection signal generated by the differential signal lines, thereby obtaining accurate detection results in real time, which provides a basis for the intelligent control of the clock signal output by the clock generator.

[0079] In conjunction with the above embodiments, in one embodiment, the present invention also provides a control method. In this method, step S12 may specifically include steps S31 and S32:

[0080] Step S31: If the detection result indicates that no external electronic component is connected to the clock signal output pin corresponding to the differential signal line, return the result signal indicating that the electronic component is not in place to the control pin corresponding to the differential signal line in the clock generator.

[0081] In this embodiment, if the detection module detects that no external electronic component is connected to the clock signal output pin corresponding to the differential signal line, the detection module generates a signal indicating that the electronic component is not in place and returns this signal to the control pin corresponding to the differential signal line in the clock generator. The signal indicating that the clock signal output pin corresponding to the currently detected differential signal line is not connected to any external electronic component and is unused; for example, the clock signal output pin corresponding to the currently detected differential signal line may be a "reserved" pin or an empty pin.

[0082] Step S32: If the detection result indicates that an electronic component is connected to the clock signal output pin corresponding to the differential signal line, return the result signal indicating that the electronic component is in place to the control pin corresponding to the differential signal line in the clock generator.

[0083] In this embodiment, when the detection module detects that an electronic component is connected to the clock signal output pin corresponding to the differential signal line, the detection module generates a signal indicating that the electronic component is present and returns this signal to the control pin corresponding to the differential signal line in the clock generator. The signal indicating that the electronic component is present signifies that an electronic component is connected to the clock signal output pin corresponding to the currently detected differential signal line, and that the clock signal output pin is in use.

[0084] In this embodiment, the detection module can generate a corresponding signal indicating whether the electronic component is present or absent based on the detection results. This signal is then returned to the control pin corresponding to the differential signal line, informing the clock generator whether an external electronic component is connected to the clock signal output pin corresponding to the current differential signal line, and whether the clock signal output pin is in use. This allows the clock generator to perform intelligent control based on the result signal, outputting the clock signal when a component is present and turning off the clock signal when no component is present. This reduces product power consumption while improving the product's electromagnetic compatibility performance and enhancing its overall market competitiveness.

[0085] In conjunction with any of the above embodiments, in one embodiment, the present invention also provides a control method. In this method, the electronic components include at least one or more of the following: a CPU, an OCP card, a PCIe card, and an NVMe card.

[0086] Among them, OCP cards, PCIe cards, and NVMe cards are all server expansion cards, serving to expand the basic functions of the server. Therefore, during the server product planning process, technicians can plan multiple pins for OCP cards, PCIe cards, and NVMe cards in the clock generator. When customers need OCP cards, PCIe cards, or NVMe cards, they can directly add these cards to the corresponding pins to meet their actual needs. However, if customers do not need this function, they can choose not to add OCP cards, PCIe cards, or NVMe cards to the pins, but instead add the corresponding server brackets in the corresponding positions. This results in the reservation of expansion cards. In addition, sometimes technicians plan general-purpose servers with 4 CPUs or 2 CPU interfaces, but in reality, only a single CPU or dual CPU configuration is used. In other words, there are CPUs that are not actually used.

[0087] The control method in this embodiment can automatically control the clock signal output when electronic components such as OCP cards, PCIe cards, NVMe cards, and CPUs are connected to the clock signal output pin; when server expansion cards such as OCP cards, PCIe cards, and NVMe cards are not in place, or when components such as CPUs are not in place, no clock signal is generated, and the clock signal output is automatically suppressed, thereby reducing product power consumption and improving the product's electromagnetic compatibility performance.

[0088] Please refer to Figure 7 , Figure 7 This is a flowchart illustrating a control method according to an embodiment of the present invention. The control method of this embodiment can be applied to a clock generator in a control system; wherein the control system includes a detection module and a clock generator, the detection module being connected to multiple differential signal lines in the clock generator; the multiple differential signal lines in the clock generator are multiple lines connecting multiple clock signal output pins in the clock generator to corresponding multiple control pins. For example... Figure 7 As shown, the control method of this embodiment may include steps S41 and S42:

[0089] Step S41: Receive the result signal returned by the detection module; the result signal is generated by the detection module based on the detection result obtained by the detection module according to whether the differential signal lines in the detection clock generator form a complete loop.

[0090] In this embodiment, the clock generator can receive the result signal returned by the detection module for the differential signal line. This result signal indicates whether the differential signal line forms a complete loop, and thus indicates whether the clock signal output pin corresponding to the differential signal line is connected to an external electronic component. If the differential signal line forms a complete loop, it indicates that the clock signal output pin is connected to an external electronic component; if the differential signal line does not form a complete loop, it indicates that the clock signal output pin is not connected to an external electronic component.

[0091] Step S42: Based on the result signal, control whether the clock signal output pin corresponding to the differential signal line outputs a clock signal.

[0092] In this embodiment, after the clock generator receives the result signal returned by the detection module, it can control the clock signal output pin corresponding to the differential signal line according to the result signal, so as to control whether the clock signal output pin corresponding to the differential signal line outputs a clock signal.

[0093] In this embodiment, the clock generator can control whether the clock signal output pin corresponding to the differential signal line outputs a clock signal based on the received result signal. This enables intelligent control of clock signal output when an external electronic component is connected to the clock signal output pin corresponding to the differential signal line, and suppression of clock signal output when no external electronic component is connected to the clock signal output pin corresponding to the differential signal line. This reduces the server's useless power, lowers the server's electromagnetic radiation, and improves the overall electromagnetic compatibility performance of the server.

[0094] In conjunction with any of the above embodiments, in one embodiment, the present invention also provides a control method. In this method, step S41 specifically includes step S51, and step S42 specifically includes S52 and S53:

[0095] Step S51: Receive the result signal through the control pin corresponding to the differential signal line.

[0096] In this embodiment, the differential signal lines of the clock generator can also be used to transmit signals, such as clock signals, detection signals, and result signals. The detection module can use the differential signal lines to return the result signal generated for the differential signal lines to the control pins corresponding to the differential signal lines, and the clock generator can receive the result signal through the control pins corresponding to the differential signal lines.

[0097] In this embodiment, after receiving the result signal through the control pin corresponding to the differential signal line, the clock generator can parse the result signal to obtain the parsing result. The clock generator then generates a control command based on the parsing result to control whether the clock signal output pin corresponding to the differential signal line outputs a clock signal.

[0098] Step S52: When the result signal is an electronic component in-place signal, control the clock signal output pin corresponding to the differential signal line to output a clock signal to the electronic component connected to the clock signal output pin.

[0099] In this embodiment, when the received result signal is an electronic component presence signal, the clock generator generates a control command that allows clock signal output based on the analysis result obtained from parsing the result signal. The clock generator then controls the clock signal output pin corresponding to the differential signal line to output a clock signal to the electronic component connected to the clock signal output pin according to the control command.

[0100] Step S53: When the result signal is the electronic component not in place signal, control the clock signal output pin corresponding to the differential signal line not to generate a clock signal.

[0101] In this embodiment, when the received result signal is an electronic component not in place signal, the clock generator generates a control command that does not allow clock signal output based on the analysis result obtained from parsing the result signal. The clock generator controls the clock signal output pin corresponding to the differential signal line not to generate a clock signal according to the control command, thereby suppressing the clock signal output pin corresponding to the differential signal line from outputting a clock signal.

[0102] In this embodiment, the clock generator analyzes the received result signal to obtain the analysis result, and generates corresponding control commands based on the analysis result. According to the control commands, it automatically controls whether the corresponding clock signal output pin outputs a clock signal, thereby completing the intelligent control of clock signal output when there is a component and clock signal off when there is no component. This reduces product power consumption, improves product electromagnetic compatibility performance, and enhances the overall market competitiveness of the product.

[0103] In conjunction with any of the above embodiments, in one embodiment, the present invention also provides a control method. In this method, the electronic components include at least one or more of the following: a CPU, an OCP card, a PCIe card, and an NVMe card. For detailed descriptions of the electronic components such as the CPU, OCP card, PCIe card, and NVMe card, please refer to the embodiments of the control method applied to the detection module.

[0104] The control method of this embodiment can automatically control the clock signal output when electronic components such as OCP cards, PCIe cards, NVMe cards, and CPUs are connected to the clock signal output pin; when server expansion cards such as OCP cards, PCIe cards, and NVMe cards are not in place, or when components such as the CPU are not in place, no clock signal is generated, and the clock signal output is automatically suppressed, thereby reducing the server's useless power, reducing the server's electromagnetic radiation, and improving the overall electromagnetic compatibility performance of the server.

[0105] In one embodiment, see Figure 8 , Figure 8 This is a schematic diagram illustrating an optimized clock generator circuit design according to an embodiment of the present invention. Figure 8 The image shows a clock generator with one input and multiple outputs, connected to a P3V3 power supply. The clock generator has multiple clock signal output pins (such as...). Figure 8 The pins A1, A3, A5...A27, A29, A31, A33, A35, A37, A38, A39, etc.) and multiple control pins (such as... Figure 8 (e.g., OE0-OE7 in the clock generator). In this clock generator, multiple clock signal output pins are connected to lines and a first resistor (e.g., ...). Figure 8 R9-R16 in the circuit are connected to multiple corresponding control pins to form multiple differential signal lines in the clock generator, and each differential signal line is connected to a second resistor (such as R9-R16 in the circuit). Figure 8 R1-R8 in the circuit are connected to power supply P3V3. For example, the clock signal output pin A31 is connected to the control pin OE2 through a line and the first resistor R11, forming a differential signal line. This differential signal line is connected to power supply P3V3 through the second resistor R3. The reference resistance values ​​for R1, R2, R3, R4, R5, R6, R7, and R8 can be 4.7kΩ, and the reference resistance values ​​for R9, R10, R11, R12, R13, R14, R15, and R16 can be 50Ω. Based on this, the detection module CPLD is connected to multiple differential signal lines in the clock generator to detect whether the differential signal lines can form a complete loop. It should be noted that... Figure 8 Only a portion of the differential signal lines are shown, such as Figure 8 The differential signal lines A1, A3, A5...A25 are not shown in the diagram, but in reality, each clock signal output pin on the clock generator can be connected to the corresponding control pin through a line to form a differential signal line. Moreover, each differential signal line is connected to the detection module CPLD, so that the detection module CPLD can detect whether each differential signal line connected to it is a complete loop.

[0106] Among them, the example, Figure 8The differential signal line of the CPU returns the clock signal CLK_100M_CPU1_MCIO_0_DN to the A31 pin via the first resistor R11. The detection module CPLD detects this differential signal line and generates the detection signal FM_CPU1_PEHP_CLK_OE_N. The CPLD determines whether the differential signal line can form a complete loop by checking the level of the detection signal FM_CPU1_PEHP_CLK_OE_N: when it is low, it is determined that a complete loop is formed, the CPU is present, that is, the CPU is connected to the A31 pin; when it is high, it is determined that a complete loop is not formed, the CPU is not present, that is, the CPU is not connected to the A31 pin. When the CPU has a device in the network, the CPLD detection module returns an in-network result signal to the OE2 pin of the clock generator, and the clock generator controls the A31 pin to output a 100MHz clock signal for the CPU. When the CPU does not have a device in the network, the CPLD detection module also returns an out-of-network result signal to the OE2 pin of the clock generator, and the clock generator does not generate a clock signal, controlling the A31 pin not to output a 100MHz clock signal for the CPU.

[0107] Example, Figure 8 The differential signal line of the OCP returns the clock signal CLK_50M_CPU1_OE0_OCP1_0_DN to the A33 pin through the first resistor R12. The detection module CPLD detects this differential signal line and generates the detection signal FM_OCP1_PEHP_CLK_OE_N. The detection module CPLD determines whether the differential signal line can form a complete loop by detecting the high or low level of the detection signal FM_OCP1_PEHP_CLK_OE_N: when it is low, it is determined that a complete loop is formed, and the OCP network card is in place, that is, the OCP network card device is installed on the A33 pin; when it is high, it is determined that a complete loop is not formed, and the OCP network card is not in place, that is, the OCP network card device is not installed on the A33 pin. When the OCP network card is connected, the detection module CPLD returns a signal indicating that it is in place to the OE3 pin of the clock generator. The clock generator then controls the A33 pin to output the OCP 50MHz clock signal. When the OCP network card is not connected, the detection module CPLD also returns a signal indicating that it is not in place to the OE3 pin of the clock generator. The clock generator does not generate a clock signal and controls the A33 pin not to output the OCP 50MHz clock signal.

[0108] The same principle, for example. Figure 8The differential signal line of the PCIe returns the clock signal CLK_100M_CPU1_OE1_PCIE1_0_DN to pin OE4 via the first resistor R13. The detection module CPLD detects this differential signal line and generates a detection signal FM_PCIE1_PEHP_CLK_OE_N. The CPLD determines whether the differential signal line can form a complete loop by checking the level of the detection signal FM_PCIE1_PEHP_CLK_OE_N: when it is low, it is determined that a complete loop is formed, and the PCIe network card is present, that is, the PCIe network card is installed on pin A35; when it is high, it is determined that a complete loop is not formed, and the PCIe network card is not present, that is, the PCIe network card is not installed on pin A35. When a PCIe network card is connected, the CPLD detection module returns an "in" signal to the OE4 pin of the clock generator, which then controls the A35 pin to output a PCIe 100MHz clock signal. When a PCIe network card is not connected, the CPLD detection module also returns an "out" signal to the OE4 pin of the clock generator, which then stops generating a clock signal and controls the A35 pin not to output a PCIe 100MHz clock signal.

[0109] NVMe devices operate on the same principle as OCP and PCIe devices, for example. Figure 8 The differential signal line of the NVME returns the clock signal CLK_50M_CPU1_OE2_NVME1_0_DN to pin OE5 via resistor R14. The detection module CPLD detects this differential signal line and generates a detection signal FM_NVME1_PEHP_CLK_OE_N. The CPLD determines whether the differential signal line can form a complete loop by checking the level of the detection signal FM_NVME1_PEHP_CLK_OE_N: when it is low, it is determined that a complete loop is formed, and the NVME network card is present, i.e., the NVME network card is connected to pin A37; when it is high, it is determined that a complete loop is not formed, and the NVME network card is not present, i.e., the NVME network card is not connected to pin A37. When the NVMe network card is installed, the detection module CPLD returns an "in-place" signal to the OE5 pin of the clock generator, and the clock generator controls the A37 pin to output the NVMe 50MHz clock signal. When the NVMe network card is not installed, the detection module CPLD also returns an "out-of-place" signal to the OE5 pin of the clock generator, and the clock generator does not generate a clock signal, controlling the A37 pin not to output the NVMe 50MHz clock signal.

[0110] like Figure 8As shown, when clock generators A38 and A39 are unused pins, NC0 and NC1 are connected to pins OE7 and OE6 respectively via resistors R16 and R15. The detection module CPLD detects this differential signal line and generates detection signals FM_NC0_PEHP_CLK_OE_N and FM_NC1_PEHP_CLK_OE_N. The detection module CPLD detects these signals via the detection signals FM_NC0_PEHP_CLK_OE_N and FM_NC1_PEHP_CLK_OE_N. The high and low levels of _CLK_OE_N are used to detect signals. The detection module CPLD can detect whether the differential signal lines can form a complete loop. When it is high, it is determined that a complete loop is not formed, and A38 and A39 are determined to be empty pins, indicating that the electronic device is not in place. The detection module CPLD also returns an absence result signal to the OE7 and OE6 pins of the clock generator. The clock generator does not generate a clock signal, and the A38 and A39 pins are controlled not to output a clock signal.

[0111] It should be noted that, Figure 8 This is merely an example of this embodiment and does not impose any restrictions on the number of pins or unused pins of each electronic component in the clock generator. These can be arbitrarily set according to actual needs.

[0112] In this embodiment, the detection module CPLD can identify whether the clock signal forms a complete loop. Therefore, when server expansion cards such as OCP cards, PCIe cards, and NVMe cards are not in place, or when components such as the CPU are not in place, the clock signal is automatically controlled not to be output. This reduces the server's useless power, reduces the server's electromagnetic radiation, and improves the overall electromagnetic compatibility performance of the server.

[0113] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of the present invention are not limited to the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0114] Based on the same inventive concept, one embodiment of the present invention provides a control device 900, which can be applied to a detection module. (See reference) Figure 9 , Figure 9 This is a structural block diagram of a control device provided in an embodiment of the present invention. Figure 9 As shown, the control device 900 includes:

[0115] The detection module 901 is used to detect whether the differential signal lines in the clock generator form a complete loop and obtain the detection result.

[0116] The return module 902 is used to return a result signal to the clock generator based on the detection result, so that the clock generator controls whether the clock signal output pin corresponding to the differential signal line outputs a clock signal based on the received result signal.

[0117] The detection module is connected to multiple differential signal lines in the clock generator; the multiple differential signal lines in the clock generator are multiple lines that connect multiple clock signal output pins in the clock generator to multiple corresponding control pins.

[0118] Optionally, the detection module 901 includes:

[0119] The signal generation module is used to detect the differential signal lines in the clock generator in real time or at preset time intervals, and generate a detection signal.

[0120] The detection submodule is used to determine whether the differential signal lines form a complete loop by measuring the level of the detection signal.

[0121] Wherein, when the level on the detection signal is high, it is determined that the differential signal line does not form a complete loop, and the detection result is that no external electronic components are connected to the clock signal output pin corresponding to the differential signal line;

[0122] When the level on the detection signal is low, it is determined that the differential signal line forms a complete loop, and the detection result is that the clock signal output pin corresponding to the differential signal line is connected to an electronic component.

[0123] Optionally, the return module 902 includes:

[0124] The first return module is used to return a result signal indicating that the electronic component is not in place to the control pin corresponding to the differential signal line in the clock generator when the detection result indicates that no external electronic component is connected to the clock signal output pin corresponding to the differential signal line.

[0125] The second return module is used to return a result signal indicating that the electronic component is in place to the control pin corresponding to the differential signal line in the clock generator when the detection result indicates that an electronic component is connected to the clock signal output pin corresponding to the differential signal line.

[0126] Optionally, the electronic components include at least one or more of the following: CPU, OCP card, PCIe card, and NVMe card.

[0127] Based on the same inventive concept, one embodiment of the present invention also provides a control device 1000, which can be applied to a clock generator. (See reference) Figure 10 , Figure 10 This is a structural block diagram of a control device provided in an embodiment of the present invention. Figure 10 As shown, the control device 1000 includes:

[0128] The receiving module 1001 is used to receive the result signal returned by the detection module; the result signal is generated by the detection module based on the detection result obtained by the detection module according to whether the differential signal lines in the detection clock generator form a complete loop;

[0129] Control module 1002 is used to control whether the clock signal output pin corresponding to the differential signal line outputs a clock signal according to the result signal.

[0130] The detection module is connected to multiple differential signal lines in the clock generator; the multiple differential signal lines in the clock generator are multiple lines that connect multiple clock signal output pins in the clock generator to multiple corresponding control pins.

[0131] Optionally, the receiving module 1001 includes:

[0132] A receiving submodule is used to receive the result signal through the control pins corresponding to the differential signal lines;

[0133] The control module 1002 includes:

[0134] The first control module is used to control the clock signal output pin corresponding to the differential signal line to output a clock signal to the electronic component connected to the clock signal output pin when the result signal is an electronic component in place signal.

[0135] The first control module is used to control the clock signal output pin corresponding to the differential signal line not to generate a clock signal when the result signal is the electronic component is not in place.

[0136] Optionally, the electronic components include at least one or more of the following: CPU, OCP card, PCIe card, and NVMe card.

[0137] Based on the same inventive concept, another embodiment of the present invention provides an electronic device 1100, such as... Figure 11 As shown. Figure 11This is a schematic diagram of an electronic device according to an embodiment of the present invention. The electronic device includes a processor 1101, a memory 1102, and a computer program stored in the memory 1102 and executable on the processor 1101. When the computer program is executed by the processor, it implements the steps of the control method described in any of the above embodiments of the present invention.

[0138] Based on the same inventive concept, another embodiment of the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the control method as described in any of the above embodiments of the present invention.

[0139] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0140] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0141] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0142] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of the present invention.

[0143] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this invention can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0144] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0145] In the embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0146] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0147] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0148] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0149] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A control system applied to a server, characterized in that, The control system includes a clock generator and a detection module. In the clock generator, multiple clock signal output pins are connected to corresponding control pins via lines, forming multiple differential signal lines in the clock generator. The detection module is connected to the multiple differential signal lines in the clock generator. The detection module is used to detect whether the differential signal lines in the clock generator form a complete loop, and obtain the detection result; based on the detection result, it returns a result signal to the clock generator. The clock generator is used to control whether the clock signal output pin corresponding to the differential signal line outputs a clock signal based on the received result signal. The detection of whether the differential signal lines in the clock generator form a complete loop, and the resulting detection, includes: The differential signal lines in the clock generator are detected in real time or at preset time intervals to generate a detection signal; the level of the detection signal is used to determine whether the differential signal lines form a complete loop. Wherein, when the level on the detection signal is high, it is determined that the differential signal line does not form a complete loop, and the detection result is that no external electronic components are connected to the clock signal output pin corresponding to the differential signal line; When the level on the detection signal is low, it is determined that the differential signal line forms a complete loop, and the detection result is that the clock signal output pin corresponding to the differential signal line is connected to an electronic component.

2. The control system according to claim 1, characterized in that, In the differential signal line, a first resistor is connected in series between the clock signal output pin and the control pin, and a second resistor is connected in series between the differential signal line and the power supply.

3. The control system according to claim 1, characterized in that, The detection module is a complex programmable logic device.

4. A control method, characterized in that, Applied to a detection module, the method includes: The detection results are obtained by detecting whether the differential signal lines in the clock generator form a complete loop. Based on the detection result, a result signal is returned to the clock generator, so that the clock generator controls whether the clock signal output pin corresponding to the differential signal line outputs a clock signal according to the received result signal; The detection module is connected to multiple differential signal lines in the clock generator; the multiple differential signal lines in the clock generator are multiple lines that connect multiple clock signal output pins in the clock generator to multiple corresponding control pins respectively. The detection result is obtained by determining whether the differential signal lines in the clock generator form a complete loop, including: The differential signal line in the clock generator is detected in real time or at preset time intervals to generate a detection signal; By determining whether the differential signal lines form a complete loop based on the high or low level of the detection signal; Wherein, when the level on the detection signal is high, it is determined that the differential signal line does not form a complete loop, and the detection result is that no external electronic components are connected to the clock signal output pin corresponding to the differential signal line; When the level on the detection signal is low, it is determined that the differential signal line forms a complete loop, and the detection result is that the clock signal output pin corresponding to the differential signal line is connected to an electronic component.

5. The control method according to claim 4, characterized in that, The step of returning a result signal to the clock generator based on the detection result includes: If the detection result indicates that no external electronic component is connected to the clock signal output pin corresponding to the differential signal line, a result signal indicating that the electronic component is not in place is returned to the control pin corresponding to the differential signal line in the clock generator. If the detection result indicates that an electronic component is connected to the clock signal output pin corresponding to the differential signal line, the result signal indicating that the electronic component is in place is returned to the control pin corresponding to the differential signal line in the clock generator.

6. The control method according to claim 5, characterized in that, The electronic components include at least one or more of the following: CPU, OCP card, PCIe card, and NVMe card.

7. A control method, characterized in that, Applied to a clock generator, the method includes: Receive the result signal returned by the detection module; the result signal is generated by the detection module based on the detection result obtained by the detection module according to whether the differential signal lines in the detection clock generator form a complete loop; Based on the result signal, control whether the clock signal output pin corresponding to the differential signal line outputs a clock signal; The detection module is connected to multiple differential signal lines in the clock generator; the multiple differential signal lines in the clock generator are multiple lines that connect multiple clock signal output pins in the clock generator to multiple corresponding control pins respectively. The detection result is obtained by determining whether the differential signal lines in the clock generator form a complete loop, including: The differential signal lines in the clock generator are detected in real time or at preset time intervals to generate a detection signal; the level of the detection signal is used to determine whether the differential signal lines form a complete loop. Wherein, when the level on the detection signal is high, it is determined that the differential signal line does not form a complete loop, and the detection result is that no external electronic components are connected to the clock signal output pin corresponding to the differential signal line; When the level on the detection signal is low, it is determined that the differential signal line forms a complete loop, and the detection result is that the clock signal output pin corresponding to the differential signal line is connected to an electronic component.

8. The control method according to claim 7, characterized in that, The result signal returned by the receiving and detection module includes: The result signal is received through the control pin corresponding to the differential signal line; The step of controlling whether the clock signal output pin corresponding to the differential signal line outputs a clock signal based on the result signal includes: When the result signal is an electronic component presence signal, the clock signal output pin corresponding to the differential signal line is controlled to output a clock signal to the electronic component connected to the clock signal output pin. When the result signal is an "electronic component not in position" signal, the clock signal output pin corresponding to the differential signal line is controlled not to generate a clock signal.

9. The control method according to claim 8, characterized in that, The electronic components include at least one or more of the following: CPU, OCP card, PCIe card, and NVMe card.

10. A control device, characterized in that, The device, applied to a detection module, includes: The detection module is used to detect whether the differential signal lines in the clock generator form a complete loop and obtain the detection result. The return module is used to return a result signal to the clock generator based on the detection result, so that the clock generator controls whether the clock signal output pin corresponding to the differential signal line outputs a clock signal according to the received result signal. The detection module is connected to multiple differential signal lines in the clock generator; the multiple differential signal lines in the clock generator are multiple lines that connect multiple clock signal output pins in the clock generator to multiple corresponding control pins respectively. The detection module includes: The signal generation module is used to detect the differential signal lines in the clock generator in real time or at preset time intervals, and generate a detection signal. The detection submodule is used to determine whether the differential signal lines form a complete loop by measuring the level of the detection signal. Wherein, when the level on the detection signal is high, it is determined that the differential signal line does not form a complete loop, and the detection result is that no external electronic components are connected to the clock signal output pin corresponding to the differential signal line; When the level on the detection signal is low, it is determined that the differential signal line forms a complete loop, and the detection result is that the clock signal output pin corresponding to the differential signal line is connected to an electronic component.

11. A control device, characterized in that, Applied to a clock generator, the device includes: The receiving module is used to receive the result signal returned by the detection module; the result signal is generated by the detection module based on the detection result obtained by the detection module according to whether the differential signal lines in the detection clock generator form a complete loop; The control module is used to control whether the clock signal output pin corresponding to the differential signal line outputs a clock signal based on the result signal. The detection module is connected to multiple differential signal lines in the clock generator; the multiple differential signal lines in the clock generator are multiple lines that connect multiple clock signal output pins in the clock generator to multiple corresponding control pins respectively. The detection module obtains a detection result based on whether the differential signal lines in the clock generator form a complete loop, including: The signal generation module of the detection module detects the differential signal line in the clock generator in real time or at preset time intervals to generate a detection signal. The detection submodule of the detection module determines whether the differential signal lines form a complete loop by measuring the level of the detection signal. Wherein, when the level on the detection signal is high, it is determined that the differential signal line does not form a complete loop, and the detection result is that no external electronic components are connected to the clock signal output pin corresponding to the differential signal line; When the level on the detection signal is low, it is determined that the differential signal line forms a complete loop, and the detection result is that the clock signal output pin corresponding to the differential signal line is connected to an electronic component.

12. An electronic device, characterized in that, include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the control method as described in any one of claims 4 to 9.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the control method as described in any one of claims 4 to 9.

Images