Solid state drive, device and operating method of solid state drive

Abstract

The present disclosure provides a solid state drive, an apparatus and an operating method of the solid state drive. The solid state drive comprises a NAND memory and a solid state drive controller comprising an interface, a non-volatile memory controller and a processor. The solid state drive controller is configured to receive a write command from a host via the interface, process the write command by the non-volatile memory controller, transmit a system message from the non-volatile memory controller to the processor, process the system message according to a zoning namespace protocol by the processor, acquire host data for storage from the host via the interface by the non-volatile memory controller, write the host data into the NAND memory based on a processing result of the system message, and perform the processing of the system message according to the zoning namespace protocol by the processor and the acquisition of the host data from the host by the non-volatile memory controller in parallel. The present disclosure is implemented in a combination of software and hardware, supports programming upgrade and adapts to subsequent protocol upgrade.

Description

Technical Field

[0001] The present disclosure relates generally to solid state drives (SSDs), and more particularly to SSDs, devices, and methods of operating SSDs. Background Art

[0002] A solid-state drive (SSD) is a storage device consisting of one or more solid-state electronic memory chips. A SSD typically includes a controller and semiconductor memory chips.

[0003] The design of enterprise-standard solid-state drives typically relies on protocols such as the high-speed Peripheral Component Interconnect Express (PCIe) protocol and the nonvolatile memory express (NVMe) protocol. Under these protocols, the host operates the solid-state drive in the same manner as a traditional hard disk drive (HDD), where the characteristics of the solid-state drive itself are invisible to the host. Therefore, the solid-state drive controller needs to adapt to the characteristics of the storage medium to ensure data reliability. The essential difference between solid-state drives and traditional hard disk drives is that the storage medium of solid-state drives needs to be erased block by block before being written. Because the characteristics of the data written by the host are inconsistent, a large number of holes / unused storage cells are generated. The solid-state drive controller needs to perform hole recovery (i.e., garbage collection (GC)) and repeatedly write the same data. This leads to increased writing and erasing in the solid-state drive, which in turn shortens the device lifespan.

[0004] The Zoned Namespaces (ZNS) protocol has been proposed for solid-state drives. A ZNS SSD differs from a traditional SSD in that the physical information of the storage medium is exposed to the host. The host can write different types of data to different physical areas on the SSD, which reduces garbage collection, thereby increasing the SSD's lifespan and reducing its power consumption. However, the ZNS protocol is non-standard and subject to change over time. Summary of the Invention

[0005] In view of the above, one object of the present disclosure is to implement a partition namespace solid-state drive controller in a combination of software and hardware.

[0006] In one aspect, a solid-state drive is provided. The solid-state drive includes a NAND memory and a solid-state drive controller. The solid-state drive controller includes an interface coupled to a host, a nonvolatile memory controller coupled to the interface, and a processor coupled to the nonvolatile memory controller. The solid-state drive controller is configured to: receive a write command from the host via the interface; process the write command via the nonvolatile memory controller; transmit a system message from the nonvolatile memory controller to the processor; process the system message via the processor according to a Zoned Namespaces (ZNS) protocol; obtain host data for storage from the host via the interface via the nonvolatile memory controller; and write the host data to the NAND memory based on the result of processing the system message. Processing the system message by the processor and obtaining the host data by the nonvolatile memory controller are performed in parallel.

[0007] In some embodiments, the interface operates according to the Peripheral Component Interconnect Express (PCIe) protocol.

[0008] In some embodiments, the nonvolatile memory controller operates according to a nonvolatile memory express (NVMe) protocol.

[0009] In some embodiments, the nonvolatile memory controller includes a submission queue (SQ) module configured to determine a submission queue identifier and initiate an operation to obtain the content of a submission queue entry (SQE) by sending a request for the content of the SQE to a host.

[0010] In some embodiments, the nonvolatile memory controller includes a submission queue entry module, and the nonvolatile memory controller receives the submission queue entry content to the submission queue entry module.The system message transmitted from the nonvolatile memory controller to the processor includes the submission queue entry content.

[0011] In some embodiments, the nonvolatile memory controller includes a completion queue (CQ) module and a merge module. The merge module is configured to send a completion queue message to the completion queue module after receiving a processing result of a system message from a processor and receiving host data from a host.

[0012] In some embodiments, the completion queue module is configured to send a completion queue entry (CQE) message to the host indicating completion of the write command in response to receiving the completion queue message from the merge module.

[0013] In some embodiments, the write command is a doorbell message.

[0014] In another aspect, a device is provided, comprising a host and a solid-state drive. The solid-state drive includes a NAND memory and a solid-state drive controller. The solid-state drive controller includes an interface coupled to the host, a non-volatile memory controller coupled to the interface, and a processor coupled to the non-volatile memory controller. The solid-state drive controller is configured to: receive a write command from the host via the interface; process the write command via the non-volatile memory controller; transmit a system message from the non-volatile memory controller to the processor; process the system message via the processor according to a Zoned Namespaces (ZNS) protocol; obtain host data for storage from the host via the interface via the non-volatile memory controller; and write the host data to the NAND memory based on the result of processing the system message. Processing the system message by the processor and obtaining the host data by the non-volatile memory controller are performed in parallel.

[0015] In yet another aspect, a method for operating a solid-state drive is provided. The solid-state drive includes a NAND memory and a solid-state drive controller coupled to the NAND memory. The solid-state drive controller includes an interface coupled to a host, a nonvolatile memory controller coupled to the interface, and a processor coupled to the nonvolatile memory controller. The operating method includes: receiving a write command from the host via the interface; processing the write command by the nonvolatile memory controller; transmitting a system message from the nonvolatile memory controller to the processor; processing the system message by the processor according to a Zoned Namespaces (ZNS) protocol; obtaining host data for storage from the host via the interface by the nonvolatile memory controller; and writing the host data to the NAND memory by the solid-state drive controller based on a result of processing the system message. Processing the system message by the processor according to the ZNS protocol and obtaining the host data from the host by the nonvolatile memory controller are performed in parallel.

[0016] In the disclosed embodiment, a partitioned namespace solid-state drive (ZNSSSD) controller is implemented in a combination of software and hardware. More mature protocols (e.g., PCIe protocol and NVMe protocol) are implemented by hardware to provide robustness in write operations, and less mature protocols (e.g., ZNS protocol) are implemented by software executed by a processor to balance performance, latency, and power consumption. Updates to less mature protocols (e.g., ZNS protocol) can be easily implemented through software updates, thereby modifying the solid-state drive system through software updates to adapt to the latest protocols that benefit from technological improvements, providing the solid-state drive system with flexibility to adapt to the latest protocol updates of emerging protocols without changing its hardware structure. By having the processor perform processing related to the ZNS protocol and obtain data for storage from the host in parallel, the waiting time for storing data in the NAND memory is reduced, thereby improving the write efficiency of the solid-state drive. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Certain features of various embodiments of the present technology are particularly set forth in the appended claims. The features and advantages of the present technology will be better understood by reference to the following detailed description, which sets forth exemplary embodiments utilizing the principles of the present disclosure, and the accompanying drawings of these exemplary embodiments are as follows:

[0018] Figure 1 A block diagram of a system according to an exemplary embodiment is shown.

[0019] Figure 2 A flow chart illustrating a method of processing a write command in a solid-state drive according to an exemplary embodiment.

[0020] Figure 3 A ladder diagram illustrating a method for processing a write command in a solid-state drive system / device including a host and a solid-state drive according to an exemplary embodiment.

[0021] Figure 4 A ladder diagram illustrating a method for processing a system command in a solid-state drive system / device including a host and a solid-state drive according to an exemplary embodiment.

[0022] Figure 5 A ladder diagram illustrating a method for processing a read command in a solid-state drive system / device including a host and a solid-state drive according to an exemplary embodiment. Specific embodiments

[0023] In order to fully understand the various embodiments of the present disclosure, certain specific details are set forth in the following description. However, those skilled in the art will appreciate that the present disclosure can be implemented without these details. In addition, although various embodiments of the present disclosure are disclosed herein, many adjustments and modifications can be made within the scope of the present disclosure based on the common knowledge of those skilled in the art. These modifications include replacing any aspect of the present disclosure with a known equivalent so as to achieve the same result in substantially the same manner.

[0024] Unless the context requires otherwise, in this specification and claims, the word "comprise" and variations thereof, such as "have" and "include", are to be interpreted in an open, inclusive sense, that is, "including but not limited to". The recitation of numerical ranges throughout this specification is intended as a shorthand notation for independent reference to each individual value falling within the range, including the values ​​defining the range. Each individual value is included in this specification as if it were individually recited herein. In addition, unless the context clearly dictates otherwise, the singular forms "a", "the", and "the" include plural referents.

[0025] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification do not necessarily all refer to the same embodiment, but may in some cases do. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0026] Various embodiments relate to technologies for providing solid-state drive controllers for programmable ZNS protocols and other extensible protocols. In some embodiments, the solid-state drive controllers add programmable ZNS protocols and other extensible protocols to standard protocols such as NVMe and PCIe to provide a flexible solution for solid-state drive technology. The disclosed technology not only supports programming upgrades and adapts to subsequent protocol upgrades, but also meets the same low-latency processing performance required of solid-state drives.

[0027] The ZNS protocol for solid-state drives can be implemented using software technology. In this implementation, the PCIe protocol can be implemented using hardware and analog and digital intellectual property (IP) solutions during processing. The NVMe protocol is implemented entirely through software processed by the central processing unit (CPU). After processing by the PCIe module, the data is sent directly to the CPU. The CPU completes NVMe protocol processing, which includes submission queue (SQ) scheduling, submission queue entry (SQE) acquisition, physical (memory) region page (Physical Region Page, PRP) / scatter gather list (SGL) acquisition, direct memory access (DMA), ZNS extension protocol, completion queue (CQ) information upload and interrupts, etc. This solution provides the flexibility to adapt to changes in the ZNS and NVMe protocols because the protocols are executed by software, which facilitates future expansion. However, since the CPU's processing efficiency is not as high as that of hardware, it is difficult to strike a good balance between performance, latency, and power consumption.

[0028] In some cases, the ZNS protocol for solid-state drives can be implemented through hardware solutions. Similar to software implementations, the PCIe protocol can be implemented through hardware in the processing process and analog and digital intellectual property (IP) solutions. The NVMe protocol and the ZNS protocol are also implemented through dedicated hardware. This solution can achieve good performance and reduce latency and power consumption. However, because the ZNS protocol has not yet been standardized, it may need to be continuously modified. Fixed hardware cannot be upgraded accordingly, so traditional solid-state drives may not be able to benefit from the latest improvements.

[0029] The technology disclosed herein provides a balanced solution for implementing the ZNS protocol and other protocols in a solid-state drive. In some embodiments, the technology provides a zoned namespace solid-state drive (ZNS SSD) controller implemented in a combination of software and hardware to balance performance, latency, and power consumption. In some embodiments, the NVMe protocol is implemented in hardware, while the ZNS protocol is handled in software and executed by a processor (e.g., an embedded processor in the solid-state drive controller).

[0030] First reference Figure 1 . Figure 1A block diagram of a system 100 according to an exemplary embodiment is shown. For example, the system can be any computer system, such as a tower server, a server platform, a server, a desktop computer, a portable computer, a notebook computer, a tablet computer, a smartphone, etc. System 100 includes a host 102 and a solid-state drive 104. The host includes one or more microprocessors and one or more host buffers / memories. Solid-state drive 104 includes a solid-state drive controller 106 and a NAND memory 108. Solid-state drive controller 106 includes an interface 110, a non-volatile memory controller 112 coupled to interface 110, and a processor 114 coupled to non-volatile memory controller 112. The non-volatile memory controller 112 includes multiple functional modules, such as a submission queue (SQ) module 120, a submission queue entry (SQE) module 122, a physical (memory) region page (PRP) / scatter gather list (SGL) module 124, a direct memory access (DMA) module 126, a completion queue (CQ) / completion queue entry (CQE) module 128, and a merge module 130.

[0031] In some embodiments, interface 110 is implemented in accordance with the PCIe protocol and includes hardware for handling analog transmissions and digital protocols. In some embodiments, non-volatile memory controller 112 is implemented in accordance with the NVMe protocol. Processor 114 is an embedded CPU configured to perform various computing tasks for solid-state drive controller 106, including, for example, executing software instructions for the ZNS protocol.

[0032] In some embodiments, the SQ module 120 is configured to process SQ-related configuration registers and SQ scheduling modules in the NVMe protocol. The SQE module 122 is configured to obtain SQE-related information from the host 102. The PRP / SGL module 124 is configured to process protocol requirements in the NVMe protocol, such as the PRP / SGL linked list. The DMA module 126 is configured to handle transfer tasks, such as obtaining data from the host 102. The CQ / CQE module 128 is configured to process CQ queues for the NVMe protocol and related protocols and send interrupts to the host 102. The merge module 130 is configured to process hardware module commands and CPU commands to merge modules and feedback status to the CQ / CQE module 128.

[0033] Now refer to Figure 2 . Figure 2 1 is a flow chart showing a method 200 for processing a write command in a solid-state drive according to an exemplary embodiment. The solid-state drive includes a NAND memory and a solid-state drive controller. The method 200 may be performed by a solid-state drive controller (e.g., Figure 1 In step 202, the solid-state drive controller receives a write command from the host via an interface. The solid-state drive controller operates the interface according to the PCIe protocol. In some embodiments, under applicable protocols (e.g., PCIe protocol and NVMe protocol), the write command is initiated through a doorbell message. In step 204, the solid-state drive controller processes the write command. For example, the SQ module (e.g., Figure 1 The SQ module 120 in the solid-state drive controller receives the doorbell message and determines the SQ identifier for obtaining the SQE content by sending a request for the SQE content to the host. In step 206, once the SQE module of the solid-state drive controller (e.g., Figure 1 The SQE module 122 in the solid-state drive controller receives the SQE content from the host, and the SQE module of the solid-state drive controller sends a system message including the SQE content to the processor of the solid-state drive controller (for example, Figure 1 In step 208, the processor of the solid-state drive controller processes the system message according to the ZNS protocol.

[0034] In step 210, the solid-state drive controller obtains host data for storage from the host in parallel with the operations of steps 206 and 208. For example, the SQE module of the solid-state drive controller transfers the SQE content to the DMA module of the solid-state drive controller (e.g., Figure 1 In some implementations, the DMA module of the solid-state drive controller calls the PRP / SGL module (e.g., Figure 1 The SSD controller uses the PRP / SGL module 124 in the host to perform address resolution for the data to be stored. The result of the address resolution is then returned to the DMA module so that the DMA module can obtain the data from the host. In step 212, the SSD controller writes the data for storage obtained from the host into the NAND memory based on the processing result of step 208.

[0035] In the technology disclosed herein, the processing related to the ZNS protocol performed by the processor and the acquisition of data for storage from the host are performed in parallel. These technologies reduce the waiting time for storing data in the NAND memory, thereby improving the write efficiency of the solid-state drive. In addition, more mature protocols (such as the PCIe protocol and the NVMe protocol) are implemented through hardware, providing robustness in write operations. Less mature protocols (such as the ZNS protocol) are implemented through software executed by the processor. Because updates to the ZNS protocol can be easily implemented through software updates, the solid-state drive system can be modified through software updates to adapt to the latest protocols that benefit from technological improvements.

[0036] Figure 3 A ladder diagram is shown of a method 300 for processing a write command in a solid-state drive system / device including a host and a solid-state drive according to an exemplary embodiment. The solid-state drive includes a NAND memory and a solid-state drive controller. The method 300 may be used, for example, in Figure 1 The SQE module of the solid-state drive controller is executed in a solid-state drive system. In step 302, the host sends a write command to the SQ module of the solid-state drive controller via the PCIe interface. The write command can be a doorbell message. In step 303, the SQ module determines an SQ identifier for obtaining SQE content according to an applicable protocol (e.g., the NVMe protocol). In step 304, the SQ module sends a request for SQE content to the host via the PCIe interface. In step 306, the host obtains the SQE content based on the request. In step 308, the host sends the SQE content to the SQE module of the solid-state drive controller. In step 310, the SQE module reads the SQE content and sends a system message including the SQE content to the processor. In addition, in step 312, the SQE module sends the SQE content to the DMA module so that the DMA module can obtain host data for storage from the host. In some embodiments, the SQE module may send the SQE content to the processor before, after, or at the same time as it sends the SQE content to the DMA module to initiate parallel processing between the processor and the DMA module. In step 314, the DMA module sends a PRP / SGL message to the PRP / SGL module so that the PRP / SGL module performs address resolution to obtain host data for storage. In step 316, the PRP / SGL module performs address resolution for the host to identify the address of the host data for storage. In step 318, the host obtains the address of the host data in the host buffer. In step 320, the host returns the address of the host data in the host buffer to the PRP / SGL module. In step 322, the PRP / SGL module returns the address of the host data to the DMA module so that the DMA module can obtain the host data.

[0037] In step 326, the DMA module initiates a request for the host data based on the address of the host data. In step 328, the host retrieves the host data based on the address of the host data. In step 330, the host sends the host data to the DMA module, which then transfers the host data to the merge module.

[0038] At the same time, in step 324, the processor sends the processing result of the system message to the merge module according to a protocol (e.g., the ZNS protocol). In step 332, in response to receiving the processing result of the system message from the processor and receiving the host data from the DMA module, the merge module sends a CQ message to the CQ module. In step 334, in response to receiving the CQ message, the CQ module sends a CQE message to the host via the PCIe interface, indicating the completion of the write command. The host records the CQE message in its buffer. In step 336, the merge module writes the host data to the NAND memory based on the processing result of the system message.

[0039] In the technology disclosed herein, the operation of step 324 is performed in parallel with the operations of steps 314, 316, 318, 320, 322, 326, 328, and 330. Once the results from these operations are received in the merge module, the solid-state drive controller can indicate to the host that the write command has been completed and is ready to receive the next command. Because parallel processing is employed in the system, efficient write operations are provided according to emerging protocols (e.g., ZNS protocol), where the emerging protocols are implemented by software and executed by the processor, and mature protocols (e.g., PCIe protocol and NVMe protocol) are implemented by hardware and / or firmware. These technologies provide the solid-state drive system with the flexibility to adapt to the latest protocol updates of emerging protocols without changing its hardware structure.

[0040] Figure 4 A ladder diagram is shown of a method 400 for processing system commands in a solid-state drive system / device including a host and a solid-state drive according to an exemplary embodiment. The solid-state drive includes a NAND memory and a solid-state drive controller. The method 400 may be performed in, for example, Figure 1The host executes a command in a solid-state drive system. In step 402, the host sends a doorbell message to the SQ module of the solid-state drive controller via the PCIe interface. The doorbell message notifies the solid-state drive controller that a command is ready for execution by the solid-state drive controller. In step 403, the SQ module determines an SQ identifier for retrieving SQE content based on an applicable protocol (e.g., the NVMe protocol). In step 404, the SQ module sends a request for SQE content to the host via the PCIe interface. In step 406, the host retrieves the SQE content based on the request. In step 408, the host sends the SQE content to the SQE module of the solid-state drive controller. In step 410, the SQE module reads the SQE content and sends a system message including the SQE content to the processor. In step 412, the processor sends the result of processing the system message to the merge module based on a protocol (e.g., the ZNS protocol). In step 414, the merge module determines that the result of processing the system message indicates a system command for managing the solid-state drive and sends a CQ message to the CQ module. In response to receiving the CQ message, the CQ module sends a CQE message to the host via the PCIe interface, indicating the completion of the system command. The host records the CQE message in its buffer. In the illustrated embodiment, when the ZNS protocol is not implemented by a hardware structure designed for the ZNS protocol, commands related to the ZNS protocol are processed by the processor.

[0041] Figure 5 A ladder diagram is shown of a method 500 for processing a read command in a solid-state drive system / device including a host and a solid-state drive according to an exemplary embodiment. The solid-state drive includes a NAND memory and a solid-state drive controller. The method 500 may be performed in, for example, Figure 1 The SQE module of the solid-state drive controller is executed in a solid-state drive system. In step 502, the host sends a doorbell message to the SQ module of the solid-state drive controller via the PCIe interface. The doorbell message notifies the solid-state drive controller that the command is ready for execution by the solid-state drive controller. In step 503, the SQ module determines the SQ identifier for obtaining the SQE content according to the applicable protocol (e.g., the NVMe protocol). In step 504, the SQ module sends a request for the SQE content to the host via the PCIe interface. In step 506, the host obtains the SQE content based on the request. In step 508, the host sends the SQE content to the SQE module of the solid-state drive controller. In step 510, the SQE module reads the SQE content and sends a system message including the SQE content to the processor. In step 511, the processor processes the system message according to the ZNS protocol to obtain a read command and returns the read command to the SQE module.

[0042] In step 512, the SQE module sends a read command to the DMA module. In step 514, based on the read command indicating the data to be read, the DMA module sends a PRP / SGL message to the PRP / SGL module, which performs host-specific address resolution to obtain the host's memory address for storing the data. In step 516, the PRP / SGL module performs host-specific address resolution to obtain the host's memory address. In step 518, the host retrieves the address from the host buffer. In step 520, the host returns the address from the host buffer to the PRP / SGL module. In step 522, the PRP / SGL module retrieves the host's memory address, saves it to local memory, and returns the local memory address to the DMA module.

[0043] In step 526, the DMA module combines the local memory address of the PRP / SGL module and the SQE key information included in the read command and sends it to the merge module. In step 528, the merge module locally stores the read command and sends the SQE key information to the processor. In step 530, the processor sends a read command to the NAND memory to retrieve the data to be read. In step 532, the NAND memory returns the data to the DMA module. In response to receiving the data, in step 534, the DMA module forwards the data to the host and, in step 536, reports the receipt to the merge module.

[0044] In step 540, in response to receiving the report from the DMA module, the merge module sends a CQ message to the CQ module. In step 542, in response to receiving the CQ message, the CQ module sends a CQE message to the host via the PCIe interface indicating the completion of the read command. The host records the CQE message in its buffer.

[0045] The technologies disclosed herein provide a solid-state drive system for parallel processing. The solid-state drive system provides efficient write operations based on emerging protocols (e.g., the ZNS protocol), where the emerging protocols are implemented in software and executed by a processor, and established protocols (e.g., the PCIe protocol and the NVMe protocol) are implemented in hardware and / or firmware. These technologies provide the solid-state drive system with the flexibility to adapt to the latest protocol updates of emerging protocols without changing its hardware structure.

[0046] The above description of the present disclosure is provided for the purpose of illustration and description. The above description is not intended to be exhaustive or to limit the present disclosure to the precise form disclosed. The breadth and scope of the present disclosure should not be limited by any of the above-mentioned exemplary embodiments. Many modifications and variations will be apparent to those skilled in the art. These modifications and variations include any relevant combination of the disclosed features. The embodiments are selected and described in order to best explain the principles of the present disclosure and its practical application, so that other persons skilled in the art can understand the various embodiments of the present disclosure and the various modifications suitable for the intended specific use. The scope of the present disclosure is defined by the above-mentioned claims and their equivalents.

Claims

1. A solid-state drive comprising: NAND memory; as well as a solid-state drive controller coupled to the NAND memory, wherein the solid-state drive controller comprises: Interface, coupled with the host; a nonvolatile memory controller coupled to the interface; and a processor coupled to the non-volatile memory controller; wherein the solid state drive controller is configured to: receiving a write command from the host via the interface; processing the write command by the non-volatile memory controller; transmitting a system message from the nonvolatile memory controller to the processor; Processing the system message according to a partition namespace protocol by the processor; Retrieving, by the nonvolatile memory controller, host data for storage from the host via the interface; and Writing the host data into the NAND memory based on a result of processing the system message; wherein, processing the system message according to the partition namespace protocol by the processor and obtaining the host data from the host by the non-volatile memory controller are executed in parallel; The solid-state drive controller is also configured to operate the non-volatile memory controller according to a non-volatile high-speed transmission bus protocol; the non-volatile high-speed transmission bus protocol is implemented by hardware; the partition namespace protocol is implemented by software executed by the processor to implement updates to the partition namespace protocol.

2. The solid-state drive according to claim 1, wherein The interface operates according to the Peripheral Component Interconnect Express protocol.

3. The solid-state drive according to claim 1, wherein The non-volatile memory controller includes a submission queue module configured to determine a submission queue identifier and initiate an operation to obtain submission queue entry contents by sending a request for the submission queue entry contents to the host.

4. The solid-state drive according to claim 3, wherein The nonvolatile memory controller includes a submission queue entry module, and the nonvolatile memory controller receives the submission queue entry content to the submission queue entry module, wherein the system message transmitted from the nonvolatile memory controller to the processor includes the submission queue entry content.

5. The solid-state drive according to claim 4, wherein The nonvolatile memory controller includes a completion queue module and a merge module, wherein the merge module is configured to send a completion queue message to the completion queue module after receiving a processing result of the system message from the processor and receiving the host data from the host.

6. The solid-state drive according to claim 5, wherein The completion queue module is configured to send a completion queue entry message indicating completion of the write command to the host in response to receiving the completion queue message from the merge module.

7. The solid-state drive according to claim 1, wherein The write command is a doorbell message.

8. A computer device comprising a host and a solid-state drive, wherein: The solid-state drive comprises: NAND memory; and a solid-state drive controller coupled to the NAND memory, wherein the solid-state drive controller comprises: Interface, coupled with the host; a nonvolatile memory controller coupled to the interface; and a processor coupled to the non-volatile memory controller; wherein the solid state drive controller is configured to: receiving a write command from the host via the interface; processing the write command by the non-volatile memory controller; transmitting a system message from the nonvolatile memory controller to the processor; Processing the system message according to a partition namespace protocol by the processor; Retrieving, by the nonvolatile memory controller, host data for storage from the host via the interface; and Writing the host data into the NAND memory based on a result of processing the system message; wherein, processing the system message according to the partition namespace protocol by the processor and obtaining the host data from the host by the non-volatile memory controller are executed in parallel; The solid-state drive controller is also configured to operate the non-volatile memory controller according to a non-volatile high-speed transmission bus protocol; the non-volatile high-speed transmission bus protocol is implemented by hardware; the partition namespace protocol is implemented by software executed by the processor to implement updates to the partition namespace protocol.

9. The apparatus according to claim 8, wherein The interface operates according to the Peripheral Component Interconnect Express protocol.

10. The apparatus according to claim 8, wherein The non-volatile memory controller includes a submission queue module configured to determine a submission queue identifier and initiate an operation to obtain submission queue entry contents by sending a request for the submission queue entry contents to the host.

11. The apparatus according to claim 10, wherein The nonvolatile memory controller includes a submission queue entry module, and the nonvolatile memory controller receives the submission queue entry content to the submission queue entry module, wherein the system message transmitted from the nonvolatile memory controller to the processor includes the submission queue entry content.

12. The apparatus according to claim 11, wherein The nonvolatile memory controller includes a completion queue module and a merge module, wherein the merge module is configured to send a completion queue message to the completion queue module after receiving a processing result of the system message from the processor and receiving the host data from the host.

13. The apparatus according to claim 12, wherein The completion queue module is configured to send a completion queue entry message indicating completion of the write command to the host in response to receiving the completion queue message from the merge module.

14. The apparatus according to claim 8, wherein The write command is a doorbell message.

15. A method for operating a solid-state drive, the solid-state drive comprising a NAND memory and a solid-state drive controller coupled to the NAND memory, wherein the solid-state drive controller comprises an interface coupled to a host, a non-volatile memory controller coupled to the interface, and a processor coupled to the non-volatile memory controller, the operating method comprising: receiving a write command from the host via the interface; processing the write command by the non-volatile memory controller; transmitting a system message from the nonvolatile memory controller to the processor; Processing the system message according to a partition namespace protocol by the processor; obtaining, by the nonvolatile memory controller, host data for storage from the host via the interface; as well as writing the host data into the NAND memory based on a result of processing the system message by the solid-state drive controller; wherein, processing the system message according to the partition namespace protocol by the processor and obtaining the host data from the host by the non-volatile memory controller are executed in parallel; The solid-state drive controller is also configured to operate the non-volatile memory controller according to a non-volatile high-speed transmission bus protocol; the non-volatile high-speed transmission bus protocol is implemented by hardware; the partition namespace protocol is implemented by software executed by the processor to implement updates to the partition namespace protocol.

16. The operating method according to claim 15, wherein: The interface operates according to the Peripheral Component Interconnect Express protocol.

17. The operating method according to claim 15, wherein: The non-volatile memory controller includes a submission queue module configured to determine a submission queue identifier and initiate an operation to obtain submission queue entry contents by sending a request for the submission queue entry contents to the host.

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