Data storage method, device, electronic device and storage medium

Abstract

The present invention discloses a data storage method, device, electronic device and storage medium. The method is applied to a chip, wherein the chip includes at least two operation cores, wherein at least two operation cores include an access core, and the method includes: for each operation core, when it is detected that the current operation core generates data to be stored, determining the core type of the current operation core; the core type includes an external access type or an internal access type; according to the core type, determining a target storage mode corresponding to the data to be stored; based on the target storage mode, storing the data to be stored in a corresponding target storage location, wherein the target storage location is independent of the chip. The method solves the problem of access conflicts when multiple operation cores access the storage chip at the same time in the prior art, realizes avoiding the problem of access conflicts when multiple operation cores access the storage chip at the same time, improves the speed and convenience of data storage, and achieves the effect of improving data storage efficiency.

Description

Technical Field

[0001] The present invention relates to the field of computer processing technology, and in particular to a data storage method, device, electronic equipment and storage medium. Background Art

[0002] As the vehicle EE (Electronic Engineering) architecture evolves from distributed to centralized, heterogeneous multi-core chips have become the main computing unit in the domain controller. In automotive heterogeneous multi-core chips, it is generally necessary to store the NVM (Non-volatile Memory) data of each computing core in the chip.

[0003] The existing storage method usually provides a storage chip for each computing core, and each computing core stores the NVM data generated by itself in the storage chip. However, this method has the risk of access conflict when multiple computing cores access the storage chip at the same time, resulting in low data storage efficiency. Summary of the invention

[0004] The present invention provides a data storage method, device, electronic device and storage medium to avoid the problem of access conflict when multiple computing cores access a storage chip at the same time, improve the speed and convenience of data storage, and achieve the technical effect of improving data storage efficiency.

[0005] According to one aspect of the present invention, a data storage method is provided, which is applied to a chip, wherein the chip includes at least two computing cores, wherein the at least two computing cores include an access core, and the method includes:

[0006] For each computing core, when it is detected that the current computing core generates data to be stored, determining the core type of the current computing core; wherein the core type includes an external access type or an internal access type;

[0007] Determining, according to the core type, a target storage mode corresponding to the data to be stored;

[0008] Based on the target storage mode, the data to be stored is stored in a corresponding target storage location, wherein the target storage location is independent of the chip.

[0009] According to another aspect of the present invention, there is provided a data storage device, which is configured in a chip, wherein the chip includes at least two computing cores, wherein the at least two computing cores include an access core, and the device includes:

[0010] A core type determination module, for each operation core, when detecting that the current operation core generates data to be stored, determines the core type of the current operation core; wherein the core type includes an external access type or an internal access type;

[0011] a target storage mode determination module, used to determine a target storage mode corresponding to the data to be stored according to the core type;

[0012] A data storage module is used to store the data to be stored in a corresponding target storage location based on the target storage method, wherein the target storage location is independent of the chip.

[0013] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0014] at least one processor; and

[0015] a memory communicatively connected to the at least one processor; wherein,

[0016] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the data storage method described in any embodiment of the present invention.

[0017] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the data storage method described in any embodiment of the present invention when executed.

[0018] The technical solution of the embodiment of the present invention is to determine the core type of the current operation core for each operation core in the chip when it is detected that the current operation core generates data to be stored; the core type includes an external access type or an internal access type; according to the core type, determine the target storage mode corresponding to the data to be stored; based on the target storage mode, store the data to be stored in the corresponding target storage location, wherein the target storage location is independent of the chip, thereby solving the problem of access conflict when multiple operation cores simultaneously access the storage chip in the prior art, and realizing whether the operation core can directly communicate with the outside or not communicate with the outside based on the core type of the current operation core, distinguishing the core type of each operation core, and selecting different target storage modes based on different core types, thereby avoiding the problem of access conflict when multiple operation cores simultaneously access the storage chip, and then storing the data to be stored in the corresponding target storage location, thereby improving the speed and convenience of data storage and achieving the technical effect of improving data storage efficiency.

[0019] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 is a flow chart of a data storage method provided according to Embodiment 1 of the present invention;

[0022] Figure 2 is a schematic diagram of the structure of a data storage device provided according to Embodiment 2 of the present invention;

[0023] Figure 3 is a schematic diagram of the structure of a data storage device provided according to Embodiment 3 of the present invention;

[0024] Figure 4 It is a schematic diagram of the structure of an electronic device for implementing the data storage method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0027] Embodiment 1

[0028] Figure 1 This is a flowchart of a data storage method provided according to Embodiment 1 of the present invention. This embodiment is applicable to data storage situations. The method can be executed by a data storage device. The data storage device can be implemented in the form of hardware and / or software. The data storage device can be configured in a chip.

[0029] It should be noted that the technical solution adopted in the embodiment of the present invention can be applied to a chip, and the chip contains at least two computing cores, and the computing core refers to the core of the chip. The computing core can be R5F, A core, R core, etc., and different application software (such as vehicle control applications) can be run on each computing core and process corresponding tasks. One computing core in each computing core can be an access core, and the access core can be used as the only interface for communicating with the target storage location to transmit data to the target storage location through the access core, thereby avoiding the problem of access conflicts caused by multiple computing cores accessing the target storage location at the same time. Among them, the target storage location refers to an external storage unit shared by each computing core, which is used to store the NVM data corresponding to each computing core. NVM data is also called memory data.

[0030] like Figure 1 As shown, the method includes:

[0031] S110 . For each computing core, when it is detected that the current computing core generates data to be stored, determine the core type of the current computing core.

[0032] Among them, the operation core refers to the core in the chip, and the chip can be a multi-core heterogeneous SOC (System on Chip). The operation core can be used to perform logical calculations, receive / store commands, process data, etc. The data to be stored refers to the data that needs to be stored. The core type includes an external access type or an internal access type. The external access type can be used to characterize the operation core as a type that can communicate with the external memory of the chip. The internal access type can be used to characterize the type that the operation core cannot communicate with the external memory of the chip. It should be noted that the method for determining the core type of each operation core is the same, and any of the operation cores is used as the current operation core for explanation.

[0033] It should be noted that in the chip, the access core is the only interface for communicating with the target storage location, that is, the access core can communicate with the external memory of the chip, and accordingly, the access core is of external access type. In practical applications, it is possible to pre-set which specific operation core in the chip is the access core and mark it, such as marking it as access core A. In this way, when determining the core type of the current operation core, if the current operation core is access core A, then the core type of the current operation core can be considered to be an external access type. If the current operation core is not access core A, then the core type of the current operation core can be considered to be an internal access type.

[0034] In this embodiment, the corresponding application program can be run based on the computing core and the corresponding task can be processed. In the process of processing the task, the computing core will generate some result data, such as self-learning results, error codes, obstacle codes, etc. These result data can be used as data to be stored. At this time, it is considered that the current computing core has been detected to generate data to be stored. Before storing the data to be stored, the core identification of the current computing core can be analyzed. If the core identification is consistent with the preset access core identification, then its core type is an external access type. If not, then the core type is an internal access type.

[0035] It should be noted that in order to prevent the redundancy of data storage, the preset data type that needs to be stored can be pre-configured, so that when it is detected that the current operation core generates result data, the data type of the result data can be compared with the preset data type to determine whether the result data is the data to be stored that needs to be stored. If so, the result data can be used as the data to be stored to store the data to be stored in an external storage unit. Among them, the preset data type can be self-learning results, obstacle information, etc. Specifically, in actual applications, it can be determined whether the data type of the result data generated by the current operation core is consistent with the preset data type. If they are consistent, the result data is considered to be the data to be stored that needs to be stored. If they are inconsistent, it is considered that the result data does not need to be stored and can be not processed. By determining the final data to be stored by judging the result data, the accuracy of data storage is improved.

[0036] It should also be noted that each computing core in the chip can run different applications (i.e., application software), and the chip can temporarily store data. After the chip is powered off, the data in the chip will be cleared. Before using the computing core to run the application, the computing core needs to read the application. The application is stored in the non-volatile memory. Every time the chip is powered on, the application can be read from the non-volatile memory based on the access core, and the application corresponding to each computing core is given to the corresponding computing core, avoiding the problem of access conflicts caused by multiple computing cores accessing the non-volatile memory at the same time, thereby improving data processing efficiency.

[0037] In this embodiment, when it is detected that the current computing core generates data to be stored, before determining the core type of the current computing core, it also includes: responding to a power-on signal; controlling the access core to read the program data corresponding to each computing core in the target storage location; writing each program data into the temporary cache corresponding to the corresponding computing core based on the access core, so that the computing core reads the corresponding program data from the corresponding temporary cache, and performs data processing according to the read program data.

[0038] Among them, the power-on signal may refer to the electrical signal generated when the chip obtains power and starts to run. The target storage location is independent of the chip, and the target storage location may be a non-volatile memory for persistent storage of data, for example, it may be ROM or NorFlash. The program data may include program code, parameter variables, etc., and the functions of the application software may be executed based on the program data. The temporary cache is built into the chip. The temporary cache may refer to a storage unit for temporarily storing data, such as RAM (Random Access Memory).

[0039] It should be noted that in the chip, all computing cores except the access core have a corresponding temporary cache to temporarily store the data to be stored in the temporary cache, and interact with the outside world with the help of the access core. For example, the access core can read the data in the temporary cache and write the data to the target cache location; the access core can also read the data in the target cache location and write the data to the temporary cache.

[0040] In this embodiment, in response to a power-on signal, the access core can be controlled to read the program data corresponding to each operation core from the target storage location. Further, if the core type of the operation core is an internal access type, then the access core can be controlled to write the program data of the operation core into a temporary cache corresponding to the operation core, and accordingly, the access core can write the program data of each operation core of the internal access type into the corresponding temporary cache, and the subsequent operation core can read the corresponding program data from the corresponding temporary cache, and perform data processing based on the read program data. If the core type of the operation core is an external access type, then the operation core is an access core, and the access core can read the program data corresponding to itself and perform data processing based on the program data. The subsequent operation core may generate data to be stored in the process of data processing based on the program data, and the data to be stored can be stored in the target cache location.

[0041] S120. Determine, according to the core type, a target storage mode corresponding to the data to be stored.

[0042] The target storage method may refer to a method for storing data.

[0043] It should be noted that, in actual applications, each computing core in the chip stores data by sharing the same external storage unit (i.e., the target storage location). There is a risk of access conflict when multiple computing cores access the target storage location at the same time. In order to avoid this risk, different storage methods can be assigned to the data of the computing core based on the core type of the computing core. For example, the access core can communicate directly with the external cache unit of the chip, so the data to be stored corresponding to the access core can be directly written into the external cache unit; or, other computing cores other than the access core can be transmitted to the access core, and the access core writes the data into the external cache unit, and indirect writing is achieved by using the access core as the middleware, thereby avoiding the situation where multiple computing cores access the target storage location at the same time and there is an access conflict. Optionally, according to the core type, the target storage method corresponding to the data to be stored is determined, including: if the core type is an external access type, the target storage method is determined to be a direct storage method; if the core type is an internal access type, the target storage method is determined to be an indirect storage method.

[0044] Specifically, if the core type is an external access type, it can be said that the computing core is an access core, which has the function of exchanging data with the target storage location, and can be stored based on the direct storage method. If the core type is an internal access type, it is considered that the corresponding computing core does not have the function of exchanging data with the target storage location, that is, the computing core cannot directly write the data to be stored to the target storage location, and can be stored based on the indirect storage method.

[0045] S130. Based on the target storage method, store the data to be stored in a corresponding target storage location.

[0046] In order to store the NVM data generated by each computing core in the chip to the target cache location and avoid the problem of conflict in accessing the target cache location. Optionally, if the target storage method is a direct storage method, the implementation method of storing the data to be stored in the corresponding target storage location based on the target storage method can be: writing the data to be stored to the target storage location based on the access core.

[0047] Specifically, if the core type is an external access type, the corresponding operation core is an access core, and the access core communicates with the target storage location. Accordingly, the access core can directly write its corresponding data to be stored into the target storage location.

[0048] In this embodiment, if the target storage method is an indirect storage method, the implementation method of storing the data to be stored in the corresponding target storage location based on the target storage method can be: writing the data to be stored into a temporary cache corresponding to the current computing core; reading the updated storage data in the temporary cache based on the access core, and writing the updated storage data to the target storage location.

[0049] The updated storage data corresponds to the data to be stored.

[0050] Specifically, if the core type of the current computing core is an internal access type, then the current computing core is not an access core, and the current computing core does not communicate with the target storage location. At this time, the current computing core can write its corresponding data to be stored into the corresponding temporary cache. Furthermore, the access core can read the updated storage data in the temporary cache periodically or read the updated storage data in the temporary cache, and write the updated storage data to the target storage location. For example, the access core can access each temporary cache at preset time intervals, and read the storage data in each temporary cache within the time period as updated storage data, and write it to the target storage location.

[0051] In this embodiment, the implementation method of storing the data to be stored in the corresponding target storage location based on the target storage method can also be: sending the data to be stored to the access core according to the communication interface; based on the access core receiving the data to be stored, writing the data to be stored to the target storage location.

[0052] Specifically, inter-core communication can be established between the access core and other computing cores in the chip. When the current computing core generates data to be stored, the current computing core can use the communication interface to send the data to be stored to the access core. When the access core receives the data to be stored, the access core can write the data to be stored to the target storage location.

[0053] In this embodiment, the implementation method of storing the data to be stored in the corresponding target storage location based on the target storage method can also be: before the chip is powered off each time, the access core is controlled to read the updated storage data in each temporary cache; based on the access core, the updated storage data is written to the target cache.

[0054] In order to improve the effectiveness of data storage and ensure the accuracy of data storage, the data to be stored can be marked before storing the data in the corresponding target storage location based on the access core to obtain the processed data to be stored, so that the processed data to be stored can be stored in the corresponding target storage location.

[0055] The processed data to be stored includes at least one of a data identifier, a core identifier, a data length, a storage attribute, and a checksum. The data identifier can be used to characterize the uniqueness of the data. The core identifier can be the ID of the core. The data length refers to the length of the data to be stored. The storage attribute can refer to the type of storage, such as power-down storage, immediate storage, or periodic storage. The checksum refers to the sum of the data to be stored.

[0056] Specifically, the data to be stored can be packaged in a certain format, and specific information can be marked for the data to be stored, such as CoreID, BlockID, storage attributes, data length, checksum, etc. CorID represents the core identifier, BlockID represents the ID number of the data on the core to which it belongs, the storage attribute is whether the data is stored after power-off or immediately, the data length is the length of the data to be stored, and the checksum is the checksum of the stored data. Accordingly, the processed data to be stored can be obtained, and the processed data to be stored can be stored as a data packet in a temporary cache. In this way, during the operation of the chip, the access core runs a periodic detection task, periodically detects the storage data packet in the temporary cache, and determines whether to store the data packet immediately in the target storage location or store the data packet in the target storage location when the power is off according to the storage attributes in the data packet.

[0057] Before writing the storage data to the target storage location based on the access core, communication between the access core and the target storage location can also be established based on the peripheral interface, so that when the access core and the target storage location establish communication, the data is written to the target cache based on the access core. Wherein, the peripheral interface can be OSPI (Octal Serial Peripheral Interface).

[0058] The technical solution of this embodiment is as follows: for each computing core in the chip, when it is detected that the current computing core generates data to be stored, the core type of the current computing core is determined; the core type includes an external access type or an internal access type; according to the core type, a target storage method corresponding to the data to be stored is determined; based on the target storage method, the data to be stored is stored in a corresponding target storage location, wherein the target storage location is independent of the chip, thereby solving the problem of access conflict when multiple computing cores simultaneously access the storage chip in the prior art, and realizing the determination of whether the computing core can directly communicate with the outside or not based on the core type of the current computing core, distinguishing the core type of each computing core, and selecting different target storage methods based on the different core types, thereby avoiding the problem of access conflict when multiple computing cores simultaneously access the storage chip, and then storing the data to be stored in the corresponding target storage location, thereby improving the speed and convenience of data storage and achieving the technical effect of improving data storage efficiency.

[0059] Embodiment 2

[0060] As an alternative embodiment of the above embodiment, Figure 2 1 is a schematic diagram of the structure of a data storage device provided according to Embodiment 2 of the present invention. For details, please refer to the following specific contents.

[0061] The technical solution provided in the embodiment of the present invention can be applied to a chip, and the chip can include multiple computing cores. Figure 2As shown, illustratively, the chip can be a multi-core heterogeneous SOC, in which there are 3 heterogeneous cores, namely A-core, B-core, and C-core, each heterogeneous core is a computing core, and different application software can be run on each core. Among them, B-core is an access core, which is the only interface for communicating with external NorFlash. NorFlash is the target cache location, and NorFlash is used to store NVM data of multi-core heterogeneous chips. A-core and C-core can interact with B core through temporary cache or inter-core communication, and the temporary cache can be RAM. For example, every time the chip is powered on, B-core can read data from NorFlash and write the NVM data (including application programs) of A-core or C-core to the temporary cache corresponding to A-core or C-core. A-core and C-core access NVM data through corresponding temporary caches. During the operation of the SOC, if the A-core or C-core needs to update the NVM data, it can be directly updated in the temporary cache. It can write the NVM data to NorFlash according to the pre-defined NVM data identifier, or when the program is running, the B-core periodically accesses the temporary cache. Or when the power is off, the B-core writes the data to NorFlash.

[0062] Exemplarily, the chip may be TI TDA4VM (including MCU domain and Main domain, the operation core of MCU domain is R5F, the operation core of Main domain is A core and R core), and the vehicle control application program runs on different operation cores. During the program running process or when the power is off, there is usually a need to store NVM data, such as storing fault codes detected during the program running process, self-learning results and other NVM data. The NVM data can be packaged in a certain format to generate an NVM data packet. The format includes CoreID, BlockID, storage attributes, data length, and checksum. CorID represents the ID of the core, BlockID is the ID number of the NVM data on the core to which it belongs, the storage attribute is whether the NVM data is stored after power-off or immediately, the data length is the length of the NVM data to be stored, and the checksum is the checksum of the NVM data. During the operation of the chip, the access core runs a periodic detection task, periodically detects the NVM data packet in the temporary cache, and according to the storage attributes in the data packet, either stores the data packet immediately in NorFlash or stores the data packet in NorFlash when the power is off.

[0063] This technical solution transmits the NVM data generated by the application software on multiple heterogeneous cores to one of the cores (i.e., the access core) through temporary caching or communication between cores. The access core is used as the only interface for communicating with the external NorFlash, so that multiple heterogeneous computing cores share the same external NorFlash / or internal NorFlash for NVM data storage, avoiding conflicts caused by multiple computing cores accessing the storage chip at the same time.

[0064] The technical solution of this embodiment is as follows: for each computing core in the chip, when it is detected that the current computing core generates data to be stored, the core type of the current computing core is determined; the core type includes an external access type or an internal access type; according to the core type, a target storage method corresponding to the data to be stored is determined; based on the target storage method, the data to be stored is stored in a corresponding target storage location, wherein the target storage location is independent of the chip, thereby solving the problem of access conflict when multiple computing cores simultaneously access the storage chip in the prior art, and realizing the determination of whether the computing core can directly communicate with the outside or not based on the core type of the current computing core, distinguishing the core type of each computing core, and selecting different target storage methods based on the different core types, thereby avoiding the problem of access conflict when multiple computing cores simultaneously access the storage chip, and then storing the data to be stored in the corresponding target storage location, thereby improving the speed and convenience of data storage and achieving the technical effect of improving data storage efficiency.

[0065] Embodiment 3

[0066] Figure 3 Schematic diagram of a data storage device according to Embodiment 3 of the present invention. Figure 3 As shown, the device includes: a core type determination module 310, a target storage mode determination module 320 and a data storage module 330.

[0067] Among them, the core type determination module 310 is used to determine the core type of the current operation core for each operation core when it is detected that the current operation core generates data to be stored; wherein the core type includes an external access type or an internal access type; the target storage method determination module 320 is used to determine the target storage method corresponding to the data to be stored according to the core type; the data storage module 330 is used to store the data to be stored in the corresponding target storage location based on the target storage method, wherein the target storage location is independent of the chip.

[0068] The technical solution of this embodiment is as follows: for each computing core in the chip, when it is detected that the current computing core generates data to be stored, the core type of the current computing core is determined; the core type includes an external access type or an internal access type; according to the core type, a target storage method corresponding to the data to be stored is determined; based on the target storage method, the data to be stored is stored in a corresponding target storage location, wherein the target storage location is independent of the chip, thereby solving the problem of access conflict when multiple computing cores simultaneously access the storage chip in the prior art, and realizing the determination of whether the computing core can directly communicate with the outside or not based on the core type of the current computing core, distinguishing the core type of each computing core, and selecting different target storage methods based on the different core types, thereby avoiding the problem of access conflict when multiple computing cores simultaneously access the storage chip, and then storing the data to be stored in the corresponding target storage location, thereby improving the speed and convenience of data storage and achieving the technical effect of improving data storage efficiency.

[0069] On the basis of the above-mentioned device, optionally, the target storage mode determination module 320 is further used to determine that the target storage mode is a direct storage mode if the core type is an external access type.

[0070] On the basis of the above device, optionally, if the target storage method is a direct storage method, the data storage module 330 is used to write the data to be stored into the target storage location based on the access core.

[0071] On the basis of the above-mentioned device, optionally, the target storage mode determination module 320 is further used to determine that the target storage mode is an indirect storage mode if the core type is an internal access type.

[0072] On the basis of the above device, optionally, if the target storage mode is an indirect storage mode, the data storage module 330 includes: a temporary cache writing unit and a data writing unit.

[0073] A temporary cache writing unit, used for writing the data to be stored into the temporary cache corresponding to the current computing core; wherein the temporary cache is built into the chip;

[0074] A data writing unit is used to read the updated storage data in the temporary cache based on the access core, and write the updated storage data into the target storage location.

[0075] On the basis of the above device, optionally, the data storage module 330 further includes: a data sending unit and a data storage unit.

[0076] A data sending unit, used for sending the data to be stored to the access core according to the communication interface;

[0077] A data storage unit is used to write the data to be stored into the target storage location based on the access core when receiving the data to be stored.

[0078] Based on the above-mentioned device, optionally, the data storage module 330 is also used to perform labeling processing on the data to be stored to obtain processed data to be stored, so that the processed data to be stored is stored in the corresponding target storage location; wherein, the processed data to be stored includes at least one of data identification, core identification, data length, storage attributes and checksum.

[0079] On the basis of the above device, optionally, the device further includes: a power-on signal response unit, a program data reading unit and a program data writing unit.

[0080] A power-on signal response unit, configured to respond to a power-on signal;

[0081] A program data reading unit, used to control the access core to read the program data corresponding to each computing core in the target storage location;

[0082] The program data writing unit is used to write each program data into the temporary cache corresponding to the corresponding operation core based on the access core, so that the operation core reads the corresponding program data from the corresponding temporary cache and performs data processing according to the read program data.

[0083] The data storage device provided in the embodiment of the present invention can execute the data storage method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0084] Embodiment 4

[0085] Figure 4 1 is a schematic diagram of the structure of an electronic device that implements the data storage method of an embodiment of the present invention. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0086] like Figure 4As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0087] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0088] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as a data storage method.

[0089] In some embodiments, the data storage method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the data storage method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the data storage method in any other appropriate manner (e.g., by means of firmware).

[0090] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0091] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0092] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0093] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0094] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0095] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0096] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0097] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A data storage method, characterized in that: Applied to a chip, the chip includes at least two computing cores, the at least two computing cores include an access core, and the method includes: For each computing core, when it is detected that the current computing core generates data to be stored, determining the core type of the current computing core; wherein the core type includes an external access type or an internal access type; Determining a target storage mode corresponding to the data to be stored according to the core type, including: if the core type is an external access type, determining the target storage mode to be a direct storage mode; if the core type is an internal access type, determining the target storage mode to be an indirect storage mode; Based on the target storage mode, storing the data to be stored in a corresponding target storage location, wherein the target storage location is independent of the chip; Wherein, if the target storage mode is a direct storage mode, storing the data to be stored in a corresponding target storage location based on the target storage mode includes: Writing the data to be stored into the target storage location based on the access core; Wherein, if the target storage mode is an indirect storage mode, storing the data to be stored in the corresponding target storage location based on the target storage mode includes: The data to be stored is indirectly written into the target storage location through the access core middleware.

2. The method according to claim 1, characterized in that The step of indirectly writing the data to be stored into the target storage location through the access core middleware includes: Writing the data to be stored into a temporary cache corresponding to the current computing core; wherein the temporary cache is built into the chip; The updated storage data in the temporary cache is read based on the access core, and the updated storage data is written into the target storage location.

3. The method according to claim 1, characterized in that The method of indirectly writing the data to be stored into the target storage location through the access core middleware further includes: Sending the data to be stored to the access core according to the communication interface; Based on the access core, when receiving the data to be stored, the data to be stored is written into the target storage location.

4. The method according to any one of claims 1, 2 or 3, characterized in that Before storing the data to be stored in the corresponding target storage location, the method further includes: Performing labeling processing on the data to be stored to obtain processed data to be stored, so that the processed data to be stored is stored in a corresponding target storage location; The processed data to be stored includes at least one of a data identifier, a core identifier, a data length, a storage attribute and a checksum.

5. The method according to claim 1, characterized in that The step of, before determining the core type of the current computing core when detecting that the current computing core generates data to be stored, further includes: responding to a power-on signal; Controlling the access core to read program data corresponding to each computing core in a target storage location; Based on the access core, each program data is written into a temporary cache corresponding to a corresponding operation core, so that the operation core reads the corresponding program data from the corresponding temporary cache and performs data processing according to the read program data.

6. A data storage device, characterized in that: The device is configured on a chip, wherein the chip includes at least two computing cores, wherein the at least two computing cores include an access core, and the device includes: A core type determination module, for each operation core, when detecting that the current operation core generates data to be stored, determines the core type of the current operation core; wherein the core type includes an external access type or an internal access type; a target storage mode determination module, used to determine a target storage mode corresponding to the data to be stored according to the core type; The target storage mode determination module is specifically used to determine that the target storage mode is a direct storage mode if the core type is an external access type, and to determine that the target storage mode is an indirect storage mode if the core type is an internal access type; A data storage module, used for storing the data to be stored in a corresponding target storage location based on the target storage mode, wherein the target storage location is independent of the chip; The data storage module is specifically used for: If the target storage mode is a direct storage mode, writing the data to be stored into the target storage location based on the access core; If the target storage mode is an indirect storage mode, the data to be stored is indirectly written into the target storage location through the access core middleware.

7. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the data storage method according to any one of claims 1 to 5.

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