An Adaptive Debugging System and Method for Server Platforms

Abstract

An adaptive debugging system and method for a server platform proposed by the present invention. The system includes: BMC, CPU, PHY chip, serial port mode switching module, I3C switch chip, and adaptive debugging interface; BMC is respectively connected to the CPU, PHY chip, serial port mode switching module, and I3C switch chip, the adaptive debugging interface is respectively connected to the PHY chip, serial port mode switching module, and I3C switch chip, and the I3C switch chip is connected to the CPU; a signal conversion module is provided in the BMC, and the signal conversion module is respectively connected to the CPU and the serial port mode switching module. The present invention can use the adaptive debugging interface to switch different serial ports, network ports, and I3C buses for debugging, which can not only save the board space resources, but also help the debugger reduce the debugging steps and quickly analyze the cause of the failure.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and more particularly to an adaptive debugging system and method for a server platform. Background Art

[0002] The PCH (Platform Controller Hub) is a platform controller on a server, also known as an integrated south bridge chip. It can be interconnected with the CPU through the DMI (Direct Media Interface) bus to complete the control between I / O buses, such as PCIe, USB, SATA, SPI, etc. However, with the rapid development of electronic technology, more and more CPUs have now integrated some functions of the PCH internally, and there is no longer a PCH on the server.

[0003] In the prior art, Figure 1 the shown debugging system with a PCH controller is generally used for debugging the server. The debugger can connect to the computer host through the USB interface of the PCH, and then cooperate with the software to send corresponding instructions to the PCH. After decoding by the PCH, the instructions are transmitted to the CPU through the DMI bus. Finally, the CPU will transmit the response signal along this link to the computer host, thus completing an interaction of debugging information. Instructions can also be sent through the network port of the BMC (Baseboard Management Controller), and the status information of the CPU can be read using the JTAG bus. In addition, the system working log can also be viewed using the serial port on the BMC, thereby helping the debugger analyze the cause of the fault.

[0004] However, the above-described debugging methods face two problems: First, when debugging using the serial port of the BMC, it usually requires the debugger to open the chassis, connect the serial port cable to the 3pin Header, and in a chassis with structural interference, some PCIe cards need to be removed to connect. The entire debugging process is very inconvenient to operate, and the network port and serial port will occupy the board space resources, bringing design difficulties to the R & D personnel. Second, although using the USB debugging interface of the PCH does not require opening the chassis, on a server platform without a PCH, this debugging method has become invalid. Summary of the Invention

[0005] Aiming at the above problems, the purpose of the present invention is to provide an adaptive debugging system and method for a server platform, which can use the adaptive debugging interface to switch different serial ports, network ports, and I3C buses for debugging, saving board space resources and helping the debugger reduce the debugging steps and quickly analyze the cause of the fault.

[0006] To achieve the above object, the present invention is realized through the following technical solutions: An adaptive debugging system for a server platform, comprising: BMC, CPU, PHY chip, serial port mode switching module, I3C switch chip, and adaptive debugging interface; BMC is respectively connected to the CPU, PHY chip, serial port mode switching module, and I3C switch chip, the adaptive debugging interface is respectively connected to the PHY chip, serial port mode switching module, and I3C switch chip, and the I3C switch chip is connected to the CPU; A signal conversion module is provided in the BMC, and the signal conversion module is respectively connected to the CPU and the serial port mode switching module.

[0007] Further, the CPU is used to transmit the self-check code of the system BIOS to the BMC through the eSPI bus, convert the eSPI signal into a UART1 serial port signal through the signal conversion module in the BMC and send it to the serial port mode switching module, and the serial port mode switching module is connected to the adaptive debugging interface through the USB interface.

[0008] Further, the BMC is connected to the serial port mode switching module through the UART2 serial port signal; the BMC is connected to the PHY chip through the RMII signal, and the PHY chip converts the RMII signal into an MDI signal and then sends it to the adaptive debugging interface; the BMC is connected to the CPU through the JTAG signal.

[0009] Further, the I3C switch chip is respectively connected to the CPU, BMC, and adaptive debugging interface through I3C signals; the adaptive adjustment interface sends an I3C control signal to the I3C switch chip through a signal control circuit.

[0010] Further, the adaptive debugging interface adopts a type-c interface, and the computer host is connected to the adaptive debugging interface through a type-c adapter cable for selecting the master-slave mode through a preset debugging software.

[0011] Further, the signal control circuit includes an AND gate chip, the CC1 pin and the CC2 pin of the adaptive debugging interface are respectively connected to the input ends of the AND gate chip, and the AND gate chip generates an I3C control signal according to the level signals of the CC1 pin and the CC2 pin and sends it to the I3C switch chip.

[0012] Further, the I3C switch chip adopts an IDTQS3VH257 chip, the B port of the I3C switch chip is connected to the CPU through an I3C signal, the S port of the I3C switch chip is connected to the output end of the AND gate chip through an I3C control signal, the A1 port of the I3C switch chip is connected to the BMC through an I3C signal, and the A2 port of the I3C switch chip is connected to the adaptive debugging interface through an I3C signal.

[0013] Further, the UART1 serial port signal is used to transmit the self - test code of the system BIOS, and the UART2 serial port signal is used to transmit the log of the BMC;

[0014] Further, the PHY chip uses the RTL8211 chip, and the serial port mode switching module uses the CP2105 chip.

[0015] Correspondingly, the present invention also discloses an adaptive debugging method for a server platform, including: connecting a computer host to an adaptive debugging interface using an adapter cable, and setting the CPU as a slave and setting the BMC or the computer host as a master through a preset debugging software built in the computer host;

[0016] Switching the host through the I3C switch chip;

[0017] When the BMC is set as the host, the CC1 pin and the CC2 pin of the adaptive debugging interface respectively output low levels to the AND gate chip, and the I3C control signal output after the AND gate is low level, so that the output terminal B of the I3C switch chip is connected to the input terminal A1;

[0018] When the computer host is set as the host, the CC1 pin and the CC2 pin of the adaptive debugging interface respectively output high levels to the AND gate chip, and the I3C control signal output after the AND gate is low level, so that the output terminal B of the I3C switch chip is connected to the input terminal A2.

[0019] Further, the method further includes: when performing serial port debugging, the CPU transmits the self - test code of the system BIOS to the BMC through the eSPI bus, and the eSPI signal is converted into a UART1 serial port signal by a signal conversion module in the BMC and sent to the serial port COMA of the serial port mode switching module. The BMC sends the log of the BMC to the serial port COMB of the serial port mode switching module through the UART2 serial port signal, and the serial port mode switching module is connected to the adaptive debugging interface through a USB interface;

[0020] Use the computer host to find the serial port COMA and the serial port COMB in device management, and select the data of the UART1 serial port signal or the UART2 serial port signal to be printed as needed.

[0021] Further, the method further includes: when performing remote debugging, configure the computer host to be in the same network segment as the BMC, send the MDI signal to the PHY chip through the adaptive debugging interface, and convert it into an RMII signal by the PHY chip and send it to the BMC; the BMC decodes the signal and converts it into a JTAG signal and sends it to the CPU, and the CPU returns the response signal to the computer host to complete an interaction of debugging information.

[0022] Compared with the prior art, the beneficial effects of the present invention are as follows: The present invention discloses an adaptive debugging system and method for a server platform. Through an adaptive debugging interface, data interaction is carried out between a computer host for debugging and various components of the server. By using the adaptive debugging interface, different serial ports, network ports, and I3C buses can be switched for debugging, which can not only save board space resources but also help debuggers reduce the debugging steps and quickly analyze the cause of the fault. The present invention realizes fast and efficient local debugging and remote debugging on a server platform without a PCH.

[0023] Thus, compared with the prior art, the present invention has prominent substantive features and significant progress, and the beneficial effects of its implementation are also obvious. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0025] Figure 1 It is a schematic diagram of a debugging system with a PCH controller in the prior art of the present invention.

[0026] Figure 2 It is a system structure diagram of Embodiment 1 of the present invention.

[0027] Figure 3 It is a system structure diagram of Embodiment 2 of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0028] The core of the present invention is to provide an adaptive debugging system for a server platform. In the prior art, when using the serial port of the BMC for debugging, usually, the debugger needs to open the chassis and connect the serial cable to the 3pin Header. In a chassis with structural interference, some PCIe cards also need to be removed to connect. The entire debugging process is very inconvenient to operate, and the network port and serial port will occupy board space resources, bringing design difficulties to R & D personnel. Although using the USB debugging interface of the PCH does not require opening the chassis, on a server platform without a PCH, this debugging method has become invalid.

[0029] The adaptive debugging system for a server platform provided by the present invention includes: BMC, CPU, PHY chip, serial port mode switching module, I3C switch chip, and adaptive debugging interface; BMC is respectively connected to the CPU, PHY chip, serial port mode switching module, and I3C switch chip, the adaptive debugging interface is respectively connected to the PHY chip, serial port mode switching module, and I3C switch chip, and the I3C switch chip is connected to the CPU; a signal conversion module is provided in the BMC, and the signal conversion module is respectively connected to the CPU and the serial port mode switching module. It can be seen that this system can use the adaptive debugging interface to switch different serial ports, network ports, and I3C buses for debugging, which can not only save the board space resources but also help the debugger reduce the debugging steps and quickly analyze the cause of the failure.

[0030] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0031] Embodiment 1:

[0032] As Figure 2 shown, this embodiment provides an adaptive debugging system for a server platform, including: BMC, CPU, PHY chip, serial port mode switching module, I3C switch chip, and adaptive debugging interface.

[0033] BMC is respectively connected to the CPU, PHY chip, serial port mode switching module, and I3C switch chip, the adaptive debugging interface is respectively connected to the PHY chip, serial port mode switching module, and I3C switch chip, and the I3C switch chip is connected to the CPU; a signal conversion module is provided in the BMC, and the signal conversion module is respectively connected to the CPU and the serial port mode switching module.

[0034] Specifically, the CPU is used to transfer the self-check code of the system BIOS to the BMC via the eSPI bus. The eSPI signal is converted into a UART1 serial port signal by the signal conversion module within the BMC and sent to the serial port mode switching module. The serial port mode switching module is connected to the adaptive debugging interface through a USB interface. The BMC is connected to the serial port mode switching module via a UART2 serial port signal; the BMC is connected to the PHY chip via an RMII signal. The PHY chip converts the RMII signal into an MDI signal and then sends it to the adaptive debugging interface; the BMC is connected to the CPU via a JTAG signal. The I3Cswitch chip is connected to the CPU, BMC, and adaptive debugging interface via I3C signals respectively; the adaptive adjustment interface sends I3C control signals to the I3C switch chip.

[0035] It should be noted that in this system, the CPU can transfer the postcode of the system BIOS to the BMC via the eSPI bus. Through the signal conversion module inside the BMC, the eSPI signal can be converted into a serial port UART1 (system serial port) signal. UART2 is the serial port of the BMC itself. UART1 and UART2 can be converted into USB signals through serial port mode switching, so as to be easily connected to the adaptive debugging interface. In addition, the RMII signal coming out of the BMC is converted into an MDI signal after passing through a PHY chip and is also connected to the adaptive debugging interface. Here, the RJ45 network port is cancelled, thus saving the board space resources.

[0036] It can be seen that this system can be debugged using I3C signals on a server platform without a PCH. Among them, both the HOST I3C output by the adaptive debugging interface and the BMC I3C output by the BMC can be used as the master, and the master can be switched by the I3C control signal.

[0037] Embodiment 2:

[0038] Based on Embodiment 1, this embodiment also provides an adaptive debugging system for a server platform.

[0039] As Figure 3 shown, the adaptive debugging interface of this system uses a type-c interface. The computer host is connected to the adaptive debugging interface through a type-c adapter cable for selecting the master-slave mode through a preset debugging software. All debugging signals are connected to the type-c interface. A typec adapter cable is needed to assist in completing the debugging. This cable can output MDI, USB, I3C, and I3C control signals.

[0040] Among them, the adaptive adjustment interface sends an I3C control signal to the I3C switch chip through the signal control circuit. The signal control circuit includes an AND gate chip. The CC1 pin and the CC2 pin of the adaptive debugging interface are respectively connected to the input ends of the AND gate chip. The AND gate chip generates an I3C control signal according to the level signals of the CC1 pin and the CC2 pin and sends it to the I3C switch chip. The AND gate chip uses the SN74LVC1G08 chip.

[0041] The I3C switch chip uses the IDTQS3VH257 chip. The B port of the I3C switch chip is connected to the CPU through the I3C signal. The S port of the I3C switch chip is connected to the output end of the AND gate chip through the I3C control signal. The A1 port of the I3C switch chip is connected to the BMC through the I3C signal. The A2 port of the I3C switch chip is connected to the adaptive debugging interface through the I3C signal. The PHY chip uses the RTL8211 chip, and the serial port mode switching module uses the CP2105 chip.

[0042] This embodiment discloses an adaptive debugging system and method for a server platform. Through the adaptive debugging interface, data interaction is carried out between the computer host for debugging and the components of the server. By using the adaptive debugging interface, different serial ports, network ports, and I3C buses can be switched for debugging, which can not only save the board space resources but also help the debugging personnel reduce the debugging steps and quickly analyze the cause of the failure.

[0043] Embodiment 3:

[0044] Based on the above embodiments, the present invention also discloses an adaptive debugging method for a server platform, including:

[0045] Connect the computer host to the adaptive debugging interface using an adapter cable, and set the CPU as a slave and the BMC or the computer host as a master through the preset debugging software built in the computer host.

[0046] Switch the host through the I3C switch chip.

[0047] When the BMC is set as the host, the CC1 pin and the CC2 pin of the adaptive debugging interface respectively output low levels to the AND gate chip, and the I3C control signal output after the AND gate is low level, so that the output end B and the input end A1 of the I3C switch chip are connected.

[0048] When the computer host is set as the host, the CC1 pin and the CC2 pin of the adaptive debugging interface respectively output high levels to the AND gate chip, and the I3C control signal output after the AND gate is low level, so that the output end B and the input end A2 of the I3C switch chip are connected.

[0049] This method realizes I3C debugging for server platforms without PCH. As an example, I3C debugging follows the master-slave mode. The CPU acts as the slave, and the BMC and the computer host can act as the master. The switching of the master is completed by the I3Cswitch chip. Specifically, the IDT QS3VH257 chip can be selected. When one end of the adapter cable is connected to the type-c interface and the other end is connected to the computer host, the master can be selected on the debugging software. When the BMC is selected as the master, the pins CC1 and CC2 output low levels respectively. After being calculated by the AND gate chip, the output I3C control signal is low level. In this way, the output terminal B of the I3Cswitch chip is connected to the input terminal A1. When the computer host is selected as the master, the pins CC1 and CC2 output high levels respectively. After being calculated by the AND gate chip, the output I3C control signal is high level. In this way, the output terminal B of the I3Cswitch chip is connected to the input terminal A2. It should be noted that when the BMC acts as the master of I3C, the MDI signal on the type-c interface needs to be converted into an RMII signal by the PHY chip (optional RTL8211) and given to the BMC, and then the BMC decodes it and outputs the I3C signal.

[0050] In addition, this method can also realize serial port debugging of the adaptive interface. The specific process is as follows:

[0051] When performing serial port debugging, the CPU transmits the self-check code of the system BIOS to the BMC through the eSPI bus. The eSPI signal is converted into a UART1 serial port signal by the signal conversion module in the BMC and sent to the serial port COMA of the serial port mode switching module. The BMC sends the log of the BMC to the serial port COMB of the serial port mode switching module through the UART2 serial port signal. The serial port mode switching module is connected to the adaptive debugging interface through the USB interface. At this time, use the computer host to find the serial port COMA and serial port COMB in the device management, and select the data of the UART1 serial port signal or the UART2 serial port signal to be printed according to the need.

[0052] As an example, when performing serial port debugging, UART1 is the system serial port. The CPU transmits it to the BMC via the eSPI bus, and then the SIO (serial input / output) module inside the BMC converts it into a UART signal, which can output the system's postcode information. UART2 is the serial port of the BMC itself and can output the BMC's log. UART1 and UART2 are connected to a serial port mode switching module (UART to USB). Specifically, the serial port mode switching module uses a CP2105 chip and can implement the function of converting 2-way UART signals into 1-way USB. When one end of the adapter cable is connected to the typec and the other end is connected to the computer host, the serial ports COMA and COMB can be found in the device management. Then, the system serial port UART1 or the BMC's serial port UART2 to be printed can be selected.

[0053] In addition, this method can also achieve remote debugging of the adaptive interface. The specific process is as follows:

[0054] When performing remote debugging, configure the computer host to be in the same network segment as the BMC. Send the MDI signal to the PHY chip through the adaptive debugging interface, and convert it into an RMII signal by the PHY chip and send it to the BMC; after decoding the signal, the BMC converts it into a JTAG signal and sends it to the CPU, and the CPU returns the response signal to the computer host to complete an interaction of debugging information.

[0055] As an example, when one end of the adapter cable is connected to the type-c and the other end is connected to the computer host, configure the computer host to be in the same network segment as the BMC. The MDI signal is converted into an RMII signal by the PHY chip (here, RTL8211 can be selected) and given to the BMC. After decoding by the BMC, it is then sent to the CPU through the JTAG signal. Finally, the CPU will transmit the response signal along this link to the computer host to complete an interaction of debugging information.

[0056] In summary, the present invention realizes fast and efficient local debugging and remote debugging on a server platform without a PCH.

[0057] In this specification, each embodiment is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the system disclosed in the embodiment, the description is relatively simple. For the relevant parts, refer to the description in the method part.

[0058] Those skilled in the art may further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been generally described according to their functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of the present invention.

[0059] In several embodiments provided by the present invention, it should be understood that the disclosed systems, systems, and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the couplings or direct couplings or communication connections shown or discussed with each other can be through some interfaces. The indirect couplings or communication connections of systems or units can be in electrical, mechanical, or other forms.

[0060] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they can be located in one place, or they can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0061] In addition, the functional modules in each embodiment of the present invention can be integrated in a processing unit, or each module can exist physically alone, or two or more modules can be integrated in a unit.

[0062] Similarly, the processing units in each embodiment of the present invention can be integrated in a functional module, or each processing unit can exist physically, or two or more processing units can be integrated in a functional module.

[0063] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent in such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0064] The above has introduced in detail the adaptive debugging system and method for a server platform provided by the present invention. Specific examples are used in this text to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only for helping to understand the method and its core idea of the present invention. It should be pointed out that for those of ordinary skill in the art in this technical field, without departing from the principle of the present invention, several improvements and modifications can still be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. An adaptive debugging system for a server platform, characterized in that, including: BMC, CPU, PHY chip, serial port mode switching module, I3C switch chip and adaptive debugging interface; The BMC is respectively connected to the CPU, PHY chip, serial port mode switching module and I3C switch chip, the adaptive debugging interface is respectively connected to the PHY chip, serial port mode switching module and I3C switch chip, and the I3C switch chip is connected to the CPU; A signal conversion module is provided in the BMC, and the signal conversion module is respectively connected to the CPU and the serial port mode switching module; The CPU is used to transmit the self-checking code of the system BIOS to the BMC through the eSPI bus, convert the eSPI signal into a UART1 serial port signal through the signal conversion module in the BMC and send it to the serial port mode switching module, and the serial port mode switching module is connected to the adaptive debugging interface through the USB interface; The BMC is connected to the serial port mode switching module through the UART2 serial port signal; The BMC is connected to the PHY chip through the RMII signal, and the PHY chip converts the RMII signal into an MDI signal and then sends it to the adaptive debugging interface; The BMC is connected to the CPU through the JTAG signal; The I3C switch chip is respectively connected to the CPU, BMC and adaptive debugging interface through the I3C signal; The adaptive adjustment interface sends an I3C control signal to the I3C switch chip through the signal control circuit; The adaptive debugging interface uses a type-c interface, and the computer host is connected to the adaptive debugging interface through a type-c adapter cable for selecting the master-slave mode through a preset debugging software; The signal control circuit includes an AND gate chip, the CC1 pin and CC2 pin of the adaptive debugging interface are respectively connected to the input ends of the AND gate chip, and the AND gate chip generates an I3C control signal according to the level signals of the CC1 pin and CC2 pin and sends it to the I3C switch chip; The UART1 serial port signal is used to transmit the self-checking code of the system BIOS, and the UART2 serial port signal is used to transmit the log of the BMC.

2. The adaptive debugging system for a server platform according to claim 1, wherein The I3C switch chip uses the IDTQS3VH257 chip, The B port of the I3C switch chip is connected to the CPU through the I3C signal, the S port of the I3C switch chip is connected to the output end of the AND gate chip through the I3C control signal, the A1 port of the I3C switch chip is connected to the BMC through the I3C signal, and the A2 port of the I3C switch chip is connected to the adaptive debugging interface through the I3C signal.

3. The adaptive debugging system for a server platform according to claim 2, wherein The UART1 serial port signal is used to transmit the self-checking code of the system BIOS, and the UART2 serial port signal is used to transmit the log of the BMC; The PHY chip uses the RTL8211 chip, and the serial port mode switching module uses the CP2105 chip.

4. An adaptive debugging method for a server platform, characterized in that, The method uses the adaptive debugging system for the server platform as described in claim 1; The method includes: Connect the computer host to the adaptive debugging interface using an adapter cable, and set the CPU as a slave and the BMC or the computer host as a master through the preset debugging software built into the computer host; Switch the host through the I3C switch chip; When the BMC is set as the host, the CC1 and CC2 pins of the adaptive debugging interface output low levels to the AND gate chip respectively, and the I3C control signal output after the AND gate is low level, so that the output terminal B of the I3C switch chip is connected to the input terminal A1; When the computer host is set as the host, the CC1 and CC2 pins of the adaptive debugging interface output high levels to the AND gate chip respectively, and the I3C control signal output after the AND gate is low level, so that the output terminal B of the I3C switch chip is connected to the input terminal A2.

5. The adaptive debugging method for a server platform according to claim 4, wherein The method further includes: When performing serial port debugging, the CPU transmits the self-check code of the system BIOS to the BMC through the eSPI bus, converts the eSPI signal into a UART1 serial port signal through the signal conversion module in the BMC and sends it to the serial port COMA of the serial port mode switching module, and the BMC sends the log of the BMC to the serial port COMB of the serial port mode switching module through the UART2 serial port signal. The serial port mode switching module is connected to the adaptive debugging interface through the USB interface; Use the computer host to find the serial port COMA and serial port COMB in device management, and select the data of the UART1 serial port signal or the UART2 serial port signal to be printed as needed.

6. The adaptive debugging method for a server platform according to claim 4, wherein The method further includes: When performing remote debugging, configure the computer host to the same network segment as the BMC, send the MDI signal to the PHY chip through the adaptive debugging interface, and convert it into an RMII signal through the PHY chip and send it to the BMC; The BMC decodes the signal and converts it into a JTAG signal and sends it to the CPU, and the CPU returns the response signal to the computer host to complete an interaction of debugging information.

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