Pixel circuit, pixel circuit driving method, and display device including pixel circuit

Abstract

In an embodiment, a pixel circuit, a method for driving the pixel circuit, and a display device including the pixel circuit are disclosed. According to the embodiment, the pixel circuit includes: a driving element including a first electrode connected to a first power line to which a pixel driving voltage is applied, a gate electrode connected to a first node, and a second electrode connected to a second node; a first switching element including a first electrode connected to a second power line to which a data voltage is applied, a gate electrode to which a first scan pulse is applied, and a second electrode connected to the first node; a second switching element including a first electrode connected to the second power line; a gate electrode to which a second scan pulse is applied, and a second electrode connected to the first node; a light-emitting element including an anode electrode connected to the second node and a cathode electrode connected to a third power line to which a low-potential power voltage is applied; and a capacitor connected between the first node and the second node.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2021-0117527, filed on September 3, 2021, and Korean Patent Application No. 10-2021-0178245, filed on December 14, 2021, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a pixel circuit and a display device including the pixel circuit. Background Art

[0004] Electroluminescent display devices are generally divided into inorganic light-emitting display devices and organic light-emitting display devices according to the material of the light-emitting layer. Active matrix organic light-emitting display devices include organic light-emitting diodes (hereinafter referred to as "OLEDs") that emit light by themselves, and have the advantages of fast response speed, high luminous efficiency, brightness and large viewing angle. In an organic light-emitting display device, an OLED is formed in each pixel. Organic light-emitting display devices not only have fast response speed, excellent luminous efficiency, brightness and viewing angle, but also have excellent contrast and color reproduction because they can express black grayscale in full black.

[0005] A pixel circuit of an electroluminescent display device includes an OLED serving as a light-emitting element and a driving element for driving the OLED.

[0006] The driving frequency applied to electroluminescent display devices gradually increases. For example, when the driving frequency increases from 120 Hz to 240 Hz, one horizontal period (1H) shortens. When one horizontal period shortens, the data charging rate in the pixel circuit may decrease, which may result in a decrease in brightness. Therefore, there is a need for a solution that can improve the data charging capability even when the driving frequency applied to the electroluminescent display device increases. Summary of the Invention

[0007] The present disclosure is directed to solving all of the above described needs and problems.

[0008] The present disclosure provides a pixel circuit capable of improving data charging capability and a display device including the pixel circuit.

[0009] It should be noted that the objects of the present disclosure are not limited to the objects described above, and other objects of the present disclosure will be apparent to those skilled in the art from the following description.

[0010] According to an embodiment of the present disclosure, a pixel circuit may include: a driving element, which includes a first electrode connected to a first power line to which a pixel driving voltage is applied, a gate electrode connected to a first node, and a second electrode connected to a second node; a first switching element, which includes a first electrode connected to a second power line to which a data voltage is applied, a gate electrode to which a first scan pulse is applied, and a second electrode connected to the first node; a second switching element, which includes a first electrode connected to the second power line; a gate electrode to which a second scan pulse is applied, and a second electrode connected to the first node; a light-emitting element, which includes an anode electrode connected to the second node and a cathode electrode connected to a third power line to which a low-potential power voltage is applied; and a capacitor connected between the first node and the second node.

[0011] According to the present disclosure, two switching elements turned on according to the gate-on voltage of the scan pulse are connected in parallel between the data voltage line and the gate node of the driving element, so that data charging capability can be improved even when the driving frequency is increased.

[0012] According to the present disclosure, dual data charging control may be achieved by adjusting the falling time of the scan pulses applied to two switching elements, and thus the data charging rate can be improved.

[0013] Effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned will be apparently understood by those skilled in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0015] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0016] Figure 2 It shows Figure 1 A diagram showing a cross-sectional structure of a display panel;

[0017] Figure 3 is a circuit diagram showing a pixel circuit according to a first embodiment of the present disclosure;

[0018] Figure 4 is a circuit diagram showing a pixel circuit according to a second embodiment of the present disclosure;

[0019] Figure 5A and Figure 5B is shown applied to Figure 4 The waveform diagram of the gate signal of the pixel circuit shown;

[0020] 6A to 6D It shows Figure 4 A circuit diagram showing the operation of the pixel circuit in stages;

[0021] Figures 7A to 7G is a graph describing the fall time of the second scanning pulse;

[0022] Figures 8A to 8C is shown applied to Figure 4 The waveform diagram of the gate signal of the pixel circuit shown;

[0023] Figure 9 is a circuit diagram showing a pixel circuit according to a third embodiment of the present disclosure;

[0024] Figure 10 is a circuit diagram showing a pixel circuit according to a fourth embodiment of the present disclosure; and

[0025] Figure 11A and Figure 11B is shown applied to Figure 10 The waveform diagram of the gate signal of the pixel circuit shown. DETAILED DESCRIPTION

[0026] The advantages and features of the present disclosure and the methods for implementing the present disclosure will be more clearly understood based on the embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments, but can be implemented in various forms. On the contrary, the present embodiments will complete the disclosure of the present disclosure and enable those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is limited only within the scope of the appended claims.

[0027] The shapes, sizes, ratios, angles, numbers, etc. shown in the drawings used to describe the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout this specification, similar reference numerals generally represent similar elements. In addition, when describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0028] Terms such as "including," "comprising," "having," and "consisting of" used herein are generally intended to allow the addition of other components unless the term is used with the term "only." Any reference to the singular may include the plural unless expressly stated otherwise.

[0029] Parts are interpreted as including ordinary error ranges even if not expressly stated.

[0030] When terms such as “on,” “over,” “below,” and “beside” are used to describe the positional relationship between two components, one or more components may be positioned between the two components unless these terms are used together with the terms “immediately” or “directly.”

[0031] Terms such as “first” and “second” may be used to distinguish components from one another, but the function or structure of a component is not limited by the sequence number or name preceding the component.

[0032] Like reference numerals may refer to substantially like elements throughout this disclosure.

[0033] The following embodiments may be combined or combined with each other in part or in whole, and may be technically connected and operated in various ways. The embodiments may be performed independently of each other or in association with each other.

[0034] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0035] Each pixel is divided into a plurality of sub-pixels having different colors to realize color, and each sub-pixel includes a transistor serving as a switching element or a driving element. Such a transistor can be realized as a thin film transistor (TFT).

[0036] The driving circuit of the display device writes pixel data of the input image into the pixels. The driving circuit of the flat panel display device includes a data driver for providing data signals to the data lines, a gate driver for providing gate signals to the gate lines, and the like.

[0037] In the display device of the present disclosure, the pixel circuit may include a plurality of transistors. The transistor may be implemented as a TFT having a metal oxide semiconductor FET (MOSFET) structure, and may be an oxide TFT including an oxide semiconductor or an LTPS TFT including low-temperature polysilicon (LTPS). Hereinafter, the transistors constituting the pixel circuit will be exemplarily described using an example of an implementation using an n-channel oxide TFT, but the present disclosure is not limited thereto.

[0038] A transistor is a three-electrode device consisting of a gate, a source, and a drain. The source is the electrode that supplies carriers to the transistor. In a transistor, carriers begin flowing from the source. The drain is the electrode through which carriers leave the transistor. In a transistor, carriers flow from the source to the drain. In an n-channel transistor, since the carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. In an n-channel transistor, the direction of current is from the drain to the source. In a p-channel transistor, since the carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain electrodes in a transistor are not fixed. For example, the source and drain electrodes can be changed depending on the applied voltage. Therefore, the present disclosure is not limited to the source and drain electrodes of a transistor. In the following description, a source and a drain of a transistor will be referred to as a first electrode and a second electrode.

[0039] The gate signal can swing between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor. The gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

[0040] The transistor is turned on in response to a gate-on voltage and turned off in response to a gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate high voltage (VGH and VEH), and the gate-off voltage may be a gate low voltage (VGL and VEL).

[0041] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following embodiments, the display device will be described focusing on an organic light emitting display device, but the present disclosure is not limited thereto.

[0042] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure, and Figure 2 It shows Figure 1 A diagram showing a cross-sectional structure of a display panel.

[0043] Reference Figure 1 and Figure 2 , a display device according to an embodiment of the present disclosure includes: a display panel 100; a display panel driver for writing pixel data to pixels of the display panel 100; and a power supply device 140 for generating power required to drive the pixels and the display panel driver.

[0044] The display panel 100 may be a display panel having a rectangular structure with a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 includes a pixel array AA that displays an input image. The pixel array AA includes: a plurality of data lines 102; a plurality of gate lines 103 intersecting the data lines 102; and pixels arranged in a matrix form. The display panel 100 may also include power lines that are generally connected to the pixels. The power lines may include: a power line to which a pixel drive voltage EVDD is applied; a power line to which an initialization voltage Vinit is applied; a power line to which a reference voltage Vref is applied; and a power line to which a low-potential power voltage EVSS is applied. These power lines are generally connected to the pixels.

[0045] The pixel array AA includes a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln includes a row of pixels arranged along the row direction X in the pixel array AA of the display panel 100. The pixels arranged in one pixel row share a gate line 103. The sub-pixels arranged in the column direction Y along the data line direction share the same data line 102. One horizontal period 1H is the time obtained by dividing one frame period by the total number of pixel rows L1 to Ln.

[0046] The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device in which an image is displayed on a screen and an actual background can be seen.

[0047] The display panel 100 may be implemented as a flexible display panel. The flexible display panel may be made of a plastic OLED panel. An organic film may be provided on the backplane of the plastic OLED panel, and a pixel array AA and a light-emitting element may be formed on the organic film.

[0048] To achieve color, each pixel in the pixel 101 can be divided into a red sub-pixel (hereinafter referred to as an "R sub-pixel"), a green sub-pixel (hereinafter referred to as a "G sub-pixel"), and a blue sub-pixel (hereinafter referred to as a "B sub-pixel"). Each pixel in the pixel can also include a white sub-pixel. Each sub-pixel includes a pixel circuit. The pixel circuit is connected to a data line, a gate line, and a power line.

[0049] Pixels can be configured as either true color pixels or PenTile pixels. PenTile pixels can achieve higher resolution than true color pixels by driving two sub-pixels of different colors as one pixel 101 using a preset pixel rendering algorithm. The pixel rendering algorithm can compensate for the lack of color representation in each pixel using the color of light emitted from adjacent pixels.

[0050] A touch sensor may be provided on the display panel 100. A separate touch sensor may be used to sense touch input, or a touch input may be sensed by a pixel. The touch sensor may be provided as an on-cell type or an add-on type on the screen of the display panel, or may be implemented as an in-cell type touch sensor embedded in the pixel array AA.

[0051] like Figure 2 As shown, when viewed from a cross-sectional structure, the display panel 100 may include a circuit layer 12 , a light emitting element layer 14 , and an encapsulation layer 16 stacked on a substrate 10 .

[0052] The circuit layer 12 may include: pixel circuits connected to wiring such as data lines, gate lines, and power lines; a gate driver (GIP) connected to the gate lines, etc. The wiring and circuit elements of the circuit layer 12 may include: multiple insulating layers; two or more metal layers separated by insulating layers therebetween; and an active layer including a semiconductor material.

[0053] The light-emitting element layer 14 may include a light-emitting element EL driven by a pixel circuit. The light-emitting element EL may include a red (R) light-emitting element, a green (G) light-emitting element, and a blue (B) light-emitting element. The light-emitting element layer 14 may include a white light-emitting element and a color filter. The light-emitting element EL of the light-emitting element layer 14 may be covered by a protective layer including an organic film and a passivation film.

[0054] Encapsulation layer 16 covers light-emitting element layer 14 to seal circuit layer 12 and light-emitting element layer 14. Encapsulation layer 16 may have a multilayer insulation structure in which organic films and inorganic films are alternately stacked. The inorganic films block the penetration of moisture and oxygen. The organic films flatten the surface of the inorganic films. When the organic and inorganic films are stacked in multiple layers, the migration path of moisture or oxygen becomes longer compared to a single layer, making it possible to effectively block the penetration of moisture and oxygen that affect light-emitting element layer 14.

[0055] A touch sensor layer may be provided on the encapsulation layer 16. The touch sensor layer may include a capacitive touch sensor that senses touch input based on a change in capacitance before and after a touch input. The touch sensor layer may include a metal wiring pattern and an insulating layer that form the capacitance of the touch sensor. The capacitance of the touch sensor may be formed between the metal wiring patterns. A polarizing plate may be provided on the touch sensor layer. The polarizing plate may improve visibility and contrast by converting the polarization of external light reflected by the metal of the touch sensor layer and the circuit layer 12. The polarizing plate may be implemented as a polarizing plate in which a linear polarizing plate is combined with a phase delay film, or as a circular polarizing plate. A cover glass may be adhered to the polarizing plate.

[0056] The display panel 100 may further include a touch sensor layer and a color filter layer stacked on the encapsulation layer 16. The color filter layer may include a red filter, a green filter, and a blue filter, as well as a black matrix pattern. The color filter layer may replace the polarizing plate and improve color purity by absorbing part of the wavelength of light reflected from the circuit layer and the touch sensor layer. In this embodiment, by applying a color filter layer having a higher transmittance than the polarizing plate to the display panel, the transmittance of the display panel PNL may be improved, and the thickness and flexibility of the display panel PNL may be improved. A cover glass may be adhered to the color filter layer.

[0057] The power supply device 140 generates the DC power required to drive the pixel array AA and the display panel driver of the display panel 100 using a DC-to-DC converter. The DC-to-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, and the like. The power supply device 140 can adjust the DC input voltage from the host system (not shown) and thereby generate DC voltages such as the gamma reference voltage VGMA, gate-on voltages VGH and VEH, gate-off voltages VGL and VEL, pixel drive voltage EVDD, pixel low-potential power supply voltage EVSS, reference voltage Vref, initial voltage Vinit, anode voltage Vano, and the like. The gamma reference voltage VGMA is provided to the data driver 110. The gate-on voltages VGH and VEH and the gate-off voltages VGL and VEL are provided to the gate driver 120. The pixel drive voltage EVDD, pixel low-potential power supply voltage EVSS, reference voltage Vref, initial voltage Vinit, anode voltage Vano, and the like are collectively provided to the pixels.

[0058] The display panel driver writes pixel data (digital data) of an input image into pixels of the display panel 100 under the control of a timing controller (TCON) 130 .

[0059] The display panel driver includes a data driver 110 and a gate driver 120. The display panel driver may further include the data driver 110 and a demultiplexer array 112 disposed between the data lines 102.

[0060] The demultiplexer array 112 sequentially supplies data voltages output from the channels of the data driver 110 to the data lines 102 using a plurality of demultiplexers (DEMUX). The demultiplexer may include a plurality of switching elements provided on the display panel 100. When the demultiplexer is provided between the output terminal of the data driver 110 and the output terminal of the data lines 102, the number of channels of the data driver 110 can be reduced. The demultiplexer array 112 may be omitted.

[0061] The display panel driver may further include a touch sensor driver for driving the touch sensor. Figure 1 The touch sensor driver is omitted. The touch sensor driver can be integrated into a driver integrated circuit (IC). In a mobile device or wearable device, the timing controller 130, the power supply device 140, the data driver 110, the touch sensor driver, etc. can be integrated into a driver integrated circuit (IC).

[0062] The display panel driver can operate in a low-speed drive mode under the control of the timing controller (TCON) 130. The low-speed drive mode can be set to reduce the power consumption of the display device when the input image does not change within a preset number of frames when analyzing the input image. In the low-speed drive mode, when a still image is input for a predetermined time or longer, the power consumption of the display panel driver and the display panel 100 can be reduced by reducing the refresh rate of the pixels. The low-speed drive mode is not limited to the case where a still image is input. For example, when the display device is operating in standby mode or when a user command or input image is not input to the display panel driver for a predetermined time or longer, the display panel driver can operate in the low-speed drive mode.

[0063] The data driver 110 generates data voltages Vdata by converting pixel data of an input image received from the timing controller 130 using a digital-to-analog converter (DAC) with a gamma compensation voltage during each frame period. The gamma reference voltage VGMA is divided for each grayscale level by a voltage divider circuit. The gamma compensation voltages divided from the gamma reference voltage VGMA are provided to the DAC of the data driver 110. The data voltages Vdata are output through an output buffer AMP in each of the channels of the data driver 110.

[0064] The gate driver 120 can be implemented as a gate-in-panel (GIP) circuit directly formed on the circuit layer 12 of the display panel 100 together with the TFT array of the pixel array AA. The gate-in-panel (GIP) circuit can be provided on the border area BZ which is the non-display area of ​​the display panel 100, or dispersed in the pixel array on which the input image is reproduced. The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130. The gate driver 120 can sequentially provide these gate signals to the gate lines 103 by shifting the gate signals using a shift register. The gate signals may include a scan pulse, an emission control pulse (hereinafter referred to as an "EM pulse"), an initial pulse, and a sensing pulse.

[0065] The shift register of the gate driver 120 outputs a pulse of a gate signal in response to a start pulse and a shift clock from the timing controller 130 , and shifts the pulse according to the shift clock timing.

[0066] The timing controller 130 receives digital video data DATA of an input image and timing signals synchronized with the digital video data DATA from a host system (not shown). The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock CLK, a data enable signal DE, and the like. Since the vertical and horizontal periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a period of one horizontal period (1H).

[0067] The host system may be any one of a television (TV) system, a tablet computer, a notebook computer, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a vehicle system. The host system may scale an image signal from a video source according to the resolution of the display panel 100 and transmit the image signal together with a timing signal to the timing controller 130.

[0068] The timing controller 130 multiplies the input frame frequency by i and controls the operating timing of the display panel driver at a frame frequency of input frame frequency × i (i is a positive integer greater than 0) Hz. The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) scheme and 50 Hz in the PAL (Phase Alternation Line) scheme. The timing controller 130 can reduce the driving frequency of the display panel driver by reducing the frame frequency to a frequency between 1 Hz and 30 Hz, thereby reducing the refresh rate of the pixels in the low-speed drive mode.

[0069] Based on the timing signals Vsync, Hsync, and DE received from the host system, the timing controller 130 generates data timing control signals for controlling the operating timing of the data driver 110, control signals for controlling the operating timing of the demultiplexer array 112, and gate timing control signals for controlling the operating timing of the gate driver 120. The timing controller 130 controls the operating timing of the display panel driver to synchronize the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gate driver 120.

[0070] The voltage levels of the gate timing control signals output from the timing controller 130 can be converted into gate-on voltages VGH and VEH and gate-off voltages VGL and VEL by a level shifter (not shown), and then provided to the gate driver 120. That is, the level shifter converts the low-level voltage of the gate timing control signal into the gate-off voltages VGL and VEL, and converts the high-level voltage of the gate timing control signal into the gate-on voltages VGH and VEH. The gate timing signal includes a start pulse and a shift clock.

[0071] Figure 3 is a circuit diagram showing a pixel circuit according to a first embodiment of the present disclosure.

[0072] Reference Figure 3 The pixel circuit according to the first embodiment of the present disclosure may include: a light emitting element EL; a driving element DT for driving the light emitting element EL; a plurality of switching elements M01 and M02; and a capacitor Cst.

[0073] The light-emitting element EL can be implemented as an OLED. The OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EML), an electron transport layer (ETL), an electron injection layer (EIL), etc., but is not limited thereto. The anode electrode of the light-emitting element EL is connected to the second node n2, and the cathode electrode is connected to the third power line PL3 to which the low potential power voltage EVSS is applied. When a voltage is applied to the anode electrode and the cathode electrode of the light-emitting element EL, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL are moved to the emission layer EML and form excitons, thereby emitting visible light in the emission layer EML.

[0074] An organic light emitting diode used as a light emitting element may have a tandem structure in which a plurality of light emitting layers are stacked. An organic light emitting diode having a tandem structure may improve the brightness and lifespan of a pixel.

[0075] The driving element DT generates a current according to the gate-source voltage Vgs and thereby drives the light emitting element EL. The driving element DT includes: a gate electrode connected to a first node n1; a first electrode connected to a first power line PL1 to which a pixel driving voltage EVDD is applied; and a second electrode connected to a second node n2.

[0076] The first switching element M01 is turned on by the gate-on voltage VEH of the first scan pulse SCAN1 and applies the data voltage to the first node n1. The first switching element M01 includes: a gate electrode to which the first scan pulse SCAN1 is applied; a first electrode connected to the second power line DL to which the data voltage Vdata is applied; and a second electrode connected to the first node n1.

[0077] The second switching element M02 is turned on by the gate-on voltage VEH of the second scan pulse SCAN2 and applies the data voltage to the first node n1. The second switching element M02 includes: a gate electrode to which the second scan pulse SCAN2 is applied; a first electrode connected to the second power line DL to which the data voltage is applied; and a second electrode connected to the first node n1.

[0078] When both the first switching element M01 and the second switching element M02 are turned on during the period when the data voltage is applied, the first switching element M01 and the second switching element M02 are connected in parallel to the second power line. This reduces the total resistance of the equivalent circuit, thereby improving the data charging capability.

[0079] The first capacitor Cst is connected between the first node n1 and the second node n2 and stores a threshold voltage. One end of the first capacitor Cst is connected to the first node n1, and the other end is connected to the second node n2.

[0080] Figure 4 is a circuit diagram showing a pixel circuit according to a second embodiment of the present disclosure, and Figure 5A and 5B is shown applied to Figure 4 The waveform diagram of the gate signal of the pixel circuit shown.

[0081] Reference Figure 4 The pixel circuit according to the second embodiment of the present disclosure may include: a light emitting element EL; a driving element DT for driving the light emitting element EL; a plurality of switching elements M01, M02, M03, and M04; and a capacitor Cst. The driving element DT and the switching elements M01, M02, M03, and M04 may be implemented as n-channel oxide TFTs.

[0082] The pixel circuit is connected to the following: a first power line PL1 to which a pixel driving voltage EVDD is applied, a second power line DL to which a data voltage Vdata is applied, a third power line PL3 to which a low-potential power voltage EVSS is applied, a fourth power line PL4 to which an initialization voltage Vinit is applied, a fifth power line RL to which a reference voltage Vref is applied, and gate lines to which gate signals INIT, SENSE, SCAN1, and SCAN2 are applied.

[0083] The driving element DT generates a current according to the gate-source voltage Vgs and thereby drives the light emitting element EL. The driving element DT includes: a gate electrode connected to a first node n1; a first electrode connected to a first power line PL1 to which a pixel driving voltage EVDD is applied; and a second electrode connected to a second node n2.

[0084] The first switching element M01 is turned on by the gate-on voltage VEH of the first scan pulse SCAN1 and applies the data voltage to the first node n1. The first switching element M01 includes: a gate electrode to which the first scan pulse SCAN1 is applied; a first electrode connected to the second power line DL to which the data voltage is applied; and a second electrode connected to the first node n1.

[0085] The second switching element M02 is turned on by the gate-on voltage VEH of the second scan pulse SCAN2 and applies the data voltage to the first node n1. The second switching element M02 includes: a gate electrode to which the second scan pulse SCAN2 is applied; a first electrode connected to the second power line DL to which the data voltage is applied; and a second electrode connected to the first node n1.

[0086] The third switching element M03 is turned on by the gate-on voltage VGH of the initialization pulse INIT and applies the initialization voltage Vinit to the first node n1. The third switching element M03 includes a first electrode connected to the fourth power line PL4 to which the initialization voltage Vinit is applied; a gate electrode to which the initialization pulse INIT is applied; and a second electrode connected to the first node n1.

[0087] The fourth switching element M04 is turned on by the gate-on voltage VGH of the sensing pulse SENSE and provides the reference voltage Vref to the second node n2. The fourth switching element M04 includes a first electrode connected to the second node n2; a gate electrode to which the sensing pulse SENSE is applied; and a second electrode connected to the fifth power line RL to which the reference voltage is applied.

[0088] like Figure 5A and Figure 5BAs shown, the pixel circuit can be driven in the order of an initialization step Ti, a sensing step Ts, a data writing step Tw, and a light emission step Tem. In the initialization step Ti, the pixel circuit is initialized. In the sensing step Ts, the threshold voltage Vth of the driving element DT is sensed and stored in the first capacitor Cst. In the data writing step Tw, the data voltage Vdata of the pixel data is applied to the first node n1. After the voltage at the first node n1 and the voltage at the second node n2 are increased in the boosting step Tboost, the light emitting element EL can emit light with a brightness corresponding to the grayscale value of the pixel data in the light emission step Tem.

[0089] The pixel circuit can apply the first scanning pulse and the second scanning pulse equally, such as Figure 5A As shown, the first scanning pulse and the second scanning pulse may also be applied differently and separately, as shown in FIG. Figure 5B shown.

[0090] 6A to 6D It shows Figure 4 Here, the circuit diagram of the pixel circuit shown in FIG. Figure 5B The operation is performed with the drive timing shown.

[0091] like Figure 6A As shown, in the initialization step Ti, the third switching element M03 and the fourth switching element M04 are turned on, while the first switching element M01 and the second switching element M02 are turned off. The initialization voltage Vinit is applied to the first node n1, and the reference voltage Vref is applied to the second node n2. At this time, the driving element DT is turned on, while the light-emitting element EL is not turned on.

[0092] like Figure 6B As shown, during the sensing step Ts, the fourth switching element M04 maintains an on state, and thus the voltage of the second node n2 increases. When the gate-source voltage Vgs of the driving element DT reaches the threshold voltage Vth, the driving element DT is turned off, and the threshold voltage Vth is stored in the first capacitor Cst. During the sensing step Ts, the sensing pulse SENSE applied to the fourth switching element M04 can be generated within approximately 1.5 horizontal periods (1.5H).

[0093] In the holding period Th, the third switching element M03 is turned off, and the second node n2 and the first node n1 float to maintain the previous voltage. The holding period Th may be generated within approximately one horizontal period (1H).

[0094] like Figure 6CAs shown, during the data writing step Tw, the first switching element M01 and the second switching element M02 are turned on. The data voltage Vdata of the pixel data is applied to the first node n1, and thus the voltage at the first node n1 is changed by the data voltage Vdata. At this time, the data voltage Vdata of the pixel data is not applied through a single switching element, but through the first switching element M01 and the second switching element M02 connected in parallel, thereby improving the charging characteristics. During the data writing step Tw, both the first switching element M01 and the second switching element M02 remain in the on state. The scan pulse SCAN applied to the first switching element M01 and the second switching element M02 during the data writing step Tw can be generated within approximately 0.7 horizontal periods (0.7H). The first switching element M01 and the second switching element M02 are both turned on at the beginning of the data writing step Tw, and the first switching element M01 and the second switching element M02 are turned off at different time points. In other words, the first switching element M01 is turned off before the data writing step Tw ends, while the second switching element M02 is turned off when the data writing step Tw ends. The reason why the turn-off time points are different from the above is to prevent data shuffling. In this case, the time point at which the first switching element M01 is turned off may be fixed, while the time point at which the second switching element M02 is turned off may be variable.

[0095] In addition, the second scanning pulse can not only reduce the falling time point, but also reduce the falling time by applying under-driving downward.

[0096] Figures 7A to 7G is a diagram showing the falling time of the second scanning pulse.

[0097] Reference Figure 7A and Figure 7B , it can be seen that when the falling time of the second scan pulse changes, the turning-off time of the second switch element also changes. As the falling time of the second scan pulse decreases, the turning-off time of the second switch element also decreases.

[0098] Due to the reduction in the off time of the second switching element, the second switching element can be turned off before the next row is turned off. This makes it possible to prevent data shuffling from occurring, thereby ensuring a more efficient charging time.

[0099] The second switching element is an auxiliary TFT for improving a charging rate, and can minimize a falling time by reducing a size and a load and applying under-driving downward as compared with the first switching element.

[0100] Reference Figure 7C, the voltage level of the first scan pulse SACN1 and the voltage level of the second scan pulse SACN2 may be separated, and the gate low voltage of the second scan pulse SACN2 may be lower than the gate low voltage of the first scan pulse SACN1. That is, the voltage swing of the first scan pulse SACN1 is between the first gate-on voltage VGH1 and the first gate-off voltage VGL1, and the voltage swing of the second scan pulse SACN2 is between the first gate-on voltage VGH1 and the second gate-off voltage VGL2 which is lower than the first gate-off voltage VGL1.

[0101] When the difference between the gate high voltage VGH1 and the gate low voltage VGL2 of the second scan pulse SACN2 increases, the falling period of the second scan pulse SACN2 is shortened, and thus the falling time may be reduced.

[0102] Reference Figure 7D , the voltage level of the first scan pulse SACN1 and the voltage level of the second scan pulse SACN2 may be separated, and the gate high voltage of the second scan pulse SACN2 may be higher than the gate high voltage of the first scan pulse SACN1. That is, the voltage swing of the first scan pulse SACN1 is between the first gate-on voltage VGH1 and the first gate-off voltage VGL1, and the voltage swing of the second scan pulse SACN2 is between the second gate-on voltage VGH2 higher than the first gate-on voltage VGH1 and the first gate-off voltage VGL1.

[0103] When the difference between the gate-on voltage VGH2 and the gate-off voltage VGL1 of the second scan pulse SACN2 increases, the falling period of the second scan pulse SACN2 is shortened, and thus the falling time may be reduced.

[0104] Reference Figure 7E , the voltage levels of the first scan pulse SACN1 and the second scan pulse SACN2 may be separated, the gate low voltage of the second scan pulse SACN2 may be lower than the gate low voltage of the first scan pulse SACN1, and the gate high voltage of the second scan pulse SACN2 may be higher than the gate high voltage of the first scan pulse SACN1. That is, the voltage swing of the first scan pulse SACN1 is between the first gate-on voltage VGH1 and the first gate-off voltage VGL1, and the voltage swing of the second scan pulse SACN2 is between the second gate-on voltage VGH2, which is higher than the first gate-on voltage VGH1, and the first gate-off voltage VGL1.

[0105] When the difference between the gate high voltage VGH2 and the gate low voltage VGL2 of the second scan pulse SACN2 increases, the falling period of the second scan pulse SACN2 is shortened, and thus the falling time may be reduced.

[0106] Reference Figure 7F Since the falling time of the scan pulse of the (n-1)th row is shortened and the turn-off time point of the switching element is advanced, the effective charging time of the nth row is increased and the data charging rate can be improved.

[0107] Reference Figure 7G As the gate low voltage VGL of the second scan pulse decreases, the difference from the gate high voltage VGH of the second scan pulse increases. Therefore, the falling period of the second scan pulse decreases, and thus the data charging rate can be improved.

[0108] For example, as shown, when the gate low voltage VGL of the second scan pulse is -6 V, the data charge rate is 12.7%, while when the gate low voltage VGL is -12 V, the data charge rate is 53.7%. In addition, when the gate low voltage VGL is -15 V, the data charge rate is 66.1%, while when the gate low voltage VGL is -18 V, the data charge rate is 74.3%. This example shows that the charge rate is improved.

[0109] During the boost step Tboost, the first switching element M01, the second switching element M02, the third switching element M03, and the fourth switching element M04 are turned off. At this time, the voltage at the first node n1 and the voltage at the second node n2 increase.

[0110] In the light emission step Tem, as Figure 6D As shown, the first switching element M01, the second switching element M02, the third switching element M03, and the fourth switching element M04 are maintained in the off state. At this time, a current generated by the gate-source voltage Vgs of the driving element DT (i.e., the voltage between the first node n1 and the second node n2) is supplied to the light-emitting element EL, thereby causing the light-emitting element EL to emit light.

[0111] In the embodiment, the case where the falling time of the scan pulse is applied equally to all pixels is exemplarily described, but the present disclosure is not limited thereto. That is, in the embodiment, the falling time of the scan pulse is applied differently for each gate line or each group of gate lines, taking into account the RC delay in the data line or the IR drop in the power lines EVDD and EVSS.

[0112] Figures 8A to 8C is shown applied to Figure 4 The waveform diagram of the gate signal of the pixel circuit shown.

[0113] Reference Figure 8A , the falling time of the second scan pulse may be applied differently for each gate line considering the RC delay in the data line or the IR drop in the power lines EVDD and EVSS.

[0114] Reference Figure 8B , considering the RC delay in the data lines or the IR drop in the power lines EVDD and EVSS, the falling time of the second scan pulse may be applied differently for each group of gate lines.

[0115] Reference Figure 8C , considering the RC delay in the data line or the IR drop in the power lines EVDD and EVSS, the rising time of the second scan pulse can be applied differently for each group of gate lines, thereby adjusting the overlapping period of the first scan pulse and the second scan pulse.

[0116] like Figures 8A to 8C As shown, the falling time of the second scan pulse or the gate low voltage according to an embodiment may vary in proportion to the RC delay or the IR drop.

[0117] Although the case where the gate low voltage of the second scan pulse is applied differently is described, the present disclosure is not limited thereto. That is, in an embodiment, at least one of the gate high voltage and the gate low voltage of the second scan pulse may be applied differently.

[0118] Figure 9 is a circuit diagram showing a pixel circuit according to a third embodiment of the present disclosure.

[0119] Reference Figure 9 The pixel circuit according to the third embodiment of the present disclosure includes: a light emitting element EL; a driving element DT for driving the light emitting element EL; a switching element M01 and a capacitor Cst.

[0120] The light-emitting element EL can be implemented as an OLED. The OLED includes an organic compound layer formed between an anode electrode and a cathode electrode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode electrode of the light-emitting element EL is connected to the second node n2, and the cathode electrode is connected to the third power line PL3 to which a low potential power voltage EVSS is applied. When a voltage is applied to the anode electrode and the cathode electrode of the light-emitting element EL, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) are moved to the emission layer EML and form excitons, thereby emitting visible light in the emission layer EML.

[0121] The driving element DT generates current according to the gate-source voltage Vgs and thereby drives the light emitting element EL. The driving element DT includes: a gate electrode connected to a first node n1; a first electrode connected to a first power line to which a pixel driving voltage is applied; and a second electrode connected to a second node n2.

[0122] The first switching element M01 can be formed with a dual gate structure and driven independently by the first scan pulse SCAN1 and the second scan pulse SCAN2. In the case of a dual gate structure, applying gate voltages to the upper and lower surfaces of the active layer can increase carriers and mobility, thereby improving current capability. Therefore, when the first switching element M01 is turned on during the period when the data voltage is applied, the current capability characteristics of the first switching element M01 with a dual gate structure can improve data charging capability.

[0123] The first capacitor Cst is connected between the first node n1 and the second node n2 and stores a threshold voltage. One end of the first capacitor Cst is connected to the first node n1, and the other end is connected to the second node n2.

[0124] Figure 10 is a circuit diagram showing a pixel circuit according to a fourth embodiment of the present disclosure, and Figure 11A and Figure 11B is shown applied to Figure 10 The waveform diagram of the gate signal of the pixel circuit shown.

[0125] Reference Figure 10 The pixel circuit according to the fourth embodiment of the present disclosure includes: a light emitting element EL; a driving element DT for driving the light emitting element EL; a plurality of switching elements M01, M02, and M03; and a capacitor Cst. The driving element DT and the switching elements M01, M02, and M03 may be implemented as n-channel oxide TFTs.

[0126] The pixel circuit is connected to the following: a first power line PL1 to which a pixel driving voltage EVDD is applied, a second power line DL to which a data voltage Vdata is applied, a third power line PL3 to which a low-potential power voltage EVSS is applied, a fourth power line PL4 to which an initialization voltage Vinit is applied, a fifth power line RL to which a reference voltage Vref is applied, and gate lines to which gate signals INIT, SENSE, SCAN1, and SCAN2 are applied.

[0127] The driving element DT generates a current according to the gate-source voltage Vgs and thereby drives the light emitting element EL. The driving element DT includes: a gate electrode connected to a first node n1; a first electrode connected to a first power line PL1 to which a pixel driving voltage EVDD is applied; and a second electrode connected to a second node n2.

[0128] The first switching element M01 is turned on by the gate-on voltage VEH of the first scan pulse SCAN1 and the second scan pulse SCAN2, and applies the data voltage to the first node n1. The first switching element M01 includes: a first gate electrode to which the first scan pulse SCAN1 is applied; a second gate electrode to which the second scan pulse SCAN2 is applied; a first electrode connected to the second power line DL to which the data voltage is applied; and a second electrode connected to the first node n1.

[0129] The second switching element M02 is turned on by the gate-on voltage VGH of the initialization pulse INIT and applies the initialization voltage Vinit to the first node n1. The second switching element M02 includes a first electrode connected to the fourth power line PL4 to which the initialization voltage Vinit is applied; a gate electrode to which the initialization pulse INIT is applied; and a second electrode connected to the first node n1.

[0130] The third switching element M03 is turned on by the gate-on voltage VGH of the sensing pulse SENSE and provides the reference voltage Vref to the second node n2. The third switching element M03 includes a first electrode connected to the second node n2; a gate electrode to which the sensing pulse SENSE is applied; and a second electrode connected to the fifth power line RL to which the reference voltage is applied.

[0131] The first capacitor Cst is connected between the first node n1 and the second node n2 and stores a threshold voltage. One end of the first capacitor Cst is connected to the first node n1, and the other end is connected to the second node n2.

[0132] like Figure 11A and Figure 11B As shown, the pixel circuit can be driven in the order of an initialization step Ti, a sensing step Ts, a data writing step Tw, and a light emission step Tem. In the initialization step Ti, the pixel circuit is initialized. In the sensing step Ts, the threshold voltage Vth of the driving element DT is sensed and stored in the first capacitor Cst. In the data writing step Tw, the data voltage Vdata of the pixel data is applied to the first node n1. After the voltage of the first node n1 and the voltage of the second node n2 are increased in the boosting step Tboost, the light emitting element EL can emit light with a brightness corresponding to the grayscale value of the pixel data in the light emission step Tem.

[0133] The pixel circuit can apply the first scanning pulse and the second scanning pulse equally, such as Figure 11A As shown, the first scanning pulse and the second scanning pulse may also be applied differently and separately, as shown in FIG. Figure 11B shown.

[0134] like Figure 11A As shown, in the initialization step Ti, the second switching element M02 and the third switching element M03 are turned on, while the first switching element M01 is turned off. The initialization voltage Vinit is applied to the first node n1, and the reference voltage Vref is applied to the second node n2. At this time, the driving element DT is turned on, while the light-emitting element EL is not turned on.

[0135] In the sensing step Ts, the second switching element M02 maintains the on state and thus the voltage of the first node n1 increases. When the gate-source voltage Vgs of the driving element DT reaches the threshold voltage Vth, the driving element DT is turned off and the threshold voltage Vth is stored in the first capacitor Cst.

[0136] In the holding period Th, the second switching element M02 is turned off, and the second node n2 and the first node n1 float to maintain the previous voltage.

[0137] In the data writing step Tw, the first switching element M01 is turned on. The data voltage Vdata of the pixel data is applied to the first node n1, and thus the voltage at the first node n1 is changed by the data voltage Vdata. The scan pulse SCAN applied to the first switching element M01 during the data writing step Tw can be generated within about 0.7 horizontal periods (0.7H). In this case, the data voltage Vdata of the pixel data is not applied through one switching element, but is applied through the first switching element M01 having a dual-gate structure, so that the charging characteristics can be improved.

[0138] During the boost step Tboost, the first switching element M01, the second switching element M02, and the third switching element M03 are turned off, and the voltage of the first node n1 and the voltage of the second node n2 increase.

[0139] In the light emission step Tem, the first switching element M01, the second switching element M02, and the third switching element M03 are maintained in the off state. At this time, a current generated by the gate-source voltage Vgs of the driving element DT (i.e., the voltage between the first node n1 and the second node n2) is supplied to the light emitting element EL, thereby causing the light emitting element EL to emit light.

[0140] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto, and the present disclosure can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the embodiments described above are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

Claims

1. A pixel circuit comprising: a driving element including a first electrode connected to a first power line to which a pixel driving voltage is applied, a gate electrode connected to a first node, and a second electrode connected to a second node; a first switching element including a first electrode connected to the second power line to which the data voltage is applied, a gate electrode to which the first scan pulse is applied, and a second electrode connected to the first node; a second switching element including a first electrode connected to the second power line, a gate electrode to which a second scan pulse is applied, and a second electrode connected to the first node; a light emitting element including an anode electrode connected to the second node and a cathode electrode connected to a third power line to which a low-potential power voltage is applied; as well as a capacitor connected between the first node and the second node, The turn-off time point of the second switch element varies with the RC delay or IR drop of the first power line, the second power line, and the third power line.

2. The pixel circuit according to claim 1, further comprising: a third switching element including a first electrode connected to a fourth power line to which an initialization voltage is applied, a gate electrode to which an initialization pulse is applied, and a second electrode connected to the first node; as well as A fourth switching element includes a first electrode connected to the second node, a gate electrode to which a sensing pulse is applied, and a second electrode connected to a fifth power line to which a reference voltage is applied.

3. The pixel circuit according to claim 1, wherein: Turn-on time points of the first switching element and the second switching element are the same, and turn-off time points of the first switching element and the second switching element are different from each other.

4. The pixel circuit according to claim 1, wherein: The voltage swing of the first scanning pulse is between the first gate-on voltage and the first gate-off voltage, and The voltage of the second scan pulse has a swing amplitude between the first gate-on voltage and a second gate-off voltage lower than the first gate-off voltage.

5. The pixel circuit according to claim 1, wherein: The voltage swing of the first scanning pulse is between the first gate-on voltage and the first gate-off voltage, and The voltage swing of the second scan pulse is between a second gate-on voltage higher than the first gate-on voltage and the first gate-off voltage. The pixel circuit according to claim 1 , wherein: The voltage swing of the first scanning pulse is between the first gate-on voltage and the first gate-off voltage, and The voltage of the second scan pulse has a swing amplitude between a second gate-on voltage higher than the first gate-on voltage and a second gate-off voltage lower than the first gate-off voltage.

7. The pixel circuit according to claim 1, wherein: During a period in which the data voltage is applied, a turn-on time point of the first switching element and a turn-on time point of the second switching element are different from each other.

8. A pixel circuit comprising: a driving element including a first electrode connected to a first power line to which a pixel driving voltage is applied, a gate electrode connected to a first node, and a second electrode connected to a second node; a first switching element including a first electrode connected to the second power line to which a data voltage is applied, a first gate electrode to which a first scan pulse is applied, a second gate electrode to which a second scan pulse is applied, and a second electrode connected to the first node; a second switching element including a first electrode connected to a fourth power line to which an initialization voltage is applied, a gate electrode to which an initialization pulse is applied, and a second electrode connected to the first node; a light emitting element including an anode electrode connected to the second node and a cathode electrode connected to a third power line to which a low-potential power voltage is applied; as well as a capacitor connected between the first node and the second node, The turn-off time point of the second switch element varies with the RC delay or IR drop of the first power line, the second power line, and the third power line.

9. The pixel circuit according to claim 8, further comprising: A third switching element includes a first electrode connected to the second node, a gate electrode to which a sensing pulse is applied, and a second electrode connected to a fifth power line to which a reference voltage is applied.

10. The pixel circuit according to claim 8, wherein: Turn-on time points of the first switching element and the second switching element are the same, and turn-off time points of the first switching element and the second switching element are different from each other.

11. A method for driving the pixel circuit according to any one of claims 1 to 10, comprising: Initializing the pixel circuit; sensing a threshold voltage of the driving element and storing the sensed threshold voltage in the capacitor; applying a data voltage of pixel data to the first node so that a voltage at the first node and a voltage at the second node increase; and Light is emitted through the light emitting element at a brightness corresponding to the grayscale value of the pixel data.

12. A display device comprising: a display panel in which a plurality of data lines, a plurality of gate lines intersecting the plurality of data lines, a plurality of power lines to which different constant voltages are applied, and a plurality of sub-pixels are provided; a data driver providing data voltages of pixel data to the plurality of data lines; as well as a gate driver providing gate signals to the plurality of gate lines; Each sub-pixel of the plurality of sub-pixels comprises: a driving element including a first electrode connected to a first power line to which a pixel driving voltage is applied among the plurality of power lines, a gate electrode connected to a first node, and a second electrode connected to a second node; a first switching element including a first electrode connected to a second power line to which a data voltage is applied among the plurality of power lines, a gate electrode to which a first scan pulse is applied, and a second electrode connected to the first node; a second switching element including a first electrode connected to the second power line, a gate electrode to which a second scan pulse is applied, and a second electrode connected to the first node; a light emitting element including an anode electrode connected to the second node and a cathode electrode connected to a third power line to which a low-potential power voltage is applied among the plurality of power lines; and a capacitor connected between the first node and the second node, The turn-off time point of the second switch element varies with the RC delay or IR drop of the first power line, the second power line, and the third power line.

13. The display device according to claim 12, wherein: Each of the plurality of sub-pixels further comprises: a third switching element including a first electrode connected to a fourth power line to which an initialization voltage is applied, a gate electrode to which an initialization pulse is applied, and a second electrode connected to the first node; and a fourth switching element including a first electrode connected to the second node, a gate electrode to which a sensing pulse is applied, and a second electrode connected to a fifth power line to which a reference voltage is applied among the plurality of power lines.

14. The display device according to claim 12, wherein: Turn-on time points of the first switching element and the second switching element are the same, and turn-off time points of the first switching element and the second switching element are different from each other.

15. The display device according to claim 12, wherein: The voltage swing of the first scanning pulse is between the first gate-on voltage and the first gate-off voltage, and The voltage of the second scan pulse has a swing amplitude between the first gate-on voltage and a second gate-off voltage lower than the first gate-off voltage.

16. The display device according to claim 12, wherein: The voltage swing of the first scanning pulse is between the first gate-on voltage and the first gate-off voltage, and A voltage of the second scan pulse is between a second gate-on voltage higher than the first gate-on voltage and the first gate-off voltage.

17. The display device according to claim 12, wherein: The voltage swing of the first scanning pulse is between the first gate-on voltage and the first gate-off voltage, and The voltage of the second scan pulse has a swing amplitude between a second gate-on voltage higher than the first gate-on voltage and a second gate-off voltage lower than the first gate-off voltage.

18. The display device according to claim 12, wherein: During a period in which the data voltage is applied, a turn-on time point of the first switching element and a turn-on time point of the second switching element are different from each other.

19. The display device according to any one of claims 12 to 18, wherein: The data driver, the gate driver, and all transistors in the sub-pixels are implemented using oxide thin film transistors including an n-channel oxide semiconductor.

20. A display device comprising: a display panel in which a plurality of data lines, a plurality of gate lines intersecting the plurality of data lines, a plurality of power lines to which different constant voltages are applied, and a plurality of sub-pixels are provided; a data driver providing data voltages of pixel data to the plurality of data lines; as well as a gate driver providing gate signals to the plurality of gate lines; Each sub-pixel of the plurality of sub-pixels comprises: a driving element including a first electrode connected to a first power line to which a pixel driving voltage is applied among the plurality of power lines, a gate electrode connected to a first node, and a second electrode connected to a second node; a first switching element including a first electrode connected to a second power line to which a data voltage is applied, a first gate electrode to which a first scan pulse is applied, a second gate electrode to which a second scan pulse is applied, and a second electrode connected to the first node; a second switching element including a first electrode connected to a fourth power line to which an initialization voltage is applied, a gate electrode to which an initialization pulse is applied, and a second electrode connected to the first node; a light emitting element including an anode electrode connected to the second node and a cathode electrode connected to a third power line to which a low-potential power voltage is applied among the plurality of power lines; and a capacitor connected between the first node and the second node, The turn-off time point of the second switch element varies with the RC delay or IR drop of the first power line, the second power line, and the third power line.

21. The display device according to claim 20, wherein Each of the plurality of sub-pixels further comprises: a third switching element including a first electrode connected to the second node, a gate electrode to which a sensing pulse is applied, and a second electrode connected to a fifth power line to which a reference voltage is applied among the plurality of power lines.

22. The display device according to claim 20 or 21, wherein: The data driver, the gate driver, and all transistors in the sub-pixels are implemented using oxide thin film transistors including an n-channel oxide semiconductor.

23. The display device according to claim 20 or 21, wherein: Turn-on time points of the first switching element and the second switching element are the same, and turn-off time points of the first switching element and the second switching element are different from each other.

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