Centralized placement of command and address swapping in memory devices

By centralizing the CA input circuitry within the memory device and using a switching circuit, the problem of high power consumption is solved, achieving more efficient power management and signal routing optimization.

CN115762585BActive Publication Date: 2026-07-10MICRON TECHNOLOGY INC

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
MICRON TECHNOLOGY INC
Filing Date
2020-02-07
Publication Date
2026-07-10

AI Technical Summary

Technical Problem

In memory devices, existing technologies struggle to effectively reduce power consumption, especially in the layout and routing design of CA input circuits, resulting in higher power consumption and longer signal routing lengths.

Method used

By centralizing the CA input circuitry within a compact CA interface area and employing a switching circuit to select the CA output, signal routing length and capacitive load are reduced, thereby lowering power consumption.

Benefits of technology

This achieves reduced power consumption in memory devices, reduced signal routing length, and improved operating efficiency and power utilization.

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Abstract

This application relates to centralized placement of command and address swapping in memory devices. A memory device, a memory system, and a system including a memory device have a bond pad region for coupling command and address (CA) input signals, and a memory cell region for storing information in memory cells. A centralized CA interface region includes input circuits coupled to the CA input signals. At least two of the input circuits are configured in pairs. Each pair includes a first input circuit coupled to a first input and configured to generate a first output, and a second input circuit coupled to a second input and configured to generate a second output. Each pair also includes a swap circuit disposed between the first input circuit and the second input circuit. The swap circuit selects one of the first output or the second output for a first internal signal and the other of the first output and the second output for a second internal signal in response to a control signal.
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