A ping-pong in-memory computing circuit based on capacitive coupling

Abstract

The application discloses a ping-pong type in-memory computing circuit based on capacitive coupling and belongs to the field of application specific integrated circuit design. The circuit comprises a computing array composed of ping-pong type in-memory computing units, a precision-adjustable quantization circuit depending on sparsity, a decoding circuit, a read-write driving circuit, a timing control circuit and a shift-addition circuit. The application is used for artificial intelligence neural network acceleration. Compared with a conventional macro unit used for neural network acceleration, the design can update weight values in a static random memory array while implementing multiplication and accumulation operations, so that the throughput of computation can be greatly improved when the acceleration of a network with more weight values is completed. The design uses a metal layer capacitor as a computing medium, so that higher area efficiency can be obtained. The design uses a precision-adjustable quantization circuit, so that higher energy efficiency can be obtained.

Description

Technical Field

[0001] This invention discloses a ping-pong in-memory computing circuit based on capacitive coupling, belonging to the field of application-specific integrated circuit design technology. Background Technology

[0002] In recent years, artificial intelligence has developed rapidly, deeply integrating into various fields and application scenarios, bringing great convenience to all aspects of life. Convolutional Neural Networks (CNNs) have become an important technology in machine learning, widely used in image recognition, speech and video recognition, and other areas of artificial intelligence. In the implementation of deep learning networks, the massive amount of data presents challenges related to workload, real-time performance, and security. Therefore, the design of low-power, high-performance AI chips and dedicated CNN hardware accelerators has become a hot research topic in both industry and academia.

[0003] In the traditional von Neumann computer architecture, the central processing unit (CPU) and memory transmit large amounts of data via a bus. The latency and power consumption waste caused by the massive data volume, along with the limited data transmission bandwidth, become the biggest bottlenecks in the traditional architecture. Therefore, in-memory computing (CIM) architectures have emerged. Since deep neural networks require performing numerous multiplication and accumulation (MAC) operations on input and weight data, their high reusability and high parallelism make them suitable for deployment in in-memory computing (CIM) circuits. This significantly reduces data transmission and energy consumption latency waste, thereby improving the system's energy efficiency and real-time performance, and has broad application prospects in high-energy-efficiency artificial intelligence systems.

[0004] However, with the increasing complexity and data volume of deep neural network models, the contradiction between the ever-growing number of parameters and the limited on-chip memory capacity exacerbates the need for updating weights. The limited write bandwidth of traditional on-chip memory, and the difficulty in simultaneous computation and updating, leads to significant weight update overhead, thereby reducing circuit performance. Simultaneously, current analog-domain in-memory computing circuits suffer from linearity issues, array internal ripple, and quantization overhead, resulting in limited computational accuracy and parallelism, thus restricting improvements in the energy efficiency of in-memory computing CIM. Summary of the Invention

[0005] Technical Problem: The purpose of this invention is to address the shortcomings of the aforementioned background technology by proposing a ping-pong in-memory computing circuit based on capacitive coupling, with the goal of high energy efficiency and low power consumption.

[0006] Technical Solution: This invention is a capacitively coupled ping-pong in-memory computing circuit, comprising: a capacitively coupled ping-pong in-memory computing array and a sparsity-dependent precision-adjustable quantization array; the capacitively coupled ping-pong in-memory computing array stores weight values, input feature values ​​are sent to the array, and the multiply-accumulate analog values ​​obtained from each column of the computing array are converted into digital signals by the corresponding quantization circuit, and then sent to the peripheral shift-add circuit to obtain the final calculated value. At the same time, the weight values ​​that need to be updated are written to the static random access memory inside the computing array through a read-write drive circuit; wherein, the multiply-accumulate calculation operation and the weight update operation are implemented by alternately using the upper multiplication unit UBMU and the lower multiplication unit DBMU to achieve the purpose of improving throughput.

[0007] The capacitively coupled ping-pong in-memory compute array (CPPCIM) consists of 64 compute columns, each column comprising 32 CPPCIM blocks. Each CPPCIM block consists of one upper multiplication unit (UBMU), one lower multiplication unit (DBMU), and one ping-pong compute unit (PPCC). The PPCC is positioned between the upper multiplication unit (UBMU) and the lower multiplication unit (DBMU). Both the upper and lower multiplication units (UBMU and DBMU) consist of four compact 6T static random access memory (SRAM) cells and four NMOS transistors (M1-M4) for gating. The gates of the first and second NMOS transistors are connected to the write gating signal, and the gates of the third and fourth NMOS transistors are connected to the compute unit (PPCC). The selection signal is calculated; the source and drain of the first NMOS transistor and the second NMOS transistor are connected to the global bit line and the local bit line, respectively, and the source and drain of the third NMOS transistor and the fourth NMOS transistor are connected to the local bit line and the calculation bit line, respectively; the ping-pong calculation unit PPCC is composed of a transmission gate formed by the fifth NMOS transistor and the PMOS transistor, a seventh NMOS transistor, and a metal layer MOM capacitor; the gates of the fifth NMOS transistor and the PMOS transistor are connected to the calculation bit line, and their sources and drains are connected to the input feature value signal corresponding to the input feature value and the internal node, respectively; the gate of the seventh NMOS transistor is connected to the calculation bit line, and its source and drain are connected to the internal node and ground; the upper and lower plates of the metal layer MOM capacitor are connected to the internal node and the multiply-accumulate bit line, respectively.

[0008] The sparsity-dependent precision-adjustable quantization array includes an input sensing detector and a one-sided successive approximation quantization circuit. The input sensing detector obtains the number of 0s in the 32 input feature values ​​of each cycle, compares them with a pre-set threshold, generates a corresponding precision configuration control signal, and sends it to the quantizer. The one-sided successive approximation quantization circuit includes a capacitive DAC array, a SAR logic-controlled quantization circuit, a dynamic latch amplifier, and a shift register. The capacitive DAC array uses metal-layer MOM capacitors with capacitance values ​​of 1C, 1C, 2C, 4C, 8C, and 16C. The upper stage of the capacitors is connected to the N-terminal of the differential input of the amplifier, and the lower stage of the capacitors is connected to the reference voltages VREF1 and VREF2 respectively through a switching circuit. The P-terminal of the differential input of the dynamic latch amplifier is connected to the multiply-accumulate bit line MBL obtained in the calculation array. The output of the amplifier is connected to the shift register, and the shift is controlled by a control signal to complete the multi-bit quantization operation. The output of the shift register is sent to an external shift-add circuit to realize the calculation from single-bit multiply-accumulate to multi-bit multiply-accumulate.

[0009] The ping-pong in-memory computing circuit supports four working modes: read, write, compute, simultaneous compute, and weight update. During the compute operation, 32 single-bit input feature values ​​are simultaneously sent to the compute unit of each column in one cycle. At the beginning of the compute cycle, the multiply-accumulate bit line and the input feature value signal of each compute column are pulled to ground by a self-timed asynchronous reset signal to clear the charge on the compute capacitor inside the compute unit, and then the compute is performed. Finally, quantization is performed.

[0010] The threshold of the input sensing detector is obtained by training a specific neural network with external software, statistically analyzing the sparsity of the input feature values ​​of each layer in the network, and obtaining the threshold used to configure the quantization accuracy. This reduces quantization power consumption and latency while ensuring accuracy.

[0011] The input sensing detector generates a corresponding precision configuration control signal by comparing with a threshold. Based on this precision configuration control signal, the quantizer circuit quantizes values ​​of different bit lengths. If the precision configuration is full precision 5 bits, the SAR logic control quantization circuit performs traditional full precision binary approximation quantization. If the precision configuration is non-full precision 3 bits, the SAR logic control quantization circuit skips the quantization of the high 2 bits, i.e., the high 2 bits are directly 0, and the low 3 bits are directly quantized. If the precision configuration is no quantization required, the quantizer is not enabled, and the quantization result is directly 0.

[0012] The sparsity-dependent precision-adjustable quantization array uses asynchronous SAR logic, meaning that regardless of the number of bits quantized, the quantization operation will be completed within the same clock cycle. Different quantization precision configurations will affect the operating frequency. The higher the sparsity of the input feature values, the lower the power consumption and delay overhead of quantization.

[0013] Beneficial Effects: This invention designs a ping-pong in-memory unit capable of simultaneous computation and weight value updates. To improve the linearity and area efficiency of in-memory computation in the analog domain, the in-memory unit uses metal-layer capacitors as the computation medium, employing a voltage divider based on capacitive coupling to obtain the voltage-divided calculated value on the multiply-accumulate bit lines. To further reduce the impact of fluctuations between quantization arrays, this invention uses a single-sided successive approximation quantization circuit SAR ADC, where the DAC array also uses metal-layer capacitors, ensuring circuit fluctuation matching between the P / N terminals of the comparator differential input. To reduce quantization overhead and improve energy efficiency, this invention uses a sparsity-dependent precision-adjustable quantization circuit to quantize the voltage values ​​on the multiply-accumulate bit lines, and finally obtains the final multi-bit convolution calculation result through an external shift-add circuit. It has the following advantages:

[0014] (1) By adopting a ping-pong type in-memory computing circuit, the weight value can be written at the same time as the calculation, reducing the weight update overhead and improving the throughput.

[0015] (2) The accumulation operation is achieved by using a metal layer MOM capacitor voltage divider, combined with a capacitor-type single-ended successive approximation quantization circuit, which reduces the chip area, effectively combats PVT fluctuations, and improves computational margin and accuracy.

[0016] (3) By adopting a sparsity-dependent quantization strategy and a hardware-software co-processing approach, the power consumption and delay of the quantization circuit can be effectively reduced and the energy efficiency improved through adjustable quantization precision configuration. Attached Figure Description

[0017] Figure 1 This is a block diagram of the ping-pong in-memory computing circuit based on capacitive coupling of the present invention.

[0018] Figure 2 This describes the operating mode of the ping-pong in-memory computing circuit based on capacitive coupling in this invention.

[0019] Figure 3 This is the ping-pong type storage unit of the present invention.

[0020] Figure 4 This is a functional waveform diagram of the ping-pong type memory unit of the present invention.

[0021] Figure 5 This invention relates to a precision-adjustable quantization circuit that depends on sparsity.

[0022] The diagram includes: first NMOS transistor M1, second NMOS transistor M2, third NMOS transistor M3, fourth NMOS transistor M4, fifth NMOS transistor M5, PMOS transistor M6, seventh NMOS transistor M7, write strobe USEL, calculation strobe CSEL; global bit lines GBL, GBLB, local bit lines LBL, LBLB, calculation bit lines CBL, CBLB, metal layer MOM capacitor Cc, input feature value signal IA, internal node Vc, and multiply-accumulate bit line MBL. Detailed Implementation

[0023] This invention designs a ping-pong in-memory computation circuit based on capacitive coupling that can simultaneously perform computation and weight value updates. To improve the linearity and area efficiency of analog domain in-memory computation, the in-memory unit uses a metal layer capacitor as the computation medium, and a voltage divider based on capacitive coupling is used to obtain the calculated value after voltage division on the multiply-accumulate bit lines. To further reduce the influence of fluctuations between quantization arrays, this invention employs a single-sided successive approximation quantization circuit SARADC, in which the DAC array also uses a metal layer capacitor, ensuring that the circuit connected to the P / N terminals of the comparator differential input is matched for fluctuations. To reduce quantization overhead and improve energy efficiency, this invention employs a sparsity-dependent precision-adjustable quantization circuit to quantize the voltage values ​​on the multiply-accumulate bit lines, and finally obtains the final multi-bit convolution calculation result through an external shift-add circuit.

[0024] The core design of the ping-pong in-memory computing circuit based on capacitive coupling of this invention includes: a ping-pong in-memory computing unit and a sparsity-dependent precision-adjustable quantization circuit.

[0025] The ping-pong in-memory computing unit consists of one upper multiplication unit (UBMU), one lower multiplication unit (DBMU), and one ping-pong in-memory computation (PPCC). The ping-pong in-memory computation PPCC is located between the upper multiplication unit (UBMU) and the lower multiplication unit (DBMU). Both multiplication units consist of four compact 6TB static random access memory (SRAM) cells and four NMOS transistors (M1-M4) for selection. The gates of the first NMOS transistor (M1) and the second NMOS transistor (M2) are connected to the write strobe signal (USEL), while the gates of the third NMOS transistor (M3) and the fourth NMOS transistor (M4) are connected to the computation strobe signal (CSEL). The write strobe signal (USEL) and the computation strobe signal (CSEL) are generated by external decoding and timing control circuits to control whether the upper multiplication unit (UBMU) and the lower multiplication unit (DBMU) perform computation or update operations. The two multiplication units share the ping-pong in-memory computation PPCC and the write drive circuit. Within the same clock cycle, the upper multiplication unit (UBMU) and the lower multiplication unit (DBMU) can simultaneously perform the calculation and update of weight values, respectively. They can interchange operations in different cycles, thus achieving ping-pong operation and improving throughput. The ping-pong in-memory computation (PPCC) consists of a transmission gate (composed of a fifth NMOS transistor M5 and a PMOS transistor M6), a seventh NMOS transistor M7, and a metal-layer MOM capacitor Cc. The gates of the fifth NMOS transistor M5 and the PMOS transistor M6 are connected to the computation bit lines CBL and CBLB, respectively, and their sources and drains are connected to the input feature value signal IA and the internal node Vc, respectively. The gate of the seventh NMOS transistor M7 is connected to the computation bit lines CBL and CBLB, and its source and drain are connected to Vc and GND. Cc is the metal-layer MOM capacitor, with its upper and lower plates connected to the internal node Vc and the multiply-accumulate bit line MBL, respectively. During a pre-computation reset, the input feature value signal IA is low, and the multiply-accumulate bit line MBL is also pulled low. At this time, regardless of the previous high or low level state of the computation bit lines CBL and CBLB, the internal node Vc and the multiply-accumulate bit line MBL are both low, and the charge on the computation metal-layer MOM capacitor Cc is cleared. After reset, calculation begins. In this calculation mode, the multiplication unit (BMU) reads the weight value of the corresponding storage unit onto the calculation bit lines CBL and CBLB. The input feature value signal IA is at the level corresponding to the input feature value, and the corresponding dot product result is reflected on the internal node Vc. The multiplication accumulation bit line MBL is in a floating state. According to the principle of charge conservation, the voltage division obtained on the multiplication accumulation bit line MBL reflects the multiplication accumulation result of the 32 CPCCIM blocks in the same column. Compared to calculation schemes that share current, time, and charge domains, the capacitively coupled calculation scheme adopted in this invention has higher linearity and is less affected by PVT fluctuations. The use of metal layer capacitors further reduces fluctuations while improving area efficiency.

[0026] The sparsity-dependent precision-tunable quantization circuit mainly consists of an input sensing detector and a single-sided quantizer. The threshold of the input sensing detector is obtained by training a specific neural network with external software, statistically analyzing the sparsity of the input feature values ​​of each layer in the network, and obtaining the threshold used to configure the quantization precision. This ensures accuracy while reducing quantization power consumption and latency overhead.

[0027] The input sensing detector obtains the number of 0s in the 32 input feature value signals IA sent to the memory array each cycle. By comparing this number with a pre-set threshold, a corresponding precision configuration control signal is generated and sent to the quantizer. Based on this precision configuration signal, the quantization circuit quantizes values ​​of different bit lengths. If the precision configuration is full precision (5 bits), the SAR logic controls the quantization circuit to perform traditional full-precision binary approximation quantization. If the precision configuration is non-full precision (3 bits), the SAR logic controls the quantizer to skip the quantization of the high 2 bits (i.e., the high 2 bits are directly 0) and directly perform the quantization of the low 3 bits. If the precision configuration is no quantization required, quantization is not enabled, and the quantization result is directly 0.

[0028] The single-sided successive approximation quantization circuit SARADC includes a capacitive DAC array, an asynchronous SAR logic control circuit, a dynamic latch amplifier, and a shift register. The capacitive DAC array uses metal-layer MOM capacitors with capacitance values ​​of 1C, 1C, 2C, 4C, 8C, and 16C. The upper stage of the capacitors is connected to the N-terminal of the amplifier, and the lower stage is connected to reference voltages VREF1 and VREF2 via switching circuits. The P-terminal of the dynamic latch amplifier is connected to the multiply-accumulate bit line MBL obtained from the calculation array. The amplifier output is connected to the shift register, and the shift is controlled by a control signal to complete the multi-bit quantization operation. The output of the shift register is sent to an external shift-add circuit to realize the calculation from single-bit multiply-accumulate to multi-bit multiply-accumulate.

[0029] Figure 1 The diagram illustrates the overall structure of a capacitively coupled ping-pong in-memory computing circuit. The entire circuit includes a 32x64 CPCCIMM block, a column-quantized array, a read / write driver circuit, a decoding circuit, an input buffer circuit, a timing control circuit, an I / O circuit, and a shift-and-add circuit. The I / O circuit receives the latched control signal; the input feature value is sent to the in-memory array via the input buffer circuit; the decoding circuit generates corresponding control signals based on the address and mode signals; the timing circuit generates self-timed pulses for reset, read / write, calculation, and quantization, thereby controlling the execution of each operation. This invention supports four operating modes: read mode, write mode, calculation mode, and calculation with simultaneous weight value update mode. It also supports adjustable precision configuration through hardware and software collaboration, as well as calculation of data with different bit depths.

[0030] The technical solution of the invention will now be described in detail with reference to the accompanying drawings.

[0031] The structural block diagram of the ping-pong in-memory computing circuit based on capacitive coupling of this invention is as follows: Figure 1 As shown, in ping-pong mode, the input feature value passes through the input buffer IABuffer circuit on the right and is then fed into the computation array in parallel. The decoding circuit on the left processes the address and control signals, opens the corresponding word lines, reads the weight values ​​from the memory into the PPCC of each memory cell, and obtains the corresponding multiply-accumulate value on the multiply-accumulate bit line MBL through capacitive voltage division. This value is then sent to the column quantization array below for quantization, and finally, the final calculated value is obtained through the peripheral shift-add circuit.

[0032] Figure 2 This demonstrates the operating mode of a ping-pong in-memory computing circuit based on capacitive coupling. This invention supports four operating modes: read mode, write mode, calculation mode, and calculation while simultaneously updating weight values. It also supports adjustable precision configuration through hardware and software collaboration, as well as calculations with data of varying bit lengths. The I / O circuit receives the latched control signal; the input feature value is sent to the in-memory array via an input buffer circuit; the weight value to be stored in the array is updated via a write drive circuit; the decoding circuit generates corresponding control signals based on the address and mode signals; and the timing circuit generates self-timed pulses for reset, read / write, calculation, and quantization, thereby controlling the execution of each operation.

[0033] Ping-pong type storage unit such as Figure 3As shown, it consists of one upper multiplication unit (UBMU), one lower multiplication unit (DBMU), and one ping-pong calculation unit (PPCC). The calculation unit PPCC is located between the upper multiplication unit (UBMU) and the lower multiplication unit (DBMU). Both multiplication units consist of four compact 6T static random access memory (SRAM) cells and four NMOS transistors (M1-M4) for selection. The gates of the first NMOS transistor (M1) and the second NMOS transistor (M2) are connected to the write strobe signal (USEL), while the gates of the third NMOS transistor (M3) and the fourth NMOS transistor (M4) are connected to the calculation strobe signal (CSEL). The upper multiplication unit (UBMU) and the lower multiplication unit (DBMU) are generated by external decoding and timing control circuits to control whether the upper multiplication unit (UBMU) and the lower multiplication unit (DBMU) perform calculation or update operations. The upper multiplication unit (UBMU) and the lower multiplication unit (DBMU) share the ping-pong in-memory calculation PPCC and write drive circuit. Within the same clock cycle, the upper multiplication unit (UBMU) and the lower multiplication unit (DBMU) can simultaneously perform calculation and weight value update operations, respectively. They can interchange operations in different cycles, thus achieving ping-pong operation and improving throughput. The ping-pong in-memory computation (PPCC) consists of a transmission gate (comprising a fifth NMOS transistor M5 and a PMOS transistor M6), a seventh NMOS transistor M7, and a metal layer MOM capacitor Cc. The gates of the fifth NMOS transistor M5 and the PMOS transistor M6 are connected to the computation bit lines CBL and CBLB, respectively, and their sources and drains are connected to the input feature value corresponding signal IA and the internal node Vc, respectively. The gate of the seventh NMOS transistor M7 is connected to the computation bit line, and its source and drain are connected to the internal node Vc and ground GND. The upper and lower plates of the metal layer MOM capacitor Cc are connected to the internal node Vc and the multiply-accumulate bit line MBL, respectively. When reset before computation, the input feature value corresponding signal IA is at a low level, and the multiply-accumulate bit line MBL is also pulled low. At this time, regardless of the previous high or low level state of the computation bit lines CBL and CBLB, the internal node Vc and the multiply-accumulate bit line MBL are both at a low level, and the charge on the computation metal layer MOM capacitor Cc is cleared. After reset, the calculation begins. At this time, the upper multiplication unit BMUM in the calculation mode reads the weight value of the corresponding storage unit and writes it to the calculation bit lines CBL and CBLB. At this time, the signal IA corresponding to the input feature value is at the level corresponding to the input feature value. The corresponding dot product result is reflected on the internal node Vc. The multiplication accumulation bit line MBL is in a floating state. According to the principle of charge conservation, the voltage division obtained on the calculation bit line reflects the multiplication accumulation result of 32 CPCCIM blocks in the same column.

[0034] Figure 4This diagram displays the functional waveforms of a ping-pong in-memory unit. The first eight clock cycles show the operation of the upper multiplication unit (UBMU) performing calculations and the lower multiplication unit (DBMU) updating weight values; the next eight clock cycles show the same operation. The input feature value signal IA is a buffered input feature value signal with reset. The internal node Vc is the dot product result of the in-memory unit. The multiply-accumulate bit line MBL is the multiply-accumulate value obtained by parallel calculation of 32 rows of in-memory units. ADCout is the quantized value of this column's quantization circuit, and PDCCout is the value after shifting and adding. Near-full precision calculation of INT8 multiplication can be completed in eight clock cycles.

[0035] Figure 5 The diagram shows a sparsity-dependent precision-adjustable quantization circuit, primarily consisting of an input sensing detector and a one-sided successive approximation quantizer. The threshold of the input sensing detector is determined by training a specific neural network using external software, statistically analyzing the sparsity of the input feature values ​​at each layer of the network, and obtaining the threshold used to configure the quantization precision. The input sensing detector obtains the number of 0s in the signal IA corresponding to the 32 input feature values ​​fed into the memory array each cycle. By comparing this number with the pre-set threshold, a corresponding precision configuration control signal is generated and sent to the quantization circuit. Based on this precision configuration signal, the quantization circuit quantizes values ​​of different bit depths. The one-sided successive approximation quantizer includes a capacitive DAC array, an asynchronous SAR logic control circuit, a dynamic latch amplifier, and a shift register. The capacitive DAC array uses metal-layer MOM capacitors with capacitance values ​​of 1C, 1C, 2C, 4C, 8C, and 16C. The upper stage of the capacitors is connected to the N-terminal of the differential input of the amplifier, and the lower stage is connected to reference voltages VREF1 and VREF2 via switching circuits. The differential input (P-terminal) of the dynamic latch amplifier is connected to the multiply-accumulate bit line (MBL) obtained in the computational array. The amplifier's output is connected to a shift register, and the shift is controlled by a control signal to complete the multi-bit quantization operation. The output of the shift register is sent to an external shift-add circuit to realize the calculation from single-bit multiply-accumulate to multi-bit multiply-accumulate.

[0036] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A ping-pong in-memory computing circuit based on capacitive coupling, characterized in that, The in-memory computing circuit includes: a capacitively coupled ping-pong in-memory computing array and a sparsity-dependent precision-adjustable quantization array. The capacitively coupled ping-pong in-memory computing array stores weight values. Input feature values ​​are sent to the array, and the multiply-accumulate analog values ​​obtained from each column of the computing array are converted into digital signals by the corresponding quantization circuit, and then sent to the peripheral shift-add circuit to obtain the final calculated value. At the same time, the weight values ​​that need to be updated are written to the static random access memory inside the computing array through the read-write drive circuit. The multiply-accumulate calculation operation and the weight update operation are implemented by alternately using the upper multiplication unit UBMU and the lower multiplication unit DBMU to achieve the purpose of improving throughput. The capacitively coupled ping-pong in-memory compute array (CPPCIM) consists of 64 compute columns, each column comprising 32 CPCCIM blocks. Each CPCCIM block consists of one upper multiplication unit (UBMU), one lower multiplication unit (DBMU), and one ping-pong compute unit (PPCC). The PPCC is positioned between the upper multiplication unit (UBMU) and the lower multiplication unit (DBMU). Both the upper and lower multiplication units (UBMU and DBMU) consist of four compact 6T... The system consists of a static random access memory and four NMOS transistors M1 to M4 for gating. The gates of the first NMOS transistor (M1) and the second NMOS transistor (M2) are connected to the write gating (USEL) signal, and the gates of the third NMOS transistor (M3) and the fourth NMOS transistor (M4) are connected to the compute gating (CSEL) signal. The source and drain of the first NMOS transistor (M1) and the second NMOS transistor (M2) are connected to the global bit line (GBL, GBLB) and the local bit line (LBL, LBLB), respectively, and the source and drain of the third NMOS transistor (M3) and the fourth NMOS transistor (M4) are connected to the local bit line (LBL, LBLB) and the compute bit line (CBL, CBLB), respectively. The ping-pong computing unit (PPCC) consists of a transmission gate composed of a fifth NMOS transistor (M5) and a PMOS transistor (M6), a seventh NMOS transistor (M7), and a metal layer MOM capacitor (Cc). The gates of the fifth NMOS transistor (M5) and the PMOS transistor (M6) are connected to the computing bit lines (CBL, CBLB), and their sources and drains are connected to the input feature value signal (IA) corresponding to the input feature value and the internal node (Vc), respectively. The gate of the seventh NMOS transistor (M7) is connected to the computing bit lines (CBL, CBLB), and its source and drain are connected to the internal node (Vc) and ground. The upper and lower plates of the metal layer MOM capacitor (Cc) are connected to the internal node (Vc) and the multiply-accumulate bit line (MBL), respectively.

2. The ping-pong in-memory computing circuit based on capacitive coupling according to claim 1, characterized in that, The sparsity-dependent precision-adjustable quantization array includes an input sensing detector and a one-sided successive approximation quantization circuit (SARADC). The input sensing detector obtains the number of 0s in the 32 input feature values ​​(IA) of each cycle, compares them with a pre-set threshold, generates a corresponding precision configuration control signal, and sends it to the quantizer. The one-sided successive approximation quantization circuit includes a capacitive DAC array, a SAR logic-controlled quantization circuit, a dynamic latch amplifier, and a shift register. The capacitive DAC array uses metal-layer MOM capacitors. The capacitors have capacitance values ​​of 1C, 1C, 2C, 4C, 8C, and 16C, respectively. The upper stage of the capacitors is connected to the N-terminal of the differential input of the amplifier. The lower stage of the capacitors is connected to the reference voltages VREF1 and VREF2 through a switching circuit. The P-terminal of the differential input of the dynamic latch amplifier is connected to the multiply-accumulate bit line MBL obtained in the calculation array. The output of the amplifier is connected to the shift register. The shift is controlled by the control signal to complete the multi-bit quantization operation. The output of the shift register is sent to the external shift-add circuit to realize the calculation from single-bit multiply-accumulate to multi-bit multiply-accumulate.

3. The ping-pong in-memory computing circuit based on capacitive coupling according to claim 1, characterized in that, The ping-pong in-memory computing circuit supports four working modes: read, write, compute, simultaneous compute, and weight update. During the compute operation, 32 single-bit input feature values ​​are sent to each column's compute unit simultaneously in one cycle. At the beginning of the compute cycle, the multiply-accumulate bit line (MBL) and the input feature value signal (IA) of each compute column are pulled to ground by a self-timed asynchronous reset signal to clear the charge on the compute capacitor inside the compute unit, and then the compute is performed. Finally, quantization is performed.

4. The ping-pong in-memory computing circuit based on capacitive coupling according to claim 2, characterized in that, The threshold of the input sensing detector is obtained by training a specific neural network with external software, statistically analyzing the sparsity of the input feature values ​​of each layer in the network, and obtaining the threshold used to configure the quantization accuracy. This reduces quantization power consumption and latency while ensuring accuracy.

5. The ping-pong in-memory computing circuit based on capacitive coupling according to claim 4, characterized in that, The input sensing detector generates a corresponding precision configuration control signal by comparing with a threshold. Based on this precision configuration control signal, the quantizer circuit quantizes values ​​of different bit lengths. If the precision configuration is full precision 5 bits, the SAR logic control quantization circuit performs traditional full precision binary approximation quantization. If the precision configuration is non-full precision 3 bits, the SAR logic control quantization circuit skips the quantization of the high 2 bits, i.e., the high 2 bits are directly 0, and the low 3 bits are directly quantized. If the precision configuration is no quantization required, the quantizer is not enabled, and the quantization result is directly 0.

6. The ping-pong in-memory computing circuit based on capacitive coupling according to claim 1, characterized in that, The sparsity-dependent precision-adjustable quantization array uses asynchronous SAR logic, meaning that regardless of the number of bits quantized, the quantization operation will be completed within the same clock cycle. Different quantization precision configurations will affect the operating frequency. The higher the sparsity of the input feature values, the lower the power consumption and delay overhead of quantization.

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