Firmware power sequencing in memory subsystems

Abstract

The present disclosure relates to firmware power-up sequencing in a memory subsystem. A front-end firmware component of a memory subsystem: receives a first request to perform a first set of initialization operations, wherein the front-end component communicates with a back-end component in a data path associated with a memory device of the memory subsystem; initiates the first set of initialization operations of the front-end component in parallel with initiating a second set of initialization operations of the back-end component in response to receiving the first request; sends a first notification to a host computer system in response to completing the first set of initialization operations to indicate that the front-end component is available to respond to a request for configuration data associated with the memory subsystem; receives a second request for configuration data associated with the memory subsystem from the host computer system, wherein the second request is received before the back-end component has completed the second set of initialization operations; and provides the configuration data to the host computer system in response to receiving the second request from the host computer system before the back-end component has completed the second set of initialization operations.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory subsystems, and more specifically, to firmware power-up sequencing in a memory subsystem. BACKGROUND

[0002] A memory subsystem can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at a memory device and to retrieve data from a memory device. SUMMARY

[0003] According to aspects of the present disclosure, a method is provided. The method includes receiving, by a processing device that executes a front-end component of a memory subsystem, a first request to execute a first set of initialization operations, wherein the front-end component communicates with a back-end component in a data path associated with a memory device of the memory subsystem; in response to receiving the first request, initiating the first set of initialization operations of the front-end component in parallel with initiating a second set of initialization operations of the back-end component; in response to completing the first set of initialization operations, sending a first notification to a host computer system to indicate that the front-end component is available to respond to a request from the host computer system for configuration data associated with the memory subsystem; receiving a second request from the host computer system for configuration data associated with the memory subsystem, wherein the second request is received before the back-end component has completed the second set of initialization operations; and in response to receiving the second request from the host computer system before the back-end component has completed the second set of initialization operations, providing the configuration data to the host computer system.

[0004] According to another aspect of the present disclosure, a method is provided. The method includes receiving, by a processing device that executes a back-end component of a memory subsystem, a first request to execute a first set of initialization operations, wherein the back-end component communicates with a front-end component in a data path associated with a memory device of the memory subsystem; in response to receiving the first request, reserving a set of file system resources to prevent allocation of the set of file system resources to a subsequently received request from the front-end component to access the memory device; initiating the first set of initialization operations of the back-end component, wherein the first set of initialization operations is executed in parallel with a second set of initialization operations executed by the front-end component; and in response to completing the first set of initialization operations, releasing the set of file system resources to allow allocation of the set of file system resources to the subsequently received request.

[0005] According to another aspect of the present disclosure, a system is provided. The system includes: a plurality of memory devices; and a processing device operatively coupled to the plurality of memory devices to perform operations comprising: receiving, by the processing device executing a front-end component of a memory subsystem, a first request to perform a first set of initialization operations, wherein the front-end component communicates with a back-end component in a data path associated with the memory devices of the memory subsystem; in response to receiving the first request, initiating the first set of initialization operations for the front-end component in parallel with initiating a second set of initialization operations for the back-end component; in response to completing the first set of initialization operations, sending a first notification to a host computer system indicating that the front-end component is available to respond to a request from the host computer system for configuration data associated with the memory subsystem; receiving, from the host computer system, a second request for configuration data associated with the memory subsystem, wherein the second request is received before the back-end component has completed the second set of initialization operations; and in response to receiving the second request from the host computer system before the back-end component has completed the second set of initialization operations, providing the configuration data to the host computer system. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2 is a flow chart of an example method to facilitate improved firmware power-up sequencing by a front-end firmware component in a memory subsystem, according to some embodiments of the present disclosure.

[0009] Figure 3 A block diagram illustrating a memory subsystem including a firmware management component to facilitate improved firmware power-up sequencing in the memory subsystem according to some embodiments of the present disclosure.

[0010] Figure 4 is a flow chart of an example method to facilitate improved firmware power-up sequencing by back-end firmware components in a memory subsystem, according to some embodiments of the present disclosure.

[0011] Figure 5 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0012] Various aspects of the present disclosure relate to firmware power-up sequencing in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. Generally speaking, a host system can utilize a memory subsystem that includes one or more components, such as memory devices, that store data. The host system can provide data to be stored at the memory subsystem and can request retrieval of data from the memory subsystem.

[0013] The memory subsystem may include a high-density non-volatile memory device, where data needs to be retained when no power is supplied to the memory device. An example of a non-volatile memory device is a NAND memory device. Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more die. Each die can be composed of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a collection of physical blocks. Each block is composed of a collection of pages. Each page is composed of a collection of memory cells ("cells"). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more bits of binary information and have various logical states related to the number of bits being stored.

[0014] A non-volatile memory device may implement a cross-point memory architecture. One example of a cross-point memory architecture is a three-dimensional cross-point (3D cross-point) memory architecture. A 3D cross-point memory architecture may be byte-addressable (e.g., similar to dynamic random access memory (DRAM)). A 3D cross-point memory array may include a stackable cross-point architecture in which cells are located at the intersection of row address lines (word lines or WLs) and column address lines (bit lines or BLs) arranged in a grid. More specifically, the WLs and BLs cross in the formation of a grid, and each 3D cross-point memory cell ("3D cross-point cell") may be coupled between the WL and the BL at the intersection. At the intersection, the WL and the BL may be located in different vertical planes such that the WL spans the BL without physical contact. The 3D cross-point architecture may be stacked to improve storage density such that the WL may span a first BL located below the WL and a second BL located above the WL.

[0015] The memory subsystem controller can perform access operations on the memory device, such as read operations, program operations, erase operations, etc. The memory subsystem controller can include a firmware data path that facilitates processing requests from the host computing system and performing access operations on the memory device. The firmware data path can include a front-end component that manages communications with the host computing system and a back-end component that manages a file system and access operations performed on the memory device. The firmware data path can also include a security component between the front-end and back-end components that manages secure access to the memory device (e.g., authentication, encryption, decryption, etc.).

[0016] In conventional memory subsystems, when the memory subsystem is powered on, various initialization operations are performed to boot components in the firmware data path. For example, the front-end component may perform operations to establish communication with the host and to initialize memory regions used in conjunction with managing requests received from the host and responses provided to the host. The security component may perform operations to establish encryption / decryption key agreements with the back-end and other security-related boot operations. The back-end may perform operations to initialize the file system and perform memory rebuild operations for the memory device. In conventional systems, the boot-up of these components is typically synchronized, one after the other, so that security component initialization does not begin until back-end initialization is complete, and front-end initialization cannot complete until both security component initialization and back-end initialization are complete.

[0017] These types of traditional boot configurations typically result in longer overall memory subsystem power-up times. Specifically, the front end waits until the back end has completed its initialization to respond to any requests from the host, even if those requests do not involve performing input / output (I / O) operations. For example, the front end typically does not accept a request from the host for configuration information associated with the memory subsystem (e.g., information associated with the type of memory subsystem controller) until the back end is fully operational. Conventional systems with a larger number of memory devices may involve much longer back end initializations, which can result in extended power-up delays.

[0018] Conventional memory subsystems attempt to mitigate these issues by reducing the amount of time required for back-end initialization. While these types of solutions can reduce back-end power-up time to a certain extent, they still involve the front-end waiting for the back-end to become ready. Consequently, there is often still a delay in processing host requests not associated with I / O operations, which can violate service level agreements and industry availability standards.

[0019] Various aspects of the present disclosure address the above and other deficiencies by improving the synchronization of various firmware components during system power-up to reduce the overall boot initialization time of the firmware data path and significantly reduce the delay when the front-end processes non-I / O requests from the host. In one embodiment, the firmware management component of the memory subsystem controller can initiate initialization operations for the front-end, security component, and back-end in parallel to improve the overall boot time. After completing its initialization, the front-end can notify the host that it is able to respond to non-I / O related requests (for example, requests for configuration information that do not involve interfacing with the memory device). After completing its initialization, the security component can begin sending file system requests and encryption / decryption requests to the back-end without waiting for the back-end to complete its initialization. The back-end can establish a request queuing mechanism before starting initialization to receive requests and hold the requests until initialization is complete. Once completed, the back-end can begin servicing the requests in the queue.

[0020] Advantages of the present disclosure include, but are not limited to, a significant reduction in the overall boot time of the memory subsystem. By initiating the initialization operation of each component in parallel, the total time to achieve media device availability can be significantly reduced. In addition, by configuring the front-end components to process non-I / O related requests from the host before the back-end has completed initialization, the delay in responding to some requests can be greatly reduced, thereby providing the ability to meet narrower service level agreements and industry standards for availability. In addition, by configuring the back-end to queue requests while performing its initialization operation, other components of the firmware data path do not need to wait for the back-end to be fully available before commencing normal operation. This, in turn, can significantly improve overall memory subsystem performance and availability efficiency.

[0021] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of these.

[0022] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

[0023] The computing system 100 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0024] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0025] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110 to, for example, write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0026] The host system 120 can be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel interface, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), and the like. The physical host interface can be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a physical host interface (e.g., a PCIe bus), the host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface can provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1Memory subsystem 110 is illustrated as an example. Generally speaking, host system 120 can access multiple memory subsystems via the same communication connection, multiple independent communication connections, and / or a combination of communication connections.

[0027] Memory devices 130 and 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0028] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, in which non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0029] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), and penta-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of these. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory devices 130 may be grouped into pages, which may refer to logical units of a memory device for storing data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0030] Although nonvolatile memory components such as a 3D cross-point nonvolatile memory cell array and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), auto-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non-OR flash memory or electrically erasable programmable read-only memory (EEPROM).

[0031] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, as well as other such operations. The memory subsystem controller 115 can include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0032] The memory subsystem controller 115 may include a processing device including one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0033] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0034] Generally speaking, the memory subsystem controller 115 may receive commands or operations from the host system 120 and convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0035] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0036] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) can externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is a raw memory device 130 with on-die control logic (e.g., local controller 132) and a controller for media management (e.g., memory subsystem controller 115) within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0037] The memory subsystem 110 may include a firmware management component 113 that can be used to facilitate improved firmware power-up sequencing by firmware components in the memory subsystem 110. In some embodiments, the memory subsystem controller 115 includes at least a portion of the firmware management component 113. In some embodiments, the firmware management component 113 is part of the host system 110, an application, or an operating system. In other embodiments, the local media controller 135 includes at least a portion of the firmware management component 113 and is configured to perform the functionality described herein.

[0038] In various implementations, the firmware management component 113 can receive a request to perform a set of initialization operations for a front-end component of the firmware, where the front-end component communicates with the secure component and back-end component of the firmware in a data path associated with the memory devices 130, 140. In response to receiving the request, the firmware management component 113 can initiate a set of initialization operations for the front-end in parallel with the initiation of a set of initialization operations for the back-end. In response to completion of the set of initialization operations for the front-end, the firmware management component 113 can send a notification to the host system 120 to indicate that the front-end is available to respond to requests from the host (e.g., non-I / O related requests) for configuration information associated with the subsystem controller 115. In response to receiving such a request from the host system 120 prior to the back-end having completed its initialization, the firmware management component 113 can provide a response to the request (e.g., provide the requested configuration data).

[0039] Additionally, the firmware management component 113 can initiate a set of initialization operations for the back-end. As noted, these operations can be performed in parallel with the operations performed by the front-end. In response to receiving this request, the firmware management component 113 can facilitate the reservation of file system resources managed by the back-end to prevent the allocation of these resources to any requests received from the front-end or secure component subsequent to the request to access the memory devices 130, 140. Once the resources have been reserved, the firmware management component 113 can initiate the initialization operations for the back-end. If a request is received by the back-end during the performance of the initialization operations, the back-end can add the request to a request queue until the reserved resources are released due to the file system resources being reserved. Once the back-end completes its initialization, the resources can be released to allow their allocation to any queued requests as well as any newly received requests.

[0040] Additional details regarding the operation of the firmware management component 113 are described below with respect to Figures 2-4

[0041] Figure 2 is an example method 200 that facilitates improved firmware power-on sequencing by a front-end firmware component in a memory subsystem, in accordance with some embodiments of the present disclosure. The method 200 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 200 is performed by the firmware management component 113. Figure 1 ​The firmware management component 113 performs. Although shown in a particular order or sequence, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the processes illustrated can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0042] At operation 210, processing logic can receive, by a front-end component of memory sub-system firmware, a request to perform a set of initialization operations during a power-up sequence of a memory sub-system (e.g., Figure 1 In various implementations, the front-end component can be configured to execute in a data path associated with a memory device (or devices) of the memory devices 130, 140 in the memory sub-system 110 in Figure 1 As noted above, the data path can also include a back-end component that manages interactions with the memory devices in the memory sub-system (e.g., I / O operations, file system management, etc.). Additionally, the data path can include a security component that manages authentication of commands received from the front-end and forwarded to the back-end component, encryption / decryption of data, cryptographic key synchronization exchanges with the back-end component, and other similar operations.

[0043] In various implementations, processing logic can receive the request from a scheduling component of firmware that manages power-up sequencing of various firmware components. In other implementations, processing logic can receive the request from another component of the memory sub-system controller.

[0044] At operation 220, processing logic can initiate, in response to receiving the request at operation 210, a group of initialization operations of the front-end component in parallel with initiating a second group of initialization operations of the back-end component. In various implementations, the initialization operations of the front-end can include identifying configuration information associated with the memory sub-system. In some implementations, this information can be loaded into a local memory space to facilitate efficient response to requests for configuration information received from host computer systems. Additionally, the initialization operations can include identifying connected host computer systems and configuring and / or implementing connectivity with these systems in preparation for receiving requests. In some implementations, the initialization operations can additionally include configuring regions of memory for queuing received commands until other firmware components in the data path (e.g., back-end components, security components, etc.) have completed initialization and are ready to receive commands / requests. As noted below with respect to Figure 4 As noted below with respect to

[0045] At operation 230, the processing logic may, in response to completing the initialization operation of the front end, send a notification to the connected host computer system to indicate that the front end is available to respond to requests from the host for configuration information associated with the memory subsystem. In various embodiments, the request for configuration information from the host may include an "identify controller" request that requests from the memory subsystem information that identifies and / or describes the memory subsystem controller device and its configuration attributes and / or capabilities. Additionally, the request from the host may include a request to create a memory queue, a request to complete a memory queue, or a request to perform a non-I / O operation (e.g., any other type of request that does not involve a file system, does not perform an I / O operation, or that can otherwise be performed solely by the front end).

[0046] Notably, by enabling these types of requests to be accepted and processed before access to the file system and / or access to the storage device has been enabled, host initialization operations can be initiated within a smaller time window, thereby being able to support shorter service level agreement requirements without incurring costly reconfiguration of back-end initialization.

[0047] As noted above, the data path may also include a security component of the firmware that manages command / request authorization, encryption / decryption operations, and the like. In such cases, the front-end may forward I / O-based requests to the back-end via the security component. For example, upon receiving a request from the host to perform an I / O operation (read, write, etc.), the front-end may forward the request to the security component. The security component may validate the request (e.g., confirm that the request was received from an authorized requestor, confirm that the request was encrypted using a valid encryption key, etc.), perform the encryption / decryption operation, and then forward the request to the back-end. Once the request has been validated by the security component, the back-end may receive the request and perform the applicable file system or I / O operation.

[0048] In such embodiments, at operation 230, the processing logic can also send a notification to the security component to cause the security component to perform its own set of initialization operations. As with the notification sent to the host, the processing logic can send the notification to the security component in response to completing the front-end initialization operations. In some cases, the processing logic can send this notification to the security component at approximately the same time that it sends the notification to the host, as described above. Alternatively, the processing logic can send the notification to the security module before or after sending the notification to the host. In other embodiments, the processing logic can send the notification to the security component before completing the front-end initialization. In such cases, the initialization operations of the front-end, security component, and back-end can all be initiated in parallel. In various embodiments, the notification sent to the security component can cause the security component to perform initialization operations such as encryption / decryption initialization, cryptographic synchronization exchange operations with the back-end to confirm encryption / decryption protocols and keys, or other similar operations.

[0049] At operation 240, the processing logic can receive a request from the host system (e.g., host computer system 120 in FIG. 1) for configuration information associated with the memory sub-system. These types of requests are described above with respect to operation 230. In various embodiments, this request can be received before the back-end component has completed its initialization operations. As noted above, the processing logic can process these requests without waiting for the back-end to complete its initialization. In some embodiments, because no access to the back-end is required, the processing logic can process these types of requests from the host without first checking the status of back-end initialization. At operation 250, the processing logic can provide configuration data to the host in response to receiving the request from the host before the back-end component has completed its initialization operations. Figure 1

[0050] In some embodiments, the front-end component can additionally monitor the status of the back-end component in order to determine when I / O commands can be forwarded to the back-end via the security component. In such cases, the processing logic can send a request to the back-end for information associated with the status of the initialization operations of the back-end. In response to receiving a response to the request, the processing logic of the front-end can determine the completion status of the back-end initialization. In other embodiments, the back-end can proactively send a broadcast notification to the front-end (and security component) to indicate that the back-end has completed initialization and can receive requests to perform I / O operations involving associated memory devices in the memory sub-system.

[0051] ​In response to determining that the completion status of the backend indicates that the backend initialization operation has not yet completed, the processing logic may prevent requests from the host to perform I / O operations from being forwarded to the backend. In some embodiments, the processing logic may completely deny the request. In these cases, in response to receiving a request from the host to perform an I / O operation associated with a memory device in the memory subsystem, the processing logic may send a response to the host indicating that the memory device is unavailable. Alternatively, the processing logic may send a notification to the host to indicate to the host that the memory device is unavailable, which causes the host to hold any requests to perform I / O operations associated with the memory device.

[0052] In other embodiments, the front end may receive I / O requests from the host, but hold the I / O requests in a request queue until the back end has completed initialization. In such cases, in response to determining that the back end's completion status indicates that the back end initialization operation has not yet completed, the processing logic may notify the host that the front end is available to receive requests to perform I / O operations. In response to receiving such requests, the processing logic of the front end component may store the requests in a request queue. Once the front end's processing logic determines that the back end is available, it may remove the stored requests from the queue and forward the requests to the back end.

[0053] In response to determining that the completion status of the backend indicates that the backend initialization operation has completed, the processing logic may enable the host to send a request to perform an I / O operation. In such a case, the processing logic may send a notification to the host to indicate that the front end is available to receive and respond to requests to perform I / O operations. In response to receiving such a request, the processing logic of the front end may forward the request to the back end. As noted above, in some embodiments, the received request may be forwarded to the back end via a security component of the data path. In such a case, the processing logic may send the request to the security component, causing the security component to authenticate the request (e.g., verify the source of the request to be authorized to access the memory device, decrypt the request from the front end, encrypt the request to the back end, etc.), and then forward the request to the back end component.

[0054] Figure 3 The present disclosure includes a firmware management component 113 (e.g., Figure 1 FIG. 1 is a block diagram of a memory subsystem 300 that includes a firmware management component 113 of a memory subsystem 110 in FIG. 1 to facilitate improved firmware power-up sequencing in a firmware path. Figure 3 One boot sequence is depicted in FIG. 1 , and in other embodiments, aspects of the present disclosure may be applied to different boot sequences for firmware components.

[0055] like Figure 3 As shown in and as above with respect to Figure 2 Compared with the followingFigure 4 As described, the firmware management component 113 can manage and synchronize the startup sequence of the front-end component 310, the security component 320, and the back-end component 330 in the firmware data path. As shown, the front-end 310 can receive a request (or other notification / indication) to perform a set of initialization operations (depicted as initialization start 311). At approximately the same time, the back-end 330 can receive a request to perform its own set of initialization operations (depicted as initialization start 331).

[0056] In response to receiving these requests, the front end 310 may initiate its own initialization operation (initialization 312) in parallel with the back end 330 initiating its initialization operation (initialization 333). In response to completing its initialization operation (initialization 312), the front end 310 may send a notification to the host 120 (e.g., Figure 1 140) to indicate that the front end 310 can respond to non-I / O requests (non-I / O request 313). As described above, this allows the front end 310 to service a request for configuration information (e.g., a request to "identify controller") from the host 120 before the back end has reported that access to the memory devices 130, 140 has been enabled for I / O requests.

[0057] As shown, in response to completing its initialization operations (initialize 312), the front end 310 may also send a notification to the security component 320 to initiate its own initialization operations (initialize 321). Once the security component 320 completes its set of initialization operations, it may send a notification to the front end 310 to indicate that it has completed its initialization operations and is ready to receive requests from the front end 310 (ready 322). Additionally, once the security component 320 has completed its initialization, it may also begin sending file system and / or security requests (f / s requests 323) to the back end 330.

[0058] As noted above, and with respect to Figure 4 Describing in more detail, the backend 330 may receive a request to perform a set of initialization operations for itself (initialization start 331). In response to receiving this request, the backend 330 may reserve file system resources that can be used to perform the received I / O and file system requests (reserve 322). This reservation process may be performed to allow requests from the frontend 310 and / or security component 320 to be received without rejecting them. Specifically, by reserving resources, the currently existing request processing infrastructure may be utilized to queue the received requests (enqueue 334) until the resources are released (release 335).

[0059] Once the applicable file system resources have been reserved, the backend 330 may perform its set of initialization operations (initialization 333). As noted above, any file system request (f / s request 323) may be added to a request queue (enterer 334) managed by the backend 330. Although not in Figure 3 , but in some embodiments, requests may be received from the front end 310 as well as the security component 320. In response to completing its initialization operations, the head end 330 may release any reserved file system resources and begin processing requests from the request queue (release 335).

[0060] Once the resources have been released, the backend 330 may send a notification to the frontend 310 indicating that the backend has completed its initialization operations and that the memory devices 130, 140 are available to service I / O requests (Ready 336). Subsequently, in response to determining that both the backend 330 and the security component 320 are ready to receive requests to perform I / O operations, the frontend 310 may send a notification to the host 120 indicating that the frontend 310 is available to respond to I / O requests. Upon receiving the I / O request (I / O 315), the frontend 310 may forward the request to the security component 320, which may perform any applicable security / encryption / decryption / authorization-related operations. The security component 320 may then forward the I / O request (I / O 324) to the backend 330 for processing. The backend 330 may receive the request and perform the necessary I / O operation (e.g., a read operation, a write operation, a delete operation, etc.) associated with the request (I / O 337). The backend 330 may then return a response, which is forwarded to the host 120 via the firmware data path (secure component 320 and then frontend 310). Figure 4 Additional details regarding the operations performed by backend 330 are described.

[0061] Figure 4 is a flow chart of an example method 400 for facilitating improved firmware power-up sequencing by back-end firmware components in a memory subsystem according to some embodiments of the present disclosure. The method 400 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1 The firmware management component 113 of FIG. 10 is executed. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0062] At operation 410, processing logic may receive, via a back-end component of the memory subsystem firmware, a request for a memory subsystem (eg, Figure 1 As noted above, in some embodiments, the back-end components may be configured to execute a set of initialization operations during a power-up sequence of the memory subsystem 110 in the memory subsystem. Figure 1 The firmware component executes in a data path associated with a memory device (or multiple memory devices) such as the memory devices 130, 140 in the example embodiment and communicates with other firmware components in the data path. Furthermore, as noted above, the data path may also include a front-end component that manages interaction with the host computer system and a security component that manages authentication of commands received from the front-end and forwarded to the back-end component, encryption / decryption of data, encryption key synchronization with the back-end component, and other similar operations.

[0063] In various embodiments, the processing logic may receive the request from a scheduling component of the firmware that manages the power-up sequencing of the various firmware components. In other embodiments, the processing logic may receive the request from another component of the memory subsystem controller. For example, the request may be received from a front-end component so that the processing logic of the back-end can initiate an initialization operation for the back-end in parallel with the front-end initiating the front-end initialization operation.

[0064] At operation 420, processing logic may, in response to receiving the request at operation 410, reserve a set of file system resources to prevent the execution of I / O or file system operations. By reserving the file system resources, processing logic may prevent those resources from being allocated to any subsequent requests received from the front end or security component to access memory devices in the memory subsystem. In various embodiments, processing logic may perform the reservation operation by setting a flag, token, semaphore, etc. to mark the resources as being in use, thereby queuing received requests rather than rejecting them.

[0065] In an illustrative example, processing logic may receive a request after file system resources have been reserved (a request received after the resource reservation). This subsequent request may be received from the front-end or security component to perform an I / O or file system operation associated with a memory device in the memory subsystem. For example, the security component may send a request for configuration information associated with the encryption protocol used by the back-end, a request to perform an encryption key synchronization operation (e.g., an operation associated with establishing an agreement between the security component and the back-end regarding encryption keys / protocols), etc. Additionally, the front-end or security module may send a request for file system configuration information. Similarly, the request may be to perform an I / O operation. In response to receiving the request, processing logic on the back-end may identify the requested file system resources and determine whether those requested resources are available. Since operation 420 should have reserved the file system resources, processing logic may determine that the requested resources are not available, causing processing logic to hold the request until the resources are released. In such cases, processing logic may add the subsequent request to a request queue until the requested resources become available.

[0066] At operation 430, processing logic may initiate a group of backend initialization operations. In some embodiments, processing logic may initiate these operations in response to completing the file system resource reservation described in operation 420. In various embodiments, processing logic may initiate backend initialization operations such that the backend initialization operations are similar to those described above with respect to Figure 2 The execution of the described initialization operations of the front end is performed in parallel. In various embodiments, the initialization operations performed by the back end may include those operations involved in preparing the memory devices to achieve an operational state. These types of operations may include initial power-up of the memory devices, initialization operations, calibration operations, memory rebuilds, garbage collection, memory training, or other similar operations. Before these operations are completed, the memory devices may not be fully operational, which may prevent the back end from servicing requests to perform I / O operations on those memory devices.

[0067] At operation 440, processing logic can release the set of file system resources reserved by operation 420 in response to completing the backend initialization operation in operation 430. As noted above, by releasing the reserved resources, processing logic can allow those resources to be allocated to any queued requests as well as any additional subsequently received requests (e.g., requests received after the resources have been enabled but have not yet been added to the request queue). For example, upon receiving a new request, processing logic can determine whether the requested resource is reserved, and if not, allow the request to be processed (or add the request to the queue if the queue is still being processed). If the request queue is still being processed, in response to determining that the requested resource has been released (e.g., not reserved, available, etc.), processing logic can retrieve the queued request from the request queue, allocate applicable resources for the request, and perform file system and / or I / O operations for the request.

[0068] In some embodiments, in response to completing the backend initialization operation, processing logic of the backend can additionally notify the front end and / or security components of the memory sub-system that the memory device is available. In such cases, processing logic of the backend can send a notification to the front end and / or security components of the memory sub-system to indicate that the backend component is available for responding to requests to perform I / O operations. Alternatively, the backend can provide its status to the front end or security components in response to receiving a specific request for such status.

[0069] Figure 5 An example machine, a computer system 500, is illustrated in FIG. 5 in which an instruction set can be executed for causing the machine to perform any one or more of the methodologies discussed herein. In some embodiments, the computer system 500 can correspond to a host system (e.g., host system 120 of FIG. 1) that includes, is coupled to, or utilizes a memory sub-system (e.g., memory sub-system 110 of FIG. 1), or can be used in performing operations of a controller (e.g., executing an operating system to perform operations corresponding to firmware management component 134 of FIG. 1). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment. Figure 1 Figure 1 Figure 1 In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0070] ​​The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0071] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0072] Processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 for communicating via a network 520.

[0073] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 526 or software embodying any one or more of the methodologies or functions described herein. The instructions 526 may also reside, completely or at least partially, within the main memory 504 and / or within the processing device 502 during execution thereof by the computer system 500, the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 1 Memory subsystem 110.

[0074] In one embodiment, instructions 526 include instructions for implementing instructions corresponding to a firmware management component (e.g., Figure 1The machine-readable storage medium 524 is a memory device that stores instructions for the functionality of the firmware management component 134. Although the machine-readable storage medium 524 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0075] Some portions of the previously described detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are a means for those skilled in the art of data processing to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, considered to be a self-consistent sequence of operations that produces a desired result. The operations are those requiring physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. At times, it has proven convenient, primarily for common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0076] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0077] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored on a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magnetic optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0078] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of various such systems will be presented as set forth in the description below. Additionally, the present disclosure is not described with reference to any particular programming language. It will be appreciated that the teachings of the present disclosure as described herein may be implemented using a variety of programming languages.

[0079] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, or the like.

[0080] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method comprising: receiving, by a processing device executing a front-end component of a memory subsystem, a first request to perform a first set of initialization operations, wherein the front-end component communicates with a back-end component in a data path associated with a memory device of the memory subsystem; In response to receiving the first request, initiating the first set of initialization operations for the front-end component in parallel with initiating the second set of initialization operations for the back-end component; responsive to completing the first set of initialization operations, sending a first notification to a host computer system to indicate that the front end component is available to respond to a request from the host computer system for configuration data associated with the memory subsystem; receiving a second request for configuration data associated with the memory subsystem from the host computer system, wherein the second request is received before the back-end component has completed the second set of initialization operations; and In response to receiving the second request from the host computer system before the back-end component has completed the second set of initialization operations, the configuration data is provided to the host computer system.

2. The method of claim 1 , wherein the front-end component further communicates with a security component in the data path, the method further comprising: In response to completing the first set of initialization operations, a second notification is sent to the secure component to cause the secure component to perform a third set of initialization operations of the secure component.

3. The method according to claim 1, further comprising: sending a third request to the backend component for information associated with a status of the second set of initialization operations; as well as In response to receiving a response to the third request, an initialization completion status of the backend component is determined.

4. The method according to claim 3, further comprising: In response to determining that the completion status of the backend component indicates that the second set of initialization operations is completed: sending a notification to the host computer system indicating that the front-end component is available to respond to input / output (I / O) requests; receiving an I / O request from the host computer system to perform an I / O operation associated with the memory device; and The I / O request is forwarded to the backend component.

5. The method according to claim 4, further comprising: In response to determining that the completion status of the backend component indicates that the second set of initialization operations has not yet completed: sending a notification to the host computer system indicating that the front-end component is available to respond to input / output (I / O) requests; receiving an I / O request from the host computer system to perform an I / O operation associated with the memory device; and The I / O request is stored in a request queue.

6. The method according to claim 4, further comprising: In response to determining that the completion status of the backend component indicates that the second set of initialization operations has not yet completed: receiving an I / O request from the host to perform an I / O operation associated with the memory device; and A response is sent to the host computer system indicating that the memory device is unavailable.

7. The method of claim 1, wherein the second request comprises at least one of a request to identify the subsystem controller, a request to create a memory queue, a request to complete the memory queue, or a request to perform a non-I / O operation.

8. A method comprising: receiving, by a processing device executing a back-end component of a memory subsystem, a first request to perform a first set of initialization operations, wherein the back-end component communicates with a front-end component in a data path associated with a memory device of the memory subsystem; In response to receiving the first request, reserving a set of file system resources to prevent allocation of the set of file system resources to a subsequently received request from the front-end component to access the memory device; Initiating the first set of initialization operations of the backend component, wherein the first set of initialization operations is performed in parallel with a second set of initialization operations performed by the frontend component; as well as In response to completing the first set of initialization operations, the set of file system resources is released to allow the set of file system resources to be allocated to the subsequently received request.

9. The method according to claim 8, further comprising: receiving a first subsequent request to access the memory device; In response to determining that the set of file system resources is reserved, adding the first subsequent request to a request queue; as well as In response to determining that the set of file system resources is released: Retrieving the first subsequent request from the request queue; and The set of file system resources is allocated to a first subsequently received request.

10. The method of claim 9, wherein the first subsequent request comprises a request from the front-end component to perform an input / output (I / O) operation.

11. The method according to claim 8, further comprising: In response to completing the first set of initialization operations for the back-end component, a first notification is sent to the front-end component to indicate that the back-end component is available to respond to requests to perform I / O operations.

12. The method of claim 9, wherein the backend component further communicates with a security component in the data path, and wherein the first subsequent request comprises at least one of an authentication operation, an encryption key synchronization exchange operation, or a request for file system configuration information.

13. The method according to claim 12, further comprising: In response to completing the first set of initialization operations for the backend component, a second notification is sent to the security component to indicate that the backend component is available to respond to requests to perform I / O operations.

14. A system comprising: a plurality of memory devices; as well as a processing device operatively coupled to the plurality of memory devices to perform operations comprising: receiving, by the processing device executing a front-end component of a memory subsystem, a first request to perform a first set of initialization operations, wherein the front-end component communicates with a back-end component in a data path associated with a memory device of the memory subsystem; In response to receiving the first request, initiating the first set of initialization operations for the front-end component in parallel with initiating the second set of initialization operations for the back-end component; responsive to completing the first set of initialization operations, sending a first notification to a host computer system to indicate that the front end component is available to respond to a request from the host computer system for configuration data associated with the memory subsystem; receiving a second request for configuration data associated with the memory subsystem from the host computer system, wherein the second request is received before the back-end component has completed the second set of initialization operations; and In response to receiving the second request from the host computer system before the back-end component has completed the second set of initialization operations, the configuration data is provided to the host computer system.

15. The system of claim 14, wherein the front-end component is further in communication with a security component in the data path, and wherein the processing device is to perform additional operations comprising: In response to completing the first set of initialization operations, a second notification is sent to the secure component to cause the secure component to perform a third set of initialization operations of the secure component.

16. The system of claim 14, wherein the processing device is to perform further operations comprising: sending a third request to the backend component for information associated with a status of the second set of initialization operations; and In response to receiving a response to the third request, an initialization completion status of the backend component is determined.

17. The system of claim 16, wherein the processing means is to perform further operations comprising: In response to determining that the completion status of the backend component indicates that the second set of initialization operations is completed: sending a notification to the host computer system indicating that the front-end component is available to respond to input / output (I / O) requests; receiving an I / O request from the host computer system to perform an I / O operation associated with the memory device; and The I / O request is forwarded to the backend component.

18. The system of claim 17, wherein the processing means is to perform further operations comprising: In response to determining that the completion status of the backend component indicates that the second set of initialization operations has not yet completed: sending a notification to the host computer system indicating that the front-end component is available to respond to input / output (I / O) requests; receiving an I / O request from the host computer system to perform an I / O operation associated with the memory device; and The I / O request is stored in a request queue.

19. The system of claim 17, wherein the processing device is to perform additional operations comprising: In response to determining that the completion status of the backend component indicates that the second set of initialization operations has not yet completed: receiving an I / O request from the host to perform an I / O operation associated with the memory device; and A response is sent to the host computer system indicating that the memory device is unavailable.

20. The system of claim 14, wherein the second request comprises at least one of a request to identify the subsystem controller, a request to create a memory queue, a request to complete the memory queue, or a request to perform a non-I / O operation.

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