A method for manufacturing a trench capacitor and a trench capacitor
By not filling the trench capacitor with metal and using metal wires to connect the upper and lower electrodes to form an MIM capacitor structure, the problems of high process integration difficulty and limited design freedom are solved, and the capacitance value is increased and the design flexibility is improved.
Patent Information
- Application Number
- CN202211656039.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-22
- Publication Date
- 2025-09-09
- Estimated Expiration
- 2042-12-22
AI Technical Summary
Existing trench capacitors have high process integration difficulty and limited design freedom, making it difficult to increase the capacitance value without increasing the design area.
The design of not filling the capacitor trench with metal is adopted. The upper and lower electrodes are connected by metal wires to avoid through-hole connection. The conductive layer of the metal wire and the electrically connected trench is connected to the metal interconnection layer to form an MIM capacitor structure.
The difficulty of process integration is reduced, the structural design freedom of the trench capacitor is improved, and the capacitance value per unit area is increased without increasing the area.
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Figure CN115763423B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a manufacturing method of a trench capacitor and a trench capacitor. Background Art
[0002] Capacitors are a conventional passive component that is widely used in integrated circuit design. In some special applications, capacitors with large unit capacitance are needed to improve product performance, such as storing signals, reducing coupling, etc. Conventional planar capacitors need to occupy a large area to obtain large capacitance, which will sacrifice the design area. For this reason, trench capacitors have become the best choice for large capacitance. Generally, trench capacitors have a metal-dielectric layer-metal sandwich (MIM) structure, in which the lower electrode is connected to the bottom metal interconnect layer, and the upper electrode metal is connected to the metal filled in the trench, and then connected to the metal interconnect layer through a through hole. However, the trench capacitor with the above-mentioned MIM structure needs to fill the trench with metal, and use a through hole to connect the upper electrode metal. The process integration difficulty is relatively high, and the design freedom of the trench structure is also limited.
[0003] Therefore, it is necessary to provide a new manufacturing solution for trench capacitors that can reduce the difficulty of process integration and improve the design freedom of trench structures. Summary of the Invention
[0004] An object of the present invention is to provide a method for manufacturing a trench capacitor and a trench capacitor, so as to reduce the difficulty of process integration and improve the degree of freedom in the structural design of the trench capacitor.
[0005] To achieve the above-mentioned object, the present invention provides a method for manufacturing a trench capacitor, comprising: providing a semiconductor substrate, forming a metal interconnection layer located in the semiconductor substrate; forming a first dielectric layer located on the semiconductor substrate; etching the first dielectric layer to form a trench array, wherein the trench array includes a capacitor trench located in a first area and an electrical connection trench located in a second area, wherein the bottoms of the capacitor trench and the electrical connection trench both expose the metal interconnection layer; forming a first conductive layer, a second dielectric layer, and a second conductive layer in the capacitor trench and the electrical connection trench, wherein the second dielectric layer is located between the first conductive layer and the second conductive layer, and the second dielectric layer completely covers the first conductive layer. Conductive layer, the first conductive layer of the capacitor trench is connected to the metal interconnection layer of the first area, and the first conductive layer of the electrically connected trench is connected to the metal interconnection layer of the second area; the second dielectric layer and the second conductive layer on the surface of the second area and the second dielectric layer and the second conductive layer at the bottom of the electrically connected trench are removed; metal is deposited and patterned to form metal lines, the metal lines cover the second conductive layer on the surface of the first area and the first conductive layer on the surface of the second area, so as to connect the second conductive layer of the capacitor trench to the metal interconnection layer of the second area through the metal lines and the first conductive layer of the electrically connected trench, and the upper electrode and the lower electrode of the trench capacitor are led to the lower metal interconnection layer.
[0006] The beneficial effect of the manufacturing method of the trench capacitor provided by the present invention is that the first conductive layer of the capacitor trench is connected to the metal interconnection layer of the first region, and the second conductive layer is connected to the metal interconnection layer of the second region by means of metal wires and the first conductive layer of the electrically connected trench. That is, the upper electrode and the lower electrode of the trench capacitor are led out to the lower metal layer without forming through holes in the capacitor trench and the electrically connected trench, thereby reducing the difficulty of process integration and improving the freedom of design of the trench capacitor structure.
[0007] In one possible implementation, metal is deposited to form a metal film. This metal film does not fill the capacitor trench, resulting in a void in the capacitor trench. The metal film is then subjected to photolithography and etching processes to form metal lines. This has the advantage that the capacitor trench does not need to be completely filled with metal, allowing for the presence of voids. This helps reduce the design dimensions of the capacitor trench, thereby increasing the capacitance per unit area. This increases the surface area of the capacitor while reducing the complexity of process integration and improving the design freedom of the trench structure.
[0008] In a possible implementation manner, before depositing the first dielectric layer, the method further includes: depositing a barrier layer on the semiconductor substrate.
[0009] In another possible implementation, the first conductive layer, the second conductive layer, and the second dielectric layer are deposited by physical vapor deposition, chemical vapor deposition, or atomic layer deposition.
[0010] In one possible embodiment, the material of the second dielectric layer is at least one high dielectric constant material selected from silicon nitride (SiN), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O5), and dysprosium oxide (Dy2O3).
[0011] In a possible implementation manner, the second dielectric layer is a single-layer thin film or a multi-layer thin film.
[0012] In a possible implementation, the first conductive layer and the second conductive layer are single-layer films or multi-layer films of TiN, Ti, TaN, or Ta, and the metal film is aluminum, TaN, or TiN.
[0013] In other possible implementations, forming a metal interconnection layer in the semiconductor substrate includes: forming a damascene groove or a dual damascene hole groove in the semiconductor substrate using a photolithography process; depositing a metal interconnection material; and forming a metal interconnection layer through a grinding process.
[0014] In a second aspect, the present invention further provides a trench capacitor, comprising a semiconductor substrate; a metal interconnection layer located in the semiconductor substrate; and a first dielectric layer located on the semiconductor substrate; wherein a trench array is formed in the first dielectric layer, the trench array comprising a capacitor trench in a first region and an electrical connection trench in a second region, a MIM capacitor structure is formed in the capacitor trench, the MIM capacitor structure comprising a first conductive layer, a second dielectric layer, and a second conductive layer, the second dielectric layer being located between the first conductive layer and the second conductive layer, the second dielectric layer completely covering the first conductive layer, the first conductive layer of the capacitor trench being connected to the metal interconnection layer in the first region, the first conductive layer being formed in the electrical connection trench, the first conductive layer of the electrical connection trench being connected to the metal interconnection layer in the second region; the second conductive layer of the capacitor trench being connected to the metal interconnection layer in the second region via a metal line and the first conductive layer of the electrical connection trench, and the upper electrode and the lower electrode of the trench capacitor being led out via the lower metal interconnection layer.
[0015] The trench capacitor provided by the present invention has the following beneficial effects: the second conductive layer of the capacitor trench is connected to the metal interconnection layer of the second region through a metal wire and the first conductive layer of the electrical connection trench, and the first conductive layer is connected to the metal interconnection layer of the first region, thereby leading the upper electrode and the lower electrode of the trench capacitor to the lower metal layer. No through-holes need to be formed in the capacitor trench and the electrical connection trench, which reduces the difficulty of process integration and improves the freedom of design of the trench capacitor structure.
[0016] In one possible embodiment, the capacitor trench is formed with a cavity. This structure has the advantage of increasing the filling process window, reducing the design size of the capacitor trench, and thus increasing the capacitance value per unit area. This increases the surface area of the capacitor while reducing the difficulty of process integration and improving the design freedom of the trench structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 A schematic cross-sectional structure diagram of a trench capacitor provided by the present invention;
[0018] Figure 2 A flow chart of a method for manufacturing a trench capacitor provided by the present invention;
[0019] Figures 3A to 3I Schematic diagram of the intermediate structural cross-section of each process preparation stage provided by the present invention.
[0020] Description of the figure mark:
[0021] Semiconductor substrate 100; metal interconnection layer 200; barrier layer 300; first dielectric layer 400;
[0022] Groove array 500 ; capacitor trench 5001 ; electrical connection trench 5002 ; first conductive layer 600 ; second dielectric layer 700 ; second conductive layer 800 ; photoresist 900 ; metal line 1000 . DETAILED DESCRIPTION
[0023] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be the common meanings understood by people with ordinary skills in the field to which the present invention belongs. The words "including" and similar words used in this article mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.
[0024] Figure 1 The cross-sectional structure of a trench capacitor provided by the present invention is shown, comprising: a semiconductor substrate 100, a metal interconnection layer 200 located in the semiconductor substrate 100, a first dielectric layer 400 sequentially located on the semiconductor substrate 100, and a trench array 500 formed on the first dielectric layer 400.
[0025] The trench array 500 includes a capacitor trench 5001 in a first region A and an electrical connection trench 5002 in a second region B. A MIM capacitor structure is formed in the capacitor trench 5001. The MIM capacitor structure includes a first conductive layer 600, a second dielectric layer 700, and a second conductive layer 800. The second dielectric layer 700 is located between the first conductive layer 600 and the second conductive layer 800, and the second dielectric layer 700 completely covers the first conductive layer 600. The first conductive layer 600 of the capacitor trench is connected to the metal interconnect layer 200 in the first region A, and the first conductive layer 600 of the electrical connection trench is connected to the metal interconnect layer 200 in the second region B. The first conductive layer 600 is formed in the electrical connection trench 5001; the second conductive layer 800 of the capacitor trench 5001 is connected to the metal interconnect layer 200 in the second region B via a metal line 1000 and the first conductive layer 600 of the electrical connection trench 5002. The upper electrode and the lower electrode of the trench capacitor are led out through the lower metal interconnection layer.
[0026] Optionally, a barrier layer 300 is further included between the semiconductor substrate 100 and the first dielectric layer 400 to prevent metal diffusion from the metal interconnect layer 200 and prevent leakage. Furthermore, a cavity is formed in the capacitor trench 5001. This structure has the advantage of reducing the design size of the capacitor trench 5001, thereby increasing the capacitance per unit area. This increases the surface area of the capacitor while reducing the difficulty of process integration and improving the design freedom of the trench structure.
[0027] The following describes the formation process of the trench capacitor in conjunction with the manufacturing process of the trench capacitor. Figure 2 FIG. 1 shows a schematic flow chart of a method for manufacturing a trench capacitor. Figures 3A to 3I Schematic diagrams of the intermediate structure cross-sections of each process preparation stage in this example are shown respectively.
[0028] See also Figure 2 The manufacturing method of the trench capacitor provided by the embodiment of the present invention includes the following steps:
[0029] S201 , providing a semiconductor substrate 100 , and forming a metal interconnection layer 200 in the semiconductor substrate 100 .
[0030] Specifically, a damascene groove or a dual damascene hole groove may be formed in the semiconductor substrate by using a photolithography and etching process; then a metal interconnection material is deposited; and a metal interconnection layer 200 is formed by a grinding process. For example, Figure 3AAs shown, in this embodiment, a copper interconnect layer is formed on a silicon substrate using a Damascene process. This copper interconnect layer serves as the metal interconnect layer 200. The metal interconnect layer 200 includes a metal interconnect layer in a first region A and a metal interconnect layer in a second region B. The semiconductor substrate 100 can be an N-type or P-type silicon substrate. The material of the semiconductor substrate 100 includes one or more combinations of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium. The semiconductor substrate 100 can also be a silicon-on-insulator semiconductor substrate or a germanium-on-insulator semiconductor substrate.
[0031] S202 , depositing and forming a first dielectric layer 400 on the semiconductor substrate 100 .
[0032] Optionally, before depositing the first dielectric layer 400, the method further includes depositing a barrier layer 300 on the semiconductor substrate 100. For example, Figure 3B As shown, a barrier layer 300 is first deposited on the surface of the metal interconnect layer 200, and then a first dielectric layer 400 is deposited. For example, the barrier layer 300 can be silicon nitride (SiN) or silicon carbonitride (SiCN), and the first dielectric layer can be silicon oxide (SiO2) or silicon oxynitride (SiON).
[0033] S203 , etching the first dielectric layer 400 to form a trench array 500 .
[0034] like Figure 3C As shown, the first dielectric layer 400 is subjected to a groove photolithography and etching process to generate a groove array, wherein the groove array 500 includes a capacitor groove 5001 in the first area A and an electrical connection groove 5002 in the second area B, wherein the bottoms of the capacitor groove 5001 and the electrical connection groove 5002 both expose the metal interconnection layer 200.
[0035] S204: A first conductive layer 600, a second dielectric layer 700, and a second conductive layer 800 are formed in the capacitor trench 5001 and the electrical connection trench 5002. The second dielectric layer 700 is located between the first conductive layer 600 and the second conductive layer 800, and the second dielectric layer 700 completely covers the first conductive layer 600. The first conductive layer 600 of the capacitor trench is connected to the metal interconnect layer 200 in the first region A, and the first conductive layer 600 of the electrical connection trench is connected to the metal interconnect layer 200 in the second region B.
[0036] Exemplarily, S204 may specifically include the following steps a to c, wherein:
[0037] Step a: forming a first conductive layer 600 in the capacitor trench 5001 and the electrical connection trench 5002 .
[0038] For example, the metal material of the first conductive layer is first deposited, such as Figure 3D Then, photolithography and etching processes are performed in sequence to define the graphic area of the first conductive layer 600, forming the first conductive layer 600, as shown. Figure 3E As shown. Exemplarily, the first conductive layer 600 can serve as the lower electrode of the trench capacitor or as a metal lead electrically connected to the trench 5002. The metal material of the first conductive layer can be a single-layer film or a multi-layer film of titanium nitride (TiN), titanium (Ti), tantalum nitride (TaN), or tantalum (Ta). Optionally, the first conductive layer 600 can be a single-layer film or a multi-layer film, and the deposition method can be physical vapor deposition, chemical vapor deposition, or atomic layer deposition.
[0039] Step b: depositing and forming a second dielectric layer 700 on the first conductive layer 600 .
[0040] For example, Figure 3F As shown, a second dielectric layer 700 is deposited on the first conductive layer 600 to form a second dielectric layer 700 located on the first conductive layer 600. The patterned area of the second dielectric layer 700 surrounds the patterned area of the first conductive layer 600, thereby ensuring that the first conductive layer 600 is completely covered by the second dielectric layer 700 and does not short-circuit with the upper electrode. Exemplarily, the material of the second dielectric layer can be SiN, HfO2, ZrO2, Al2O3, La2O3, Ta2O5, Y2O5, Dy2O3, etc., which has a high dielectric constant. The second dielectric layer can be a single-layer thin film or a multi-layer thin film, and can be deposited by chemical vapor deposition or atomic layer deposition.
[0041] Step c: depositing and forming a second conductive layer 800 on the second dielectric layer 700 .
[0042] For example, Figure 3G As shown, a second conductive layer 800 is deposited on the second dielectric layer 700 to form a second conductive layer 800 located on the second dielectric layer 700. Exemplarily, the second conductive layer 800 can serve as the upper electrode of the capacitor. The material of the second conductive layer 800 can be a single-layer film or a multi-layer film of titanium nitride (TiN), titanium (Ti), tantalum nitride (TaN), or tantalum (Ta). The second conductive layer 800 can be a single-layer film or a multi-layer film, wherein the second conductive layer 800 uniformly covers the second dielectric layer 700 so as not to short-circuit with the lower electrode. Optionally, the second conductive layer 800 can be deposited by physical vapor deposition, chemical vapor deposition, or atomic layer deposition.
[0043] S205 , removing the second dielectric layer 700 and the second conductive layer 800 on the surface of the second region B and the second dielectric layer 700 and the second conductive layer 800 at the bottom of the electrical connection trench.
[0044] Optionally, in this embodiment, a photoresist 900 covering the first area A is first formed, and the exposed second area B is etched to remove the second dielectric layer 700 and the second conductive layer 800 on the surface of the second area B, as well as the second dielectric layer 700 and the second conductive layer 800 at the bottom of the electrically connected groove, so as to expose the first conductive layer 600 on the surface of the second area B and the first conductive layer 600 at the bottom of the electrically connected groove.
[0045] like Figure 3H As shown, a photolithography process is first used to form a photoresist layer 900 covering the first area A, while exposing the second area B. Then, an etching process is performed to remove the second dielectric layer 700 and the second conductive layer 800 on the surface of the second area B, and to remove the second dielectric layer 700 and the second conductive layer 800 at the bottom of the electrically connected trench. The effect after etching is as shown in FIG. Figure 3I It is worth noting that this embodiment requires the etching process to stop at the surface of the first conductive layer in the second region B, thereby reducing the etching consumption of the first conductive layer.
[0046] S206, depositing metal and patterning to form a metal line 1000, the metal line 1000 covers the second conductive layer 800 on the surface of the first area A and the first conductive layer 600 on the surface of the second area B, so as to connect the second conductive layer 800 of the capacitor groove to the metal interconnection layer 200 of the second area B through the metal line 1000 and the first conductive layer 600 of the electrical connection groove.
[0047] For example, the photoresist layer is first removed, and then a metal is deposited to form a metal film, and then the metal film is patterned to form a metal line 1000, so as to connect the second conductive layer 800 to the metal interconnection layer 200 of the second region B through the metal line 1000 and the first conductive layer 600 of the electrical connection groove. Figure 1 shown.
[0048] Specifically, in this embodiment, metal can be first deposited to form a metal film, which covers the surface of the first area A and the second area B, but does not completely fill the capacitor trench 5001, so that a cavity is formed in the capacitor trench 5001; then, the metal film is subjected to a photolithography and etching process to form a metal line. The final effect diagram can be seen in FIG. Figure 1As shown. The metal film is aluminum, titanium nitride (TiN) or tantalum nitride (TaN). Exemplarily, the method of forming the metal film in this step can refer to the standard aluminum wire process, that is, depositing a multilayer metal film, from bottom to top TaN, TiN, Ti, Al, Ti, TiN, thereby forming an aluminum film, which serves as a metal film, and then adopts a photolithography and etching process to form aluminum wiring, which serves as a metal wiring, and connects the second conductive layer to the metal interconnection layer of the second region B through the aluminum wiring. It can be seen that this embodiment connects the second conductive layer of the MIM capacitor, that is, the upper electrode, to the metal interconnection layer while completing the metal wire. It can be seen that because the capacitor trench 5001 is relatively narrow, the metal film will not completely fill the capacitor trench 5001, so a cavity will be formed in the capacitor trench, which is conducive to reducing the design size of the capacitor trench, thereby increasing the capacitance value per unit area.
[0049] In a possible embodiment, the material of the first conductive layer 600 and the second conductive layer 800 may be copper, aluminum or tungsten.
[0050] It is worth noting that after forming the second conductive layer 800 and before etching the second dielectric layer 700 and the second conductive layer 800, the semiconductor structure may further be further deposited with more dielectric layers and conductive layers, which will not be shown one by one in this embodiment.
[0051] In this embodiment, the first conductive layer is connected to the metal interconnect layer of the first region A, and the second conductive layer is connected to the metal interconnect layer of the second region B via metal wires and the first conductive layer of the electrical connection trench. This allows the upper and lower electrodes of the trench capacitor to be led out to the underlying metal interconnect layer without forming vias in the capacitor trench and the electrical connection trench, thus reducing the difficulty of process integration. In addition, the capacitor trench does not need to be filled with metal, allowing for voids. This helps reduce the design size of the capacitor trench and thereby increases the capacitance per unit area. This increases the surface area of the capacitor while reducing the difficulty of process integration and improving the design freedom of the trench structure.
[0052] While the embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations of these embodiments are possible. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the claims. Furthermore, the invention described herein is susceptible to other embodiments and may be practiced or implemented in a variety of ways.
Claims
1. A method for manufacturing a trench capacitor, characterized in that: include: Providing a semiconductor substrate, and forming a metal interconnection layer in the semiconductor substrate; Depositing and forming a first dielectric layer on the semiconductor substrate; Etching the first dielectric layer to form a trench array, wherein the trench array includes a capacitor trench located in the first area and an electrical connection trench located in the second area, wherein the bottoms of the capacitor trench and the electrical connection trench both expose the metal interconnection layer; forming a first conductive layer, a second dielectric layer, and a second conductive layer in the capacitor trench and the electrical connection trench, wherein the second dielectric layer is located between the first conductive layer and the second conductive layer, the first conductive layer of the capacitor trench is connected to the metal interconnection layer of the first region, and the first conductive layer of the electrical connection trench is connected to the metal interconnection layer of the second region; removing the second dielectric layer and the second conductive layer on the surface of the second region and the second dielectric layer and the second conductive layer at the bottom of the electrical connection trench; Deposit metal and pattern it to form a metal line, wherein the metal line covers the second conductive layer on the surface of the first area and the first conductive layer on the surface of the second area, so as to connect the second conductive layer of the capacitor trench to the metal interconnection layer of the second area through the metal line and the first conductive layer of the electrical connection trench.
2. The method according to claim 1, characterized in that The step of depositing metal and patterning the metal lines comprises: Depositing metal to form a metal film, wherein the metal film does not fill the capacitor trench, so that a cavity is formed in the capacitor trench; Performing photolithography and etching processes on the metal film to form metal lines; Wherein, the metal film is aluminum, TaN or TiN.
3. The method according to claim 1, characterized in that Before depositing the first dielectric layer, the method further includes: A barrier layer is deposited on the semiconductor substrate.
4. The method according to claim 1, wherein The first conductive layer, the second conductive layer and the second dielectric layer are deposited by physical vapor deposition, chemical vapor deposition or atomic layer deposition.
5. The method according to claim 1, wherein The material of the second dielectric layer is at least one material with a high dielectric constant selected from the group consisting of SiN, HfO2, ZrO2, Al2O3, La2O3, Ta2O5, Y2O5, and Dy2O3.
6. The method according to claim 5, characterized in that The second dielectric layer is a single-layer thin film or a multi-layer thin film.
7. The method according to any one of claims 1 to 6, characterized in that The first conductive layer and the second conductive layer are single-layer films or multi-layer films of TiN, Ti, TaN, or Ta.
8. The method according to claim 1, characterized in that Forming a metal interconnection layer in the semiconductor substrate, comprising: forming a damascene groove or a dual damascene hole groove in the semiconductor substrate by using a photolithography and etching process; Deposit metal interconnect material; and form a metal interconnect layer through a grinding process.
9. A trench capacitor, characterized in that: include: semiconductor substrates; a metal interconnect layer located in the semiconductor substrate; a first dielectric layer located on the semiconductor substrate; A trench array is formed in the first dielectric layer, the trench array including capacitor trenches in a first region and electrical connection trenches in a second region; a MIM capacitor structure is formed in the capacitor trenches, the MIM capacitor structure including a first conductive layer, a second dielectric layer, and a second conductive layer; the second dielectric layer is located between the first conductive layer and the second conductive layer, the second dielectric layer completely covers the first conductive layer; the first conductive layer of the capacitor trench is connected to the metal interconnection layer of the first region; the first conductive layer is formed in the electrical connection trench, and the first conductive layer of the electrical connection trench is connected to the metal interconnection layer of the second region; the second conductive layer of the capacitor trench is connected to the metal interconnection layer of the second region through a metal line and the first conductive layer of the electrical connection trench; the upper electrode and the lower electrode of the trench capacitor are led out through the lower metal interconnection layer.
10. The trench capacitor according to claim 9, wherein The capacitor trench is further formed with a cavity.