Vertical enhancement-mode β-ga2o3 umosfet device and method of manufacturing the same

Abstract

The application discloses a vertical enhancement type beta-Ga2O3 UMOSFET device and a preparation method thereof. The vertical enhancement type beta-Ga2O3 UMOSFET device comprises an epitaxial structure, a source, a drain and a gate which are arranged in cooperation with the epitaxial structure. The epitaxial structure comprises a gallium oxide substrate, a gallium oxide drift layer, a carrier depletion zone and a highly-doped gallium oxide epitaxial layer which are arranged in a stack. Electrons in the carrier depletion zone are depleted. The bottom of a groove-shaped structure is arranged in the gallium oxide drift layer. The source is arranged on the highly-doped gallium oxide epitaxial layer and forms an ohmic contact with the highly-doped gallium oxide epitaxial layer. The drain is arranged on the gallium oxide substrate and forms an ohmic contact with the gallium oxide substrate. The preparation method of the vertical enhancement type beta-Ga2O3 UMOSFET device provided by the embodiment of the application can control the threshold voltage by regulating the injection concentration of the N ion compensation acceptor material, so that the misopening condition can be effectively avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to a vertical enhancement-mode β-Ga2O3 UMOSFET device and a preparation method thereof, and belongs to the technical field of semiconductors. BACKGROUND

[0002] Compared with GaN, SiC and other wide-bandgap semiconductors, β-Ga2O3 has an ultra-wide bandgap of ~4.9 eV, a high critical breakdown field of 8 MV / cm, a Baliga figure of merit (BFOM) of 3444 times, and the advantage of β-Ga2O3 substrates that can be grown by melting, making β-Ga2O3 an important member of the new generation of power and radio frequency electronic fields. In the past few years, some significant performances of lateral and vertical devices based on β-Ga2O3 have been reported. However, from the aspect of fully exerting the two advantages of β-Ga2O3 material, vertical devices have a better electric field distribution, and at the same time, using a high-doped low-resistance β-Ga2O3 self-supporting substrate, an extremely high breakdown voltage and low on-resistance can be achieved, which has been proven to be beneficial in terms of breakdown voltage, dynamic characteristics and reliability in the transition from lateral to vertical devices for many material systems (such as Si, SiC and GaN). Due to the lack of p-type β-Ga2O3 doping technology, the development of bipolar power devices is limited, and more efforts need to be made to realize high-performance enhancement-mode (E-mode) transistors. Due to this great challenge, there is little research on β-Ga2O3 E-mode vertical transistors.

[0003] At present, there are only two main structures of β-Ga2O3 vertical transistors, which are fin field effect transistor (FinFET) and current aperture vertical electron transistor (CAVET). The structure of the fin field effect transistor (FinFET) is shown in FIG. 1, since p-Ga2O3 has not been realized at present, the use of fin-type gate can avoid the necessity of p-type material, a high-doped Ga2O3 film is first obtained on the Ga2O3 drift layer by epitaxy or ion implantation, then a fin-type structure is etched on the Ga2O3 drift layer by using electron beam lithography and ICP etching technology, and finally a vertical Ga2O3 MOSFET device with a fin-type gate structure is successfully prepared by depositing gate metal and source-drain metal. Figure 1 The structure of the current aperture vertical electron transistor (CAVET) is shown in FIG. 2, the CAVET device mainly uses ion implantation to implant Mg ions or N ions into the Ga2O3 drift layer to form a current blocking layer, a high-doped Ga2O3 film is formed on the upper end of the Ga2O3 drift layer by epitaxy or ion implantation of Si to form ohmic contact with the source, and finally a vertical Ga2O3 MOSFET device with a planar gate structure is successfully prepared by depositing gate metal and source-drain metal. Figure 2 The structure of the current aperture vertical electron transistor (CAVET) is shown in FIG. 2, the CAVET device mainly uses ion implantation to implant Mg ions or N ions into the Ga2O3 drift layer to form a current blocking layer, a high-doped Ga2O3 film is formed on the upper end of the Ga2O3 drift layer by epitaxy or ion implantation of Si to form ohmic contact with the source, and finally a vertical Ga2O3 MOSFET device with a planar gate structure is successfully prepared by depositing gate metal and source-drain metal.

[0004] However, the fin-type gate structure of the fin field effect transistor (FinFET) causes the trench corner gate oxide field stress to intensify, affecting the reliability of the device and reducing the withstand voltage capability of the device. In addition, the small size of the fin-type gate requires high lithography and etching processes, which are difficult to implement. Moreover, the deposition of the gate medium on the sidewall and bottom of the fin-type gate causes high capacitance and parasitic effects of the three-dimensional profile. The planar gate process used in the current aperture vertical electron transistor (CAVET) is simple, avoids damage caused by dry etching, and can obtain a high-quality MOS interface. However, the thickness of the channel layer is limited due to the reliance on the gate to deplete the electrons in the channel layer, and the current aperture in the CAVET structure also limits the improvement of the current density, making it difficult to meet the needs of high breakdown voltage. In addition, the CAVET device also has a gate-source leakage problem. In addition, these devices work in an accumulation mode, making it difficult to ensure a sufficient threshold voltage to prevent false conduction. The normally-off operation in the inverter mode is considered necessary to achieve a suitable threshold voltage (power MOSFET is usually > 3V). SUMMARY

[0005] The main purpose of the present application is to provide a vertical enhancement type β-Ga2O3 UMOSFET device and a preparation method thereof, thereby overcoming the deficiencies in the prior art.

[0006] To achieve the above-mentioned purposes, the technical solutions adopted by the present application include:

[0007] The present application provides a vertical enhancement type β-Ga2O3 UMOSFET device, comprising:

[0008] a β-Ga2O3 drift layer having a first surface and a second surface arranged oppositely,

[0009] a carrier depletion region formed in a surface layer region on the side of the first surface of the β-Ga2O3 drift layer;

[0010] a highly doped β-Ga2O3 epitaxial layer formed on the carrier depletion region, and the doping concentration of the highly doped β-Ga2O3 epitaxial layer is higher than that of the β-Ga2O3 drift layer;

[0011] a slot-shaped structure having a slot opening arranged on the surface of the highly doped β-Ga2O3 epitaxial layer and a slot bottom arranged in the β-Ga2O3 drift layer;

[0012] a dielectric layer continuously covering the surface of the highly doped β-Ga2O3 epitaxial layer and the slot wall of the slot-shaped structure;

[0013] a gate electrode, at least a partial region of which is continuously arranged on the groove wall of the groove structure, and the gate electrode is separated from the groove wall of the groove structure by a dielectric layer;

[0014] a source electrode, which is arranged on the highly-doped β-Ga2O3 epitaxial layer and forms an ohmic contact with the highly-doped β-Ga2O3 epitaxial layer;

[0015] a drain electrode, which is electrically connected to the second surface of the β-Ga2O3 drift layer.

[0016] The embodiment of the present application also provides a preparation method of a vertical enhancement-mode β-Ga2O3 UMOSFET device, which comprises the following steps:

[0017] providing a β-Ga2O3 drift layer, implanting a compensating acceptor material into a surface layer region on one side of the first surface of the β-Ga2O3 drift layer and activating the compensating acceptor material to deplete electrons in the surface layer region of the β-Ga2O3 drift layer and form a carrier depletion region,

[0018] forming a highly-doped β-Ga2O3 epitaxial layer on the carrier depletion region, the doping concentration of the highly-doped β-Ga2O3 epitaxial layer being higher than that of the β-Ga2O3 drift layer;

[0019] forming a groove structure, and arranging a groove opening of the groove structure on the surface of the highly-doped β-Ga2O3 epitaxial layer and arranging a groove bottom in the β-Ga2O3 drift layer;

[0020] forming a dielectric layer, and continuously arranging the dielectric layer on the surface of the highly-doped β-Ga2O3 epitaxial layer and the groove wall of the groove structure;

[0021] forming a source electrode, a drain electrode and a gate electrode, at least a partial region of the gate electrode is continuously arranged on the groove wall of the groove structure, and the gate electrode is separated from the groove wall of the groove structure by a dielectric layer; the source electrode is arranged on the highly-doped β-Ga2O3 epitaxial layer and forms an ohmic contact with the highly-doped β-Ga2O3 epitaxial layer; the drain electrode is electrically connected to the second surface of the β-Ga2O3 drift layer, and the second surface is arranged opposite to the first surface.

[0022] Compared with the prior art, the present application has the following advantages:

[0023] 1) The embodiment of the present application provides a vertical enhancement type beta-Ga2O3 UMOSFET device, which realizes electron depletion by using N ions and the like injected into a beta-Ga2O3 drift layer as a compensation acceptor, successfully prepares a vertical enhancement type beta-Ga2O3 UMOSFET device, and has the advantages of small process difficulty, small capacitance and parasitic effect, and controllable threshold voltage compared with a FinFET device; compared with a CAVET device, the vertical enhancement type beta-Ga2O3 UMOSFET device has the advantages of large current density, small gate-source leakage current, and can work at high voltage.

[0024] 2) The preparation method of the vertical enhancement type beta-Ga2O3 UMOSFET device can control the threshold voltage by adjusting the injection concentration of the compensation acceptor material of N ions and the like, so that the condition of accidental opening can be effectively avoided.

[0025] 3) The preparation method of the vertical enhancement type beta-Ga2O3 UMOSFET device can improve the voltage resistance performance of the device by optimizing the shape of the groove structure. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 It is a structure schematic diagram of a fin field effect transistor (FinFET);

[0027] Figure 2 It is a structure schematic diagram of a current aperture vertical electron transistor (CAVET);

[0028] Figure 3 It is a structure schematic diagram of a vertical enhancement type beta-Ga2O3 UMOSFET device provided in a typical embodiment of the present application;

[0029] Figure 4 It is a preparation flow structure schematic diagram of a vertical enhancement type beta-Ga2O3 UMOSFET device provided in a typical embodiment of the present application;

[0030] Figure 5a It is a transfer output curve of a vertical enhancement type beta-Ga2O3 UMOSFET device provided in a typical embodiment of the present application;

[0031] Figure 5b It is a transfer output curve of a vertical enhancement type beta-Ga2O3 UMOSFET device provided in a typical embodiment of the present application;

[0032] Figure 6a , Figure 6b N ion injection concentration is 5x1018 cm -3 When , the output curve and transfer curve of a vertical enhancement mode β-Ga2O3 UMOSFET device provided in an embodiment of the present invention;

[0033] Figure 6c 、 Figure 6d The N ion implantation concentration is 1×10 19 cm -3 When , the output curve and transfer curve of a vertical enhancement mode β-Ga2O3 UMOSFET device provided in an embodiment of the present invention;

[0034] Figure 7a 、 Figure 7b The N ion implantation concentrations are 5×10 18 cm -3 , 1×10 19 cm -3 When , a breakdown curve of a vertical enhancement mode β-Ga2O3 UMOSFET device provided in an embodiment of the present invention;

[0035] Figure 8a 、 Figure 8b The breakdown curves of a vertical enhancement mode β-Ga2O3 UMOSFET device provided in an embodiment of the present invention are shown when the groove structure is U-shaped and inverted trapezoidal. DETAILED DESCRIPTION

[0036] In view of the shortcomings of the prior art, the inventors of this case, after long-term research and extensive practice, have proposed the technical solution of the present invention. The following will further explain this technical solution, its implementation process and principles.

[0037] An embodiment of the present invention provides a vertical enhancement mode β-Ga2O3 UMOSFET device, comprising:

[0038] The β-Ga2O3 drift layer has a first surface and a second surface disposed opposite to each other,

[0039] a carrier depletion region formed in a surface region on the side where the first surface of the β-Ga2O3 drift layer is located;

[0040] a highly doped β-Ga2O3 epitaxial layer, formed on the carrier depletion region, wherein the doping concentration of the highly doped β-Ga2O3 epitaxial layer is higher than that of the β-Ga2O3 drift layer;

[0041] A groove structure, wherein the groove opening is arranged on the surface of the highly doped β-Ga2O3 epitaxial layer and the groove bottom is arranged in the β-Ga2O3 drift layer;

[0042] a dielectric layer continuously covering the surface of the high-doped β-Ga2O3 epitaxial layer and the sidewall of the groove-shaped structure;

[0043] a gate continuously covering at least a partial region of the sidewall of the groove-shaped structure, and the gate and the sidewall of the groove-shaped structure are separated by a dielectric layer;

[0044] a source electrode disposed on the high-doped β-Ga2O3 epitaxial layer and forming an ohmic contact with the high-doped β-Ga2O3 epitaxial layer;

[0045] a drain electrode electrically connected to the second surface of the β-Ga2O3 drift layer.

[0046] In an embodiment, the carrier depletion region is formed by implanting a compensating acceptor material into the surface layer region on the side of the first surface of the β-Ga2O3 drift layer.

[0047] In an embodiment, the compensating acceptor material includes, but is not limited to, N ions or Mg ions, etc.

[0048] In an embodiment, the concentration of the compensating acceptor material in the carrier depletion region is 1×10 18 cm -3 ~ 1×10 19 cm -3 .

[0049] In an embodiment, the thickness of the carrier depletion region is 300-600 nm, and the thickness of the β-Ga2O3 drift layer is 4-10 μm.

[0050] In an embodiment, the doping concentration of the high-doped β-Ga2O3 epitaxial layer is 1×10 19 cm -3 ~ 5×10 19 cm -3 .

[0051] In an embodiment, the thickness of the high-doped β-Ga2O3 epitaxial layer is 100-300 nm.

[0052] In an embodiment, the depth of the groove-shaped structure is 800-1000 nm.

[0053] In an embodiment, the groove-shaped structure is a U-shaped groove, a V-shaped groove, or an inverted trapezoidal groove, etc.

[0054] In an embodiment, the vertical enhancement-mode β-Ga2O3 UMOSFET device further comprises a β-Ga2O3 substrate, the β-Ga2O3 drift layer is disposed on the β-Ga2O3 substrate, and the drain is disposed on a side surface of the β-Ga2O3 substrate away from the β-Ga2O3 drift layer and forms an ohmic contact with the β-Ga2O3 substrate.

[0055] In an embodiment, the carrier concentration of the high-doped β-Ga2O3 epitaxial layer > the carrier concentration of the β-Ga2O3 substrate > the carrier concentration of the β-Ga2O3 drift layer.

[0056] In an embodiment, the β-Ga2O3 substrate, the β-Ga2O3 drift layer, and the high-doped β-Ga2O3 epitaxial layer are all of n-type, and the carrier depletion region is a high-resistance layer.

[0057] The embodiment of the present application also provides a preparation method of a vertical enhancement-mode β-Ga2O3 UMOSFET device, comprising:

[0058] providing a β-Ga2O3 drift layer, implanting a compensating acceptor material into a surface layer region on a side where a first surface of the β-Ga2O3 drift layer is located and activating the compensating acceptor material to deplete electrons in the surface layer region of the β-Ga2O3 drift layer and form a carrier depletion region,

[0059] forming a high-doped β-Ga2O3 epitaxial layer on the carrier depletion region, the doping concentration of the high-doped β-Ga2O3 epitaxial layer being higher than that of the β-Ga2O3 drift layer;

[0060] making a groove-shaped structure, and setting a groove opening of the groove-shaped structure on a surface of the high-doped β-Ga2O3 epitaxial layer and a groove bottom in the β-Ga2O3 drift layer;

[0061] making a dielectric layer, and continuously covering the dielectric layer on the surface of the high-doped β-Ga2O3 epitaxial layer and a groove wall of the groove-shaped structure;

[0062] making a source electrode, a drain electrode, and a gate electrode, at least a local region of the gate electrode being continuously disposed on the groove wall of the groove-shaped structure, and the gate electrode and the groove wall of the groove-shaped structure being separated by the dielectric layer; the source electrode is disposed on the high-doped β-Ga2O3 epitaxial layer and forms an ohmic contact with the high-doped β-Ga2O3 epitaxial layer; and the drain electrode is electrically combined with a second surface of the β-Ga2O3 drift layer, the second surface being disposed opposite to the first surface.

[0063] In one embodiment, the method for manufacturing the vertical enhancement-mode β-Ga2O3 UMOSFET device includes: implanting a compensating acceptor material into a surface layer region on a side of the first surface of the β-Ga2O3 drift layer and activating the compensating acceptor material, and then annealing at 1000-1200°C for 30-60 minutes to activate the compensating acceptor material and deplete electrons in the surface layer region.

[0064] In one embodiment, the compensating acceptor material includes, but is not limited to, N ions or Mg ions, etc.

[0065] In one embodiment, the concentration of the compensating acceptor material in the carrier depletion region is 1x10 18 cm- 3 ~1x10 19 cm -3 .

[0066] In one embodiment, the method for manufacturing the vertical enhancement-mode β-Ga2O3 UMOSFET device includes: first forming an ion implantation sacrificial layer on the first surface of the β-Ga2O3 drift layer, and then implanting a compensating acceptor material into a surface layer region on a side of the first surface of the β-Ga2O3 drift layer.

[0067] In one embodiment, the material of the ion implantation sacrificial layer includes, but is not limited to, silicon oxide, etc.

[0068] In one embodiment, the thickness of the ion implantation sacrificial layer is 50-200 nm.

[0069] In one embodiment, the method for manufacturing the vertical enhancement-mode β-Ga2O3 UMOSFET device includes: epitaxially growing a highly-doped β-Ga2O3 epitaxial layer directly on the carrier depletion region, or first epitaxially growing a β-Ga2O3 epitaxial layer on the carrier depletion region, and then converting the β-Ga2O3 epitaxial layer into a highly-doped β-Ga2O3 epitaxial layer by ion implantation.

[0070] For example, the β-Ga2O3 epitaxial layer or the highly-doped β-Ga2O3 epitaxial layer can be grown by MOCVD (metal organic chemical vapor deposition), CVD (chemical vapor deposition), or MBE (molecular beam epitaxy), etc.

[0071] In one embodiment, the method includes: implanting Si ions into the β-Ga2O3 epitaxial layer to convert the β-Ga2O3 epitaxial layer into a highly-doped β-Ga2O3 epitaxial layer.

[0072] In one embodiment, the high-doped β-Ga2O3 epitaxial layer has a doping concentration of 1x1018~5x1019cm-3. 19 cm -3 ~5x1019cm-3. 19 cm -3 .

[0073] In one embodiment, the high-doped β-Ga2O3 epitaxial layer has a thickness of 100~300nm.

[0074] In one embodiment, the trench structure can be formed by ICP (inductively coupled plasma etching), RIE (reactive ion etching) or other processes in the gate region of the high-doped β-Ga2O3 epitaxial layer.

[0075] In one embodiment, the trench structure has a depth of 800~1000nm.

[0076] In one embodiment, the trench structure is a U-shaped trench, a V-shaped trench or an inverted trapezoidal trench, etc.

[0077] In one embodiment, the β-Ga2O3 drift layer is disposed on a β-Ga2O3 substrate, and the drain is disposed on a side surface of the β-Ga2O3 substrate away from the β-Ga2O3 drift layer and forms an ohmic contact with the β-Ga2O3 substrate.

[0078] In one embodiment, the carrier concentration of the high-doped β-Ga2O3 epitaxial layer > the carrier concentration of the β-Ga2O3 substrate > the carrier concentration of the β-Ga2O3 drift layer.

[0079] In one embodiment, the β-Ga2O3 substrate, the β-Ga2O3 drift layer and the high-doped β-Ga2O3 epitaxial layer are all n-type, and the carrier depletion region is a high-resistance layer.

[0080] The technical solutions, implementation processes and principles will be further explained in combination with the drawings and specific implementation cases. It should be noted that the MOCVD, CVD or MBE epitaxial growth process, equipment, ion implantation process, equipment, etching process, equipment, annealing process, equipment, etc. used in the embodiments of the present application can be known to those skilled in the art, and the selection of different process methods and different process equipment models will not change the essence of the implementation and effects of the solutions in the embodiments of the present application.

[0081] In a more typical embodiment, a vertical enhancement-mode β-Ga2O3 UMOSFET device is as shown in FIG. 1. Figure 3As shown, the vertical enhancement-mode β-Ga2O3 UMOSFET device comprises an epitaxial structure and a source 50, a drain 60 and a gate 70 arranged in cooperation with the epitaxial structure;

[0082] The epitaxial structure comprises a β-Ga2O3 substrate 10, a β-Ga2O3 drift layer 20, a carrier depletion region 30 in which electrons are depleted, and a highly-doped β-Ga2O3 epitaxial layer 40, a region of the highly-doped β-Ga2O3 epitaxial layer 40 corresponding to the gate 70 is provided with a groove-shaped structure, an opening of the groove-shaped structure is arranged on a surface of the highly-doped β-Ga2O3 epitaxial layer 40, a groove bottom of the groove-shaped structure is arranged in the β-Ga2O3 drift layer 20, at least a local region of the gate 70 is continuously arranged on a groove wall of the groove-shaped structure, the gate 70 and the groove wall of the groove-shaped structure are separated by a dielectric layer 80, the source 50 is arranged on the highly-doped β-Ga2O3 epitaxial layer 40 and forms an ohmic contact with the highly-doped β-Ga2O3 epitaxial layer 40, and the drain 60 is arranged on a surface of the β-Ga2O3 substrate 10 opposite to the β-Ga2O3 drift layer 20 and forms an ohmic contact with the β-Ga2O3 substrate 10; the β-Ga2O3 substrate 10, the β-Ga2O3 drift layer 20 and the highly-doped β-Ga2O3 epitaxial layer 40 are all of n-type, and the carrier depletion region 30 is a high-resistance layer.

[0083] In this embodiment, a carrier concentration of the highly-doped β-Ga2O3 epitaxial layer 40 > a carrier concentration of the β-Ga2O3 substrate 10 > a carrier concentration of the β-Ga2O3 drift layer 20.

[0084] In this embodiment, the carrier depletion region 30 is converted from a surface layer region on a side where a first surface of the β-Ga2O3 drift layer 20 is arranged after being implanted with a compensating acceptor material, the compensating acceptor material can be N ions or Mg ions, etc., a concentration of the compensating acceptor material in the carrier depletion region 30 is 1×10 18 cm -3 ~ 1×10 19 cm -3 , and a thickness of the carrier depletion region 30 is 300-600 nm and a thickness of the β-Ga2O3 drift layer 20 is 4-10 μm.

[0085] In this embodiment, a doping concentration of the highly-doped β-Ga2O3 epitaxial layer 40 is 1×10 19 cm -3 ~ 5×10 19 cm -3 , and a thickness of the highly-doped β-Ga2O3 epitaxial layer is 100-300 nm.

[0086] In the embodiment, the depth of the groove-shaped structure is greater than the sum of the thicknesses of the highly doped β-Ga2O3 epitaxial layer 40 and the carrier depletion region 30 and is less than the sum of the thicknesses of the highly doped β-Ga2O3 epitaxial layer 40, the carrier depletion region 30 and the β-Ga2O3 drift layer 20, and preferably, the depth of the groove-shaped structure is 800-1000 nm; and the groove-shaped structure can be a U-shaped groove, a V-shaped groove or an inverted trapezoidal groove, etc.

[0087] The embodiment of the present application utilizes N ions or the like to compensate for the electron depletion in the drift layer by means of the acceptor material injection technology to obtain a vertical enhancement type β-Ga2O3 UMOSFET device; specifically, the N ions or Mg ions or the like as the compensation acceptor are injected into the β-Ga2O3 drift layer to achieve electron depletion, and then a layer of high-concentration β-Ga2O3 film is epitaxially grown on the surface of the β-Ga2O3 drift layer where the electrons are depleted to facilitate the formation of the subsequent source ohmic contact; at the same time, the ICP etching is utilized to obtain a groove-shaped structure of U-shaped structure or the like to facilitate the deposition of the dielectric layer and the gate metal; when a positive voltage is applied to the gate, the electron accumulation occurs on the sidewall of the groove-shaped structure until the device is turned on. The present application realizes the vertical enhancement type β-Ga2O3 UMOSFET device by utilizing the ion injection technology to deplete the electrons in the β-Ga2O3 drift layer, which has important significance for improving the performance and reliability of Ga2O3-based power devices.

[0088] The key of the present application is that the current density and the breakdown voltage of the device can be optimized by adjusting the injection concentration of the compensation acceptor material to meet the application of various scenarios; the injection concentration of the compensation acceptor material is 1×10 18 cm -3 ~ 1×10 19 cm -3 .

[0089] Embodiment 1

[0090] Please refer to Figure 4 , a preparation method of a vertical enhancement type β-Ga2O3 UMOSFET device can include the following steps:

[0091] 1) The β-Ga2O3 substrate 10 with a 10 μm thick β-Ga2O3 drift layer 20 is subjected to organic cleaning;

[0092] 2) A 100 nm thick SiO2 film is grown on the first surface of the β-Ga2O3 drift layer 20 as an ion implantation sacrifice layer by means of PECVD (plasma enhanced chemical vapor deposition) or the like;

[0093] 3) The N ions or the like as the compensation acceptor material are injected into the β-Ga2O3 drift layer 20 at a distance of 600 nm from the first surface by means of an ion implanter, and 1×1018 cm -3 N ion concentration, the first side surface being a side surface facing away from the β-Ga2O3 substrate 10, and the like;

[0094] 4) Annealing at 1100°C for 30 minutes using a tube furnace or the like to activate N ions, thereby forming a β-Ga2O3 high resistance layer 30 having a thickness of 600 nm in the β-Ga2O3 drift layer 20, and depleting electrons in the β-Ga2O3 high resistance layer 30;

[0095] 5) Epitaxially growing a 100 nm thick high-doped (doping concentration: 1 x 10 19 cm -3 ~ 5 x 10 19 cm -3 ) β-Ga2O3 epitaxial layer 40 on the surface of the β-Ga2O3 high resistance layer 30, thereby forming an epitaxial structure;

[0096] 6) Using ICP etching technology, etching a U-shaped groove structure having a depth of 800 nm to 1000 nm on the gate region of the surface of the high-doped β-Ga2O3 epitaxial layer 40, and setting the opening of the groove structure on the surface of the high-doped β-Ga2O3 epitaxial layer and the bottom of the groove in the β-Ga2O3 drift layer 20, and then performing wet etching repair;

[0097] 7) Depositing a 40 nm thick Al2O3 film as a dielectric layer 80 on the surface of the high-doped β-Ga2O3 epitaxial layer 40 and the groove structure using an ALD (atomic layer deposition) device, and performing opening on the source region of the Al2O3 film to expose the high-doped β-Ga2O3 epitaxial layer 40;

[0098] 8) Depositing Ti / Au metal (thickness: 50 / 150 nm) on the front surface (the surface of the high-doped β-Ga2O3 epitaxial layer 40 facing away from the β-Ga2O3 high resistance layer) and the back surface (the surface of the β-Ga2O3 substrate facing away from the β-Ga2O3 drift layer) of the epitaxial structure using electron beam evaporation or the like, and performing metal lift-off using a lift-off process, thereby preparing a source electrode 50 and a drain electrode 60 of the device;

[0099] 9) Rapidly annealing the sample using an RTP (rapid thermal processing) or the like, so as to achieve ohmic contact of the source electrode 50 with the high-doped β-Ga2O3 epitaxial layer 40 and the drain electrode 60 with the β-Ga2O3 substrate;

[0100] 10) Depositing Ni / Au metal (50 / 150 nm) on the dielectric layer 80 as a gate electrode 70 of the device using electron beam evaporation or the like, thereby obtaining a vertical enhancement type β-Ga2O3 UMOSFET device, and denoted as device A.

[0101] Example 2

[0102] Please refer to Figure 4 A method for manufacturing a vertical enhancement β-Ga2O3 UMOSFET device can include the following steps:

[0103] 1) Organic cleaning is performed on a β-Ga2O3 substrate 10 having a 10 μm thick β-Ga2O3 drift layer 20;

[0104] 2) A 100 nm thick SiO2 film is grown on a first surface of the β-Ga2O3 drift layer 20 as an ion implantation sacrificial layer using PECVD (plasma enhanced chemical vapor deposition) or the like;

[0105] 3) N ions are implanted into the β-Ga2O3 drift layer 20 at a distance of 600 nm from the first surface as an acceptor compensating material using an ion implanter, and a 5 x 10 18 cm -3 N ion concentration is formed;

[0106] 4) Annealing is performed at 1100°C for 30 minutes using a tube furnace or the like to activate the N ions, thereby forming a 600 nm thick β-Ga2O3 high resistance layer 30 in the β-Ga2O3 drift layer 20, and the electrons in the β-Ga2O3 high resistance layer 30 are depleted;

[0107] 5) A 100 nm thick highly doped (doping concentration: 1 x 10 19 cm -3 ~ 5 x 10 19 cm -3 ) β-Ga2O3 epitaxial layer 40 is epitaxially grown on the surface of the β-Ga2O3 high resistance layer 30 using MOCVD, thereby forming an epitaxial structure;

[0108] 6) An ICP etching technique is used to etch a U-shaped groove structure 800 nm ~ 1000 nm deep in the gate region on the surface of the highly doped β-Ga2O3 epitaxial layer 40, and the groove opening of the groove structure is disposed on the surface of the highly doped β-Ga2O3 epitaxial layer, and the groove bottom is located in the β-Ga2O3 drift layer 20, and then wet etching is performed for repair;

[0109] 7) An ALD (atomic layer deposition) device is used to deposit a 40 nm thick Al2O3 film as a dielectric layer 80 on the surface of the highly doped β-Ga2O3 epitaxial layer 40 and the groove structure, and a hole is formed in the source region of the Al2O3 film to expose the highly doped β-Ga2O3 epitaxial layer 40;

[0110] 8) Ti / Au metal (50 / 150 nm) is deposited on the front side (the surface of the highly doped β-Ga2O3epilayer 40 facing away from the β-Ga2O3high resistance layer) and the back side (the surface of the β-Ga2O3substrate facing away from the β-Ga2O3drift layer) of the epitaxial structure by electron beam evaporation or the like, and a lift-off process is used to remove the metal, thereby preparing the source electrode 50 and the drain electrode 60 of the device;

[0111] 9) The sample is annealed rapidly by RTP (rapid thermal processing) or the like to achieve ohmic contact between the source electrode 50 and the highly doped β-Ga2O3epilayer 40 and between the drain electrode 60 and the β-Ga2O3substrate;

[0112] 10) Ni / Au metal (50 / 150 nm) is deposited on the dielectric layer 80 by electron beam evaporation or the like to serve as the gate electrode 70 of the device, thereby obtaining a vertical enhancement β-Ga2O3UMOSFET device, which is denoted as device B.

[0113] Example 3

[0114] Referring to Figure 4 , a method for preparing a vertical enhancement β-Ga2O3UMOSFET device can include the following steps:

[0115] 1) The β-Ga2O3substrate 10 having a 10 μm thick β-Ga2O3drift layer 20 is subjected to organic cleaning;

[0116] 2) A 100 nm thick SiO2film is grown on the first side of the β-Ga2O3drift layer 20 as an ion implantation sacrificial layer by PECVD (plasma enhanced chemical vapor deposition) or the like;

[0117] 3) N ions or the like are implanted into the β-Ga2O3drift layer 20 at a distance of 600 nm from the first side by an ion implanter, and a 1 x 10 19 cm -3 N ion concentration is formed;

[0118] 4) The N ions are activated by annealing at 1100°C for 30 minutes using a tube furnace or the like, thereby forming a 600 nm thick β-Ga2O3high resistance layer 30 in the β-Ga2O3drift layer 20, and the electrons in the β-Ga2O3high resistance layer 30 are depleted;

[0119] 5) A 100 nm thick highly doped (doping concentration: 1 x 10 19 cm -3 ~ 5 x 10 19 cm -3)β-Ga2O3 epitaxial layer 40, thereby forming an epitaxial structure;

[0120] 6) A U-shaped groove structure with a depth of 800nm-1000nm is etched on the gate region of the surface of the high-doped β-Ga2O3 epitaxial layer 40 using ICP etching technology, and the opening of the groove structure is arranged on the surface of the high-doped β-Ga2O3 epitaxial layer, and the bottom of the groove is located in the β-Ga2O3 drift layer 20. Then, wet etching repair is performed;

[0121] 7) A 40nm-thick Al2O3 film is deposited on the surface of the high-doped β-Ga2O3 epitaxial layer 40 and the groove structure as a dielectric layer 80 using an ALD (atomic layer deposition) device, and the source region of the Al2O3 film is opened to expose the high-doped β-Ga2O3 epitaxial layer 40;

[0122] 8) Ti / Au metal (thickness of 50 / 150nm) is deposited on the front surface (the surface of the high-doped β-Ga2O3 epitaxial layer 40 facing away from the β-Ga2O3 high-resistance layer) and the back surface (the surface of the β-Ga2O3 substrate facing away from the β-Ga2O3 drift layer) of the epitaxial structure using electron beam evaporation or the like, and metal lift-off is performed using a lift-off stripping process, thereby preparing the source 50 and the drain 60 of the device;

[0123] 9) Rapid thermal annealing is performed on the sample using an RTP (rapid thermal annealing furnace) or the like, so as to realize ohmic contact between the source 50 and the high-doped β-Ga2O3 epitaxial layer 40, and between the drain 60 and the β-Ga2O3 substrate;

[0124] 10) Ni / Au metal (50 / 150nm) is deposited on the dielectric layer 80 as the gate 70 of the device using electron beam evaporation or the like, thereby obtaining a vertical enhancement type β-Ga2O3 UMOSFET device, and the device is recorded as device C.

[0125] Example 4

[0126] Please refer to Figure 4 A method for preparing a vertical enhancement type β-Ga2O3 UMOSFET device can include the following steps:

[0127] 1) The β-Ga2O3 substrate 10 with a 10μm-thick β-Ga2O3 drift layer 20 is subjected to organic cleaning;

[0128] 2) A 100nm-thick SiO2 film is grown on the first surface of the β-Ga2O3 drift layer 20 as an ion implantation sacrificial layer using PECVD (plasma enhanced chemical vapor deposition) or the like;

[0129] 3) using an ion implanter to implant N ions into the first face of the β-Ga2O3 drift layer 20 at a distance of 300 nm, and forming a 3 x 10 18 cm -3 N ion concentration;

[0130] 4) annealing at 1200°C for 30 minutes using a tube furnace to activate the N ions, thereby forming a 300 nm thick β-Ga2O3 high resistance layer 30 in the β-Ga2O3 drift layer 20, the electrons in the β-Ga2O3 high resistance layer 30 being depleted;

[0131] 5) using MOCVD to epitaxially grow a 100 nm thick high-doped (doping concentration of 1 x 10 19 cm -3 ~ 5 x 10 19 cm -3 β-Ga2O3 epitaxial layer 40 on the surface of the β-Ga2O3 high resistance layer 30, thereby forming an epitaxial structure;

[0132] 6) using ICP etching technology to etch a U-shaped groove structure of 800 nm ~ 1000 nm deep on the gate region of the surface of the high-doped β-Ga2O3 epitaxial layer 40, and the groove of the groove structure is arranged on the surface of the high-doped β-Ga2O3 epitaxial layer, and the groove bottom is located in the β-Ga2O3 drift layer 20, and then wet etching repair is performed;

[0133] 7) using ALD (atomic layer deposition) equipment to deposit a 40 nm thick Al2O3 film as a dielectric layer 80 on the surface of the high-doped β-Ga2O3 epitaxial layer 40 and the groove structure, and opening a hole in the source region of the Al2O3 film to expose the high-doped β-Ga2O3 epitaxial layer 40;

[0134] 8) using electron beam evaporation or the like to deposit Ti / Au metal (thickness of 50 / 150 nm) on the front surface (the surface of the high-doped β-Ga2O3 epitaxial layer 40 facing away from the β-Ga2O3 high resistance layer) and the back surface (the surface of the β-Ga2O3 substrate facing away from the β-Ga2O3 drift layer) of the epitaxial structure, and using lift-off stripping process to strip the metal, thereby preparing the source electrode 50 and the drain electrode 60 of the device;

[0135] 9) using RTP (rapid thermal annealing furnace) or the like to rapidly anneal the sample, so as to realize ohmic contact of the source electrode 50 and the high-doped β-Ga2O3 epitaxial layer 40, and the drain electrode 60 and the β-Ga2O3 substrate;

[0136] 10) Ni / Au metal (50 / 150 nm) is deposited on the dielectric layer 80 by electron beam evaporation or the like as the gate 70 of the device, thereby obtaining a vertical enhancement mode β-Ga2O3 UMOSFET device, which is recorded as device D.

[0137] Example 5

[0138] See also Figure 4 A method for preparing a vertical enhancement mode β-Ga2O3 UMOSFET device may include the following steps:

[0139] 1) organic cleaning of the β-Ga2O3 substrate 10 having the 10 μm thick β-Ga2O3 drift layer 20;

[0140] 2) using PECVD (plasma enhanced chemical vapor deposition) or other methods to grow a 100 nm thick SiO2 film on the first surface of the β-Ga2O3 drift layer 20 as an ion implantation sacrificial layer;

[0141] 3) Use an ion implanter to implant Mg ions and other compensation acceptor materials into the first surface of the β-Ga2O3 drift layer 20 at a distance of 300nm, and form a 1×10 18 cm -3 Mg ion concentration;

[0142] 4) Annealing at 1000° C. for 30 minutes in a tubular annealing furnace or the like to activate Mg ions, thereby forming a 300 nm thick β-Ga2O3 high-resistance layer 30 in the β-Ga2O3 drift layer 20, wherein electrons in the β-Ga2O3 high-resistance layer 30 are depleted;

[0143] 5) Using MOCVD to grow a 100nm thick high-doped layer (doping concentration of 1×10 19 cm -3 ~5×10 19 cm -3 ) β-Ga2O3 epitaxial layer 40, thereby forming an epitaxial structure;

[0144] 6) Using ICP etching technology, a U-shaped groove structure with a depth of 800nm ​​to 1000nm is etched in the gate area on the surface of the highly doped β-Ga2O3 epitaxial layer 40, with the notch of the groove structure set on the surface of the highly doped β-Ga2O3 epitaxial layer and the bottom of the groove located in the β-Ga2O3 drift layer 20, followed by wet etching repair;

[0145] 7) Using ALD (atomic layer deposition) equipment, a 40 nm thick Al203 film is deposited on the surface of the highly doped β-Ga203 epitaxial layer 40 and the groove-shaped structure as a dielectric layer 80, and a hole is made in the source area of the Al203 film to expose the highly doped β-Ga203 epitaxial layer 40;

[0146] 8) Using electron beam evaporation and the like, Ti / Au metal (thickness: 50 / 150 nm) is deposited on the front surface (the surface of the highly doped β-Ga203 epitaxial layer 40 facing away from the β-Ga203 high-resistance layer) and the back surface (the surface of the β-Ga203 substrate facing away from the β-Ga203 drift layer) of the epitaxial structure, and a lift-off process is used to peel off the metal, thereby preparing the source 50 and the drain 60 of the device;

[0147] 9) Using an RTP (rapid thermal processor) and the like, the sample is subjected to rapid annealing to achieve ohmic contact between the source 50 and the highly doped β-Ga203 epitaxial layer 40 and between the drain 60 and the β-Ga203 substrate;

[0148] 10) Using electron beam evaporation and the like, Ni / Au metal (50 / 150 nm) is deposited on the dielectric layer 80 as the gate 70 of the device, thereby obtaining a vertical enhancement-type β-Ga203 UMOSFET device, which is denoted as device E.

[0149] Example 6

[0150] Please refer to Figure 4 A method for manufacturing a vertical enhancement-type β-Ga203 UMOSFET device can include the following steps:

[0151] 1) The β-Ga203 substrate 10 having a 10 μm thick β-Ga203 drift layer 20 is subjected to organic cleaning;

[0152] 2) Using PECVD (plasma-enhanced chemical vapor deposition) and the like, a 100 nm thick SiO2 film is grown on the first surface of the β-Ga203 drift layer 20 as an ion implantation sacrificial layer;

[0153] 3) Using an ion implanter, N ions or the like are implanted into the β-Ga203 drift layer 20 at a distance of 600 nm from the first surface, and a 5 x 1018cm-2 N ion concentration is formed; 18 cm -3

[0154] 4) Using a tube furnace and the like, annealing is performed at 1200°C for 30 minutes to activate the N ions, thereby forming a 600 nm thick β-Ga203 high-resistance layer 30 in the β-Ga203 drift layer 20, and the electrons in the β-Ga203 high-resistance layer 30 are depleted; ​

[0155] 5) 100 nm thick high-doped (doping concentration of 1 x 1019cm-3) β-Ga2O3 epitaxial layer 40 is epitaxially grown on the surface of the β-Ga2O3 high-resistance layer 30 by MOCVD, thereby forming an epitaxial structure; 19 cm -3 ~ 5 x 1019cm-3 19 cm -3 ;

[0155] 6) A U-shaped groove structure with a depth of 800 nm to 1000 nm is etched on the gate region of the surface of the high-doped β-Ga2O3 epitaxial layer 40 by ICP etching technology, and the opening of the groove structure is arranged on the surface of the high-doped β-Ga2O3 epitaxial layer, and the bottom of the groove is located in the β-Ga2O3 drift layer 20, and then wet etching repair is performed;

[0156] 7) A 40 nm thick Al2O3 film is deposited as a dielectric layer 80 on the surface of the high-doped β-Ga2O3 epitaxial layer 40 and the groove structure by ALD (atomic layer deposition) equipment, and the source region of the Al2O3 film is opened to expose the high-doped β-Ga2O3 epitaxial layer 40;

[0157] 8) Ti / Au metal (thickness of 50 / 150 nm) is deposited on the front surface (the surface of the high-doped β-Ga2O3 epitaxial layer 40 facing away from the β-Ga2O3 high-resistance layer) and the back surface (the surface of the β-Ga2O3 substrate facing away from the β-Ga2O3 drift layer) of the epitaxial structure by electron beam evaporation or the like, and metal lift-off is performed by lift-off stripping process, thereby preparing the source 50 and the drain 60 of the device;

[0158] 9) Rapid thermal annealing is performed on the sample by RTP (rapid thermal annealing furnace) or the like, so as to realize ohmic contact between the source 50 and the high-doped β-Ga2O3 epitaxial layer 40, and between the drain 60 and the β-Ga2O3 substrate;

[0159] 10) Ni / Au metal (50 / 150 nm) is deposited on the dielectric layer 80 as the gate 70 of the device by electron beam evaporation or the like, thereby obtaining a vertical enhancement type β-Ga2O3 UMOSFET device, and denoted as device F.

[0160] Example 7

[0161] Please refer to

[0162] , a preparation method of a vertical enhancement type β-Ga2O3 UMOSFET device can include the following steps: Figure 4 1) The β-Ga2O3 substrate 10 with a 10 μm thick β-Ga2O3 drift layer 20 is subjected to organic cleaning;

[0163]

[0164] 2) A 100 nm thick SiO2 film is grown as an ion implantation sacrificial layer on the first surface of the β-Ga2O3 drift layer 20 by PECVD (plasma enhanced chemical vapor deposition) or the like;

[0165] 3) N ions are implanted as a compensating acceptor material into the β-Ga2O3 drift layer 20 at a distance of 600 nm from the first surface, and a 1 x 10 19 cm -3 N ion concentration is formed;

[0166] 4) Annealing is performed at 1200°C for 30 minutes using a tube furnace or the like to activate the N ions, thereby forming a 600 nm thick β-Ga2O3 high resistance layer 30 in the β-Ga2O3 drift layer 20, and the electrons in the β-Ga2O3 high resistance layer 30 are depleted;

[0167] 5) A 100 nm thick highly doped (doping concentration of 1 x 10 19 cm -3 to 5 x 10 19 cm -3 ) β-Ga2O3 epitaxial layer 40 is epitaxially grown on the surface of the β-Ga2O3 high resistance layer 30 by MOCVD, thereby forming an epitaxial structure;

[0168] 6) A U-shaped groove-shaped structure with a depth of 800 nm to 1000 nm is etched on the gate region of the surface of the highly doped β-Ga2O3 epitaxial layer 40 using ICP etching technology, and the opening of the groove-shaped structure is disposed on the surface of the highly doped β-Ga2O3 epitaxial layer, and the bottom of the groove is located in the β-Ga2O3 drift layer 20, and then wet etching is performed for repair;

[0169] 7) A 40 nm thick Al2O3 film is deposited as a dielectric layer 80 on the surface of the highly doped β-Ga2O3 epitaxial layer 40 and the groove-shaped structure by ALD (atomic layer deposition) equipment, and the source region of the Al2O3 film is opened to expose the highly doped β-Ga2O3 epitaxial layer 40;

[0170] 8) Ti / Au metal (thickness of 50 / 150 nm) is deposited on the front surface (the surface of the highly doped β-Ga2O3 epitaxial layer 40 facing away from the β-Ga2O3 high resistance layer) and the back surface (the surface of the β-Ga2O3 substrate facing away from the β-Ga2O3 drift layer) of the epitaxial structure by electron beam evaporation or the like, and metal lift-off is performed by lift-off peeling process, thereby preparing a source electrode 50 and a drain electrode 60 of the device;

[0171] 9) Rapid annealing of the sample is performed using RTP (rapid thermal processing) or the like to achieve ohmic contact of the source 50 with the highly doped β-Ga2O3 epitaxial layer 40 and the drain 60 with the β-Ga2O3 substrate;

[0172] 10) Ni / Au metal (50 / 150 nm) is deposited on the dielectric layer 80 as the gate 70 of the device by electron beam evaporation or the like to obtain a vertical enhancement β-Ga2O3 UMOSFET device, which is denoted as device G.

[0173] Comparative Example 1

[0174] A method for manufacturing a vertical enhancement β-Ga2O3 UMOSFET device can include the following steps:

[0175] 1) The β-Ga2O3 substrate 10 having a 10 μm thick β-Ga2O3 drift layer 20 is subjected to organic cleaning;

[0176] 2) A 100 nm thick SiO2 film is grown on the first face of the β-Ga2O3 drift layer 20 as an ion implantation sacrificial layer by PECVD (plasma enhanced chemical vapor deposition) or the like;

[0177] 3) N ions or the like are implanted into the β-Ga2O3 drift layer 20 at a distance of 600 nm from the first face as an acceptor material compensation by an ion implanter, and a 1.5 x 10 19 cm -3 N ion concentration is formed;

[0178] 4) Annealing is performed at 1100°C for 30 minutes by a tube furnace or the like to activate the N ions, thereby forming a 600 nm thick β-Ga2O3 high resistance layer 30 in the β-Ga2O3 drift layer 20, and the electrons in the β-Ga2O3 high resistance layer 30 are depleted;

[0179] 5) A 100 nm thick highly doped (doping concentration: 1 x 10 19 cm -3 ~ 5 x 10 19 cm -3 ) β-Ga2O3 epitaxial layer 40 is epitaxially grown on the surface of the β-Ga2O3 high resistance layer 30 by MOCVD, thereby forming an epitaxial structure;

[0180] 6) A U-shaped groove-like structure having a depth of 800 nm ~ 1000 nm is etched on the gate region of the surface of the highly doped β-Ga2O3 epitaxial layer 40 by ICP etching technology, and the groove opening of the groove-like structure is disposed on the surface of the highly doped β-Ga2O3 epitaxial layer, and the groove bottom is located in the β-Ga2O3 drift layer 20, and then wet etching is performed for repair;

[0181] 7) using ALD (atomic layer deposition) equipment to deposit a 40 nm thick Al2O3 film as a dielectric layer 80 on the surface of the highly doped β-Ga2O3 epitaxial layer 40 and the groove-shaped structure, and opening a hole in the source area of the Al2O3 film to expose the highly doped β-Ga2O3 epitaxial layer 40;

[0182] 8) using electron beam evaporation or the like to deposit Ti / Au metal (thickness 50 / 150 nm) on the front surface (the surface of the highly doped β-Ga2O3 epitaxial layer 40 facing away from the β-Ga2O3 high resistance layer) and the back surface (the surface of the β-Ga2O3 substrate facing away from the β-Ga2O3 drift layer) of the epitaxial structure, and using a lift-off stripping process to strip the metal, thereby preparing the source 50 and drain 60 of the device;

[0183] 9) using RTP (rapid thermal annealing furnace) or the like to rapidly anneal the sample, so as to achieve ohmic contact between the source 50 and the highly doped β-Ga2O3 epitaxial layer 40, and between the drain 60 and the β-Ga2O3 substrate;

[0184] 10) using electron beam evaporation or the like to deposit Ni / Au metal (50 / 150 nm) on the dielectric layer 80 as the gate 70 of the device, thereby obtaining a vertical enhancement type β-Ga2O3 UMOSFET device, and denoted as device H.

[0185] Comparative Example 2

[0186] A method for preparing a vertical enhancement type β-Ga2O3 UMOSFET device can include the following steps:

[0187] 1) performing organic cleaning on a β-Ga2O3 substrate 10 having a 10 μm thick β-Ga2O3 drift layer 20;

[0188] 2) using PECVD (plasma enhanced chemical vapor deposition) or the like to grow a 100 nm thick SiO2 film as an ion implantation sacrificial layer on the first surface of the β-Ga2O3 drift layer 20;

[0189] 3) using an ion implanter to implant N ions or the like as an acceptor material into the β-Ga2O3 drift layer 20 at a distance of 600 nm from the first surface, and forming a 5×10 17 cm -3 N ion concentration;

[0190] 4) using a tube furnace or the like to anneal at 1100°C for 30 minutes to activate the N ions, thereby forming a 600 nm thick β-Ga2O3 high resistance layer 30 in the β-Ga2O3 drift layer 20, and depleting the electrons in the β-Ga2O3 high resistance layer 30;

[0191] 5) Using MOCVD to epitaxially grow a 100 nm thick highly doped (doping concentration of 1 x 10 19 cm -3 ~ 5 x 10 19 cm -3 ) β-Ga2O3 epitaxial layer 40 on the surface of the β-Ga2O3 high resistance layer 30, thereby forming an epitaxial structure;

[0192] 6) Using ICP etching technology to etch a 800 nm to 1000 nm deep U-shaped groove structure on the gate region of the surface of the highly doped β-Ga2O3 epitaxial layer 40, and arranging the groove opening of the groove structure on the surface of the highly doped β-Ga2O3 epitaxial layer, and arranging the groove bottom in the β-Ga2O3 drift layer 20, and then performing wet etching repair;

[0193] 7) Using ALD (atomic layer deposition) equipment to deposit a 40 nm thick Al2O3 film as a dielectric layer 80 on the surface of the highly doped β-Ga2O3 epitaxial layer 40 and the groove structure, and performing opening on the source region of the Al2O3 film to expose the highly doped β-Ga2O3 epitaxial layer 40;

[0194] 8) Using electron beam evaporation and the like to deposit Ti / Au metal (thickness of 50 / 150 nm) on the front surface (the surface of the highly doped β-Ga2O3 epitaxial layer 40 facing away from the β-Ga2O3 high resistance layer) and the back surface (the surface of the β-Ga2O3 substrate facing away from the β-Ga2O3 drift layer) of the epitaxial structure, and using lift-off stripping process to strip the metal, thereby preparing the source 50 and the drain 60 of the device;

[0195] 9) Using RTP (rapid thermal annealing furnace) and the like to perform rapid annealing on the sample, so as to realize ohmic contact of the source 50 and the highly doped β-Ga2O3 epitaxial layer 40, and the drain 60 and the β-Ga2O3 substrate;

[0196] 10) Using electron beam evaporation and the like to deposit Ni / Au metal (50 / 150 nm) on the dielectric layer 80 as the gate 70 of the device, thereby obtaining a vertical enhancement type β-Ga2O3 UMOSFET device, and recording the device as device I.

[0197] Comparative Example 3

[0198] A preparation method of a vertical enhancement type β-Ga2O3 UMOSFET device is basically the same as that of Example 1, except that steps 3) and 4) in Comparative Example 3 are to use Mg-doped spin-on-glass as a doping source to prepare an electron blocking layer by Mg diffusion. The device obtained in Comparative Example 3 is recorded as device I.

[0199] Comparative Example 4

[0200] Comparative Example 4 is as follows Figure 1 A FinFET device is shown, denoted as device.

[0201] Comparative Example 5

[0202] Comparative Example 5 is as follows Figure 2 A CAVET device is shown, denoted as device K.

[0203] Comparative Example 6

[0204] An enhancement-mode gallium oxide MOSFET obtained by the preparation method disclosed in CN 110571275 A is denoted as device L.

[0205] The transfer output curve of a vertical enhancement mode β-Ga2O3 UMOSFET device provided in Examples 1-7 of the present invention is as follows: Figure 5a As shown, it can be seen that the threshold voltage of the device (V th ) is 7.6V (defined as current reaching 1A / cm 2 The device is turned on when the device is turned on), which proves that the device has achieved enhancement characteristics, and the threshold voltage is in a safe area, avoiding the situation where the device is turned on by mistake; the transfer output curve of a vertical enhancement mode β-Ga2O3 UMOSFET device provided in Examples 1-7 of the present invention is as follows Figure 5b As shown in Figure 2, after considering the current expansion, the current density of the device can reach 219.3A / cm 2 , which is much higher than the current density of the CAVET device. Among them, the N ion implantation concentration, annealing temperature and annealing time all affect the threshold voltage and saturation current density values.

[0206] Specifically, when the N ion implantation concentration is 5×10 18 cm -3 The output curve of the device is as follows Figure 6a As shown, when the N ion implantation concentration is 5×10 18 cm -3 The transfer curve of the device is as follows Figure 6b As shown; when the N ion implantation concentration is 1×10 19 cm -3 The output curve of the device is as follows Figure 6c As shown, when the N ion implantation concentration is 1×10 19 cm -3 The device transfer curve is as follows Figure 6d As shown. Among them, Figure 6a 、 Figure 6c The output curves of device B and device C are respectively, where device B is at V DS =10V and V GSThe saturation current density at 15V is about 7 times of that of device C (the current diffusion effect is not considered in the calculation of current density of both devices); the main reason for the significant difference in current density is that the difference in N ion implantation concentration affects the number of free-moving electrons in the Ga2O3 drift layer, thereby affecting the resistivity of the channel layer, resulting in a change in current density. Figure 6b and Figure 6d are the transfer curves of device B and device C respectively, defining the device current density reaching 1A / cm 2 when the device is turned on, so the threshold voltage of device B and device C is 4.2V and 10.7V respectively; the change in device threshold voltage is also caused by the change in N ion concentration, when the N ion implantation concentration is higher, a higher gate voltage is needed to accumulate enough electrons on the U-shaped groove sidewall to make the device conductive.

[0207] Figure 7a , Figure 7b show the breakdown curves of device B and device C respectively when the N ion implantation concentration is 5×10 18 cm -3 and 1×10 19 cm -3 respectively; it can be seen that the breakdown voltage of device C is slightly higher than that of device B; although the breakdown voltage of Ga2O3 UMOSFET device is still relatively low at present, Ga2O3 UMOSFET device is still in the early stage of development, and the withstand voltage performance can be greatly improved through subsequent optimization scheme. According to the current data, it can be predicted that the device prepared with low N ion implantation concentration has the characteristics of low threshold voltage, large current density and low breakdown voltage, which can be applied in small power low voltage such as electronic switch; the device prepared with high N ion implantation concentration has the characteristics of high threshold voltage, low current density and high breakdown voltage, which can be applied in small power medium and high voltage such as small power high voltage auxiliary power supply.

[0208] Specifically, the effect of annealing temperature on the device is similar to the effect of implantation concentration. After N ion implantation, annealing at 1100 DEG C for 30 minutes is needed to activate N ions. However, due to the stability of N ions, the activation efficiency is not very high. Therefore, under the same N ion implantation concentration, increasing the annealing temperature or time to improve the activation efficiency of N ions has a similar effect to directly increasing the N ion implantation concentration. The difference is that increasing the N ion implantation concentration will introduce more implantation damage, affecting the leakage current and electron mobility of the device, while increasing the annealing temperature or annealing time will reduce the damage to the device. The U-shaped groove in the Ga2O3 UMOSFET device is obtained by dry etching, but dry etching will cause etching damage to the sidewall of the U-shaped groove, affecting the electron mobility and reducing the saturation current density. Moreover, the etching damage of the interface will also affect the MOS interface quality and the threshold voltage of the device. If a better interface processing method is selected, this situation will be changed. In addition, the U-shaped groove bottom near the sidewall region often cannot obtain an arc-shaped morphology due to process problems and is 90 DEG, which causes the field strength in this region to concentrate and causes the device gate to break down, thereby affecting the voltage withstanding performance of the device. If the U-shaped groove is replaced by an inverted trapezoidal groove, the bottom of the groove near the sidewall region will have an obtuse angle, which can greatly reduce the electric field strength in this region and thus improve the voltage withstanding performance of the device. Figure 8a 、 Figure 8b The breakdown curves of Ga2O3 MOSFET devices with U-shaped grooves and inverted trapezoidal grooves are shown respectively.

[0209] Correspondingly, the characterization curves of the devices formed in Embodiment 1 and Embodiments 4-7 can refer to the characterization curves of the devices B and C formed in Embodiments 2 and 3.

[0210] The working principle of the present application is to use ion implantation technology to implant N ions into the Ga2O3 drift layer, to capture electrons by N ions and thus deplete the electrons in the Ga2O3 drift layer to achieve the purpose of blocking the source-drain current. After applying a certain gate voltage, enough electrons will accumulate on the sidewall of the U-shaped groove to make the device conductive. Therefore, the concentration of N ion implantation controls the number of captured electrons, indirectly affects the number of free-moving electrons, and thus affects the threshold voltage and current density of the device.

[0211] Compared with the device obtained in Comparative Examples 1-6, the key of the preparation method of the vertical enhancement type β-Ga2O3 UMOSFET device provided by the embodiment of the application is to realize electron depletion in the β-Ga2O3 drift layer based on ion implantation technology, and successfully prepare the vertical enhancement type β-Ga2O3 UMOSFET device; and the current density and breakdown voltage of the device can be optimized by adjusting the N ion implantation concentration to meet the application of various scenes; and the device performance can be greatly improved by optimizing the annealing temperature, implantation concentration, better interface processing method and optimizing the U-shaped groove shape; at the same time, the preparation method of the vertical enhancement type β-Ga2O3 UMOSFET device provided by the embodiment of the application gets rid of the dependence of the β-Ga2O3 UMOSFET device on the p-type material, and provides a new implementation path for the β-Ga2O3 power device.

[0212] The vertical enhancement type β-Ga2O3 UMOSFET device provided by the embodiment of the application uses N ions implanted into the β-Ga2O3 drift layer as a compensating acceptor to realize electron depletion, successfully prepares the vertical enhancement type β-Ga2O3 UMOSFET device, has small process difficulty, small capacitance and parasitic effect, and controllable threshold voltage compared with the FinFET device; and has large current density, small gate-source leakage current and can work at high voltage compared with the CAVET device.

[0213] The preparation method of the vertical enhancement type β-Ga2O3 UMOSFET device provided by the embodiment of the application can control the threshold voltage by adjusting the implantation concentration of the compensating acceptor material such as N ions, so as to effectively avoid the mis-opening condition, and specifically, when the N ion implantation concentration is high, more electrons will be captured in the implantation region to form a high-resistance region with good effect, that is, the number of free-moving electrons in this region is extremely small, so that a larger gate voltage is needed to attract a sufficient number of electrons to accumulate on the U-shaped groove sidewall to promote the conduction of the device; on the contrary, when the N ion implantation concentration is low, a smaller gate voltage can attract a sufficient number of electrons to accumulate. For example: when the N ion implantation concentration is 1x10 18 cm -3 , the device can be turned on only when the gate voltage is 4V, that is, the threshold voltage is 4V, and if the N ion implantation concentration is 1x10 19 cm -3 , the device can be turned on only when the gate voltage is 6V, that is, the threshold voltage is 6V.

[0214] The preparation method of the vertical enhancement type beta-Ga2O3 UMOSFET device can improve the withstand voltage performance of the device by optimizing the shape of the groove structure.

[0215] It should be understood that the above embodiments are only to illustrate the technical concept and characteristics of the present application, and the purpose is to enable those skilled in the art to understand the content of the present application and to implement it, and cannot limit the protection scope of the present application. Any equivalent changes or modifications made in accordance with the spirit and essence of the present application shall be covered within the protection scope of the present application.

Claims

1. A method for preparing a vertical enhancement mode β-Ga2O3 UMOSFET device, characterized in that: include: providing a β-Ga2O3 drift layer, injecting a compensating acceptor material into a surface region of the β-Ga2O3 drift layer on a side where the first surface is located, and activating the compensating acceptor material to deplete electrons in the surface region of the β-Ga2O3 drift layer to form a carrier depletion region, forming a highly doped β-Ga2O3 epitaxial layer on the carrier depletion region, wherein the doping concentration of the highly doped β-Ga2O3 epitaxial layer is higher than that of the β-Ga2O3 drift layer; Making a groove-shaped structure, with the groove opening of the groove-shaped structure being arranged on the surface of the highly doped β-Ga2O3 epitaxial layer and the groove bottom being arranged in the β-Ga2O3 drift layer; Fabricating a dielectric layer so that the dielectric layer continuously covers the surface of the highly doped β-Ga2O3 epitaxial layer and the groove wall of the groove structure; A source electrode, a drain electrode, and a gate electrode are fabricated, wherein at least a partial region of the gate electrode is continuously covered on the groove wall of the groove structure, and the gate electrode and the groove wall of the groove structure are isolated by a dielectric layer; the source electrode is disposed on a highly doped β-Ga2O3 epitaxial layer and forms an ohmic contact with the highly doped β-Ga2O3 epitaxial layer; the drain electrode is electrically coupled to the second surface of the β-Ga2O3 drift layer, and the second surface is disposed opposite to the first surface.

2. The method for preparing a vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 1, characterized in that: include: A compensation acceptor material is injected into the surface region of the first side of the β-Ga2O3 drift layer, and then annealed at 1000-1200°C for 30-60 minutes to activate the compensation acceptor material and deplete electrons in the surface region.

3. The method for preparing a vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 2, characterized in that: The compensating acceptor material includes N ions or Mg ions.

4. The method for preparing a vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 2, characterized in that: The concentration of the compensation acceptor material in the carrier depletion region is 1×10 18 cm -3 ~1×10 19 cm -3 .

5. The method for preparing a vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 1, 2, 3 or 4, characterized in that: include: An ion implantation sacrificial layer is first formed on the first surface of the β-Ga2O3 drift layer, and then a compensation acceptor material is implanted into the surface region of the side where the first surface of the β-Ga2O3 drift layer is located.

6. The method for preparing a vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 5, characterized in that: The material of the ion implantation sacrificial layer includes silicon oxide.

7. The method for preparing a vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 5, characterized in that: The thickness of the ion implantation sacrificial layer is 50-200 nm.

8. The method for preparing a vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 2, characterized in that: include: A highly doped β-Ga2O3 epitaxial layer is directly grown on the carrier depletion region, or a β-Ga2O3 epitaxial layer is first grown on the carrier depletion region and then the β-Ga2O3 epitaxial layer is transformed into a highly doped β-Ga2O3 epitaxial layer by ion implantation.

9. The method for preparing a vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 8, characterized in that: The preparation method comprises: injecting Si ions into the β-Ga2O3 epitaxial layer to transform the β-Ga2O3 epitaxial layer into a highly doped β-Ga2O3 epitaxial layer.

10. The method for preparing a vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 8 or 9, characterized in that: The doping concentration of the highly doped β-Ga2O3 epitaxial layer is 1×10 19 cm -3 ~5×10 19 cm -3 .

11. The method for preparing a vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 8 or 9, characterized in that: The thickness of the highly doped β-Ga2O3 epitaxial layer is 100-300 nm.

12. The method for preparing a vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 2, characterized in that: The depth of the groove structure is 800-1000 nm.

13. The method for preparing a vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 2, characterized in that: The groove structure is a U-shaped groove, a V-shaped groove or an inverted trapezoidal groove.

14. The method for preparing a vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 2, characterized in that: The β-Ga2O3 drift layer is arranged on a β-Ga2O3 substrate, and the drain is arranged on a surface of the β-Ga2O3 substrate away from the β-Ga2O3 drift layer and forms an ohmic contact with the β-Ga2O3 substrate.

15. The method for preparing a vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 14, characterized in that: The carrier concentration of the highly doped β-Ga2O3 epitaxial layer is greater than the carrier concentration of the β-Ga2O3 substrate and greater than the carrier concentration of the β-Ga2O3 drift layer.

16. The method for preparing a vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 14, characterized in that: The conductivity types of the β-Ga2O3 substrate, the β-Ga2O3 drift layer, and the highly doped β-Ga2O3 epitaxial layer are all n-type, and the carrier depletion region is a high resistance layer.

17. A vertical enhancement mode β-Ga2O3 UMOSFET device obtained by the method for preparing a vertical enhancement mode β-Ga2O3 UMOSFET device according to any one of claims 1 to 16, characterized in that: include: The β-Ga2O3 drift layer has a first surface and a second surface disposed opposite to each other, a carrier depletion region formed in a surface region on the side where the first surface of the β-Ga2O3 drift layer is located; a highly doped β-Ga2O3 epitaxial layer, formed on the carrier depletion region, wherein the doping concentration of the highly doped β-Ga2O3 epitaxial layer is higher than that of the β-Ga2O3 drift layer; A groove structure, wherein the groove opening is arranged on the surface of the highly doped β-Ga2O3 epitaxial layer and the groove bottom is arranged in the β-Ga2O3 drift layer; a dielectric layer continuously covering the surface of the highly doped β-Ga2O3 epitaxial layer and the groove wall of the groove structure; a gate electrode, at least a partial area of ​​which is continuously covered on the groove wall of the groove structure, and the gate electrode and the groove wall of the groove structure are isolated by a dielectric layer; a source electrode, which is disposed on the highly doped β-Ga2O3 epitaxial layer and forms an ohmic contact with the highly doped β-Ga2O3 epitaxial layer; A drain electrode is electrically coupled to the second surface of the β-Ga2O3 drift layer.

18. The vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 17, characterized in that: The carrier depletion region is formed by converting the surface region of the first surface of the β-Ga2O3 drift layer into a compensation acceptor material.

19. The vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 18, characterized in that: The compensating acceptor material includes N ions or Mg ions.

20. The vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 18, characterized in that: The concentration of the compensation acceptor material in the carrier depletion region is 1×10 18 cm -3 ~1×10 19 cm -3 .

21. The vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 18, characterized in that: The thickness of the carrier depletion region is 300-600 nm, and the thickness of the β-Ga2O3 drift layer is 4-10 μm.

22. The vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 17, characterized in that: The doping concentration of the highly doped β-Ga2O3 epitaxial layer is 1×10 19 cm -3 ~5×10 19 cm -3 .

23. The vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 17, characterized in that: The thickness of the highly doped β-Ga2O3 epitaxial layer is 100-300 nm.

24. The vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 17, characterized in that: The depth of the groove structure is 800-1000 nm.

25. The vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 17, characterized in that: The groove structure is a U-shaped groove, a V-shaped groove or an inverted trapezoidal groove.

26. The vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 17, characterized in that: It also includes a β-Ga2O3 substrate, the β-Ga2O3 drift layer is arranged on the β-Ga2O3 substrate, and the drain is arranged on a side surface of the β-Ga2O3 substrate away from the β-Ga2O3 drift layer and forms an ohmic contact with the β-Ga2O3 substrate.

27. The vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 26, characterized in that: The carrier concentration of the highly doped β-Ga2O3 epitaxial layer is greater than the carrier concentration of the β-Ga2O3 substrate and greater than the carrier concentration of the β-Ga2O3 drift layer.

28. The vertical enhancement mode β-Ga2O3 UMOSFET device according to claim 26, characterized in that: The conductivity types of the β-Ga2O3 substrate, the β-Ga2O3 drift layer, and the highly doped β-Ga2O3 epitaxial layer are all n-type, and the carrier depletion region is a high resistance layer.

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