Beam control system and beam control method of phased array antenna

Abstract

The application discloses a beam control system and a beam control method of a phased array antenna. The beam control system of the phased array antenna comprises a processor, a first FPGA circuit and the phased array antenna. The first FPGA circuit is coupled with the processor. The phased array antenna is coupled with the first FPGA circuit. The first FPGA circuit has at least two antenna operating modes. The processor is configured to send a switching instruction to the first FPGA circuit. The first FPGA circuit is configured to select an antenna operating mode corresponding to the switching instruction in response to the switching instruction, and control the phased array antenna to operate in the selected antenna operating mode. In this way, the flexibility of the phased array antenna control can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of phased array antenna control, in particular to a phased array antenna beam control system and a beam control method. BACKGROUND

[0002] In a satellite on-the-move antenna and a base station antenna, as long as the antenna and the target move relatively, the antenna beam tracking problem is inevitably involved. The faster the relative motion speed, the higher the requirement for the beam pointing speed and accuracy, which is the main problem to be solved by the antenna stabilization system and the prerequisite for satellite communication and wireless communication. Under such circumstances, compared with the traditional mechanical antenna, the phased array antenna has incomparable advantages and can meet the needs of various emergency communication and multimedia communication under mobile conditions, and has extremely wide development prospects in military and civilian fields.

[0003] The rapid, efficient and flexible performance of phased array antenna beam switching is realized through the wave control system. The wave control system is unique to the phased array antenna, which replaces the function of the servo driver in the traditional mechanical scanning radar. Its main function is to calculate the control code required by each antenna unit phase shifter under the control of the calculation unit according to the angle of beam pointing, and transmit, amplify and send to each phase shifter to control the phase of each antenna unit receiving and transmitting. The signal energy of each antenna unit of the phased array antenna is superimposed in a specified direction in space to form the required antenna beam. SUMMARY

[0004] The technical problem solved by the present application is to provide a phased array antenna beam control system and a beam control method, which can flexibly control the operation of the phased array antenna.

[0005] To solve the above technical problems, one technical solution adopted by the present application is to provide a phased array antenna beam control system, wherein the phased array antenna beam control system comprises a processor, a first FPGA circuit and a phased array antenna; the first FPGA circuit is coupled to the processor; the phased array antenna is coupled to the first FPGA circuit; the first FPGA circuit has at least two antenna operation modes; the processor is configured to send a switching instruction to the first FPGA circuit; the first FPGA circuit is configured to select an antenna operation mode corresponding to the switching instruction in response to the switching instruction, and control the phased array antenna to operate according to the selected antenna operation mode.

[0006] To solve the above technical problems, another technical solution adopted by the present application is to provide a beam control method, which comprises: generating a switching instruction; selecting an antenna operation mode corresponding to the switching instruction; and controlling the phased array antenna to operate according to the selected antenna operation mode.

[0007] Compared with the prior art, the application has the beneficial effects that: by setting at least two antenna operation modes in the first FPGA circuit, the first FPGA circuit switches to the antenna operation mode corresponding to the switching instruction of the processor in response to the switching instruction, the working mode of the antenna can be adjusted according to different use scenarios, the control of the phased array antenna is more flexible and free, and the FPGA has natural advantages of self-definition, parallel calculation, pipeline processing and the like, can process faster in mode switching and antenna control, can effectively reduce the pressure of the processor, and then realize fast mode switching, fast and accurate antenna beam pointing, and practically widen the application scenarios of the phased array antenna. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a first schematic block diagram of a beam control system embodiment of the phased array antenna of the application;

[0009] Figure 2 is a second schematic block diagram of a beam control system embodiment of the phased array antenna of the application;

[0010] Figure 3 is a third schematic block diagram of a beam control system embodiment of the phased array antenna of the application;

[0011] Figure 4 is a fourth schematic block diagram of a beam control system embodiment of the phased array antenna of the application;

[0012] Figure 5 is a schematic diagram of phased array antenna arrangement in the beam control system embodiment of the phased array antenna of the application;

[0013] Figure 6 is a first FPGA circuit schematic block diagram in the beam control system embodiment of the phased array antenna of the application;

[0014] Figure 7 is a circuit schematic block diagram of a random function module of the first FPGA circuit shown in Figure 6 ;

[0015] Figure 8 is a circuit schematic block diagram of a scanning function module of the first FPGA circuit shown in Figure 6 ;

[0016] Figure 9 is a circuit schematic block diagram of a dot position function module of the first FPGA circuit shown in Figure 6 ;

[0017] Figure 10 is a circuit schematic block diagram of a de-framing function module of the first FPGA circuit shown in Figure 6 ;

[0018] Figure 11yes Figure 6 A schematic block diagram of a circuit of an interrupt module of the first FPGA circuit shown;

[0019] Figure 12 This is a schematic block diagram of a second FPGA circuit of an embodiment of the beam control system of the phased array antenna of the present application;

[0020] Figure 13 yes Figure 12 A schematic block diagram of a circuit of a de-framing functional module of the second FPGA circuit shown;

[0021] Figure 14 yes Figure 12 A schematic block diagram of the circuit of the numbered functional modules of the second FPGA circuit shown;

[0022] Figure 15 yes Figure 12 A schematic block diagram of a circuit of a temperature control module of the second FPGA circuit shown;

[0023] Figure 16 yes Figure 12 A schematic block diagram of a circuit of an array scanning module of the second FPGA circuit shown;

[0024] Figure 17 yes Figure 12 A schematic block diagram of a circuit of a calibration function module of the second FPGA circuit shown;

[0025] Figure 18 yes Figure 12 A schematic block diagram of a circuit of a scheduling function module of the second FPGA circuit shown;

[0026] Figure 19 yes Figure 12 A schematic block diagram of a modulation output module of the second FPGA circuit shown;

[0027] Figure 20 It is a flowchart of an embodiment of the beam control method of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0029] See Figure 1The beam control system 1 (not labeled) described in the embodiment of the beam control system of the phased array antenna of the present application can include a processor 100, a first FPGA circuit 200, a phased array antenna 300, a beamforming chip 400 and a second FPGA circuit 500.

[0030] The first FPGA circuit 200 can be coupled with the processor 100. The phased array antenna 300 can be coupled with the first FPGA circuit 200. Optionally, the second FPGA circuit 500 can be coupled with the first FPGA circuit 200, and the beamforming chip 400 can be coupled with the second FPGA circuit 500 and the phased array antenna 300.

[0031] The first FPGA circuit 200 has at least two antenna operating modes. The processor 100 is configured to send a switching instruction to the first FPGA circuit 200. The first FPGA circuit 200 is configured to select an antenna operating mode corresponding to the switching instruction in response to the switching instruction, and control the phased array antenna 300 to operate in the selected antenna operating mode. Optionally, the second FPGA circuit 500 is configured to perform corresponding calculations in the selected antenna operating mode. The beamforming chip 400 is configured to phase the phased array antenna 300 according to the selected antenna operating mode.

[0032] Optionally, referring to Figure 2 The processor 100 and the first FPGA circuit 200 are integrated on a first circuit board, and the second FPGA circuit 500 and the beamforming chip 400 are integrated on a second circuit board. Specifically, the first circuit board includes the processor 100, the first FPGA circuit 200 and other auxiliary devices. According to the function of the first circuit board, which is to control the phased array antenna 300, the first circuit board can be classified as an antenna control unit (ACU), i.e., an ACU board card 10. The second circuit board includes the second FPGA circuit 500, the beamforming chip 400, the phased array antenna 300 and auxiliary devices. According to the function of the second circuit board, which is to enable the phased array antenna 300 to operate in the corresponding antenna operating mode, the second circuit board can be classified as an active antenna unit (AAU), i.e., an AAU board card 20. The auxiliary devices can be a sensor peripheral for collecting the operating temperature of the phased array antenna 300, a GPS with positioning function, or an external FLASH with storage function, etc.

[0033] The processor 100, which can also be referred to as a CPU (Central Processing Unit), can be configured to control the operation of the beam control system 1 (not labeled), for example. The processor 100 can be an integrated circuit chip with processing capability. The processor 100 can also be a general purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. The general purpose processor can be a microprocessor or the processor 100 can also be any conventional processor.

[0034] The beam-forming IC 400 can be integrated with phase shifters, attenuators, transceiver switches and the like.

[0035] Optionally, switching instructions corresponding to the antenna operation modes can be generated to switch between different antenna operation modes. When one of the switching instructions is sent to the first FPGA circuit 200, the first FPGA circuit 200 receives the switching instruction and executes the antenna operation mode corresponding to the switching instruction, and the phased array antenna 300 operates according to the antenna operation mode of the first FPGA circuit 200.

[0036] The switching of the antenna operation modes can be related to the state, position and number of external devices, or can also be related to the state of the phased array antenna 300. For example, the beam control system 1 (not labeled) obtains the state and position of the external devices, generates a switching instruction corresponding to the state, and sends the switching instruction to the first FPGA circuit 200. Different antenna operation modes can be suitable for different scenarios.

[0037] By setting at least two antenna operation modes in the first FPGA circuit 200, the first FPGA circuit 200 switches to the antenna operation mode corresponding to the switching instruction in response to the switching instruction of the processor 100, and the antenna operation mode can be adjusted according to different use scenarios, so that the control of the phased array antenna 300 is more flexible and free. Moreover, the FPGA has the natural advantages of customization, parallel calculation, pipeline processing and the like, and can process faster in mode switching and antenna control, which can effectively reduce the pressure of the processor 100, and further realize fast mode switching, fast and accurate pointing of the antenna beam, and effectively expand the application scenarios of the phased array antenna 300.

[0038] Optionally, the at least two antenna operation modes can include a random mode and a non-random mode. The random mode is, for example, a random mode in which the processor 100 generates frame content for beam switching, and the non-random mode is, for example, a mode in which the first FPGA circuit 200 generates frame content for beam switching. The phased array antenna 300 is used to perform operation corresponding to the frame content for beam switching.

[0039] The random mode is described as follows:

[0040] Optionally, when the first FPGA circuit 200 selects the random mode, the processor 100 is configured to set frame content for beam switching and send the frame content to the first FPGA circuit 200. The processor 100 can set the frame content for beam switching to be of any frequency, pointing angle, etc. In this way, the function of freely operating the phased array antenna 300 can be achieved. The pointing angle can include, for example, an azimuth angle and an elevation angle, etc.

[0041] Specifically, in the random mode, the processor 100 can set any frame content for beam switching and write the frame content into a register of the first FPGA circuit 200, and control the phased array antenna 300 to perform operation corresponding to the frame content for beam switching through the first FPGA circuit 200.

[0042] Further, in the random mode, the processor 100 can also generate an instruction frame or a data frame for calling an auxiliary device, such as a temperature frame for controlling a temperature sensor to collect the operating temperature of the phased array antenna 300, an instruction frame for calling external FLASH content, or a data frame for writing into external FLASH.

[0043] In the random mode, by setting any frame content through the processor 100, manual control of the phased array antenna 300 and calling of the auxiliary device can be achieved.

[0044] The non-random mode is described as follows:

[0045] Optionally, when the first FPGA circuit 200 selects the non-random mode, the first FPGA circuit 200 is configured to read table item information in a storage table thereof to generate frame content for beam switching.

[0046] In the non-random mode, the frame content for beam switching is generated by the first FPGA circuit 200, and the frame content can be pre-stored in the first FPGA circuit 200. After the processor 100 issues a switching instruction of the non-random mode, the first FPGA circuit 200 receives the switching instruction and performs the non-random mode, generates the frame content for beam switching, and controls the phased array antenna 300 to perform operation corresponding to the frame content for beam switching.

[0047] In the non-random mode, at least one storage table in the first FPGA circuit 200, the first FPGA circuit 200 can read the table information in the storage table, and the table information is used as the frame content to control the phased array antenna 300 to switch the beam. Through the pre-stored table information in the storage table, the frame content is quickly searched and generated, thereby saving the time for obtaining the frame content for beam switching, and further improving the speed of beam pointing.

[0048] Specifically, the non-random mode can include a scanning mode and a point mode. The scanning mode refers to the phased array antenna 300 working in a corresponding range of elevation angle and azimuth angle in a scanning manner. The point mode refers to the phased array antenna 300 working at a specific elevation angle and azimuth angle.

[0049] (1) Scanning mode

[0050] The first FPGA circuit 200 is used to read the corresponding table information in the storage table in a preset order in the scanning mode. The corresponding table information can refer to all table information in the storage table, or part of the table information. For example, the table information in the storage table is from the first item to the 100th item, and the scanning mode can scan all table information or part of the table information, for example, the 50th-80th table information. Alternatively, the table information of the storage table can be customized.

[0051] In the scanning mode, the first FPGA circuit 200 sends the frame content for switching the beam pre-stored in the storage table to the phased array antenna 300, and then the first FPGA circuit 200 reads the corresponding table information in the storage table in a preset order. The storage table can contain azimuth angle, elevation angle, or frequency content, and different content can be saved as table information in the storage table. The first FPGA circuit 200 can poll from the first table information to the Nth table information, and so on, and the scanning time of one round depends on the number of scanned table information, the number of data frames, the interface rate, and the response speed of the phased array antenna 300.

[0052] By scanning the table information in the storage table to obtain the frame content for beam switching, the processor 100 process occupation time can be greatly saved, and the fast operation of beam switching is realized. Further, in the scanning mode, the first FPGA circuit 200 repeatedly polls the table information, and further generates the frame content for beam switching, thereby realizing the full-automatic control of the phased array antenna 300.

[0053] In the scan mode, the beam control system 1 (not labeled) supports the breakpoint resume. For example, the first FPGA circuit 200 is used to receive the switching instruction of switching to the random mode in the scan mode, and then save the position information of the current unread next table item information in the storage table, and then switch to the random mode in response to the switching instruction. The first FPGA circuit 200 resumes the scan mode after completing the random mode, and reads the position information to continue reading the remaining unread table item information in the preset order. The current unread next table item information refers to the next table item information that has been read completely.

[0054] When the first FPGA circuit 200 performs the scan working mode, and polls to a certain position of the storage table, and receives the switching instruction of the processor 100 switching to the random access working mode, the first FPGA circuit 200 ends the current table item information transmission, saves the position information of the unread next table item information in the storage table, that is, saves the breakpoint, and then switches to the random access mode. After the access in the random mode ends, the first FPGA circuit 200 switches to the scan working mode again, and then continues to read the remaining unread table item information in the preset order from the saved position information.

[0055] By setting the breakpoint saving function in the scan mode process, the first FPGA circuit 200 does not need to re-scan the table item information that has been scanned in the storage table, and directly continues to complete the scan work from the unread table item information, which can save the repeated scan time.

[0056] (2) Point mode

[0057] The first FPGA circuit 200 receives the point information sent by the processor 100 in the point mode, and reads the table item information specified by the point information in the storage table. The point information is, for example, a point number, which is used to identify the position of the table item information in the storage table. Each table item information in the storage table of the first FPGA circuit 200 can have a corresponding point number.

[0058] In the point mode, the first FPGA circuit 200 receives the point information sent by the processor 100, and reads the table item information specified by the point information in the storage table. For example, for a 5G base station antenna, 64 point numbers can be set, the first FPGA circuit 200 selects the point mode, the processor 100 sends the point number to the first FPGA circuit 200, and the first FPGA circuit 200 directly reads the table item information corresponding to the point number in the storage table after receiving the point number. The first FPGA circuit 200 directly obtains the frame content for beam switching through the point number informed by the processor 100, which is faster in operation and can be an important supplement to the random mode. Further, in the point mode, the processor 100 controls the first FPGA circuit 200 to directly obtain the table item information corresponding to the point information through the sent point information, and then generates the frame content for beam switching, realizing the semi-automatic control of the phased array antenna 300.

[0059] The two different non-random modes can switch different non-random modes according to different working environments, so that the phased array antenna 300 adapts to different scenes.

[0060] Any of the above random mode, scanning mode and point mode can be used as the default working mode of the phased array antenna 300, and the antenna working modes can be freely switched. Therefore, by switching different antenna working modes, different scene requirements can be adapted, and the phased array antenna 300 beam can be quickly and accurately pointed.

[0061] After the first FPGA circuit 200 selects the corresponding antenna working mode, if the phased array antenna 300 needs to be phased to realize beam switching, the wave control code needs to be calculated. The process of calculating the wave control code is described below:

[0062] Alternatively, the first FPGA circuit 200 is configured to obtain the frame content corresponding to the selected antenna working mode for beam switching and send it to the second FPGA circuit 500. The second FPGA circuit 500 is configured to calculate the frame content for beam switching sent by the first FPGA circuit 200 to obtain the wave control code and send it to the beamforming chip 400. The beamforming chip 400 is configured to phase the phased array antenna 300 using the wave control code.

[0063] The second FPGA circuit 500 receives the frame content for switching the beam from the first FPGA circuit 200, such as angle-related data and frequency-related data, calculates the wave control code, and sends the wave control code to the beamforming chip 400.

[0064] The second FPGA circuit 500 can realize fast calculation of the wave control code by obtaining the frame content for beam switching from the first FPGA circuit 200 and performing wave control code calculation on the frame content. The first FPGA circuit 200 sends the frame content set by the processor 100 in the random mode or obtained by querying the storage table in the non-random mode to the second FPGA circuit 500. The second FPGA circuit 500 performs wave control code calculation after receiving the above information and sends the obtained wave control code to the beamforming chip 400. The beamforming chip 400 receives the wave control code and controls the phase distribution of the phased array antenna 300 according to the wave control code.

[0065] The first FPGA circuit 200 is configured to obtain the frame content, and the second FPGA circuit 500 is configured to calculate the frame content, so that the frame content can be obtained and the wave control code can be calculated quickly, the calculation efficiency is improved, real-time processing can be realized, and the phased array antenna 300 can be quickly and accurately pointed. Moreover, the beamforming chip 400 can be configured to realize the quick phase distribution of the phased array antenna 300.

[0066] Specifically, after the antenna working mode is selected, the first FPGA circuit 200 can be configured to encode the obtained frame content, add a check code, and form a data frame by framing, and send the data frame to the second FPGA circuit 500. The second FPGA circuit 500 is configured to decode the data frame and check whether the frame content is transmitted incorrectly by using the check code. After the frame content is checked to be correct, the frame content of the data frame is obtained, and the wave control code is calculated by using the frame content. The check is, for example, CRC check, and the check code is, for example, CRC check code. The encoding is, for example, 8b / 10b encoding.

[0067] The first FPGA circuit 200 encodes the frame content, adds a check code, and frames to form a data frame after scanning the table item information, obtaining the point number information, or receiving the frame content for beam switching sent by the processor 100, and then sends the data frame to the second FPGA circuit 500. The second FPGA circuit 500 receives the data frame from the first FPGA circuit 200, checks the data frame to determine whether transmission error occurs, does not process if error is found, and returns an error frame to indicate the first FPGA circuit 200 to resend. After the frame content is checked to be correct, the operation code type of the data frame is obtained, and the wave control code is calculated by using the frame content.

[0068] Optionally, the second FPGA circuit 500 is configured to decode the data frame to obtain the operation code type of the data frame. The second FPGA circuit 500 classifies and processes the data frame according to the operation code type of the data frame after the frame content is checked to be correct, so that different data frames can be processed differently. For example, the temperature / power reading frame is used to read temperature / power, the beam switching frame is used to switch the beam, and the array number / version number configuration frame is used to configure the array number / version number.

[0069] Further, the first FPGA circuit 200 has the advantage of fast parallel computing. The first FPGA circuit 200 can be used to process multiple frame contents in parallel to form multiple data frames, and convert the multiple data frames into serial data and send to the second FPGA circuit 500. The second FPGA circuit 500 receives the serial data and converts the serial data into multiple parallel data frames, and obtains the operation code type of each of the multiple data frames, and processes the multiple data frames according to the operation code type of each of the multiple data frames.

[0070] When the first FPGA circuit 200 converts the parallel data into serial data, it can be through the first FPGA circuit 200, or a dedicated serialization chip peripheral can be used. Similarly, when the second FPGA circuit 500 converts serial data into parallel data, it can be through the second FPGA circuit 500, or a dedicated deserialization chip peripheral can be used. For example, the serialization chip SN65LV1023A and the deserialization chip SN65LV1224B need to be used in pairs at the sending and receiving ends.

[0071] If the second FPGA circuit 500 receives a configuration array frame, the second FPGA circuit 500 receives the frame content of the configuration array number of the phased array antenna 300, and then the second FPGA circuit 500 writes the array number into the corresponding register. The array number of the phased array antenna 300 will not be changed after being written in its life cycle, and finally the second FPGA circuit 500 also needs to form a correct configuration frame and send it to the processor 100 through the first FPGA circuit 200.

[0072] If the second FPGA circuit 500 receives a temperature reading frame, the temperature reading peripheral data is read. There can be multiple temperature sensors on the board, and the temperature sensors have multiple types, and the interface can be single bus, I2C, SPI, etc. If the second FPGA circuit 500 and the beamforming chip 400 have a junction temperature sensor (not shown in the figure), it can also be read. Then form a temperature return frame and send it to the processor 100 through the first FPGA circuit 200. Similarly, receiving a power reading frame is also a similar operation.

[0073] In some embodiments, the functions of the second FPGA circuit 500 can be implemented on the first FPGA circuit 200, so the second FPGA circuit 500 can be cancelled, and in this case, the beamforming chip 400 can be coupled to the first FPGA circuit 200 and the phased array antenna 300.

[0074] Specifically, referring to Figure 3The first FPGA circuit 200 can be configured to obtain the frame content for beam switching corresponding to the selected antenna operating mode, and perform calculation on the obtained frame content for beam switching to obtain the wave control code and send the wave control code to the beamforming chip 400. The beamforming chip 400 is configured to perform phase distribution on the phased array antenna 300 by using the wave control code.

[0075] The first FPGA circuit 200 obtains the angle-related data and the frequency-related data by using the random operating mode or the non-random mode, calculates the wave control code, and sends the wave control code to the beamforming chip 400.

[0076] Referring to Figure 4 In some other embodiments, the phase distribution on the phased array antenna 300 by using the wave control code can also be completed by the first FPGA circuit 200. For example, the first FPGA circuit 200 can be integrated with an FPGA device, a phase shifter, an attenuator, and the like, and further configured as a system on chip, so as to realize the phase distribution. In other words, the first FPGA circuit 200 configured as a system on chip is equivalent to integrating the beamforming chip 400 directly into the first FPGA circuit 200, and can realize the function of the beamforming chip 400. In this case, the beamforming chip 400 can also not be separately and additionally arranged.

[0077] Based on the above, the storage table, the wave control code, and the beam switching are exemplarily described as follows:

[0078] If the beam switching frame is received, the wave control code is calculated according to the received frame content for beam switching, and the phase distribution on the phased array antenna 300 is completed by the beamforming chip 400.

[0079] Referring to Figure 5 Taking the two-dimensional phased array antenna 300 arranged in an M*N rectangular form as an example, the calculation formula of the antenna beam pointing coefficients a and β is as follows:

[0080] a = 2pdx cos θ sin Φ / λ (1).

[0081] β = 2pdy sin θ / λ (2).

[0082] Wherein, Φ is the azimuth angle; θ is the elevation angle; dx and dy are the horizontal and vertical distances between adjacent antenna elements; λ is the wavelength, f is the frequency, and λ = c / f.

[0083] The wave control code calculation formula of the antenna element (m, n) is as follows:

[0084]

[0085] Wherein, a and β are the pointing coefficients; m and n are the coordinates of the antenna element. The compensation value is used for calibrating the antenna elements.

[0086] An exemplary calculation process: first, the wave control code of the original array element can be calculated according to the above formula. Taking the case where the horizontal and vertical coordinates of each element of the phased array antenna 300 are equidistant, the wave control code of the remaining elements is calculated one by one by addition, and then the compensation parameters in the memory, such as the compensation parameters calculated by reading the operating temperature of the phased array antenna 300, are superimposed on the corresponding antenna elements to calculate the final wave control code required by each phase shifter unit corresponding to the array in the beamforming chip 400, generate a beam control timing signal to drive the phase shifter, and realize fast and accurate beam pointing.

[0087] Specifically, the first FPGA circuit 200 can use a pipeline time-sharing call storage table to find the corresponding angle-related data and frequency-related data in the storage table, and form the corresponding frame content. The second FPGA circuit 500 calculates using the above formula. In this way, a processing mode combining table lookup and multiplication and addition can be formed to quickly complete the calculation of the wave control code.

[0088] Optionally, the storage table includes an angle data storage table and a frequency data storage table. The angle data storage table is used to store angle-related data corresponding to each of a plurality of groups of angle combinations formed by permutation and combination of a plurality of azimuth angles and a plurality of elevation angles. The frequency data storage table is used to store frequency-related data corresponding to each of a plurality of frequencies. Each table entry information corresponds to a group of angle-related data and a piece of frequency-related data, and the angle-related data and the frequency-related data are used to calculate the wave control code for beam switching.

[0089] The angle-related data can include the sine value of the azimuth angle, the cosine value of the elevation angle, and the sine value of the elevation angle, or the product of the cosine value of the elevation angle and the sine value of the azimuth angle and the sine value of the elevation angle.

[0090] Based on the above formula, the angle-related data can include cosθ, sinΦ and sinθ, or cosθsinΦ and sinθ.

[0091] The frequency-related data includes the ratio between twice the product of the distance of adjacent elements of the phased array antenna 300 in the horizontal direction and π and the wavelength corresponding to the corresponding frequency, and the ratio between twice the product of the distance of adjacent elements of the phased array antenna 300 in the vertical direction and π and the wavelength corresponding to the corresponding frequency.

[0092] Based on the above formula, the frequency-related data can include 2πdx / λ and / or 2πdy / λ. When dx is equal to dy, 2πdx / λ and 2πdy / λ are equal, so the frequency data table can only keep one, that is, dx and dy can share a frequency data storage table. The table capacity is related to the frequency step, the smaller the step, the larger the required storage space, and in practice, a balance can be achieved according to resources and needs. Generally, after the phased array antenna 300 is prepared, dx and dy are fixed, so λ changes.

[0093] For example, for a 5G base station antenna, the azimuth angle can be set to horizontal ±50°, the elevation angle can be set to vertical ±15°, and 8 angles are taken in each angle range, such as azimuth angle: -50, -37.5, -25, -12.5, 0, +12.5, +25, +37.5, +50, elevation angle: -15, -11.5, -7.5, 0, +7.5, +11.5, +15, through permutation and combination, a total of 64 beam pointing directions can be formed, and the angle data storage table is to store the related data of the 64 angle combinations. For the azimuth angle or the elevation angle, the angle range can be set according to the needs and the existing process technology, and the specific step distance can also be set according to the needs and the like.

[0094] For example, the 5G frequency band of the 5G base station is n77, n78, and n79, that is, 3.3GHz-4.2GHz, 4.4GHz-5.0GHz. Then, the corresponding step distance can be set to obtain a plurality of frequency values, and the frequency data storage table is to store the related data of the plurality of frequencies.

[0095] Of course, the angle-related data can also include the angle value itself, and the cosine value and the sine value can be calculated after obtaining the angle data itself. The frequency-related data can also include the wavelength, the distance between adjacent elements in the horizontal direction, and the distance between adjacent elements in the vertical direction, and the multiplication and division operations among them can be performed later.

[0096] Compared with storing the value itself, by storing the above sine value, the above cosine value, and the above ratio, a half data frame form can be formed, and after the first FPGA circuit 200 obtains the half data frame, subsequent operations on the data can be quickly performed, so that the subsequent calculation amount is reduced, and the half data frame form is conducive to framing processing, saves the data frame processing time, and improves the data frame transmission rate.

[0097] As for in random mode, the processor 100 can set the frame content for beam switching, which can include the above-mentioned angle-related data and frequency-related data, etc., and then send to the first FPGA circuit 200. The first FPGA circuit 200 stores, encodes, checks the operation, and frames and then sends to the second FPGA circuit 500. The second FPGA circuit 500 calculates the frame content to calculate the beam control code.

[0098] After the second FPGA circuit 500 calculates the beam control code for beam switching, it is sent to the beamforming chip 400 to realize the fast beam switching of the phased array antenna 300 through the beamforming chip 400. When the number of array elements is insufficient for a single antenna, the overall transceiving performance of the antenna can be improved by the way of array group array of multiple phased array antennas 300. At this time, the array element number, version number, array surface number, etc. have a one-to-one matrix relationship, and the large amount of data requires the first FPGA circuit 200 to realize the correct and reasonable pipeline operation process.

[0099] Due to the differences in antenna PCB, array elements, frequency points, etc., the antenna needs to be calibrated before leaving the factory to achieve the most accurate pointing and best performance. If the second FPGA circuit 500 receives an antenna calibration instruction frame, the antenna is calibrated. Specifically, QSPI FLASH is used, and calibration information is written into the external FLASH through darkroom testing. When the antenna is working, the second FPGA circuit 500 pre-reads the compensation information inside the FLASH, combines the pitch angle, azimuth angle, frequency point, etc. to calculate the final beam control code, and sends it to the beamforming chip 400 to phase the phased array antenna 300.

[0100] The beam control system 1 (not marked) of the present application is an open system, and the phased array antenna 300 can be attached to multiple functions. In actual application, it includes but is not limited to the above-mentioned data frame type, and various data frame contents can also be customized according to the actual application scenario.

[0101] Based on the foregoing description, the beam control system 1 (not marked) can perform corresponding interrupt processing in the process of receiving data in the corresponding antenna working mode, which can improve the reception efficiency. For specific reference, see the following exemplary description.

[0102] The phased array antenna 300 is used to send data and / or receive data according to the selected antenna working mode. The phased array antenna 300 can send data or receive data in the corresponding antenna working mode, or can simultaneously send data and receive data.

[0103] In the process of receiving data, the first FPGA circuit 200 is used to calculate the number of received bytes and the time interval of the bytes when receiving data, and to judge whether the number of bytes reaches the depth threshold and whether the time interval reaches the timeout threshold.

[0104] If the number of bytes reaches the depth threshold or the time interval exceeds the timeout threshold, an interrupt signal is generated and sent to the processor 100, so that the processor 100 is used to read the data corresponding to the interrupt signal after receiving the interrupt signal. By processing the interrupt through the first FPGA circuit 200, the interrupt processing efficiency can be improved, and the access frequency of the processor 100 can be reduced, thereby reducing the pressure of the processor 100.

[0105] The first FPGA circuit 200 receives data from the phased array antenna 300 and calculates the number of received bytes and the time interval of receiving bytes. When the number of received bytes exceeds the pre-set depth threshold, the first FPGA circuit 200 generates an interrupt signal to notify the processor 100. When the number of received bytes does not exceed the pre-set depth threshold, the first FPGA circuit 200 waits for a pre-set time and does not continue to receive the number of bytes, i.e. the time interval of receiving bytes exceeds the timeout threshold, then the first FPGA circuit 200 generates an interrupt signal and sends it to the processor 100. As long as the processor 100 receives the interrupt signal generated by the first FPGA circuit 200, it will read the data corresponding to the interrupt signal.

[0106] The number of received bytes refers to the number of received bytes when the time interval between adjacent two bytes is less than the timeout threshold. For example, the timeout threshold is 30ms, and 4 bytes have been received. The time interval between receiving the 4 bytes is 5ms, and 35ms after receiving the 4th byte, no 5th byte is received, which means that the time interval of receiving bytes after the 4th byte exceeds the timeout threshold, so an interrupt signal will be generated at this point.

[0107] Specifically, the first FPGA circuit 200 is used to store the received data and update the interrupt vector register by channel when generating the interrupt signal, and the processor 100 is used to read the interrupt vector register after receiving the interrupt signal to obtain the channel corresponding to the interrupt signal, and then read the corresponding data in the storage space matched with the corresponding channel. In this way, the corresponding data can be quickly read, and the efficiency of data reading and processing can be improved.

[0108] Further, the first FPGA circuit 200 is used to aggregate the interrupt signals corresponding to the multiple peripherals respectively when receiving the data of the multiple peripherals within a pre-set time period, generate a final interrupt signal, and send the final interrupt signal to the processor 100. In this way, the processing efficiency of the processor 100 can be further improved, and the burden of the processor 100 can be reduced.

[0109] For example, the first FPGA circuit 200 receives data sent by the phased array antenna 300 or other peripherals, parses the data and the enable signal by byte; on one hand, stores the data into the corresponding memory, on the other hand, calculates the enable signal and the number of received bytes, and judges whether the number of bytes reaches the set depth threshold, and whether the set timeout threshold is reached; if one of them exceeds the threshold, an interrupt signal is generated, the first FPGA circuit 200 performs interrupt aggregation, supports one-way or multiple-way interrupt aggregation and processing according to requirements, generates a final interrupt signal, and outputs the final interrupt signal to the processor 100 through a hardware IO pin, updates the interrupt vector register according to the channel, and waits for 500us or other waiting time set according to requirements.

[0110] If the processor 100 does not process the interrupt, the interrupt vector register is updated again, and the interrupt is output until the processor 100 processes all interrupts. After the processor 100 receives the interrupt of the IO pin, the interrupt vector register is read to know which channel of the peripheral generates the interrupt, and then the processor 100 reads the corresponding register of the channel, and after reading the content of the corresponding register, the first FPGA circuit 200 automatically clears the interrupt of the channel. Among them, the processor 100 processes the interrupt in the rising edge mode, and supports interrupt masking and interrupt construction test, and the interrupt pulse output by the first FPGA circuit 200 can be set to 1us, 2us, 3us, etc. according to requirements.

[0111] In the above embodiment, communication is realized between the first FPGA circuit 200 and the second FPGA circuit 500 through at least one of UART, HDLC, SPI and LVDS; and / or, communication is realized between the processor 100 and the first FPGA circuit 200 through at least one of LOCALBUS, PCIE, AXI and SPI.

[0112] The communication frame between the ACU board card 10 and the AAU board card 20, wherein the error response frame is actively reported by the phased array antenna 300 when an error frame is received, the global reset frame has no response frame, and other types of frames are in a question and answer mode.

[0113] Table 1 is one embodiment of a sending / receiving message frame:

[0114] Table 1 is one embodiment of a sending / receiving message frame:

[0115]

[0116]

[0117] To further illustrate the above, the embodiment can build a functional unit framework related to the first FPGA circuit 200 and the second FPGA circuit 500, as follows:

[0118] As shown in (I), the functional framework of the first FPGA circuit 200 is exemplarily introduced as follows: Figures 6-11

[0119] 1. Transmission direction

[0120] implemented by the transmission module, wherein:

[0121] Referring to (III), the configuration module 201 can be used for the processor 100 to configure information such as frame length, frame content, bus rate, mode switching switch, etc. In the scan mode, it is also used to set the table item information; in the point mode, it is also used to set the point information. Figure 6

[0122] Referring to (IV), the random function module 203 is used to implement the random mode, i.e. the processor 100 sets any frame content to be sent to the first FPGA circuit 200. The random function module 203 can contain: a FIFO storage module 2031 for storing the frame content to be sent by the processor 100; an encoding module 2035 for implementing encoding; a check module 2033 for calculating the check result of each frame of data; a first control module 2032 which is a central state machine, for controlling the content reading of the FIFO storage module 2031, frame data transformation, check code calculation and addition, etc.; and a framing module 2034 for framing. Figure 7

[0123] Referring to (V), the scan function module 204 is used to implement the scan mode, i.e. the first FPGA circuit 200 frames and sends to the AAU board 20 according to the table item information in turn. The scan function module 204 can contain: an ITEM module 2041 for storing table item information; an encoding module 2045 for implementing encoding; a check module 2043 for calculating the check result of each frame of data; a second control module 2042 which is a central state machine, for controlling the table item content reading, frame data transformation, check code calculation and addition, etc.; and a framing module 2044 for framing. Figure 8

[0124] Referring to (VI), the scan function module 204 is used to implement the scan mode, i.e. the first FPGA circuit 200 frames and sends to the AAU board 20 according to the table item information in turn. The scan function module 204 can contain: an ITEM module 2041 for storing table item information; an encoding module 2045 for implementing encoding; a check module 2043 for calculating the check result of each frame of data; a second control module 2042 which is a central state machine, for controlling the table item content reading, frame data transformation, check code calculation and addition, etc.; and a framing module 2044 for framing. Figure 9 ​​​​The point function module 205 is used to implement the point mode, that is, the processor 100 informs the first FPGA circuit 200 of a point number, and the first FPGA circuit 200 sends a frame to the AAU board 20 after querying the beam pointing angle according to the point number. The point function module 205 can include a POINT module 2051 for storing point information, an encoding module 2055 for implementing encoding, a check module 2053 for calculating a check result of each frame of data, a third control module 2052 which is a central state machine and is used to control reading of table content, transformation of frame data, calculation and addition of check codes, and a framing module 2054 for framing.

[0125] In the three modes, the encoding module and the check module have consistent functions and can be reused; the ITEM module 2041 table information and the POINT module 2051 point information can also be reused if they are consistent; the framing module has some differences, and reuse can save FPGA resource occupation, but the control will be relatively complex.

[0126] The switching module 202 is used to implement mode switching. The beam control system 1 (not marked) supports random mode, scanning mode and point mode. Any one of the three modes can be used as the default operation mode, and a custom handshake mechanism is used to realize free switching between modes. In actual application, the three modes can be trimmed according to needs to enable one, two or all three modes.

[0127] If the random mode or the point mode needs to be started, the corresponding switch needs to be turned on. The first FPGA circuit 200 can automatically switch to the corresponding mode. For example, the switch is implemented through a register. The switch of each mode corresponds to 1 bit of the same register, and only 1 bit of the 3 bits can be 1 in the same period.

[0128] The data selection module 208 is used for frame routing output of the three modes. The frames can be output according to priority scheduling queue. If the frames of the three modes are not output at the same time, the routing output can be directly performed according to the enable signal.

[0129] 2, receiving direction

[0130] Referring to Figure 10 The deframing function module 206 is used to parse the frame information sent by the AAU board 20 and inform the processor 100 to read. The deframing function module 206 can include a deframing module 2064 for deframing data frames, a decoding module 2065 for decoding the frame content after deframing, a check module 2063 for checking whether the frame content is transmitted incorrectly, discarding and informing the processor 100 if an error occurs, a storage module 2061 for storing the information after decoding the frame content, and a fourth control module 2062 which is a central state machine and is used to schedule the series of operations.

[0131] Referring toFigure 11 The interrupt module 207 is used to generate an interrupt, output a hardware interrupt IO pin, and notify the processor 100 to read the received data. The interrupt module 207 can include a FIFO storage module 2073 used to store data, an interrupt generation module 2072 used to set a depth threshold and a timeout threshold, and determine whether to generate an interrupt signal according to the two thresholds and send the interrupt signal to an interrupt process module 2071, a pulse module 2074 used to generate a pulse signal and provide the interrupt module with a pulse signal with a set pulse width, and the interrupt process module 2071 used to count and perform interrupt aggregation by a state machine (not labeled) and a interrupt aggregation module (not labeled) and generate a final interrupt signal, output the final interrupt signal to the processor 100 through a hardware IO pin, and update an interrupt vector register according to a channel.

[0132] The peripheral device can be various devices, chips, modules, etc. The data sent by the peripheral device is parsed by the de-framing function module 206 according to bytes to obtain data and an enable signal. The data is stored in the FIFO storage module 2073, and the enable signal is input into the interrupt generation module 2072. The interrupt generation module 2072 calculates the number of received bytes by using a counting module (not labeled) and determines whether the set depth threshold is reached by using a state machine module (not labeled). The interrupt generation module 2072 also calculates whether the set timeout threshold is reached. If one of the thresholds is exceeded, an interrupt signal INT is generated and sent to the interrupt process module 2071. The state machine (not labeled) of the interrupt process module 2071 controls the interrupt aggregation module (not labeled) to perform interrupt aggregation, generates a final interrupt signal INT, outputs the final interrupt signal INT to the processor 100 through a hardware IO pin, and updates an interrupt vector register (not shown) according to a channel. After the processor 100 receives the interrupt of the IO pin, the processor 100 reads the interrupt vector register (not shown) to know which peripheral device generates the interrupt, and then reads the FIFO storage module corresponding to the peripheral device. After reading the content of the FIFO storage module, the first FPGA circuit 200 automatically clears the interrupt of the channel.

[0133] (II) As shown in Figures 12-19 , the following exemplary introduces the functional framework of the second FPGA circuit 500:

[0134] 1. Transmission direction

[0135] Referring to Figure 12 and Figure 13The frame-decoding function module 501 can include: a serial-to-parallel module 5011 for performing deserializing processing on the frame content to convert the external serial data into parallel data in byte units; a classification module 5014 for performing classification processing on the parallel frame data according to the operation code type if the check result of the check module 5013 is correct; a check module 5013 for performing bit-by-bit check on the frame content to determine whether the correct data frame is received, and returning an error frame to the ACU board 10 to retransmit if an error is found; and a first state machine 5012 for controlling the above operations.

[0136] Referring to Figure 14 The numbering function module 505 is configured to configure the array number or the version number. The numbering function module 505 can include: a framing module 5052 for composing a correct frame to be sent to the ACU board 10; and a fifth state machine 5051 for controlling the second FPGA circuit 500 to write the array number into the corresponding register to number the numbering module 510 or write the version number, and control a series of operations of the framing module.

[0137] Referring to Figure 15 The temperature control module 506 can include: a sixth state machine 5061 for driving the reading module 509 to read the temperature sensing data of the peripheral temperature sensor (not labeled), and there can be multiple temperature sensors on the board, and the temperature sensors can be of multiple types, and the interface can be a single bus, I2C, SPI, etc., and if the second FPGA circuit 500 and the beamforming chip 400 have temperature sensors inside, the temperature sensing data can also be read, and then the temperature return frame is composed by the framing module 5062 and sent to the ACU board 10.

[0138] Similarly, if the power needs to be read, similar modules and operations are also needed.

[0139] Referring to Figure 16 The array scanning module 507 can include: a storage module 5071 for storing relevant information for beam control code calculation; a calculation module 5074 for beam control code calculation; a framing module 5073 for composing a correct frame to be sent to the beamforming chip 400 through the control module 508; the control module 508 also includes a beamforming chip 400 control module (not shown) for controlling the beamforming chip 400 and an array control module (not shown) for controlling the matrix phased array antenna 300; and a seventh state machine 5072 for controlling the above operations.

[0140] Referring to Figure 17 The antenna calibration function module 504 can include: a framing module 5042 for composing a correct frame; and a fourth state machine 5041 for controlling the peripheral driving circuit 511 and the above operations.

[0141] 2, Return direction

[0142] Referring to Figure 18 The scheduling function module 502 is used for returning frame scheduling processing. The scheduling function module 502 can comprise a data selection module 5023 used for various return frame routing outputs; a checking module 5021 used for checking return data frames and verifying whether the return data frames are correct; the checking module 5021 can be a common module, and the aggregation here can save logic resources; a FIFO storage module 5024 stores the final data frames for reading by the next stage; and a second state machine 5022 controls the above operations.

[0143] Referring to Figure 19 The modulation output module 503 is used for return frame modulation output. The modulation output module 503 can comprise a parallel-to-serial module 5031 used for converting parallel signals into serial signals and temporarily buffering reading of the FIFO storage module 5024 in a busy state; and a third state machine 5032 controls the above operations.

[0144] Referring to Figure 20 The beam control method embodiment of the present application is applied to the above-mentioned beam control system embodiment of the present application, and the beam control method described in the embodiment can comprise:

[0145] S100: generating a switching instruction.

[0146] The processor 100 generates a switching instruction for switching the working mode of the first FPGA circuit 200, and the switching instruction at least comprises a random mode and a non-random mode, or a random mode, a scanning mode and a point mode.

[0147] S200: selecting an antenna working mode corresponding to the switching instruction.

[0148] The first FPGA circuit 200 receives the instruction for switching the working mode, and will execute the antenna working mode corresponding to the switching instruction.

[0149] S300: controlling the phased array antenna 300 to work in the selected antenna working mode.

[0150] The first FPGA circuit 200 executes the antenna working mode, and controls the phased array antenna 300 to work in the selected antenna working mode.

[0151] More detailed contents about the beam control method embodiment of the present application can be referred to the description of the above-mentioned beam control system embodiment of the phased array antenna of the present application, and will not be described here.

[0152] The above-mentioned only is the embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent flow transformation using the content of the specification and the drawings of the present application, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A beam control system for a phased array antenna, characterized in that: include: processor; a first FPGA circuit, coupled to the processor; a phased array antenna, coupled to the first FPGA circuit; The first FPGA circuit has at least two antenna operating modes, the processor is used to send a switching instruction to the first FPGA circuit, and the first FPGA circuit is used to respond to the switching instruction, select the antenna operating mode corresponding to the switching instruction, and control the phased array antenna to operate according to the selected antenna operating mode; Among them, the at least two antenna operating modes include a random pattern of frame content generated by the processor for beam switching and a non-random pattern of frame content generated by the first FPGA circuit for beam switching, and the phased array antenna is used to perform work corresponding to the corresponding frame content for beam switching.

2. The beam control system according to claim 1, characterized in that When the first FPGA circuit selects the random mode, the processor is used to set frame content for beam switching and send it to the first FPGA circuit.

3. The beam control system according to claim 1, wherein: When the first FPGA circuit selects the non-random mode, the first FPGA circuit is used to read the table entry information in its storage table to generate frame content for beam switching.

4. The beam control system according to claim 3, characterized in that The non-random mode includes a scanning mode and a point mode, and the first FPGA circuit is used to read the corresponding entry information in the storage table according to a preset order in the scanning mode; The first FPGA circuit receives the point information sent by the processor in the point mode, and reads the table entry information specified by the point information in the storage table.

5. The beam control system according to claim 4, characterized in that: The first FPGA circuit is configured to, upon receiving the switching instruction to switch to the random mode during the scanning mode, save the position information of the next entry that is not currently read in the storage table, and then switch to the random mode in response to the switching instruction; The first FPGA circuit resumes the scanning mode after completing the random mode, and reads the position information to continue reading the remaining unread table entry information in the preset order.

6. The beam control system according to claim 4, characterized in that The storage table includes an angle data storage table and a frequency data storage table, wherein the angle data storage table is used to store angle-related data corresponding to each of a plurality of angle combinations formed by permutations and combinations of a plurality of azimuth angles and a plurality of elevation angles; The frequency data storage table is used to store frequency-related data corresponding to multiple frequencies, each of the table entry information corresponds to a set of angle-related data and a set of frequency-related data, and the angle-related data and the frequency-related data are used to calculate the wave control code for beam switching.

7. The beam control system according to claim 6, characterized in that The angle-related data includes the sine value of the azimuth angle, the cosine value of the pitch angle, and the sine value of the pitch angle, or the product of the cosine value of the pitch angle and the sine value of the azimuth angle and the sine value of the pitch angle; The frequency-related data includes a ratio of a horizontal distance between adjacent array elements of the phased array antenna and twice the product of pi to a wavelength corresponding to a corresponding frequency, and a ratio of a vertical distance between adjacent array elements of the phased array antenna and twice the product of pi to a wavelength corresponding to a corresponding frequency.

8. The beam control system according to claim 1, wherein: A beamforming chip is included, the beamforming chip is coupled to the first FPGA circuit and the phased array antenna, and the beamforming chip is used to arrange the phases of the phased array antenna according to the selected antenna working mode.

9. The beam control system according to claim 8, characterized in that The first FPGA circuit is used to obtain the frame content for beam switching corresponding to the selected antenna operating mode, and calculate the obtained frame content for beam switching to obtain a beam control code and send it to the beamforming chip. The beamforming chip is used to use the beam control code to arrange the phase of the phased array antenna.

10. The beam control system according to claim 9, characterized in that: The second FPGA circuit is coupled to the first FPGA circuit and the beamforming chip, and the first FPGA circuit is used to obtain frame content for beam switching corresponding to the selected antenna operating mode and send it to the second FPGA circuit; The second FPGA circuit is used to calculate the frame content sent by the first FPGA circuit and used for beam switching to obtain a beam control code and send it to the beamforming chip; The beamforming chip is used to arrange the phases of the phased array antenna using the beam control code.

11. The beam control system according to claim 10, characterized in that The first FPGA circuit is used to encode the frame content, add a check code, and frame it to form a data frame, and send it to the second FPGA circuit; The second FPGA circuit is used to decode the data frame and use the check code to check whether the frame content is transmitted incorrectly. After checking that the frame content is correct, the frame content is obtained, and the wave control code is calculated using the frame content.

12. The beam control system according to claim 10, wherein: The first FPGA circuit is used to process multiple frame contents in parallel to form multiple data frames, convert the multiple data frames into serial data, and send the serial data to the second FPGA circuit; The second FPGA circuit receives the serial data and converts the serial data into the multiple parallel data frames, obtains the operation code type of each of the multiple data frames, and classifies and processes the multiple data frames according to the operation code type of each of the multiple data frames.

13. The beam control system according to claim 10, wherein: The phased array antenna is used to send data and / or receive data according to the selected antenna operating mode; The first FPGA circuit is used to calculate the number of bytes received and the time interval for receiving bytes when receiving data, and determine whether the number of bytes reaches a depth threshold and whether the time interval reaches a timeout threshold; If the number of bytes reaches the depth threshold or the time interval exceeds the timeout threshold, an interrupt signal is generated and sent to the processor, so that the processor reads the data corresponding to the interrupt signal after receiving the interrupt signal.

14. The beam control system according to claim 13, wherein: The first FPGA circuit is used to store data after receiving it, and to update its interrupt vector register by channel when an interrupt signal is generated. The processor is used to read the interrupt vector register after receiving the interrupt signal to obtain the channel corresponding to the interrupt signal, and then read the corresponding data in the storage space matching the corresponding channel.

15. The beam control system according to claim 14, characterized in that: The first FPGA circuit is used to aggregate the interrupt signals corresponding to the multiple peripheral devices when receiving data from the multiple peripheral devices within a preset time period, generate a final interrupt signal, and send the final interrupt signal to the processor.

16. The beam steering system according to claim 10, wherein: The first FPGA circuit and the second FPGA circuit communicate with each other via at least one of UART, HDLC, SPI and LVDS; And / or, the processor communicates with the first FPGA circuit via at least one of LOCALBUS, PCIE, AXI and SPI.

17. The beam control system according to claim 10, characterized in that: The processor and the first FPGA circuit are integrated on a first circuit board, and the second FPGA circuit and the beamforming chip are integrated on a second circuit board.

18. A beam steering method, characterized in that: The beam control system as claimed in any one of claims 1 to 17 comprises: generating a switching instruction; selecting the antenna operating mode corresponding to the switching instruction; The phased array antenna is controlled to operate according to the selected antenna operating mode.

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